Two-stage pipelined delta-sigma modulator with inter-stage low-pass filter

Abstract

A two-stage pipelined delta-sigma modulator with an inter-stage low-pass filter is characterized in that a residual signal of a whole first-stage delta-sigma loop is extracted, the residual signal passes through the inter-stage low-pass filter and then reaches the input end of a second-stage delta-sigma loop, and finally digital outputs of two stages of delta-sigma loop modules are spliced together through digital fitting, so that the two-stage pipelined delta-sigma modulator with the inter-stage low-pass filter is obtained. And the complete output of the delta-sigma modulator is obtained. The two-stage pipelined delta-sigma modulator with the inter-stage low-pass filter solves two problems of a traditional two-stage pipelined delta-sigma modulator at a low oversampling rate, namely that the quantization noise levels of two stages of loops are unbalanced and the mirror image signal of a digital-to-analog converter is too strong; and the signal-to-noise ratio of the two-stage pipelined delta-sigma modulator at a low oversampling rate is greatly enhanced.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design, and particularly to a two-stage pipelined ΔΣ modulator with an inter-stage low-pass filter-like structure. Background Art

[0002] With the continuous development of wireless communication technology, higher bandwidth and accuracy requirements are put forward for analog-to-digital converters (ADCs). Under limited process nodes, higher bandwidth requirements mean a smaller oversampling ratio. The traditional two-stage pipelined ΔΣ (Delta-Sigma) modulator architecture has the problem of unbalanced quantization noise at each stage. When the oversampling ratio decreases, this problem is further amplified, which not only exacerbates the deterioration of the signal-to-noise ratio (SNR) of the system, but also seriously affects the energy efficiency ratio of the system, becoming a major obstacle to performance improvement. Secondly, a DAC is required for signal feedback in the ΔΣ modulator loop, which will generate an image signal. The amplitude of this signal is inversely proportional to the oversampling ratio, that is, the amplitude of the image signal will increase as the oversampling ratio decreases. In the two-stage pipelined architecture, the enhancement of the image signal will directly affect the effective maintenance of the inter-stage gain, and further weaken the SNR performance of the system. Therefore, how to effectively design and optimize the ΔΣ modulator while reducing the oversampling ratio to achieve high-precision conversion has become the focus and difficult problem of both academia and industry.

[0003] In summary, for the design of a high-precision ΔΣ modulator in a low oversampling ratio environment, it is necessary not only to solve the problem of non-uniform distribution of quantization noise, but also to effectively control the influence of the image signal introduced by DAC feedback, so as to significantly improve the SNR performance while ensuring the energy efficiency of the system. This is the focus and challenge of current research. Summary of the Invention

[0004] To solve the above problems, the present invention proposes a two-stage pipelined ΔΣ modulator with an inter-stage low-pass filter-like structure. First, the residual signal of the overall first-stage ΔΣ loop is extracted, passed through the inter-stage low-pass filter-like structure, and reaches the input end of the second-stage ΔΣ loop. Finally, through digital fitting, the digital outputs of the two-stage ΔΣ loop modules are spliced together to obtain the output of the ΔΣ modulator. By specially designing the signal transfer function of the second-stage ΔΣ loop module and the digital-analog matching during splicing, in the finally formed high-order noise transfer function, the quantization noise introduced during the quantization process of the quantizer module in the first-stage ΔΣ loop module is suppressed by the noise transfer functions of both the first-stage loop and the second-stage loop, and the quantization noise introduced during the quantization process of the quantizer module in the second-stage ΔΣ loop module is suppressed by the noise transfer function of the second-stage loop and the digital fitting of the inter-stage low-pass filter-like structure, greatly enhancing the SNR of the two-stage pipelined ΔΣ modulator at low oversampling ratios.

[0005] The present invention can be implemented through the following technical solutions:

[0006] A two-stage pipelined ΔΣ modulator with an inter-stage low-pass-like filter, comprising a first-stage ΔΣ loop module and a second-stage ΔΣ loop module. It is characterized in that it further comprises an inter-stage low-pass-like filter, a residual signal extraction module, and a digital processing module, wherein:

[0007] The first-stage ΔΣ loop module includes a first digital processing module, a first loop filter, a first quantizer, and a first DAC;

[0008] The second-stage ΔΣ loop module includes a second digital processing module, a second loop filter, a second quantizer, and a second DAC;

[0009] The residual signal extraction module is integrated in the first loop filter and is used to extract the residual signal of the first-stage ΔΣ loop module;

[0010] The digital processing module includes a digital subtractor and a digital fitter, and is used to process signal splicing and digital fitting;

[0011] The input end of the first digital processing module is a continuous input signal input end. The output end of the first digital processing module is connected to the input end of the first loop filter. The output end of this first loop filter is connected to the input end of the first quantizer via the first sampling clock. The output end of the first quantizer is divided into two paths: one path is fed back to the second input end of the first digital processing module via the first DAC, and the other path is connected to the first input end of the digital subtractor;

[0012] The output end of the residual signal extraction module is connected to the input end of the inter-stage low-pass-like filter, and the output end of this inter-stage low-pass-like filter is connected to the input end of the second digital processing module;

[0013] The input end of the second loop filter is connected to the output end of the second digital processing module. The output end of the second loop filter is connected to the input end of the second quantizer via the second sampling clock. The output end of the second quantizer is divided into two paths: one path is connected to the second input end of the second digital processing module via the second DAC, and the other path is connected to the second input end of the digital subtractor via the digital fitter. The output end of the digital subtractor serves as the output end of the two-stage pipelined ΔΣ modulator with an inter-stage low-pass-like filter.

[0014] Further, the signal transfer function STF of the second-stage ΔΣ loop module 2a = 1 - (1 - z -1 ) n，Among them, n represents the order of the loop filter of the second - stage loop, which is equivalent to the number of cascaded first - order integrators in this loop, and is specifically determined according to the design requirements of the ΔΣ analog - to - digital converter.

[0015] The signal transfer function of the second - stage ΔΣ loop module matches the digital - to - analog during splicing. In the formed high - order noise transfer function, the quantization noise introduced by the quantizer in the first - stage ΔΣ loop module is suppressed by the noise transfer functions of both the first - stage loop and the second - stage loop. The quantization noise introduced by the quantizer in the second - stage ΔΣ loop module is suppressed by the noise transfer function of the second - stage loop and the digital fitting of the inter - stage low - pass - like filter, thereby enhancing the signal - to - noise ratio of the two - stage pipelined ΔΣ modulator at low oversampling rates.

[0016] Furthermore, the output end of the first quantizer is fed back to the input end of the first loop filter via the first DAC and coupled with the continuous input signal. The output end of the second quantizer is fed back to the input end of the second loop filter via the second DAC and coupled with the signal obtained after amplifying the residual continuous signal extracted from the first - stage loop.

[0017] Both the first loop filter and the second loop filter adopt continuous - time loop filters. Compared with the prior art, the beneficial technical effects of the present invention are as follows:

[0018] 1) An inter - stage low - pass - like filter is introduced between the two - stage ΔΣ loop modules to filter the residual signal of the first stage, ensuring that the high - frequency noise in it is attenuated before the residual signal is passed to the second stage, thereby reducing the influence on the quantization noise introduced by the second - stage quantizer, reducing the mirror - image signal component in the residual signal, and at the same time, the digital fitting part in its digital domain can further suppress the quantization noise in the second - stage loop.

[0019] 2) The digital processing module includes a digital subtractor and a digital fitter. Among them, the digital subtractor is used to subtract the fitted residual signal from the output of the second stage to eliminate the delay and phase distortion introduced by the inter - stage filter; the digital fitter is used to model and compensate the response of the inter - stage filter to ensure seamless splicing between the two - stage outputs.

[0020] 3) The quantization noise introduced by the first - stage quantizer is suppressed by the noise transfer functions of both the first - stage loop and the second - stage loop, while the quantization noise introduced by the second - stage quantizer is suppressed by the noise transfer function of the second - stage loop and the digital fitting of the inter - stage low - pass - like filter. This dual - suppression mechanism significantly improves the signal - to - noise ratio of the modulator. At low oversampling rates, the introduction of the inter - stage filter and the digital processing module enables the modulator to maintain high performance at low oversampling rates. Description of the Drawings

[0021] Figure 1It is a schematic structural diagram of a traditional two-stage pipelined ΔΣ modulator;

[0022] Figure 2 It is a schematic structural diagram of a two-stage pipelined ΔΣ modulator with an inter-stage low-pass-like filter according to the present invention;

[0023] Figure 3 It is a spectrum comparison diagram of the present invention and a traditional two-stage pipelined ΔΣ modulator;

[0024] Figure 4 It is a comparison of the input and output waveforms of the low-pass-like filter in the present invention; Specific embodiments

[0025] The specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings and embodiments.

[0026] Figure 1 It is a schematic structural diagram of a traditional two-stage pipelined ΔΣ modulator. The structure includes a ΔΣ dual-loop module, a residual signal extraction module, and a digital subtractor module. The ΔΣ dual-loop module includes a first-stage ΔΣ loop module and a second-stage ΔΣ loop module. The residual signal extracted from the overall first-stage ΔΣ loop module is used as the input of the second-stage ΔΣ loop module. The digital subtractor module connects the output ends of the first-stage and second-stage ΔΣ loop modules, and the signals at its output end are directly subtracted by this subtractor as the output of the entire two-stage pipelined analog-to-digital converter. The actual expression is shown in Equation (1). If the noise shaping levels of the two loops are inconsistent, it will cause a significant decrease in the signal-to-noise ratio of the system. Therefore, this problem can be greatly alleviated by the inter-stage low-pass-like filter in the following invention content.

[0027] Y MASH =STF 1 ·X+NTF 1 ·NTF 2 ·E q1 -NTF 2 ·E q2 (1)

[0028] Where Y MASH is the final output of the traditional two-stage pipelined ΔΣ modulator, STF and NTF are the signal transfer function and the noise transfer function respectively, Eq represents the quantization error, and the numbers "1" and "2" in the subscripts respectively indicate that this item belongs to the first and second loops. The symbols in the following text are all marked in this way.

[0029] Examples are as follows Figure 2As shown in the figure, an embodiment of a two-stage pipelined ΔΣ modulator with an inter-stage low-pass filter-like structure according to the present invention includes a ΔΣ double-loop module, a residual signal extraction module, an inter-stage low-pass filter-like structure, and a digital processing module. The ΔΣ double-loop module includes a first-stage ΔΣ loop module and a second-stage ΔΣ loop module. The digital processing module includes a digital subtractor and a digital fitting device.

[0030] Specifically, both loops in the ΔΣ double-loop module include a loop filter, a quantizer, and a digital-to-analog converter (DAC). That is, the first-stage ΔΣ loop module includes a first loop filter, which is sequentially connected to a first sample-and-hold circuit and a first quantizer. The output end of the first quantizer is coupled to the input end of the first loop filter through the first DAC and is fed back to the input end of the first loop filter with the help of the input signal; the second-stage ΔΣ loop module includes a second loop filter, which is sequentially connected to a second sample-and-hold circuit and a second quantizer. The output end of the second quantizer is coupled to the output of the residual signal amplifier through the second DAC and is fed back to the input end of the second loop filter with the help of the input end of the second loop filter.

[0031] The residual extraction module is integrated in the loop filter.

[0032] The second-stage ΔΣ loop module must satisfy the following conditions:

[0033] NTF 2 +STF 2 =1 (2)

[0034] Where STF2 and NTF2 represent the signal transfer function and noise transfer function generated by the second-stage ΔΣ loop module. At the same time, both the first loop filter and the second loop filter adopt continuous-time loop filters. Due to the low-pass filtering anti-aliasing inherent characteristics of the continuous-time loop filter, the design requirements of the pre-stage anti-aliasing filter in practical applications are greatly reduced; in addition, the input impedance of the continuous-time loop filter is resistive and is easy to drive by the pre-stage, so the bandwidth limit is significantly higher than that of the discrete-time loop filter.

[0035] The transfer function LPF(s) of the inter-stage low-pass filter-like structure becomes LPF(z) after bilinear transformation and is reciprocal to the digital fitting device, that is, the expressions of both need to satisfy

[0036] LPF(z)·H(z)=1 (3)

[0037] If the expression of the digital fitting device satisfies the following expression (a is a variable greater than 0 and less than 1)

[0038] H(z)=(1-az -1 ) (4)

[0039] Then the digital-domain expression of the inter-stage low-pass filter is

[0040]

[0041] After performing bilinear transformation on it, the analog-domain expression of the inter-stage low-pass filter is

[0042]

[0043] This expression shows that the inter-stage low-pass filter can filter out the high-frequency mirror signals of the digital-to-analog converter, and at the same time, its fitting function in the digital domain can perform noise shaping on the quantization noise of the second-stage ΔΣ. Thus, the two-stage pipelined ΔΣ modulator can achieve a higher signal-to-noise ratio at a low oversampling rate.

[0044] Specifically, in the working process, first, the input continuous signal passes through the loop filter and quantizer in the first-stage ΔΣ loop module, generating a digital output with quantization noise Eq 1 The digital signal is converted into an analog signal by the first DAC and fed back to the input end of the first loop filter. After the negative feedback loop stabilizes, the output signal of the first quantizer is the digital output signal Y 1 of the first-stage ΔΣ loop module. The residual extraction module integrated in the first-stage loop filter extracts the residual signal Eq 1 ·NTF 1 and transmits it to the input end of the inter-stage low-pass filter. The output signal of the inter-stage low-pass filter serves as the input signal of the second-stage ΔΣ loop module. This signal passes through the second loop filter and then enters the second quantizer in the second-stage ΔΣ loop module, generating a digital output containing quantization noise Eq 2 The digital output is converted into an analog signal by the second DAC and fed back to the input end of the second loop filter in the second-stage ΔΣ loop module. After the negative feedback loop stabilizes, the output signal of the second quantizer in the second-stage ΔΣ loop module is the digital output signal Y 2 of the second-stage ΔΣ loop module.

[0045] Y 1 = STF 1 ·X + NTF 1 ·E q1 (7)

[0046] Y 2 = STF 2 ·LPF·NTF 1 ·E q1 + NTF 2 ·E q2 (8)

[0047] The digital output signal Y of the second - stage ΔΣ loop module 2 After passing through the digital fitter, together with Y 1 Serve as the input of the digital subtractor, and the output of the digital subtractor is the final modulator output signal Y MASH :

[0048] Y MASH = Y 1 -(1 / H(z))·Y 2

[0049] = STF 1 ·X + NTF 1 ·(1 - LPF(s)·H(z)·STF 2 )·E q1 -H(z)·NTF 2 ·E q2 (9)

[0050] From equations (2) and (3), it can be transformed into

[0051] Y MASH = Y 1 -(1 / H(z))·Y 2 = STF 1 ·X + NTF 1 ·NTF 2 ·E q1 -H(z)·NTF 2 ·E q2 (10)

[0052] Therefore, compared with the expression of the traditional two - stage pipelined ΔΣ modulator shown in equation (1), it can be seen from equation (10) that the two - stage pipelined ΔΣ modulator with an inter - stage low - pass - like filter proposed by the present invention further suppresses the second - stage quantization noise and can improve the signal - to - noise ratio of the overall modulator.

[0053] Figure 3 Figure is the spectrum comparison diagram between the present invention and the traditional two - stage pipelined ΔΣ modulator. The inter - stage low - pass - like filter can reduce the noise floor and improve the signal - to - noise ratio of the overall DSM architecture. Figure 4 Figure is the comparison of the input and output waveforms of the low - pass - like filter in the present invention. The low - pass - like filter can filter out the high - frequency components in the DAC feedback, reduce the inter - stage output swing, and thus can increase the inter - stage gain and further improve the signal - to - noise ratio of the DSM system.

[0054] Those skilled in the art should understand that these are only examples. Without departing from the principle and essence of the present invention, various changes or modifications can be made to these embodiments. Therefore, the protection scope of the present invention is defined by the appended claims.

Claims

1. A two-stage pipeline ΔΣ modulator with an inter-stage low-pass filter, comprising a first-stage ΔΣ loop module and a second-stage ΔΣ loop module, characterized in that it also includes an inter-stage low-pass filter, a residual signal extraction module and a digital processing module, wherein: The first-stage ΔΣ loop module includes a first digital processing module, a first loop filter, a first quantizer and a first DAC; The second-stage ΔΣ loop module includes a second digital processing module, a second loop filter, a second quantizer, and a second DAC; The residual signal extraction module is integrated in the first loop filter and is used to extract the residual signal of the first-stage ΔΣ loop module; The digital processing module includes a digital subtractor and a digital fitter, which are used to process signal splicing and digital fitting; The input end of the first digital processing module is a continuous input signal input end, the output end of the first digital processing module is connected to the input end of the first loop filter, the output end of the first loop filter is connected to the input end of the first quantizer via the first sampling clock, and the output end of the first quantizer is divided into two paths: one path is fed back to the second input end of the first digital processing module via the first DAC, and the other path is connected to the first input end of the digital subtractor; The output end of the residual signal extraction module is connected to the input end of the inter-stage low-pass filter, and the output end of the inter-stage low-pass filter is connected to the input end of the second digital processing module; The input end of the second loop filter is connected to the output end of the second digital processing module, the output end of the second loop filter is connected to the input end of the second quantizer via the second sampling clock, the output end of the second quantizer is divided into two paths: one path is fed back to the second input end of the second digital processing module via the second DAC, and the other path is connected to the second input end of the digital subtractor via the digital fitter, and the output end of the digital subtractor serves as the output end of a two-stage pipeline ΔΣ modulator with an inter-stage low-pass filter.

2. The two-stage pipeline ΔΣ modulator with an inter-stage low-pass filter according to claim 1, characterized in that: The signal transfer function STF of the second-stage ΔΣ loop module 2a =1-(1-z -1 ) n , where n represents the order of the loop filter of the second-stage loop, which is equivalent to the number of cascades of the first-order integrators in the loop; the signal transfer function of the second-stage ΔΣ loop module matches the digital simulation during splicing, so that in the formed high-order noise transfer function, the quantization noise introduced by the quantizer in the first-stage ΔΣ loop module is suppressed by the noise transfer functions of the first-stage loop and the second-stage loop at the same time, and the quantization noise introduced by the quantizer in the second-stage ΔΣ loop module is suppressed by the noise transfer function of the second-stage loop and the digital fitting of the inter-stage low-pass filter at the same time, thereby enhancing the signal-to-noise ratio of the two-stage pipeline ΔΣ modulator at a low oversampling rate.

3. The two-stage pipeline ΔΣ modulator with an inter-stage low-pass filter according to claim 1 or 2, characterized in that: The output end of the first quantizer is fed back to the input end of the first loop filter via the first DAC and coupled with the continuous input signal; the output end of the second quantizer is fed back to the input end of the second loop filter via the second DAC and coupled with the signal obtained after amplifying the residual continuous signal extracted from the first-stage loop.

4. The two-stage pipeline ΔΣ modulator with an inter-stage low-pass filter according to claim 1 or 2, characterized in that: The first loop filter and the second loop filter are both continuous time loop filters.

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