High-throughput QC-LDPC (Quasi-Cyclic Low-Density Parity-Check Code) coding method and device adaptive to various code patterns

Abstract

The invention discloses a high-throughput QC-LDPC (Quasi-Cyclic Low-Density Parity-Check) code encoding method and device adaptive to various code patterns, and mainly solves the problems that the encoding throughput rate is low, various code lengths and code rates are not supported and the hardware utilization rate is low in the prior art. The implementation scheme comprises the following steps of: storing an information sequence S into an input register and then outputting in parallel to obtain a parallel information sequence S '; constructing an H1 XOR tree, and performing row-by-row XOR on the parallel information sequence S'by using the H1 XOR tree to generate a multi-code-length and multi-code-rate intermediate sequence qn; constructing an H2 inverse XOR tree, and generating a multi-code-length and multi-code-rate coding sequence pn by using the H2 inverse XOR tree to carry out XOR on the intermediate sequence qn according to rows; performing one-out-of-multiple selection on the multi-code-length and multi-code-rate coding sequence pn by using a code pattern selector to generate a single-code-length and code-rate check sequence p; and splicing the parallel information sequence S'and the verification sequence p, and outputting a coding sequence through parallel-serial conversion. According to the invention, the clock period required by coding can be reduced, the hardware utilization rate can be improved, and the method can adapt to various code lengths and various code rates at the same time, and can be used for channel coding in various high-speed communication scenes.

Description

Technical Field

[0001] The present invention belongs to the technical field of electronic communications, and particularly relates to a quasi-cyclic low-density parity-check (QC-LDPC) coding method and apparatus, which can be used for channel coding in various high-speed communication scenarios. Background Art

[0002] With the development of wireless communication technologies, modern wireless communications have put forward higher requirements for high-speed data transmission and reliability. Low-density parity-check (LDPC) codes are a type of forward error correction code. Due to their excellent error correction performance close to the Shannon limit, they have been widely applied in a series of standards such as the IEEE 802.11 communication standard, 5G NR, and Bluetooth. Among them, quasi-cyclic low-density parity-check (QC-LDPC) codes are a special type of LDPC codes, whose generator matrix and parity-check matrix both have a quasi-cyclic structure, giving them irreplaceable advantages in storage and decoder design. However, existing QC-LDPC encoders still face many problems: First, although taking the number of column blocks of the base matrix as the encoder parallelism can improve the throughput of the encoder to a certain extent, during the calculation of each part of the parity-check sequence, a large number of shift registers are required to serially encode data, making it difficult to further improve the throughput of the encoder; Second, there are multiple different code lengths and code rates under existing standards, and the adaptation to multiple types of code patterns has always been a research difficulty: Existing encoders often only design for a single code length and code rate, and such encoders have a low hardware reuse rate.

[0003] "Design and implementation of LDPC encoder based on FPGA" published by WANG Guodong et al. in Journal of Measurement Science and Instrumentation encodes a single code length and rate with a code length of 8176 and a code rate of 7 / 8 using a generation sub-shift algorithm. Although the encoder structure has a relatively low complexity, it can only achieve a throughput of 800 Mbps at a working clock of 159 MHz, requires 1420 clock cycles for a single encoding, and the encoder structure only supports a single code length and rate.

[0004] "Implementation of a Flexible Encoder for Structured Low-Density Parity-Check Codes" published by Sunitha Kopparthi et al. in the IEEE Pacific Rim Conference on Communications, Computers and Signal Processing, which uses a fast iterative algorithm to encode five code lengths and four code rates in the IEEE wireless metropolitan area network standard. Its theoretical throughput can be increased to 3.22 Gbps to 6.28 Gbps. However, due to the encoder still using the idea of separate encoding for different code lengths and different code rates, its hardware utilization rate is low.

[0005] The problems existing in the above-mentioned prior art all affect the throughput of the QC-LDPC encoder and its flexible adaptation to different code lengths and different code rates, resulting in the inability to meet the performance requirements in high-speed communication scenarios and poor hardware reuse rate, and it is difficult to meet the dual requirements of performance and cost of the actual communication system. Summary of the Invention

[0006] The purpose of the present invention is to propose a QC-LDPC encoding method and device with high throughput and adaptable to multiple code types in view of the above-mentioned deficiencies of the prior art, so as to make full use of the parallel characteristics between bit positions in the QC-LDPC encoding process, improve the throughput of the encoder, and on this basis, reduce the number of operations by using the common operations of different code lengths and different code rates, and improve the hardware reuse rate of the encoder and its adaptability to multiple code lengths and code rates.

[0007] The technical solutions for achieving the purpose of the present invention include:

[0008] Technical Solution 1:

[0009] A QC-LDPC encoding method with high throughput and adaptable to multiple code types, characterized by including:

[0010] Store the information sequence S into the input register and then output it in parallel to obtain the parallel information sequence S';

[0011] Construct an H1 exclusive-OR tree and use it to perform exclusive-OR on the parallel information sequence S' row by row to generate an intermediate sequence qn with multiple code lengths and multiple code rates;

[0012] Construct an H2 inverse exclusive-OR tree and use it to perform exclusive-OR on the intermediate sequence qn row by row to generate an encoded sequence pn with multiple code lengths and multiple code rates;

[0013] Use a code type selector to select one from multiple encoded sequences pn with multiple code lengths and multiple code rates to generate a parity-check sequence p with a single code length and code rate;

[0014] The parallel information sequence S′ and the check sequence p are concatenated and then converted from parallel to serial to output encoded data.

[0015] Preferably, the construction of the H1 XOR tree includes:

[0016] For each known code pattern, a corresponding check base matrix is successively column-divided to obtain all pre-sub matrices of the check base. where is the i-th check base matrix, with the number of rows being and the number of columns being is the i-th check base matrix 's first columns, is the i-th check base matrix 's last m b columns;

[0017] All the pre-sub matrices of the check base are sorted in ascending order of row code length and column code rate to obtain a sorted sequence of pre-sub matrices of the check base

[0018] Each row element of the sorted sequence of pre-sub matrices of the check base is respectively concatenated with a zero matrix to obtain g XOR tree base matrices of the same code length where is the j-th XOR tree base matrix of the same code length, I ZERO is a zero matrix of z j ×z j and z j is the expansion factor corresponding to the j-th XOR tree base matrix of the same code length, 1 ≤ j ≤ g; All the XOR tree base matrices of the same code length

[0019] are concatenated with a zero matrix to obtain the H1 XOR tree base matrix

[0020] The H1 XOR tree base matrix is expanded to obtain the H1 XOR tree expansion matrix H 1EX and then a common operation of merging is performed on it to obtain the H1 XOR tree merging matrix H 1COM ;

[0021] The column index value where the k-th row element value of the H1 XOR tree merging matrix H 1COM is 1 is denoted as The input register's bits are connected by XOR gates, and the H1 XOR tree merging matrix H 1COMThe exclusive-OR gate encapsulations generated by all rows are obtained to form the H1 exclusive-OR tree;

[0022] Preferably, the construction of the H2 inverse exclusive-OR tree includes:

[0023] For each known code pattern, a corresponding parity-check basis matrix is successively column-divided to obtain all post-parity-check basis submatrices where is the i-th parity-check basis matrix, with the number of rows being and the number of columns being is the first columns of the i-th parity-check basis matrix , is the i-th parity-check basis matrix 's last m b columns;

[0024] All post-parity-check basis submatrices are successively inverted to obtain all post-parity-check basis inverse matrices

[0025] All post-parity-check basis inverse matrices are sorted in ascending order of row code length and descending order of column code rate to obtain a sorted sequence of post-parity-check basis inverse matrices

[0026] Each row element of the sorted sequence of post-parity-check basis inverse matrices is respectively concatenated with a zero matrix to obtain g inverse basis matrices of exclusive-OR trees with the same code length where is the j-th inverse basis matrix of the exclusive-OR tree with the same code length, I ZERO is the zero matrix of z j ×z j , z j is the expansion factor corresponding to the j-th inverse basis matrix of the exclusive-OR tree with the same code length , 1 ≤ j ≤ g;

[0027] All inverse basis matrices of exclusive-OR trees with the same code length are concatenated with a zero matrix to obtain the H2 inverse exclusive-OR tree basis matrix

[0028] The H2 inverse exclusive-OR tree basis matrix is expanded to obtain the H2 inverse exclusive-OR tree expansion matrix H 2EX , and then a common operation of merging is performed on it to obtain the H2 inverse exclusive-OR tree merging matrix H 2COM ;

[0029] The column index value where the value of the k-th row element of the H2 inverse exclusive-OR tree merging matrix H 2COM is 1 is denoted as Connect the input register between the bits with an exclusive-OR gate, and merge the inverse exclusive-OR tree of H2 into matrix H 2COM Encapsulate the exclusive-OR gates generated by all rows to obtain the inverse exclusive-OR tree of H2.

[0030] Technical solution 2:

[0031] 2. A QC-LDPC encoding device with high throughput and adaptable to multiple code patterns, characterized by comprising:

[0032] A serial-to-parallel conversion module for converting the input serial information sequence S into a parallel information sequence S' and inputting it into the parallel-to-serial conversion module;

[0033] An H1 exclusive-OR tree module for performing exclusive-OR operations on the parallel information sequence S' row by row to generate an intermediate sequence qn with multiple code lengths and multiple code rates, and storing it in the intermediate sequence register;

[0034] An H2 inverse exclusive-OR tree module for performing exclusive-OR operations on the intermediate sequence qn row by row to generate an encoded sequence pn with multiple code lengths and multiple code rates, and inputting it into the code pattern selector module;

[0035] A code pattern selector module for selecting one from multiple encoded sequences pn with multiple code lengths and multiple code rates to generate a parity check sequence p with a single code length and code rate, and inputting it into the parallel-to-serial conversion module;

[0036] A parallel-to-serial conversion module for performing parallel-to-serial conversion after splicing the parallel information sequence and the parity check sequence p, and outputting the encoded sequence.

[0037] Compared with the prior art, the present invention has the following advantages:

[0038] First, the present invention uses a parity check matrix for encoding. By constructing an H1 exclusive-OR tree and an H2 inverse exclusive-OR tree, the main encoding process is divided into two steps: calculating the intermediate sequence qn and calculating the parity check sequence p, reducing the required clock cycles for theoretical encoding, increasing the theoretical throughput rate of the encoder while improving the computational parallelism.

[0039] Second, the present invention adopts a full code pattern encoder. When calculating the intermediate sequence qn and the parity check sequence pn, the encoding results of all code lengths and code rates are calculated simultaneously, and the encoding output is performed according to the externally input code length and code rate, increasing the flexibility and adaptability of the encoder.

[0040] Third, the present invention can reduce the number of exclusive-OR gates required for encoding by merging the common operations of the H1 exclusive-OR tree matrix and the H2 inverse exclusive-OR tree matrix, thereby improving the reuse rate of logical hardware while ensuring the correctness of the encoding result.

[0041] Fourth, the present invention uses an exclusive - or tree to replace the shift registers widely used in traditional coding schemes, which can save hardware storage resources. At the same time, it supports generating the simplest H1 exclusive - or tree and H2 inverse exclusive - or tree when only a single code length and code rate are required, further improving the hardware utilization rate. Description of the Drawings

[0042] Figure 1 is the implementation flowchart of the present invention;

[0043] Figure 2 is the sub - flowchart for constructing the H1 exclusive - or tree in the present invention;

[0044] Figure 3 is the sub - flowchart for constructing the H2 inverse exclusive - or tree in the present invention;

[0045] Figure 4 is the structural schematic diagram of the device of the present invention;

[0046] Figure 5 is the comparison chart of the theoretical throughput rate between the present invention and existing algorithms;

[0047] Figure 6 is the comparison chart of the hardware resource consumption between the present invention and existing algorithms. Detailed Description of the Invention

[0048] The implementation and effects of the present invention are further described in detail below with reference to the accompanying drawings.

[0049] Example 1: A QC - LDPC coding method with high throughput and adaptable to multiple code types.

[0050] Refer to Figure 1 , the implementation steps of this example are as follows:

[0051] Step 1, obtain the parallel information sequence S′ and store it in the output register.

[0052] 1.1) Serially store the information sequence S into the input register with a carry width of r max ×g max ;

[0053] 1.2) Parallel - output the first L bits of the input register to obtain the parallel information sequence S′;

[0054] 1.3) Store the parallel information sequence S′ into the first L bits of the output register with a width of g max .

[0055] In this example, the information sequence S=(s 1 , s 2 , … s L), that is, there are L bits in the information bits; the encoder supports a total of t code patterns with r code rates and g code lengths. Among them, the maximum code rate among the r code rates is denoted as r max , and the maximum code length among the g code lengths is denoted as g max .

[0056] Step 2, construct the H1 XOR tree.

[0057] Referring to Figure 2 , the implementation of this step includes the following:[[]]

[0058] 2.1) Perform column splitting on each known check basis matrix corresponding to each code pattern in sequence to obtain all the front sub-matrices of the check basis where:[[]]

[0059] is the i-th check basis matrix, and its number of rows is and the number of columns is

[0060] is the i-th check basis matrix 's first columns, is the i-th check basis matrix 's last m b columns,

[0061] The element values in[]] are all composed of numbers not greater than z i , and z i is the basis matrix expansion factor.

[0062] 2.2) Sort all the front sub-matrices of the check basis in ascending order of row code length and column code rate to obtain the sorted sequence of front sub-matrices of the check basis

[0063]

[0064] where is the sub-matrix at the j-th row and k-th column of the sorted sequence of front sub-matrices of the check basis .

[0065] In this example, for the sorted matrix sequence, the code lengths corresponding to the elements in each row are equal, and the code rates corresponding to the elements in each column are equal, that is, it satisfies:[[]]

[0066]

[0067] where Length(·) is used to find the code length of the code pattern corresponding to the element, and Rate(·) is used to find the code rate of the code pattern corresponding to the element.

[0068] 2.3) Concatenate the zero matrix to each element in each row of the sorted pre-check basis submatrix sequence to obtain g XOR tree basis matrices with the same code length where:

[0069] is the j-th XOR tree basis matrix with the same code length, and I ZERO is the zero matrix of z j ×z j and z j is the expansion factor corresponding to the j-th XOR tree basis matrix with the same code length.

[0070] 2.4) Concatenate the zero matrix to all the XOR tree basis matrices with the same code length to obtain the H1 XOR tree basis matrix

[0071]

[0072] where I ZERO represents the zero matrix of z j ×z j and z j is the expansion factor corresponding to the j-th XOR tree basis matrix with the same code length. Each element value in represents a square matrix obtained by circularly shifting a z j order identity matrix to the right by this value;

[0073] In this example, is a matrix with the number of rows and the number of columns , and the upper right part of the matrix is a zero matrix.

[0074] 2.5) Expand the H1 XOR tree basis matrix to obtain the H1 XOR tree expansion matrix H 1EX , and then perform the common operation of merging on it to obtain the H1 XOR tree merging matrix H 1COM :

[0075] 2.5.1) Calculate the expansion factor z for each row of the H1 XOR tree basis matrix i :

[0076]

[0077] where refers to the common code length of each basis matrix in the XOR tree basis matrix with the same code length, and is the number of columns of the check basis matrix of the i-th code length;

[0078] 2.5.2) Expand each element value in into a square matrix obtained by cyclically shifting a z i order identity matrix to the right by that value, obtaining the extended matrix H of the H1 XOR tree 1EX :

[0079]

[0080] where h (u1,v1) is the element in the u1-th row and v1-th column of H 1EX , h (u1,v2) is the element in the u1-th row and v2-th column of H 1EX , h (u2,v1) is the element in the u2-th row and v1-th column of H 1EX , h (u2,v2) is the element in the u2-th row and v2-th column of H 1EX , and h (u1,v1) = h (u1,v2) = h (u2,v1) = h (u2,v2) = 1.

[0081] 2.5.3) Perform a combined AND operation on the extended matrix H of the H1 XOR tree, that is, traverse all elements of the extended matrix H of the H1 XOR tree 1EX , and combine the XOR gates at h 1EX and h (u2,v1) to obtain the combined matrix H of the H1 XOR tree (u2,v2) : 1COM :

[0082]

[0083] 2.6) Denote the column index value where the element value in the k-th row of the combined matrix H of the H1 XOR tree is 1 as 1COM , connect the -th bits of the input register with XOR gates, and encapsulate the XOR gates generated by all rows of the combined matrix H of the H1 XOR tree to obtain the H1 XOR tree. 1COM

[0084] Step 3, use the H1 XOR tree to perform an XOR operation on the parallel information sequence S′ row by row to generate an intermediate sequence qn with multiple code lengths and multiple code rates.

[0085] 3.1) Store the column subscripts where the element values in each row of the H1 XOR tree are 1, where the subscripts of the elements with value 1 in the k-th row are denoted as

[0086] 3.2) Perform an XOR operation on the -th bit of the parallel information sequence S′ to obtain the k-th bit of the i-th group of intermediate sequence qi;

[0087] ​3.3) Traverse all rows of the H1 XOR tree, and perform XOR operations on the parallel information sequence S′ in turn according to the stored column subscript values to generate an intermediate sequence qn with multiple code lengths and multiple code rates.

[0088] Step 4, construct the inverse H2 XOR tree.

[0089] Refer to Figure 3 , and the implementation of this step includes the following:

[0090] 4.1) Perform column splitting on each known parity-check basis matrix corresponding to each code pattern in turn to obtain all post-parity-check basis submatrices where:

[0091] is the i-th parity-check basis matrix, with the number of rows being and the number of columns being

[0092] is the first columns of the i-th parity-check basis matrix , is the last m columns of the i-th parity-check basis matrix b ,

[0093] The element values in i are all composed of numbers not greater than z i , and z

[0094] 4.2) Invert all post-parity-check basis submatrices in turn to obtain all post-parity-check inverse matrices

[0095] 4.3) Sort all post-parity-check inverse matrices in ascending order of row code length and descending order of column code rate to obtain a sorted sequence of post-parity-check inverse matrices

[0096]

[0097] where is the submatrix at the j-th row and k-th column of the sorted sequence of post-parity-check inverse matrices .

[0098] In this example, for the sorted matrix sequence, the code lengths corresponding to the elements in each row are equal, and the code rates corresponding to the elements in each column are equal, that is, it satisfies:

[0099]

[0100] Where Length(·) refers to calculating the code length corresponding to the element, and Rate(·) refers to calculating the code rate corresponding to the element.

[0101] 4.4) The sequence of inverse matrices of the parity check bases after sorting Append the zero matrix to each element in each row to obtain g inverse basis matrices of the XOR tree with the same code length Where:

[0102] is the j-th inverse basis matrix of the XOR tree with the same code length, I ZERO represents the zero matrix of z j ×z j and z j is the expansion factor corresponding to the j-th inverse basis matrix of the XOR tree with the same code length corresponding to it.

[0103] 4.5) Append the zero matrix to all the inverse basis matrices of the XOR tree with the same code length to obtain the inverse XOR tree basis matrix H2

[0104]

[0105] Where I ZERO represents the zero matrix of z j ×z j and z j is the expansion factor corresponding to the j-th inverse basis matrix of the XOR tree with the same code length corresponding to it, and each element value in it represents a square matrix obtained by circularly shifting a z j order identity matrix to the right by this value;

[0106] In this example, is a matrix with the number of rows being and the number of columns being and the upper right part of the matrix is a zero matrix.

[0107] 4.6) Expand the inverse XOR tree basis matrix to obtain the expanded matrix H of the inverse XOR tree of H2 2EX , and then perform the combined common operation on it to obtain the combined matrix H of the inverse XOR tree of H2 2COM :

[0108] 4.6.1) Calculate the expansion factor z for each row of the inverse XOR tree basis matrix i of H2:

[0109]

[0110] Where is the inverse basis matrix of the XOR tree with the same code length The common code length of each base matrix in is the check base matrix of the i-th code length The number of columns;

[0111] 4.6.2) Expand each element value in into a square matrix obtained by cyclically shifting the value of a z i order identity matrix to the right, and obtain the H2 inverse XOR tree merging matrix H 2EX :

[0112]

[0113] where e (u1,v1) is the element in the u1-th row and v1-th column of H 2EX , e (u1,v2) is the element in the u1-th row and v2-th column of H 2EX , e (u2,v1) is the element in the u2-th row and v1-th column of H 2EX , e (u2,v2) is the element in the u2-th row and v2-th column of H 2EX , and e (u1,v1) = e (u1,v2) = e (u2,v1) = e (u2,v2) = 1;

[0114] 4.6.3) Perform the common merging operation on the H2 inverse XOR tree merging matrix H 2EX , that is, traverse all elements of the H2 inverse XOR tree expansion matrix H 2EX , merge the XOR gates at e (u2,v1) and e (u2,v2) , and obtain the H2 inverse XOR tree merging matrix H 2COM :

[0115]

[0116] 4.7) Denote the column index value where the element value of the k-th row of the H2 inverse XOR tree merging matrix H 2COM is 1 as Connect the th bits of the input register with XOR gates, and encapsulate the XOR gates generated by all rows of the H2 inverse XOR tree merging matrix H 2COM to obtain the H2 inverse XOR tree.

[0117] Step 5, use the H2 inverse XOR tree to perform row-wise XOR on the intermediate sequence qn to generate a multi-code length and multi-code rate encoded sequence pn.

[0118] 5.1) Store the column subscripts where the element values of each row of the H2 inverse XOR tree are 1, where the subscripts of the elements with value 1 in the k-th row are marked as

[0119] 5.2) Perform an exclusive OR operation on the -th bit of the i-th intermediate sequence qi to obtain the k-th bit of the i-th check sequence pi.

[0120] 5.3) Traverse all rows of the inverse exclusive OR tree of H2, and perform exclusive OR operations on the intermediate sequence qn in sequence according to the stored column subscript values to generate a coding sequence pn with multiple code lengths and multiple code rates.

[0121] Step 6: Use a code pattern selector to perform a one-of-many selection on the coding sequence pn with multiple code lengths and multiple code rates to generate a check sequence p with a single code length and code rate.

[0122] 6.1) Combine all code rates, all code lengths, and the check sequence values q 1 , q 2 , …, q i , …, q t to establish a code pattern selection table;

[0123] 6.2) Generate a multiplexer according to the code pattern selection table;

[0124] 6.3) Input the required coding code rate r n , the required coding code length g n into the multiplexer to generate the required code pattern check sequence.

[0125] In this example, the inputs to the code pattern selector are the required coding code rate r n , the required coding code length g n , and t groups of check sequences q 1 , q 2 , …, q i , …, q t . The output of the code pattern selector is the required code length and code rate check sequence, which is stored in the output register and stored in sequence from the low bit to the high bit starting from the (L + 1)-th bit of the output register.

[0126] Step 7: Concatenate the parallel information sequence S′ and the check sequence p and perform a parallel-to-serial conversion to output the encoded data.

[0127] 7.1) Store the 1st to L-th bits of the parallel information sequence S′ in the corresponding 1st to L-th bits of the output register; 7.2) Store the 1st to r n × g n bits of the stored check sequence p into the (L + 1)-th to (L + r n × g n

[0128] -th bits of the output register;

[0129] 7.3) Output the 1st to (L + r n × g nPerform serial-to-parallel conversion on the bits to obtain the required encoded data, and output it sequentially from the low bit to the high bit of the output register.

[0130] Embodiment 2: High-throughput QC-LDPC encoding device adapted to multiple types of code patterns

[0131] Refer to Figure 4 , the device of this embodiment includes: a serial-to-parallel conversion module 1, an H1 exclusive-OR tree module 2, an H2 inverse exclusive-OR tree module 3, a code pattern selector module 4, and a parallel-to-serial conversion module 5. Its encoding principle is as follows:

[0132] The serial-to-parallel conversion module 1 converts the input serial information sequence S into a parallel information sequence S′ and inputs it to the parallel-to-serial conversion module; the H1 exclusive-OR tree module 2 performs exclusive-OR on the parallel information sequence S′ row by row to generate an intermediate sequence qn with multiple code lengths and multiple code rates, and stores it in the intermediate sequence register; the H2 inverse exclusive-OR tree module 3 takes out the intermediate sequence qn stored in the intermediate sequence register, performs exclusive-OR on the intermediate sequence qn row by row to generate an encoded sequence pn with multiple code lengths and multiple code rates, and inputs it to the code pattern selector module; the code pattern selector module 4 establishes a code pattern selection table for all code rates, all code lengths and the encoded sequence pn, generates a multiplexer according to the code pattern selection table, and inputs the required encoding code rate r n , the required encoding code length g n into the multiplexer to generate a check sequence p, and inputs it to the parallel-to-serial conversion module; the parallel-to-serial conversion module 5 performs parallel-to-serial conversion after splicing the parallel information sequence S′ and the check sequence p, and outputs the encoded sequence.

[0133] The effects of the present invention will be further described through simulation experiments below.

[0134] I. Simulation conditions:

[0135] This simulation uses an Inter Core i9-10900F CPU with a main frequency of 2.80 GHz, 32.0 GB of memory, a 64-bit operating system and Microsoft Windows 10 Professional Edition, and the simulation software is MATLAB2022a.

[0136] The simulation standard is the IEEE 802.11 series standard. This standard has 3 code lengths: 648, 1296, and 1944. Each code length has 4 code rates: 1 / 2, 2 / 3, 3 / 4, and 5 / 6. That is, there are 12 code patterns, and each code pattern corresponds to a check base matrix.

[0137] II. Simulation content and result analysis:

[0138] Simulation 1: Under the above simulation conditions, set the information sequences of 12 code patterns as pseudo-random sources, and at the same time set the MATLAB random number seed to a fixed value. Use the method of the present invention, the traditional generating sub-shift algorithm, and the fast iterative coding algorithm to encode the information sequences of their respective code patterns respectively. The results are shown in Table 1.

[0139] Table 1 Comparison of Coding Results between the Present Invention and Traditional Algorithms

[0140]

[0141] As can be seen from Table 1, under all 12 code patterns, the coding results obtained by the present invention, the traditional generating sub-shift algorithm, and the fast iterative coding algorithm are the same, indicating that the coding result of the present invention is correct.

[0142] Simulation 2: Under the above simulation conditions, set the required code length to 1944, the required code rate to 5 / 6, set the clock frequency to 200 MHz, and calculate the theoretical maximum throughput supported by the present invention, the traditional generating sub-shift algorithm, and the fast iterative coding algorithm respectively: Where N L is the coding code length, N R is the code rate, f CLK is the working clock frequency, and N CC is the number of clock cycles required for one encoding.

[0143] Compare the theoretical maximum throughput of the three methods. The results are as Figure 5 .

[0144] From Figure 5 it can be seen that under the given 12 code patterns, when the code length is 1944 and the code rate is 5 / 6, the theoretical throughput of the present invention reaches the maximum value of 162 Gbps. Its theoretical throughput is 40.5 times that of the traditional generating sub-shift algorithm and 12 times that of the fast iterative coding algorithm. At the same time, under other code patterns, the theoretical throughput of the present invention is better than that of other algorithms, indicating that the present invention has a high theoretical coding throughput.

[0145] Simulation 3: Under the above simulation conditions, calculate the computing resources and storage resources required for encoding by the present invention, the traditional generating sub-shift algorithm, and the fast iterative coding algorithm respectively. The results are as Figure 6 .

[0146] Since the encoding process performs exclusive OR operations on the bit stream, the computing resources refer to the number of exclusive OR operations, and the storage resources refer to the total number of bits of the registers required to store variables.

[0147] From Figure 6 it can be seen that the present invention requires 41,588 exclusive OR calculations and 3564 bits of memory occupancy. The hardware resource consumption is lower than that of the traditional generating sub-shift algorithm and the fast iterative coding algorithm.

[0148] The above description is only a preferred embodiment of the present invention and does not constitute any limitation to the present invention. For professionals in the field, after understanding the principles and implementation methods of the present invention, they may make modifications and substitutions in form and details without departing from the principles and structures of the present invention. However, the above modifications should all be included within the protection scope of the present invention.

[0149] It should be noted that the step numbers in the specification and claims of the present invention are only for clearly describing the implementation schemes of the present invention for easy understanding, and the sequence order of their numbers is not limited.

Claims

1. A high-throughput, multi-code adaptive QC-LDPC encoding method, characterized in that: include: The information sequence S is stored in the input register and then output in parallel to obtain a parallel information sequence S′; Construct H1 XOR tree and use it to perform row-wise XOR on parallel information sequence S′ to generate intermediate sequence qn with multiple code lengths and multiple code rates; Construct an H2 inverse XOR tree and use it to perform row-wise XOR on the intermediate sequence qn to generate a multi-code length and multi-rate coding sequence pn; The code type selector is used to select one of the coding sequences pn with multiple code lengths and multiple code rates to generate a check sequence p with a single code length and code rate; The parallel information sequence S′ is concatenated with the check sequence p, and then parallel-to-serial conversion is performed to output the coded sequence.

2. The method according to claim 1, characterized in that: The bit width of the input register is equal to the maximum code length L of all code types in the information sequence S to be encoded. max ; The information sequence S and the parallel information sequence S′ are respectively expressed as follows: S=(s1,s2,…s L ) where s1′=s1,s2′=s2,…,s L ′=s L .

3. The method according to claim 1, characterized in that The construction of H1 XOR tree includes: (3a) For each known code type, a check matrix corresponding to Perform column splitting in sequence to obtain all the check basis pre-matrices in is the i-th check basis matrix, and its number of rows is The number of columns is is the i-th check basis matrix Before List, is the i-th check basis matrix The back of b List; (3b) All the check basis pre-matrices Sort by increasing row code length and column code rate to get the sorted check base pre-submatrix sequence in is the sorted check basis pre-submatrix sequence The submatrix with row j and column k; (3c) The sorted check base pre-submatrix sequence Each row of elements is concatenated with a zero matrix to obtain g XOR tree base matrices with the same code length. in is the jth XOR tree base matrix with the same code length, I ZERO For z j × j The zero matrix, z j is the jth XOR tree base matrix with the same code length The corresponding expansion factor is 1≤j≤g; (3d) All the same code length XOR tree base matrix Concatenate the zero matrix to get the H1 XOR tree base matrix Among them I ZERO Represents z j × j The zero matrix, z j is the jth XOR tree base matrix with the same code length The corresponding expansion factor, 1≤j≤g, Each element value in represents a z j The square matrix obtained by cyclically right shifting the unit matrix of order by this value; (3e) For H1 XOR tree base matrix Expand to get H1 XOR tree expansion matrix H 1EX , and then perform a merge and share operation on it to obtain the H1 XOR tree merge matrix H 1COM ; (3f) Merge the H1 XOR tree into the matrix H 1COM The column index value of the element value 1 in the kth row is recorded as Enter the register The bits are connected by XOR gates, and the H1 XOR tree is merged into the matrix H 1COM All row-generated XOR gates are encapsulated to obtain the H1 XOR tree.

4. The method according to claim 1, characterized in that The method of using the H1 XOR tree to perform row-wise XOR on the parallel information sequence S′ to generate an intermediate sequence qn with multiple code lengths and multiple code rates includes: The column subscripts of the element values ​​of each row of the H1 XOR tree are stored, where the subscripts of the element values ​​of 1 in the kth row are For the parallel information sequence S′ The kth bit of the i-th group of intermediate sequence qi is obtained by performing XOR operation on the bits; Traverse all rows of the H1 XOR tree, perform XOR operations on the parallel information sequence S′ in turn according to the stored column index values, and generate an intermediate sequence qn with multiple code lengths and multiple code rates.

5. The method according to claim 1, characterized in that The construction of the H2 inverse XOR tree includes: (5a) For each known code type, a check matrix corresponding to Perform column splitting in sequence to obtain all the check base sub-matrices in is the i-th check basis matrix, and its number of rows is The number of columns is is the i-th check basis matrix Before List, is the i-th check basis matrix The back of b List; (5b) All the check base submatrices Inverse them one by one to get the inverse matrix of all the check bases (5c) All the check bases are inverted Sort by increasing row code length and decreasing column code rate to obtain the sorted check base inverse matrix sequence in is the sorted check base inverse matrix sequence The submatrix with row j and column k; (5d) The sorted check base inverse matrix sequence Each row of elements is concatenated with a zero matrix to obtain g inverse base matrices of the same code length XOR tree. in is the jth XOR tree base matrix with the same code length, I ZERO Represents z j × j The zero matrix, z j is the inverse basis matrix of the j-th XOR tree with the same code length The corresponding expansion factor is 1≤j≤g; (5e) Inverse the base matrix of all XOR trees with the same code length Concatenate the zero matrices to get the H2 inverse XOR tree base matrix Among them I ZERO Represents z j × j The zero matrix, z j is the inverse basis matrix of the j-th XOR tree with the same code length The corresponding expansion factor is 1≤j≤g; Each element value in represents a z j The square matrix obtained by cyclically right shifting the unit matrix of order by this value; (5f) For H2 inverse XOR tree base matrix Expand to get the H2 inverse XOR tree expansion matrix H 2EX , and then perform a merge and share operation on it to obtain the H2 inverse XOR tree merge matrix H 2COM ; (5g) Merge the H2 inverse XOR tree into the matrix H 2COM The column index value of the kth row element value 1 is recorded as Enter the register The bits are connected by XOR gates, and the H2 inverse XOR tree is merged into the matrix H 2COM All row-generated XOR gates are encapsulated to obtain the H2 inverse XOR tree.

6. The method according to claim 1, characterized in that: The method of using the H2 inverse XOR tree to perform row-wise XOR on the intermediate sequence qn to generate a coding sequence pn with multiple code lengths and multiple code rates includes: The column subscripts of the element values ​​of each row of the H2 inverse XOR tree are stored, where the subscripts of the element values ​​of 1 in the kth row are For the first intermediate sequence qi of the i-th group The kth bit of the i-th group check sequence pi is obtained by performing an XOR operation on the bits; Traverse all rows of the H2 inverse XOR tree, perform XOR operations on the intermediate sequence qn in turn according to the stored column subscript values, and generate a coded sequence pn with multiple code lengths and multiple code rates.

7. The method according to claim 1, characterized in that The method of using a code type selector to select one of the coding sequences pn with multiple code lengths and multiple code rates to generate a check sequence p with a single code length and code rate includes: All code rates, all code lengths and check sequence values ​​q1, q2, ..., q i ,…,q t Establish a code selection table; Generate a multiplexer according to the code pattern selection table; The required encoding rate r n , the required encoding length g n Input multiplexer to generate the required pattern check sequence.

8. The method according to claim 1, characterized in that The process of concatenating the parallel information sequence S′ and the check sequence p, performing parallel-to-serial conversion, and outputting coded data comprises: storing the 1st to the Lth bits of the parallel information sequence S′ in the corresponding 1st to the Lth bits in the output register; Store the first to the rth bits of the check sequence p n ×g n The bits are stored in the output register from bit L+1 to bit L+r n ×g n Bit; Output register bit 1 to bit L+r n ×g n The bits are converted into parallel and serial bits to obtain the required encoded data, and are output in sequence from the low bit to the high bit of the output register.

9. The method according to claim 3, characterized in that: The H1 XOR tree expansion matrix H constructed in step (3e) 1EX , which is expressed as follows: where h (u1,v1) Yes H 1EX The element in row u1 and column v1, h (u1,v2) Yes H 1EX The element in row u1 and column v2, h (u2,v1) Yes H 1EX The element in row u2 and column v1, h (u2,v2) Yes H 1EX The element in row u2 and column v2, and h (u1,v1) =h (u1,v2) =h (u2,v1) =h (u2,v2) =1.

10. The method according to claim 3, characterized in that: In step (3e), the matrix H 1EX To perform the merge and share operation, traverse the H1 XOR tree to expand the matrix H 1EX All elements, merge h (u2,v1) and h (u2,v2) At the XOR gate, we get the H1 XOR tree merge matrix H 1COM , which is expressed as follows: Among them, h (u1,v2) Yes H 1EX The element in row u1 and column v2, h (u2,v1) Yes H 1EX The element at row u2 and column v1.

11. The method according to claim 5, characterized in that The H2 inverse XOR tree merge matrix H constructed in step (5f) 2EX , which is expressed as follows: where e (u1,v1) Yes H 2EX The element in row u1 and column v1, e (u1,v2) Yes H 2EX The element in row u1 and column v2, e (u2,v1) Yes H 2EX The element in row u2 and column v1, e (u2,v2) Yes H 2EX The element in row u2 and column v2, and e (u1,v1) =e (u1,v2) =e (u2,v1) =e (u2,v2) =1.

12. The method according to claim 5, characterized in that: In step (5f), the matrix H 2EX To perform the merge and share operation, traverse the H2 inverse XOR tree and expand the matrix H 2EX All elements, merged (u2,v1) and e (u2,v2) At the XOR gate, we get the H2 inverse XOR tree merge matrix H 2COM , which is expressed as follows: where e (u1,v2) Yes H 2EX The element in row u1 and column v2, e (u2,v1) Yes H 2EX The element at row u2 and column v1.

13. A high-throughput QC-LDPC encoding device that is adaptable to multiple types of codes, characterized in that: include: A serial-to-parallel conversion module, used to convert the input serial information sequence S into a parallel information sequence S′ and input it into the parallel-to-serial conversion module; H1 XOR tree module, used to perform XOR on the parallel information sequence S′ by row, generate an intermediate sequence qn with multiple code lengths and multiple code rates, and store it in the intermediate sequence register; H2 inverse XOR tree module, used to perform row-wise XOR on the intermediate sequence qn to generate a coding sequence pn with multiple code lengths and multiple code rates, and input it into the code type selector module; The code type selector module is used to select one of the coding sequences pn with multiple code lengths and multiple code rates, generate a check sequence p with a single code length and code rate, and input it into the parallel-to-serial conversion module; The parallel-to-serial conversion module is used to concatenate the parallel information sequence and the check sequence p, perform parallel-to-serial conversion, and output a coding sequence.

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