Audio data transmission method and device and computer readable storage medium

Abstract

The invention discloses an audio data transmission method and device, and a computer readable storage medium. The audio data transmission method comprises the following steps: acquiring a first audio data storage amount cached in a first first-in first-out buffer; and adjusting a first clock frequency of a first clock circuit based on the first audio data storage amount: when the first audio data storage amount is greater than a first target audio data storage amount, increasing the first clock frequency, the reading speed of the first audio hardware interface for reading the audio data from the first first-in first-out buffer is increased; and when the first audio data storage amount is smaller than the first target audio data storage amount, reducing the first clock frequency so as to reduce the reading speed of the first audio hardware interface. By adopting the scheme, low-delay audio data synchronous transmission can be realized.

Description

Technical Field

[0001] The present invention relates to the technical field of data processing, and in particular, to an audio data transmission method, an apparatus, and a computer-readable storage medium. Background Art

[0002] The system clocks of different electronic devices are difficult to keep completely consistent. When transmitting audio data between different devices, due to the inconsistent system clocks, it is difficult to achieve synchronous transmission of audio data between different devices.

[0003] In the prior art, when synchronizing different devices, it is necessary to process the audio data. Although synchronization can be achieved, the processing of the audio data will cause an increase in transmission delay and even cause the interruption of audio data transmission. Summary of the Invention

[0004] The purpose of the present invention is at least to provide an audio data transmission method that can achieve low-latency synchronous transmission of audio data.

[0005] In a first aspect, the present invention provides an audio data transmission method, including: obtaining the storage amount of first audio data cached in a first first-in-first-out buffer; adjusting a first clock frequency of a first clock circuit based on the storage amount of the first audio data, including: when the storage amount of the first audio data is greater than a first target audio data storage amount, increasing the first clock frequency to increase the reading speed of a first audio hardware interface for reading audio data from the first first-in-first-out buffer; when the storage amount of the first audio data is less than the first target audio data storage amount, decreasing the first clock frequency to decrease the reading speed of the first audio hardware interface.

[0006] Based on the storage amount of the first audio data cached in the first first-in-first-out buffer, the first clock frequency of the first clock circuit is adjusted, and further the reading speed of the first audio data interface is adjusted, so as to adjust the data flow in the first first-in-first-out buffer. When the storage amount of the first audio data is large, the reading speed of the first audio hardware interface is increased, thereby reducing the data storage amount in the first first-in-first-out buffer; when the storage amount of the first audio data is small, the reading speed of the first audio hardware interface is decreased, thereby increasing the data storage amount in the first first-in-first-out buffer. Thus, the data storage amount in the first first-in-first-out buffer can be stabilized within a range, the audio data can be kept continuous, and since there is no need to process the audio data, while achieving synchronous transmission of audio data, the transmission delay of the audio data is low.

[0007] Optionally, adjusting the first clock frequency of the first clock circuit based on the first audio data storage amount includes: adjusting the first clock frequency based on the first clock frequency, the first target audio data storage amount, the first audio data storage amount, and the audio data storage amount cached in the first first-in-first-out buffer when audio data was last received.

[0008] Optionally, the adjusted first clock frequency is: F t1 =F 1 +A 0 × (N t1 -N 1 ) +A 1 × (N 1 -N 21 ) ; where F t1 is the adjusted first clock frequency, F 1 is the first clock frequency, N t1 is the first target audio data storage amount, N 1 is the first audio data storage amount, N 21 is the audio data storage amount cached in the first first-in-first-out buffer when audio data was last received, A 0 is a preset first coefficient, A 1 is a preset second coefficient.

[0009] Optionally, the adjusted first clock frequency is: F t1 =F 1 +A 0 × (N t1 -N 1 ) +A 1 × (N 1 -N 21 ) +A 2 × △ 1 ; where F t1 is the adjusted first clock frequency, F 1 is the first clock frequency, N t1 is the first target audio data storage amount, N 1 is the first audio data storage amount, N 21 is the audio data storage amount cached in the first first-in-first-out buffer when audio data was last received, A 0 is a preset first coefficient, A 1 is a preset second coefficient, A 2 is a preset third coefficient, △ 1 is the cumulative data storage amount error of the first first-in-first-out buffer over a period of time.

[0010] Optionally, the value of the first target audio data storage amount is associated with the interference type; when the interference type is clock asynchronization, the value of the target audio data is a first value; when the interference type is clock asynchronization and there is a transmission delay in the input audio data, the value of the target audio data is a second value; the second value is greater than or equal to the first value.

[0011] Optionally, the audio data transmission method further includes: obtaining the storage amount of the second audio data cached in the second first-in-first-out buffer; based on the storage amount of the second audio data, adjusting the second clock frequency of the second clock circuit, including: when the storage amount of the second audio data is greater than the second target audio data storage amount, reducing the second clock frequency to reduce the writing speed of the second audio hardware interface for writing audio data to the second first-in-first-out buffer; when the storage amount of the second audio data is less than the second target audio data storage amount, increasing the second clock frequency to increase the writing speed of the second audio hardware interface.

[0012] Based on the storage amount of the second audio data cached in the second first-in-first-out buffer, the second clock frequency of the second clock circuit is adjusted, and then the writing speed of the second audio data interface is adjusted, thereby adjusting the data traffic in the second first-in-first-out buffer. When the storage amount of the second audio data is large, the writing speed of the second audio hardware interface is reduced, thereby reducing the data storage amount in the second first-in-first-out buffer; when the storage amount of the second audio data is small, the writing speed of the second audio hardware interface is increased, thereby increasing the data storage amount in the second first-in-first-out buffer. Thus, the data storage amount in the second first-in-first-out buffer can be stabilized within a range, the audio data can be kept continuous, and since there is no need to process the audio data, the transmission delay of the audio data is low while achieving audio data synchronization.

[0013] Optionally, the adjusting the second clock frequency of the second clock circuit based on the storage amount of the second audio data includes: adjusting the second clock frequency based on the second clock frequency, the second target audio data storage amount, the storage amount of the second audio data, and the storage amount of the audio data cached in the second first-in-first-out buffer when the previous input audio data was received.

[0014] Optionally, the adjusted second clock frequency is: F t2 =F 2 +B 0 ×(N t2 -N 2 )+B 1 ×(N 2 -N 22 );wherein, F t2is the adjusted second clock frequency, F 2 is the second clock frequency, N t2 is the second target audio data storage amount, N 2 is the second audio data storage amount, N 22 is the audio data storage amount cached in the second first-in-first-out buffer when sending audio data last time, B 0 is a preset fourth coefficient, B 1 is a preset fifth coefficient.

[0015] Optionally, the adjusted second clock frequency is: F t2 =F 2 +B 0 × (N t2 -N 2 ) +B 1 × (N 2 -N 22 ) +B 2 × △ 2 ; where F t2 is the adjusted second clock frequency, F 2 is the second clock frequency, N t2 is the second target audio data storage amount, N 2 is the second audio data storage amount, N 22 is the audio data storage amount cached in the second first-in-first-out buffer when sending audio data last time, B 0 is a preset fourth coefficient, B 1 is a preset fifth coefficient, B 2 is a preset sixth coefficient, △ 2 is the cumulative data storage amount error of the second first-in-first-out buffer within a period of time.

[0016] Optionally, the value of the second target audio data storage amount is associated with the interference type; when the interference type is clock asynchronization, the value of the target audio data is the third value; when the interference type is clock asynchronization and there is a transmission delay in the input audio data, the value of the target audio data is the fourth value; the fourth value is less than or equal to the third value.

[0017] Second aspect, the present invention further provides an audio data transmission device, including: a first first-in-first-out buffer adapted to buffer input audio data; a first processing module coupled to the first first-in-first-out buffer and adapted to obtain a first audio data storage amount buffered in the first first-in-first-out buffer; based on the first audio data storage amount, adjust a first clock frequency of a first clock circuit, including: when the first audio data storage amount is greater than a first target audio data storage amount, increase the first clock frequency; when the first audio data storage amount is less than the first target audio data storage amount, decrease the first clock frequency; the first clock circuit coupled to the first processing module and a first audio hardware interface and adapted to provide a clock signal with the first clock frequency for the first audio hardware interface; the first audio hardware interface coupled to the first first-in-first-out buffer and adapted to read buffered audio data from the first first-in-first-out buffer; a reading speed of the first audio hardware interface is positively correlated with the first clock frequency.

[0018] Optionally, the audio data transmission device further includes: a second first-in-first-out buffer adapted to buffer output audio data; a second processing module coupled to the second first-in-first-out buffer and adapted to adjust a second clock frequency of a second clock circuit based on a second audio data storage amount, including: when the second audio data storage amount is greater than a second target audio data storage amount, decrease the second clock frequency; when the second audio data storage amount is less than the second target audio data storage amount, increase the second clock frequency; the second clock circuit coupled to the second processing module and a second audio hardware interface and adapted to provide a clock signal with the second clock frequency for the second audio hardware interface; the second audio hardware interface coupled to the second first-in-first-out buffer and adapted to write audio data into the second first-in-first-out buffer; a writing speed of the second audio hardware interface is positively correlated with the second clock frequency.

[0019] Third aspect, the present invention further provides a computer-readable storage medium, which is a non-volatile storage medium or a non-transient storage medium, and has a computer program stored thereon. When the computer program is run by a processor, it executes the steps of any one of the above-mentioned audio data transmission methods. Description of the Drawings

[0020] Figure 1 is a flowchart of an audio data transmission method in an embodiment of the present invention;

[0021] Figure 2 is a schematic structural diagram of an audio data receiving module in an embodiment of the present invention;

[0022] Figure 3It is a flowchart of data transmission of an audio data receiving module in an embodiment of the present invention;

[0023] Figure 4 It is a waveform diagram of a first target clock frequency in an embodiment of the present invention;

[0024] Figure 5 is Figure 4 A waveform diagram of the first audio data storage amount corresponding to the first target clock frequency;

[0025] Figure 6 It is a schematic structural diagram of an audio data sending module in an embodiment of the present invention;

[0026] Figure 7 It is a flowchart of data transmission of an audio data sending module in an embodiment of the present invention;

[0027] Figure 8 It is a flowchart of another audio data transmission method in an embodiment of the present invention;

[0028] Figure 9 It is a waveform diagram of a second target clock frequency in an embodiment of the present invention;

[0029] Figure 10 is Figure 9 A waveform diagram of the second audio data storage amount corresponding to the second target clock frequency. Detailed implementation manners

[0030] In the prior art, when synchronizing audio data transmitted between different devices, it is necessary to process the audio data, such as processing the audio data by adding timestamps, inserting frames, and filling frames in the audio data. However, the processing of audio data will increase the transmission delay and even cause the interruption of audio data transmission.

[0031] In the embodiment of the present invention, the data storage amount in the first first-in-first-out buffer can be stabilized within a range, the audio data can be kept continuous, and since there is no need to process the audio data, the transmission delay of the audio data is relatively low.

[0032] To make the above objects, features, and beneficial effects of the present invention more obvious and understandable, the following detailed description of the specific embodiments of the present invention will be given with reference to the accompanying drawings.

[0033] The embodiment of the present invention provides an audio data transmission method, which will be described in detail through the following specific steps. Figure 1 as follows.

[0034] In an embodiment of the present invention, the audio data processing device may include an audio data sending module and / or an audio data receiving module, where: the audio data sending module may be configured to convert an audio signal into corresponding audio data and send the corresponding audio data to other audio devices; the audio data receiving module may receive the audio data sent by other audio devices, convert it into a corresponding audio signal and output it.

[0035] In a specific implementation, the above-mentioned audio data processing device may perform audio data transmission with other audio devices.

[0036] The number of other audio devices may be one or more. The audio data processing device may perform audio data transmission with one audio device, and while receiving a segment of audio data sent by the audio device, send another segment of audio data to the audio device. Alternatively, the audio data processing device may perform audio data transmission with multiple audio devices, send audio data to multiple audio devices, and receive the audio data sent by multiple audio devices.

[0037] Refer to Figure 2 , a schematic structural diagram of an audio data receiving module in an embodiment of the present invention is given. Refer to Figure 3 , a flowchart of data transmission of an audio data receiving module in an embodiment of the present invention is given. The following is described in conjunction with Figures 1 to 3 .

[0038] In a specific implementation, the audio data receiving module may include an audio data input interface, a first configuration information input interface, a first digital communication interface, a first first-in-first-out buffer, a first processing module, a first clock circuit, a first audio hardware interface, etc.

[0039] In an embodiment of the present invention, the data transmission process of the audio data receiving module may include the following steps:

[0040] Step 301, the audio data input interface receives audio data.

[0041] Step 302, the audio data input interface inputs the audio data to the first digital communication interface.

[0042] Step 303, the first communication digital interface inputs the audio data into the first first-in-first-out buffer.

[0043] Step 304, under the control of the first processing module, the first audio hardware interface converts the audio data stored in the first first-in-first-out buffer into an audio signal and outputs it.

[0044] In an embodiment of the present invention, the audio data transmission method provided in the following steps 101 to 102 can be executed by a first processing module in an audio data receiving module. In a specific implementation, the first processing module can be a chip or device with data processing capabilities, such as a microcontroller (MCU), a central processing unit (CPU), a digital signal processing (DSP) chip, etc.

[0045] Step 101, obtain the storage amount of the first audio data currently cached in the first first-in-first-out buffer.

[0046] In a specific implementation, the audio data receiving module can receive audio data (in digital signal format) sent by other audio devices. The received audio data is input to a first digital communication interface through an audio data input interface. The first digital communication interface inputs the received audio data into the first first-in-first-out buffer. The first processing module can communicate with the first first-in-first-out buffer to obtain the storage status of the first audio data currently cached in the first first-in-first-out buffer, that is, the storage amount of the first audio data currently cached in the first first-in-first-out buffer.

[0047] The first processing module can be coupled to a first clock circuit. The first clock circuit is coupled to a first audio hardware interface and provides a clock signal for the first audio hardware interface. The first audio hardware interface is coupled to the first first-in-first-out buffer and converts the audio data cached in the first first-in-first-out buffer into an audio signal and outputs it. The audio signal format output by the first audio hardware interface can be in digital signal format or in analog signal format.

[0048] Based on the clock signal provided by the first clock circuit, the first audio hardware interface reads the cached audio data from the first first-in-first-out buffer and converts the read audio data into an audio signal and outputs it.

[0049] In a specific implementation, the frequency of the clock signal output by the first clock circuit is positively correlated with the reading speed at which the first audio hardware interface reads audio data from the first first-in-first-out buffer. That is to say, the higher the frequency of the clock signal output by the first clock circuit, the faster the reading speed of the first audio hardware interface; conversely, the lower the frequency of the clock signal output by the first clock circuit, the slower the reading speed of the first audio hardware interface.

[0050] Step 102, adjust the first clock frequency of the first clock circuit based on the first audio data storage amount.

[0051] In an embodiment of the present invention, after obtaining the first audio data storage amount, the first processing module can adjust the first clock frequency of the first clock circuit based on the first audio data storage amount.

[0052] As can be seen above, since the reading speed of the first audio hardware interface is related to the first clock frequency, therefore, by adjusting the first clock frequency, the reading speed of the first audio hardware interface can be adjusted, thereby adjusting the storage amount of audio data cached in the first first-in-first-out buffer.

[0053] In a specific implementation, adjusting the first clock frequency may mean that: when the first audio data storage amount is greater than the first target audio data storage amount, the first clock frequency is increased; when the first audio data storage amount is less than the first target audio data storage amount, the first clock frequency is decreased.

[0054] By increasing the first clock frequency to accelerate the reading speed of the first audio hardware interface. When the input speed of inputting audio data to the first first-in-first-out buffer via the first digital communication interface remains unchanged, the increase in the reading speed of the first audio hardware interface can gradually reduce the storage amount of audio data cached in the first first-in-first-out buffer.

[0055] Correspondingly, by decreasing the first clock frequency to slow down the reading speed of the first audio hardware interface. When the input speed of inputting audio data to the first-in-first-out buffer via the first digital communication interface remains unchanged, the slowdown in the reading speed of the first audio hardware interface gradually increases the storage amount of audio data cached in the first first-in-first-out buffer.

[0056] That is to say, by adjusting the first clock frequency, the storage amount of audio data cached in the first first-in-first-out buffer can be gradually approximated to the first target audio data storage amount.

[0057] In the embodiment of the present invention, adjusting the first clock frequency based on the first audio data storage amount may specifically be:

[0058] Adjusting the first clock frequency based on the first clock frequency, the first target audio data storage amount, the first audio data storage amount, and the storage amount of audio data cached in the first first-in-first-out buffer when audio data was received last time.

[0059] In a specific implementation, the adjusted first clock frequency (hereinafter simply referred to as the first target clock frequency) is:

[0060] F t1 =F 1 +A 0 ×(N t1 -N 1 )+A 1 ×(N 1 -N 21 );(1)

[0061] Wherein, F t1is the first target clock frequency, F 1 is the first clock frequency, N t1 is the first target audio data storage capacity, N 1 is the first audio data storage capacity, N 21 is the audio data storage capacity cached in the first FIFO buffer when audio data was received last time, A 0 is a preset first coefficient (the influence coefficient of the first clock frequency on the first audio data storage capacity), A 1 is a preset second coefficient (the influence coefficient of the first clock frequency on the change speed of the first audio data storage capacity). When the audio data receiving module starts to work, N 1 has an initial value of 0, N 21 has an initial value of 0, A 0 has an initial value of the user - set value, A 1 has an initial value of the user - set value, F 1 has an initial value of the user - set value.

[0062] In the embodiment of the present invention, when adjusting the first clock frequency to adjust the audio data flow cached in the first FIFO buffer, there is a steady - state error. Considering the steady - state error, the first target clock frequency F t1 is:

[0063] F t1 = F 1 + A 0 × (N t1 - N 1 ) + A 1 × (N 1 - N 21 ) + A 2 × △ 1 ; (2)

[0064] wherein, A 2 is a preset third coefficient, △ 1 is the cumulative data storage capacity error of the first FIFO buffer within a period of time. When adjusting the first clock frequency each time, △ 1 will be added with the difference between the first target audio data storage capacity and the first audio data storage capacity, that is, (N t1 - N 1 ). When the audio data receiving module starts to work, A 2 has an initial value of the user - set value, and △ 1 has an initial value of 0.

[0065] In a specific implementation, the effect of A 0 on the audio data storage capacity cached in the first FIFO buffer is: making the first audio data storage capacity adjust towards the first target audio data storage capacity. A0 The larger the value of

[0066] A 1 is, the greater the adjustment amount is, and the less likely the first-in-first-out buffer is to overflow.

[0067] A 2 functions to eliminate the steady-state error generated when adjusting the audio data flow in the first-in-first-out buffer. The steady-state error is that when the first audio data storage amount remains unchanged for a long time, there is still a deviation between the first target audio data storage amount and the first audio data storage amount. The steady-state error is caused by the interference of other uncontrollable factors, such as interference encountered during communication with other audio devices.

[0068] In a specific implementation, A 0 、A 1 、A 2 are adjustable parameters. Users can configure the specific values of A 0 、A 1 、A 2 through the first configuration information input interface.

[0069] Referring to Figure 4 , a waveform diagram of a first target clock frequency in an embodiment of the present invention is given; referring to Figure 5 , a waveform diagram of the first audio data storage amount corresponding to the first target clock frequency is given. Figure 4 In Figure 4 , the abscissa is time, and the unit is second (s); the ordinate is the clock frequency, and the unit is kilohertz (KHz). Figure 5 In

[0070] As Figure 4 and Figure 5 shown, in the initial state, the first target clock frequency F t1 is less than the ideal first clock frequency, the first audio data storage amount is less than the first target audio data storage amount, and the reading speed of the audio data of the first audio hardware interface is less than the input speed of the audio data of the first digital communication interface. When the first target clock frequency is the ideal first clock frequency, the first audio data storage amount remains at the first target audio data storage amount.

[0071] When the first target clock frequency is F t1 =F 1 +A 0 × (Nt1 -N 1 When it is at (), the amplitude of the first target clock frequency is relatively large; and the first audio data storage amount oscillates on both sides of the first target audio data storage amount, and the amplitude of the first audio data storage amount is also relatively large.

[0072] When the first target clock frequency is F t1 =F 1 +A 0 ×(N t1 -N 1 )+A 1 ×(N 1 -N 21 )), the adjustment amplitude of the first audio data storage amount rapidly becomes smaller. Thus, by setting A 1 , it is possible to make the first audio data storage amount rapidly approach the first target audio data storage amount.

[0073] In a specific implementation, the above-mentioned first target audio data storage amount can be configured by the user through the first configuration information input interface. The first target audio data storage amount can be associated with the maximum audio data storage amount of the first first-in-first-out buffer. The above-mentioned maximum audio data storage amount can be configured by the user through the first configuration information input interface and is used to represent the maximum value of the audio data storage amount that the first first-in-first-out buffer can cache.

[0074] In the embodiment of the present invention, the value of the above-mentioned first target audio data storage amount can be associated with the interference type. The above-mentioned interference type is used to represent the interference existing during the communication process between the audio data receiving module and other audio devices.

[0075] If the interference type is clock asynchronization, the value of the first target audio data storage amount can be set to the first value; if the interference type is clock asynchronization and there is a transmission delay, the value of the first target audio data storage amount is set to the second value, and the second value can be greater than or equal to the first value.

[0076] In some embodiments, if the interference type is clock asynchronization, the first target audio data storage amount is set to 1 / 2 of the maximum audio data storage amount; if the interference is clock asynchronization and there is a transmission delay, the first target audio data storage amount is set to 3 / 4 of the maximum audio data storage amount.

[0077] In the embodiment of the present invention, the working state of the first digital communication interface and the working state of the first audio hardware interface will affect the running state of the audio data receiving module, and the association relationship among the three can be as shown in Table 1 below.

[0078]

[0079] Table 1

[0080] Operating state 1: When the first digital communication interface is in the closed state (i.e., unable to receive audio data) and the first audio hardware interface is in the closed state (i.e., not outputting audio data), the above audio data transmission method may not run.

[0081] Operating state 2: When the first digital communication interface is in the open state (i.e., able to receive audio data) and the first audio hardware interface is in the closed state, the first first-in-first-out buffer caches the input audio data. When the stored amount of audio data cached in the first first-in-first-out buffer reaches the first target audio data storage amount, the first audio hardware interface is turned on (i.e., the first audio hardware interface can read and output audio data from the first-in-first-out buffer). The operating state of the audio data receiving module changes to operating state 3. F will be initialized before the state change 1 、A 0 、A 1 、A 2 、N t1 、N 1 、N 21 、△ 1 。

[0082] Operating state 3: When the first digital communication interface is in the open state and the first audio hardware interface is in the open state, the first processing module can execute the above audio data transmission method.

[0083] Operating state 4: When the first digital communication interface is in the closed state (i.e., unable to receive audio data) and the first audio hardware interface is in the open state, the above audio data transmission method may no longer run. And, since the first audio hardware interface continuously obtains and outputs audio data from the first first-in-first-out buffer, when there is no cached audio data in the first first-in-first-out buffer, it means there is no audio data that needs to be continuously transmitted, so the first audio hardware interface can be turned off. The operating state of the audio data receiving module changes to operating state 1.

[0084] In an embodiment of the present invention, the user can, through the first configuration information input interface, configure the initial clock frequency and clock frequency adjustment range for the first clock circuit; configure the format of the output audio signal and the working state (including the open state and the closed state) of the first audio hardware interface to improve versatility.

[0085] The user can also, through the first configuration information input interface, configure the working states of the first digital communication interface and the first audio hardware interface to turn on / off the first digital communication interface and the first audio hardware interface. The user can also, through the first configuration information input interface, configure the digital communication protocol, data transmission speed, etc. of the first digital communication interface.

[0086] In an embodiment of the present invention, another audio data transmission method is further provided, which can be executed by an audio data sending module in an audio data processing device.

[0087] Refer to Figure 6 , a schematic structural diagram of an audio data sending module in an embodiment of the present invention is given. Refer to Figure 7 , a flowchart of data transmission of an audio data sending module in an embodiment of the present invention is given.

[0088] In a specific implementation, the audio data sending module may include an audio data sending interface, a second configuration information input interface, a second digital communication interface, a second first-in first-out buffer, a second processing module, a second clock circuit, a second audio hardware interface, etc.

[0089] In an embodiment of the present invention, the data transmission process of the audio data sending module may include the following steps:

[0090] Step 701, the second audio hardware interface converts an audio signal into audio data and inputs the audio data into the second first-in first-out buffer.

[0091] Step 702, the second digital communication interface obtains audio data from the second first-in first-out buffer.

[0092] Step 703, the second digital communication interface sends the audio data to other audio devices.

[0093] In a specific implementation, through the second processing module, the frequency of the clock signal output by the second clock circuit is adjusted to adjust the writing speed of the second audio hardware interface. Refer to Figure 8 , another audio data transmission method in an embodiment of the present invention is given, and the following is a detailed description through specific steps.

[0094] In an embodiment of the present invention, the audio data transmission method provided in the following steps 801 to 802 can be executed by the second processing module. The second processing module may be a chip or device with data processing capabilities, such as a microcontroller (MCU), a central processing unit (CPU), a digital signal processing (DSP) chip, etc.

[0095] In an embodiment of the present invention, the first processing module and the second processing module may be the same processing module in the audio data processing device, or two independent processing modules.

[0096] Step 801, obtain the current storage amount of the second audio data cached in the second first-in first-out buffer.

[0097] In a specific implementation, the audio data sending module can convert an audio signal into audio data and send the audio data (in digital signal format) to other audio devices. The audio data sending module can send the audio data to other audio devices through the audio data sending interface.

[0098] Specifically, the second audio hardware interface can convert the audio signal into corresponding audio data and input the audio data into the second first-in-first-out buffer. The audio signal format input by the second audio hardware interface can be in digital signal format or analog signal format.

[0099] The second audio hardware interface is coupled to the second clock circuit, and the second clock circuit provides a clock signal for the second audio hardware interface. The second audio hardware interface converts the audio signal based on the clock signal provided by the second clock circuit and inputs the converted audio data into the second first-in-first-out buffer. The frequency of the clock signal output by the second clock circuit is the second clock frequency.

[0100] In a specific implementation, the second processing module can communicate with the second first-in-first-out buffer to obtain the storage status of the second audio data currently cached in the second first-in-first-out buffer, that is, the storage amount of the second audio data currently cached in the second first-in-first-out buffer. The second processing module can also be coupled to the second clock circuit to control the adjustment of the second clock frequency.

[0101] In a specific implementation, the second clock frequency is positively correlated with the writing speed at which the second audio hardware interface writes audio data to the second first-in-first-out buffer.

[0102] That is to say, the higher the second clock frequency of the clock signal output by the second clock circuit, the faster the writing speed of the second audio hardware interface; conversely, the lower the frequency of the clock signal output by the second clock circuit, the slower the writing speed of the second audio hardware interface.

[0103] Step 802, adjust the second clock frequency of the second clock circuit based on the second audio data storage amount.

[0104] In an embodiment of the present invention, after obtaining the second audio data storage amount, the second processing module can adjust the second clock frequency of the second clock circuit based on the second audio data storage amount.

[0105] As can be seen above, since the writing speed of the second audio hardware interface is related to the second clock frequency, by adjusting the second clock frequency, the writing speed of the second audio hardware interface can be adjusted, thereby adjusting the audio data flow rate cached in the second first-in-first-out buffer.

[0106] In a specific implementation, adjusting the second clock frequency may mean that when the second audio data storage amount is greater than the second target audio data storage amount, the second clock frequency is decreased; when the second audio data storage amount is less than the second target audio data storage amount, the second clock frequency is increased.

[0107] By increasing the second clock frequency, the writing speed of the second audio hardware interface is accelerated. When the speed of sending audio data to other audio devices through the second digital communication interface remains unchanged, the increase in the writing speed of the second audio hardware interface can gradually increase the storage amount of audio data cached in the second first-in-first-out buffer.

[0108] Correspondingly, by decreasing the second clock frequency, the writing speed of the second audio hardware interface is slowed down. When the speed of sending audio data to other audio devices through the second digital communication interface remains unchanged, the decrease in the writing speed of the second audio hardware interface gradually reduces the storage amount of audio data cached in the second first-in-first-out buffer.

[0109] That is to say, by adjusting the second clock frequency, the storage amount of audio data cached in the second first-in-first-out buffer can gradually approach the second target audio data storage amount.

[0110] In the embodiment of the present invention, adjusting the second clock frequency based on the second audio data storage amount may specifically be:

[0111] Adjusting the second clock frequency based on the second clock frequency, the second target audio data storage amount, the second audio data storage amount, and the storage amount of audio data cached in the second first-in-first-out buffer when sending audio data to other audio devices last time.

[0112] In a specific implementation, the adjusted second clock frequency (hereinafter simply referred to as the second target clock frequency) is:

[0113] F t2 =F 2 +B 0 ×(N t2 -N 2 )+B 1 ×(N 2 -N 22 );(3)

[0114] Wherein, F t2 is the second target clock frequency, F 2 is the second clock frequency, N t2 is the second target audio data storage amount, N 2 is the second audio data storage amount, N 22is the storage amount of audio data cached in the second first-in-first-out buffer during the previous audio data transmission, B 0 is a preset fourth coefficient (the influence coefficient of the second clock frequency on the second audio data storage amount), B 1 is a preset fifth coefficient (the influence coefficient of the second clock frequency on the change speed of the second audio data storage amount). When the audio data sending module starts to work, N 2 has an initial value of 0, N 22 has an initial value of 0, B 0 has an initial value of the user-specified value, B 1 has an initial value of the user-specified value, F 2 has an initial value of the user-specified value.

[0115] In the embodiment of the present invention, when adjusting the second clock frequency to adjust the audio data flow cached in the second first-in-first-out buffer, there is a steady-state error. Considering the steady-state error, the target clock frequency can be determined as:

[0116] F t2 =F 2 +B 0 ×(N t2 -N 2 )+B 1 ×(N 2 -N 22 )+B 2 ×△ 2 ; (4)

[0117] wherein, B 2 is a preset sixth coefficient, △ 2 is the cumulative data storage amount error of the second first-in-first-out buffer within a period of time. Each time the second clock frequency is adjusted, △ 2 will be added with the difference between the second target audio data storage amount and the second audio data storage amount, that is, (N t2 -N 2 ). When the audio data sending module starts to work, B 2 has an initial value of the user-specified value, and △ 2 has an initial value of 0.

[0118] In specific implementation, the effect of B 0 on the audio data storage amount cached in the second first-in-first-out buffer is: making the second audio data storage amount adjust towards the second target audio data storage amount. The larger the value of B 0 , the greater the adjustment amount, and the less likely the second first-in-first-out buffer is to overflow.

[0119] B 1The function of the audio data storage amount cached in the second FIFO buffer is to reduce the change speed of the second audio data storage amount, so that the audio data storage amount in the second FIFO buffer remains stable.

[0120] B 2 The function is to eliminate the steady-state error generated when adjusting the audio data flow in the second FIFO buffer. The steady-state error is: when the second audio data storage amount remains unchanged for a long time, there is still a deviation between the second target audio data storage amount and the second audio data storage amount. The cause of the steady-state error is the interference of other uncontrollable factors, such as interference encountered during communication with other audio devices.

[0121] In a specific implementation, B 0 、B 1 、B 2 are adjustable parameters. Users can configure the specific values of B 0 、B 1 、B 2 through the second configuration information input interface.

[0122] Referring to Figure 9 , a waveform diagram of a second target clock frequency in an embodiment of the present invention is given; referring to Figure 10 , a waveform diagram of the second audio data storage amount corresponding to the second target clock frequency is given. Figure 9 In Figure 9 , the abscissa is time, with the unit of second (s); the ordinate is the clock frequency, with the unit of kilohertz (KHz). Figure 10 In

[0123] As Figure 9 and Figure 10 shown, in the initial state, the second target clock frequency F t2 is less than the ideal second clock frequency, the second audio data storage amount is less than the second target audio data storage amount, and the reading speed of the audio data of the second audio hardware interface is less than the input speed of the audio data of the second digital communication interface. When the second target clock frequency is the ideal second clock frequency, the second audio data storage amount remains at the second target audio data storage amount.

[0124] When the second target clock frequency is F t2 =F 2 +B 0 ×(N t2 -N 2 ), the amplitude of the second target clock frequency is larger; and the second audio data storage amount oscillates on both sides of the second target audio data storage amount, and the amplitude of the second audio data storage amount is also larger.

[0125] When the second target clock frequency is F t2 =F 2 +B 0 × (N t2 -N 2 ) +B 1 × (N 2 -N 22 ), the adjustment range of the second audio data storage amount rapidly becomes smaller. Thus, by setting B 1 , the second audio data storage amount can rapidly approach the second target audio data storage amount.

[0126] In a specific implementation, the above-mentioned second target audio data storage amount can be configured by the user through the second configuration information input interface. The second target audio data storage amount can be associated with the maximum audio data storage amount of the second first-in-first-out buffer. The above-mentioned maximum audio data storage amount can be configured by the user through the second configuration information input interface and is used to represent the maximum value of the audio data storage amount that the second first-in-first-out buffer can cache.

[0127] In the embodiments of the present invention, the value of the above-mentioned second target audio data storage amount can be associated with the interference type. The above-mentioned interference type is used to represent the interference existing during the communication process between the audio data sending module and other audio devices.

[0128] If the interference type is clock asynchronization, the value of the second target audio data storage amount can be set to a third value; if the interference type is clock asynchronization and there is a transmission delay, the value of the second target audio data storage amount is set to a fourth value, and the third value can be less than or equal to the fourth value.

[0129] In some embodiments, if the interference type is clock asynchronization, the second target audio data storage amount is set to 1 / 2 of the maximum audio data storage amount; if the interference is clock asynchronization and there is a transmission delay, the second target audio data storage amount is set to 1 / 4 of the maximum audio data storage amount.

[0130] In the embodiments of the present invention, the second digital communication interface and the second audio hardware interface will affect the operating state of the audio data sending module, as shown in Table 2 below.

[0131]

[0132] Table 2

[0133] Operating state 5: When the second digital communication interface is in a closed state (i.e., unable to send audio data), and the second audio hardware interface is in a closed state (i.e., does not convert the input audio signal), the above-mentioned audio data transmission method may not run.

[0134] Operating state 6: When the second digital communication interface is in the closed state and the second audio hardware interface is in the open state (i.e., capable of converting the input audio signal), the second first-in-first-out buffer caches the audio data output by the second audio hardware interface. When the storage amount of the audio data cached in the second first-in-first-out buffer reaches the second target audio data storage amount, the second processing module can control to turn on the second digital communication interface (i.e., the second digital communication interface can send audio data). The operating state of the audio data sending module changes to operating state 7. F will be initialized before the state change. 2 、B 0 、B 1 、B 2 、N t2 、N 2 、N 22 、△ 2 。

[0135] Operating state 7: When the second digital communication interface is in the open state and the second audio hardware interface is in the open state, the second processing module can execute the audio data transmission method provided in the above step 801 to step 802.

[0136] Operating state 8: When the second digital communication interface is in the open state and the second audio hardware interface is in the closed state, the above audio data transmission method can stop running. And, since the second digital communication interface continuously obtains and outputs the audio data from the second first-in-first-out buffer, when there is no cached audio data in the second first-in-first-out buffer, it means that there is no audio data that needs to be continuously transmitted, so the second digital communication interface can be turned off. The operating state of the audio data sending module changes to operating state 5.

[0137] In the embodiment of the present invention, the user can, through the second configuration information input interface, configure the initial clock frequency and the clock frequency adjustment range for the second clock circuit; configure the format of the output audio signal and the working state (including the open state and the closed state) of the second audio hardware interface, so as to improve the versatility.

[0138] The user can also, through the second configuration information input interface, configure the working states of the second digital communication interface and the second audio hardware interface to turn on / off the second digital communication interface and the second audio hardware interface. The user can also, through the second configuration information input interface, configure the digital communication protocol, data transmission speed, etc. of the second digital communication interface.

[0139] In the embodiment of the present invention, the above step 101 to step 102 and step 801 to step 802 can be independent steps, and there may not be an inevitable logical sequence relationship between the two sets of steps.

[0140] As can be seen from the above, in the embodiment of the present invention, based on the storage amount of the first audio data cached in the first first-in-first-out buffer, the first clock frequency of the first clock circuit is adjusted, and then the reading speed of the first audio data interface is adjusted, so as to adjust the data flow in the first first-in-first-out buffer. When the storage amount of the first audio data is large, the reading speed of the first audio hardware interface is increased, thereby reducing the data storage amount in the first first-in-first-out buffer; when the storage amount of the first audio data is small, the reading speed of the first audio hardware interface is reduced, thereby increasing the data storage amount in the first first-in-first-out buffer. Thus, the data storage amount in the first first-in-first-out buffer can be stabilized within a range, the audio data can be kept continuous, and since there is no need to process the audio data, the transmission delay of the audio data is low.

[0141] Correspondingly, based on the storage amount of the second audio data cached in the second first-in-first-out buffer, the second clock frequency of the second clock circuit is adjusted, and then the writing speed of the second audio data interface is adjusted, so as to adjust the data flow in the second first-in-first-out buffer. When the storage amount of the second audio data is large, the writing speed of the second audio hardware interface is reduced, thereby reducing the data storage amount in the second first-in-first-out buffer; when the storage amount of the second audio data is small, the writing speed of the second audio hardware interface is increased, thereby increasing the data storage amount in the second first-in-first-out buffer. Thus, the data storage amount in the second first-in-first-out buffer can be stabilized within a range, the audio data can be kept continuous, and since there is no need to process the audio data, the transmission delay of the audio data is low.

[0142] The embodiment of the present invention also provides a computer-readable storage medium, which is a non-volatile storage medium or a non-transitory storage medium, on which a computer program is stored. When the computer program is run by a processor, it executes the steps of the audio data transmission method provided in any one of the above embodiments.

[0143] Those of ordinary skill in the art can understand that all or part of the steps in the various methods of the above embodiments can be completed by a program instructing relevant hardware. The program can be stored in a computer-readable storage medium, and the storage medium can include: ROM, RAM, magnetic disk or optical disc, etc.

[0144] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.

Claims

1. An audio data transmission method, characterized in that: include: Obtaining a storage amount of first audio data cached in a first first-in-first-out buffer; Adjusting a first clock frequency of a first clock circuit based on the first audio data storage amount includes: when the first audio data storage amount is greater than a first target audio data storage amount, increasing the first clock frequency to increase a reading speed of the first audio hardware interface reading audio data from the first first-in-first-out buffer; When the first audio data storage capacity is less than the first target audio data storage capacity, the first clock frequency is reduced to reduce a reading speed of the first audio hardware interface.

2. The audio data transmission method according to claim 1, characterized in that: The adjusting the first clock frequency of the first clock circuit based on the first audio data storage amount includes: The first clock frequency is adjusted based on the first clock frequency, the first target audio data storage capacity, the first audio data storage capacity, and the audio data storage capacity cached in the first first-in-first-out buffer when audio data was last received.

3. The audio data transmission method according to claim 2, characterized in that: The adjusted first clock frequency is: F t1 =F1+A0×(N t1 -N1)+A1×(N1-N 21 ); Among them, F t1 is the adjusted first clock frequency, F1 is the first clock frequency, N t1 is the first target audio data storage capacity, N1 is the first audio data storage capacity, N 21 is the storage amount of audio data cached in the first FIFO buffer when audio data was received last time, A0 is a preset first coefficient, and A1 is a preset second coefficient.

4. The audio data transmission method according to claim 2, characterized in that: The adjusted first clock frequency is: F t1 =F1+A0×(N t1 -N1)+A1×(N1-N 21 )+A2×△1; Among them, F t1 is the adjusted first clock frequency, F1 is the first clock frequency, N t1 is the first target audio data storage capacity, N1 is the first audio data storage capacity, N 21 is the amount of audio data stored in the first FIFO buffer when the audio data was received last time, A0 is a preset first coefficient, A1 is a preset second coefficient, A2 is a preset third coefficient, and △1 is the cumulative data storage error of the first FIFO buffer over a period of time.

5. The audio data transmission method according to claim 1, characterized in that: The value of the first target audio data storage amount is associated with the interference type; when the interference type is clock asynchrony, the value of the target audio data is a first value; when the interference type is clock asynchrony and there is a transmission delay in the input audio data, the value of the target audio data is a second value; the second value is greater than or equal to the first value.

6. The audio data transmission method according to any one of claims 1 to 5, characterized in that: Also includes: Obtaining a storage amount of second audio data cached in a second first-in-first-out buffer; Adjusting the second clock frequency of the second clock circuit based on the second audio data storage capacity includes: when the second audio data storage capacity is greater than the second target audio data storage capacity, reducing the second clock frequency to reduce the writing speed of the second audio hardware interface writing audio data to the second first-in first-out buffer; When the second audio data storage capacity is less than the second target audio data storage capacity, the second clock frequency is increased to increase the writing speed of the second audio hardware interface.

7. The audio data transmission method according to claim 6, characterized in that: The adjusting the second clock frequency of the second clock circuit based on the storage amount of the second audio data includes: The second clock frequency is adjusted based on the second clock frequency, the second target audio data storage capacity, the second audio data storage capacity, and the audio data storage capacity cached in the second first-in-first-out buffer when audio data was last input.

8. The audio data transmission method according to claim 7, characterized in that: The adjusted second clock frequency is: F t2 =F2+B0×(N t2 -N2)+B1×(N2-N 22 ); Among them, F t2 is the adjusted second clock frequency, F2 is the second clock frequency, N t2 is the second target audio data storage capacity, N2 is the second audio data storage capacity, N 22 is the storage amount of audio data cached in the second FIFO buffer when the audio data was sent last time, B0 is the preset fourth coefficient, and B1 is the preset fifth coefficient.

9. The audio data transmission method according to claim 7, characterized in that: The adjusted second clock frequency is: F t2 =F2+B0×(N t2 -N2)+B1×(N2-N 22 )+B2×△2; Among them, F t2 is the adjusted second clock frequency, F2 is the second clock frequency, N t2 is the second target audio data storage capacity, N2 is the second audio data storage capacity, N 22 is the amount of audio data stored in the second first-in-first-out buffer when the audio data was sent last time, B0 is the preset fourth coefficient, B1 is the preset fifth coefficient, B2 is the preset sixth coefficient, and △2 is the cumulative data storage error of the second first-in-first-out buffer over a period of time.

10. The audio data transmission method according to claim 6, characterized in that: The value of the second target audio data storage amount is associated with the interference type; when the interference type is clock asynchrony, the value of the target audio data is a third value; when the interference type is clock asynchrony and there is a transmission delay in the input audio data, the value of the target audio data is a fourth value; the fourth value is less than or equal to the third value.

11. An audio data transmission device, characterized in that: include: A first first-in first-out buffer, adapted to buffer input audio data; a first processing module, coupled to the first FIFO buffer, adapted to obtain the amount of first audio data stored in the first FIFO buffer; Based on the first audio data storage capacity, adjusting the first clock frequency of the first clock circuit includes: when the first audio data storage capacity is greater than the first target audio data storage capacity, increasing the first clock frequency; when the first audio data storage capacity is less than the first target audio data storage capacity, decreasing the first clock frequency; The first clock circuit is coupled to the first processing module and the first audio hardware interface, and is adapted to provide a clock signal of a first clock frequency to the first audio hardware interface; The first audio hardware interface is coupled to the first first-in-first-out buffer and is suitable for reading cached audio data from the first first-in-first-out buffer; the reading speed of the first audio hardware interface is positively correlated with the first clock frequency.

12. The audio data transmission device according to claim 11, characterized in that: Also includes: A second first-in first-out buffer, adapted to buffer output audio data; A second processing module is coupled to the second FIFO buffer and is adapted to adjust the second clock frequency of the second clock circuit based on the second audio data storage capacity, including: when the second audio data storage capacity is greater than the second target audio data storage capacity, reducing the second clock frequency; when the second audio data storage capacity is less than the second target audio data storage capacity, increasing the second clock frequency; The second clock circuit is coupled to the second processing module and the second audio hardware interface, and is adapted to provide a clock signal of a second clock frequency for the second audio hardware interface; The second audio hardware interface is coupled to the second FIFO buffer and is suitable for writing audio data into the second FIFO buffer; the writing speed of the second audio hardware interface is positively correlated with the second clock frequency.

13. A computer-readable storage medium, wherein the computer-readable storage medium is a non-volatile storage medium or a non-transient storage medium, and a computer program is stored thereon, wherein: When the computer program is executed by a processor, the steps of the audio data transmission method according to any one of claims 1 to 10 are executed.

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