One-step timestamp in network devices

Abstract

A media access control (MAC) processor of a network device receives a timing packet to be transmitted by the network device. The MAC processor generates one or more indicators to be used by a physical layer (PHY) device of the network device to embed timing information in the timing packet. The one or more indicators include at least an indicator indicating that the timing packet is a type of packet in which the timing information is to be embedded, an indicator of the location of a field in the timing packet in which the timing information is to be embedded, and an indicator of whether the timing information in the timing packet is to be updated. The MAC processor transmits the timing packet and the one or more indicators to the PHY device for further processing of the timing packet and subsequent transmission of the timing packet from the network device.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of U.S. Provisional Patent Application No. 62 / 993,524, filed on March 23, 2020, entitled “1-Step PTP Time-Stamping Over USXGMII / USGMII Interfaces,” the disclosure of which is expressly incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates generally to communication networks, and more particularly to timestamping packets in network devices. Background Art

[0004] Clock synchronization protocols are commonly used in packet-based networks to synchronize clocks maintained at different network devices. In such clock synchronization protocols, a first network device, maintaining a master clock, transmits a timing packet containing a transmission timestamp generated based on the master clock's time to a second network device, maintaining a slave clock. The second network device uses the timing packet's transmission timestamp and estimated network delay to adjust the slave clock to synchronize it with the master clock. In a two-step timestamp scenario, a timestamp corresponding to the transmission time of the timing packet is transmitted in a subsequent packet. Because the timestamp corresponding to the timing packet is transmitted in the subsequent packet, a two-step timestamp system does not require hardware "on-the-fly" timestamp embedding into the packet. However, two-step timestamps require the transmission of additional packets, which increases overhead and, in at least some cases, can affect network throughput. Furthermore, two-step timestamps require that the subsequent packet match the corresponding timing packet at the second network device, which increases implementation complexity and can sometimes lead to synchronization errors when the matching is not performed correctly.

[0005] Some systems utilize a one-step timestamping mechanism, in which a timestamp corresponding to the transmission time of a timing packet is dynamically embedded in the timing packet as the packet is transmitted from the network device. One-step timestamping eliminates some of the inefficiencies and complexities associated with two-step timestamping, but one-step timestamping typically increases the hardware requirements, cost, and power consumption of the physical layer modules in the network device because the network device typically needs to perform parsing and timing calculation operations on the packet at line speed in order to dynamically embed the timestamp or other timing information in the timing packet as it is transmitted from the network device. Summary of the Invention

[0006] In one embodiment, a method for processing timing packets in a network device for synchronizing the network device comprises: receiving, at a media access control (MAC) processor of the network device, a timing packet to be transmitted by the network device; performing, by the MAC processor, initial processing of the timing packet, including generating one or more indicators of one or more parameters to be used by a PHY device of the network device for embedding timing information in the timing packet, the one or more indicators comprising at least i) an indicator indicating that the timing packet is a type of packet into which the timing information is to be embedded by the PHY device, ii) an indicator of a position of a field in the timing packet at which the timing information is to be embedded in the timing packet by the PHY device, and iii) an indicator of whether the timing information in the timing packet needs to be updated by the PHY device; and transmitting i) the timing packet and ii) the one or more indicators from the MAC processor to the PHY device for further processing of the timing packet based on the one or more indicators and subsequent transmission of the timing packet from the network device.

[0007] In another embodiment, a network device configured to operate in a network includes a media access control (MAC) processor, the MAC processor being configured to: receive a timing packet to be transmitted by the network device; generate one or more indicators of one or more parameters to be used by a PHY device of the network device for embedding timing information in the timing packet, the one or more indicators including at least i) an indicator indicating that the timing packet is a type of packet into which the timing information is to be embedded by the PHY device, ii) an indicator of a position of a field in the timing packet at which the timing information is to be embedded in the timing packet by the PHY device, and iii) an indicator of whether the timing information in the timing packet needs to be updated by the PHY device; and transmit i) the timing packet and ii) the one or more indicators to the PHY device for further processing of the timing packet based on the one or more indicators and subsequent transmission of the timing packet from the network device.

[0008] In yet another embodiment, a network device configured to operate in a network includes a media access control (MAC) processor coupled to a physical layer (PHY) device, wherein the MAC processor is configured to: receive a timing packet to be transmitted by the network device; generate one or more indicators of one or more parameters to be used by the PHY device of the network device for embedding timing information in the timing packet, the one or more indicators including at least i) an indicator indicating that the timing packet is a type of packet into which the PHY device is to embed timing information, ii) an indicator of a position of a field in the timing packet at which the PHY device is to embed timing information in the timing packet, and iii) an indicator of whether the timing information in the timing packet needs to be updated by the PHY device; and transmit i) the timing packet and ii) the one or more indicators to the PHY device. The PHY device is configured to: receive i) the timing packet from the MAC processor and ii) the one or more indicators from the MAC processor; embed timing information in the timing packet based on the one or more indicators; and forward the timing packet to one or more network ports of the network device for transmission of the timing packet from the network device.

[0009] In another embodiment, a method for embedding timing information in a timing packet to be transmitted by a network device includes: receiving, at a physical layer (PHY) device of the network device, a timing packet to be transmitted by the network device, the timing packet including initial timing information provided by one or both of i) a media access control (MAC) processor and ii) a host processor of the network device; receiving, at the PHY device, from the MAC processor, one or more indicators of one or more parameters to be used by the PHY device for embedding the timing information in the timing packet, the one or more indicators including at least i) an indicator indicating that the timing packet is a type of packet into which the PHY device is to embed the timing information, ii) an indicator of a position of a field in the timing packet at which the timing information is to be embedded in the timing packet by the PHY device, and iii) an indicator of whether the timing information in the timing packet needs to be updated by the PHY device; updating, by the PHY device, the initial timing information in the timing packet based on the one or more indicators to embed final timing information in the timing packet; and forwarding, by the PHY device, the timing packet to one or more network ports of the network device for transmission of the timing packet from the network device.

[0010] In another embodiment, a network device configured to operate in a network includes a physical layer (PHY) device processor configured to: receive a timing packet to be transmitted by the network device, the timing packet including initial timing information provided by one or both of i) a media access control (MAC) processor and ii) a host processor of the network device; receive one or more indicators of one or more parameters to be used by the PHY device for embedding the timing information in the timing packet, the one or more indicators including at least i) an indicator indicating that the timing packet is a type of packet into which the timing information is to be embedded by the PHY device, ii) an indicator of a position of a field in the timing packet at which the timing information is to be embedded in the timing packet by the PHY device, and iii) an indicator of whether the timing information in the timing packet needs to be updated by the PHY device; update the initial timing information in the timing packet based on the one or more indicators to embed final timing information in the timing packet; and forward the timing packet to one or more network ports of the network device for transmission of the timing packet from the network device. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a block diagram of an example network device configured to generate and / or update timing packets to allow one or more other devices in the network to synchronize with a master clock in the network, according to one embodiment.

[0012] Figure 2 According to one embodiment, Figure 1 A diagram of timing packets generated and / or updated by network devices.

[0013] Figure 3A-3B is inserted according to various embodiments Figure 2 Figure 2 shows a control header in a timing packet.

[0014] Figure 4 According to one embodiment Figure 3B Figure 2 shows a diagram of the physical layer (PHY) tags included in the control header of a UDP packet.

[0015] Figure 5 is a flow chart illustrating an example method for processing timing packets in a network device for synchronizing the network device, according to one embodiment.

[0016] Figure 6 is a flow chart illustrating an example method for embedding timing information in timing packets to be transmitted by a network device, according to one embodiment. DETAILED DESCRIPTION

[0017] In an embodiment described below, a network device includes a physical layer (PHY) processor configured to implement one-step timestamping of timing packets by dynamically embedding timing information corresponding to the timing packets as the timing packets are transmitted from the network device. In one embodiment, one or more higher-level processors of the network device (such as a media access control (MAC) processor and / or a host processor) are configured to perform a portion of the operations associated with embedding timestamps into packets, such as embedding initial timing information into the timing packets, and providing one or more tags containing relevant information to the PHY device so that the PHY device can dynamically and efficiently embed final timing information into the timing packets as the timing packets are transmitted from the network device. For example, in one embodiment, the host processor of the network device is configured to set a timestamp field and a correction field in the timing packets to indicate an initial time corresponding to a transmission time of the timing packets from the network device. As another example, the MAC processor of the network device is configured to update a correction field in the timing packets to set the correction field to an initial value corresponding to a residence time of the timing packets in the network device.

[0018] In one embodiment, the MAC processor is configured to, when transmitting a timing packet to a PHY device, also provide one or more indicators of one or more parameters to be used by the PHY device for embedding timing information in the timing packet. In one embodiment, the one or more indicators or tags indicate to the PHY device at least: i) the type of packet into which the timing packet is to be embedded by the PHY device, ii) the location of a field in the timing packet at which the timing information is to be embedded in the timing packet by the PHY device, and iii) whether the timing information in the timing packet needs to be updated by the PHY device. As a more specific example, in one embodiment, the MAC processor is configured to provide to the PHY device an indicator of the location of a correction field in the timing packet. As another example, in one embodiment, the MAC processor is configured to provide to the PHY device an indicator of whether a checksum trailer field in the timing packet needs to be updated by the PHY device. The PHY device is configured to utilize the one or more indicators provided by the MAC processor to embed the timing information in the timing packet. For example, the PHY device is configured to utilize one or more indicators to quickly locate and update the correction field in the timing packet to reflect the accurate transmission time of the timing packet from the network device or the accurate residence time of the timing packet in the network device, to determine whether the checksum tail field needs to be updated, and if so, to quickly update the checksum tail field, etc.

[0019] Performing initial processing and timestamping of timing packets at the MAC and / or host processor of a network device, and providing relevant information for ultimately embedding timing information into timing packets to a PHY device of the network device enables the PHY device to dynamically, efficiently, and accurately embed timing information into timing packets as packets are transmitted from the network device, utilizing the hardware and / or processing capabilities of the MAC and / or host processor (which may be necessary for the MAC and / or host processor to perform general MAC and / or host processing operations) to perform operations associated with timestamping packets, and facilitating a reduction in hardware and corresponding reduction in power consumption, cost, etc., of a PHY device that performs one-step type timestamping (where timestamp information is embedded into outgoing packets) as compared to a system in which the PHY device is configured to dynamically embed timing information into timing packets without relevant information being provided from the MAC processor and / or the MAC processor and / or host processor does not embed initial timing information into timing packets.

[0020] Figure 1 is a block diagram of an example network device 100 according to one embodiment, the network device 100 being configured to transmit time-stamped packets in a network to allow one or more other devices to synchronize with a master clock in the network. The network device 100 is configured to operate according to a synchronization protocol for timing synchronization. In one embodiment, the network device 100 is configured to operate according to the Institute of Electrical and Electronics Engineers (IEEE) 1588 standard (commonly referred to as the "Precision Time Protocol" or "PTP"). The network device 100 is configured to operate according to another synchronization protocol, such as the Network Time Protocol (NTP) or another suitable synchronization protocol. In one embodiment, the network device 100 is configured to implement one-step timestamping. In this embodiment, the network device 100 is configured to dynamically embed timing information corresponding to the transmission time of the timing packets directly into the timing packets as the timing packets are transmitted from the network device 100.

[0021] In various embodiments, the network device 100 is configured to operate as: an ordinary clock device that implements a master clock or a slave clock on the network, a boundary clock device that synchronizes with a master clock and relays the master clock to one or more slave devices on the network, or a transparent clock as an intermediate device that is configured to relay system dwell time from a master device to one or more slave devices on the network. Generally, in various embodiments, the network device 100 is configured to generate timing packets and / or update timing information in received timing packets, and transmit timing packets to one or more other devices on the network to allow the one or more other devices to synchronize with the master clock on the network. As used herein, the term "timing packet" refers to a network data packet that includes a timing message generated and transmitted by a network device in a network and used to direct time-related processes in the network, such as clock synchronization between network devices in the network.

[0022] The network device 100 includes one or more network ports 104 configured to be coupled to corresponding one or more network links 106 to couple the network device 100 to one or more other devices in the network. In one embodiment, the network device 100 also includes one or more physical layer (PHY) processors 108 coupled to the one or more network ports 104. Although the network device 100 is Figure 1 104, but in some embodiments, the network device 100 includes a PHY device 108 coupled to multiple (e.g., all) network ports 104. In another embodiment, the network device 100 is a single-port device that includes only a single PHY device 108 coupled to a single port 104. For the sake of brevity, one or more PHY devices 106 are sometimes referred to herein as "a PHY device 108."

[0023] In various embodiments, PHY device 108 includes one, or any suitable combination of two or more, of a digital-to-analog converter (DAC), an amplifier, a modulator, and the like (not shown) to convert digital signals corresponding to packets into analog signals suitable for transmission via communication link 106. PHY device 108 also includes one or more timing modules configured to implement timing synchronization operations. For example, in one embodiment, PHY device 108-1 includes an egress timing module 110, and PHY device 108-2 includes an ingress timing module 112. In one embodiment, egress timing module 110 of PHY device 108-1 is configured to embed timing information based on a clock maintained by PHY clock 113 into timing packets, the timing information corresponding to the transmission time of the timing packets from network device 100. In one embodiment, ingress timing module 112 of PHY device 108-2 is configured to generate a timestamp for received timing packets based on the clock maintained by PHY clock 113, the timestamp corresponding to the time the timing packets were received by network device 100. In another embodiment, PHY device 108-1 and PHY device 108-2 are independent entities that maintain respective PHY clocks 113. In some such embodiments, a suitable clock synchronization mechanism is employed to synchronize the respective PHY clocks 113.

[0024] In one embodiment, the egress timing module 110 and the ingress timing module 112 are implemented in hardware configured to perform dynamic operations at line speed. For example, in one embodiment, the egress timing module 110 of the PHY device 108-1 is configured to dynamically embed timing information corresponding to the transmission time of the packet as the packet is transmitted from the network device 100. In one embodiment, the ingress timing module 112 is configured to dynamically generate a timestamp for the packet as the packet is received by the network device 100. Although the PHY device 108-1 is Figure 1 is shown as including an egress timing module, and the PHY device 108-2 ... Figure 1 1 as including an ingress timing module, but in one embodiment, the PHY device 108 includes both an egress timing module configured to embed timing information in packets transmitted from the network device 100 and an ingress timing module configured to generate time stamps for packets received by the network device 100.

[0025] In one embodiment, the network device 100 further includes a media access control (MAC) processor 114 and a host processor 116. In one embodiment, the MAC processor 114 is implemented using one or more integrated circuits (e.g., one or more application-specific integrated circuits (ASICs)). In one embodiment, the host processor 116 is or is implemented by a processing unit such as a central processing unit (CPU) of the network device 100. In one embodiment, the host processor 116 is configured to implement computer-readable instructions stored in a memory (not shown) of the network device 100. The MAC processor 114 is coupled to the one or more PHY devices 108 and the host processor 116. In one embodiment, the MAC processor is configured to receive packets from the one or more PHY devices 108, perform MAC operations on the packets received from the one or more PHY devices 108, such as parsing and decapsulating the packets, and transmit the packets to the host processor 116 for further processing. In one embodiment, the MAC processor 114 is further configured to receive packets from the host processor 116, perform MAC operations on the packets received from the host processor 116, such as encapsulating the packets with one or more protocol headers, and pass the packets to the appropriate one or more PHY devices 108 for transmission from the network device 100. As will be discussed in more detail below, in various embodiments, the MAC processor 114 is configured to perform initial processing of timing packets and provide one or more indicators or tags to a PHY device (e.g., PHY device 108-2) containing relevant information for updating initial timing information in the timing packets by the PHY device.

[0026] In embodiments and / or scenarios in which network device 100 operates as a normal clock device or a boundary clock device, host processor 116 is configured to generate timing packets originating from network device 100. In one embodiment, network device 100 includes or implements a timing module 118, which is configured to generate timing packets for transmission from network device 100. In one embodiment, timing module 118 is configured to generate timing packets to include initial timing information indicating a transmission time of the timing packets. In one embodiment, the initial timing information is determined based on a host clock 120 maintained by host processor 116. In one embodiment, timing module 118 is configured to set a timestamp field in the timing packets generated by timing module 118 to the current value of host clock 120 maintained by host processor 116. Timing module 118 is also configured to set a correction field in the timing packets to the initial correction value to compensate for the transmission delay of the current value of host clock 120 that the timing packets are expected to experience between the current time and the time the timing packets are actually transmitted from network device 100. The host processor is configured to transmit the timing packets to MAC processor 114. The MAC processor 114 is configured to, in turn, communicate the timing packets to the appropriate PHY device 108 for transmission of the packet from the network port 104 of the network device 100 .

[0027] In one embodiment, host clock 120, used by host processor 116 to generate initial timing information for timing packets, is less accurate than PHY clock 113. For example, in one embodiment, host clock 120 maintains the time of day with an accuracy of one millisecond or a few milliseconds, while PHY clock 113 maintains the time of day with an accuracy of one nanosecond or a few nanoseconds. As will be explained in greater detail below, upon transmission of a timing packet from network device 100, the correction field of the timing packet is subsequently updated by the egress timing module in PHY device 108 based on PHY clock 113. In at least some embodiments, updating the correction field by PHY device 108 based on PHY clock 113 can compensate for inaccuracies in host clock 120.

[0028] Continue to refer Figure 1In embodiments and / or scenarios in which the network device 100 operates as a transparent clock device, the PHY device 108 is configured to receive a timing packet received by the network device 100 via the first network port 104, timestamp the timing packet with an ingress time of the timing packet, and transmit the timing packet along with the timestamp to the MAC processor 114. The MAC processor 114 is configured to process the timing packet, locate a correction field with the timing packet, and update the correction field in the timing packet to reflect the residence time of the timing packet in the network device 100. The MAC processor 114 is configured to then transmit the timing packet to the appropriate PHY device 108 for transmission of the timing packet from the second network port 104 of the network device 100.

[0029] Still refer to Figure 1 , MAC processor 114 is shown transmitting timing packet 119 to PHY device 108-2. In one embodiment, timing packet 119 is an Ethernet packet, for example, as a User Datagram Protocol (UDP) packet over Internet Protocol version 6 (IPv6). In another embodiment, timing packet 119 is another suitable type of packet, such as UDP or a Data Link (L2) layer protocol packet over Internet Protocol version 6 (IPv4). Timing packet 119 includes timing message 122. In one embodiment, timing message 122 is a PTP message, such as a PTP Synchronization (Sync) message or a PTP Delay Request message. In other embodiments, timing message 122 is another suitable type of timing message. In one embodiment, timing packet 119 is a timing packet generated by timing module 118 of host processor 116. In another embodiment, timing module 116 generates timing message 122, and MAC processor 114 encapsulates timing message 122 with one or more protocol headers, labels, etc. to generate timing packet 119. In another embodiment, the timing packet 119 is a timing packet received by the MAC processor 114 from the PHY device 108 .

[0030] Brief Reference Figure 2In one embodiment, example timing message 200 corresponds to timing message 122. In another embodiment, timing message 122 is different from timing message 200. Timing message 200 includes a header 202 and a data portion 204. In one embodiment, header 202 includes a correction field 206. In some embodiments, header field 202 includes one or more other fields in addition to correction field 206. Data portion 204 includes a timestamp field 208. In some embodiments, data portion 204 includes one or more other fields in addition to timestamp field 206. For example, data portion 206 includes a checksum trailer field 210, such as a UDP trailer field or another type of checksum trailer field. In some embodiments, data portion 204 omits the checksum trailer field.

[0031] Now refer to Figure 1 and Figure 2 In embodiments where the timing message 122 is generated by the host processor 116, such as in embodiments where the network device 100 operates as an ordinary clock or boundary clock device, in one embodiment, the timing module 118 of the host processor 116 sets the timestamp field 208 of the timing message 122 to the current value of the host clock 120. The timing module 118 also optionally generates a correction field value for the timing message 122 and sets the correction field 206 of the timing message 122 to the generated correction field value. In one embodiment, the timing module 118 generates the correction field value to be equal to the negative of the nanosecond portion of the timestamp in the timestamp field 208, so that the nanosecond portion of the timestamp can be subsequently updated by the PHY device 108 based on the PHY clock 113 upon transmission of the timing packet 119 from the network device 100. In one embodiment, the timing module 118 also adds an egress pipeline delay to the correction field value, where the egress pipeline delay is a preconfigured value of a static delay from the point at which the PHY device 108 timestamps the timing packet to the egress pin of the PHY device via which the timing packet is egressed from the PHY device 108. In one embodiment, the timing message 122 includes a checksum trailer field, such as checksum trailer 210, and the timing module 118 sets the checksum trailer field 210 of the timing packet 119 based on the values ​​of the timestamp field 208 and the correction field 206 to maintain the correctness of the checksum (such as a UDP checksum) in the timing packet 119.

[0032] Still refer to Figure 1 and Figure 2In one embodiment, timing packet 119 is a timing packet received by PHY device 108 (e.g., PHY device 108-1) from network port 104 (e.g., network port 104-1). In one embodiment, when network device 100 receives timing packet 119, ingress timing module 112 of PHY device 108-1 generates a timestamp for timing packet 119 corresponding to the time of receipt of timing packet 119 by network device 100 or the ingress time of timing packet 119. PHY device 108-1 then transmits timing packet 119 to MAC processor 114 along with the timestamp generated for timing packet 119. In one embodiment, PHY device 108-1 generates a control header for timing packet 119, embeds the timestamp in the control header, and transmits timing packet 119 along with the control header to MAC processor 114. In one embodiment, PHY device 108-1 replaces the preamble of timing packet 119 with a control header generated for timing packet 119 and transmits the timing packet together with the control header to MAC processor 114. In other embodiments, PHY device 108-1 transmits the timestamp generated for timing packet 119 to MAC processor 114 in other suitable manners.

[0033] In one embodiment, the MAC processor 114 includes an egress re-marking engine 124 configured to process a timing packet received by the MAC processor 114 from a PHY device 108 (e.g., PHY device 108-1) to locate and update a correction field in a timing message included in the timing packet to indicate a residency time of the timing packet in the network device 100. In one embodiment, the egress re-marking engine 124 is configured to process a timing packet 119 received from the PHY device 108-1 and locate and update a correction field 206 of the timing message 122 in the timing packet 119 to indicate a residency time of the timing packet 119 in the network device 100. In one embodiment, the egress re-marking engine 124 is configured to update the correction field 206 of the timing message 122 by subtracting the ingress time of the timing packet 119 indicated by a timestamp generated for the timing packet 119 from a current correction value of the correction field 206. In one embodiment, the egress re-marking engine 124 is configured to further add an egress pipeline delay to the correction field value of the correction field 206, where the egress pipeline delay is a preconfigured value of a static delay from the point at which the PHY device 108 timestamps the timing packet to the egress pin of the PHY device via which the timing packet is egressed from the PHY device 108.

[0034] Continue to refer Figure 1, the MAC processor 114 is configured to transmit the timing packet 119 to the appropriate PHY device 108 (e.g., PHY device 108-2) for transmission of the timing packet 119 from the network port 104 (e.g., network port 104-2). In one embodiment, the MAC processor 114 is configured to also provide one or more indicators of one or more parameters to the PHY device 108-2 to enable the PHY device 108-2 to quickly and efficiently embed timing information into the timing packet 119. In one embodiment, the one or more parameters provided by the MAC processor 114 to the PHY device 108-2 enable the PHY device 108-2 to determine that the timing packet 119 requires a timing information update and to quickly locate the field in the timing packet 119 for embedding the timing information update without performing classification and / or parsing of the timing packet 119. In one embodiment, the one or more indicators or tags indicate to the PHY device at least i) the type of packet into which the timing packet is to be embedded by the PHY device, ii) the location of a field in the timing packet at which the timing information is to be embedded by the PHY device, and iii) whether the timing information in the timing packet needs to be updated by the PHY device. In some embodiments, the MAC processor 114 provides one or more additional indicators to the PHY device 108-2 to facilitate timing information updates by the PHY device 108-2. For example, the one or more indicators provided by the MAC processor 114 to the PHY device 108-2 include one or more of the following: i) an indicator of the location of the correction field 206 in the timing message 122 in the timing packet 119, which is used to enable the PHY device 108 to locate and update the correction field 206 without parsing the timing packet 119 to determine the location of the correction field 206 in the timing packet 119, ii) an indicator of whether a checksum trailer field (e.g., the checksum trailer field 210) is present in the timing message 122 in the timing packet 119, iii) an indicator of a time application interface (TAI) field to be used to embed timing information in the timing packet 119, and iv) an indicator of whether wraparound processing needs to be accounted for in conjunction with embedding the timing information in the timing packet 119. In other embodiments, other suitable indicators are additionally or alternatively provided by the MAC processor 114 to the PHY device 108 - 2 to enable the PHY device 108 - 2 to efficiently and dynamically embed timing information in the timing packets 119 as they are transmitted from the network device 100 .

[0035] In one embodiment, the MAC processor 114 is configured to include one or more indicators of the one or more parameters in a control header generated for the timing packet 119 (the control header including the PHY tag 126) and to insert the control header into the timing packet 119. The MAC processor 114 includes a control header engine 128 that is configured to generate a control header for the timing packet 119 (e.g., in an embodiment where the timing packet 119 is a timing packet originated by the network device 100) or to modify an existing control header in the timing packet 119 (e.g., in an embodiment where the timing packet 119 is a timing packet received by the MAC processor 114 from the PHY device 108 of the network device 100). In an embodiment where the timing packet 119 is received by the MAC processor 114 from the host processor 116, the control header engine 128 is configured to generate a control header for the timing packet 119 and to embed the PHY tag 126 in the control header generated for the timing packet 119. In one embodiment, when the host processor 116 generates the timing packet 119, the PHY tag 126 is configured by the host processor 116 for the timing packet 119. In embodiments where the timing packet 119 is received by the MAC processor 114 from the PHY device 108 (e.g., the PHY device 108-1), the control header engine 120 is configured to generate a PHY tag 128 for the timing packet 119 and insert the PHY tag 128 into a control header generated by the PHY device 108 for the timing packet 119. In various embodiments, example control headers generated by the PHY device 108 or the MAC processor 114 for the timing packet 119 are described below with reference to Figure 3A-3B An example PHY tag inserted into the control header of the timing packet 119 according to one embodiment is described below with reference to Figure 4 Describe in more detail.

[0036] Still refer to Figure 1, the PHY device 108-2 is configured to receive the timing packet 119 from the MAC processor 114 and embed timing information in the timing packet 119 based on one or more indicators provided by the MAC processor 114 to the PHY device 108-2. In one embodiment, the egress timing module 110 of the PHY device 108-2 is configured to embed the timing information in the timing packet 119. In one embodiment, because the initial timing information has already been embedded in the timing packet 119 by the MAC processor 114 or the PHY device 108, the PHY device 108 only needs to update the relevant timing information in the timing packet 119 to indicate the actual transmission time of the timing packet 119 from the network device 100 or the residence time of the timing packet 119 in the network device 100. For example, in one embodiment, the egress timing module 110 is configured to update the correction field value in the timing message 122 in the timing packet 119 to add the current value of the PHY clock 113 (e.g., the current nanosecond value) to the correction value.

[0037] In one embodiment, the egress timing module 110 is configured to embed timing information in the timing packet 119 based on one or more indicators provided by the MAC processor 114 to the PHY device 108-2. For example, the egress timing module 110 is configured to update the correction value of the correction field 206 at the location determined by the PHY device 108-2 based on an indicator of the location of the correction field provided by the MAC processor 114 (e.g., included in the PHY tag 126). As another example, in one embodiment, the PHY device 108-2 is configured to determine whether a checksum trailer field (e.g., the checksum trailer field 210) is present in the timing packet 119 and needs to be updated by the PHY device 108-2 based on the indicator provided by the MAC processor 114, and if so, update the checksum trailer field in the timing packet 119.

[0038] Compared to a system in which initial timing information is not embedded in the timing packet by a higher-level processor (such as a MAC processor or a host processor), embedding the final timing information in the packet 119 (as performed by the PHY device 108-1) by updating the timing information already included in the timing packet 119 is less computationally intensive. Furthermore, in various embodiments, because the relevant indicators for embedding the timing information in the timing packet 119 are provided to the PHY device 108-2 by the MAC processor 114, the PHY device 108-2 does not need to parse the timing packet 119, for example, to determine the location of the correction field 206 in the timing message 122 in the timing packet 119 and / or to determine whether a checksum trailer field is present in the timing message 122 in the timing packet 119 and needs to be updated by the PHY device 108-2. Thus, in at least some embodiments, the PHY device 108 - 2 may be implemented using reduced hardware, which reduces power consumption, cost, etc., compared to a system in which the PHY device is configured to dynamically perform one-step timestamping without an indicator provided by the MAC processor and / or without initial timing information embedded in the timing packet by the MAC processor or the host processor.

[0039] Still refer to Figure 1 It should be noted that although the network device 100 is Figure 1 1. Although illustrated as including a PHY device 108-1 coupled to network port 104-1 and a PHY device 108-2 coupled to network interface 104-2, in some embodiments, network device 100 omits PHY device 108-1 and one or both of PHY devices 108-1 and / or 108-2. For example, in some embodiments, MAC processor 114 is directly coupled to one or both of network port 104-1 and / or network port 104-2. In embodiments where MAC processor 114 is directly coupled to network port 104-1, MAC processor 114 generates an ingress timestamp for timing packets received by MAC processor 114 from network port 104-1. Additionally, in embodiments where MAC processor 114 is directly coupled to network port 104-2, MAC processor 114 updates timing information in timing packets before forwarding the timing packets to network port 104-2 for transmission of the timing packets. For example, in various embodiments, MAC processor 114 updates a correction field in the timing packet based on a MAC clock (not shown) maintained by MAC processor 114 to indicate a transmission time or timing packet from network device 100, or to add a residence time of the timing packet in network device 100.

[0040] Now go to Figure 3AAccording to one embodiment, a control header 300 is generated by a PHY device 108 (e.g., PHY device 108-1) for a timing packet. In one embodiment, the control header 300 generally conforms to a known control header format specified for a media independent interface, such as the Universal Serial 10GE Media Independent Interface (USXGMII) or the Universal Serial Gigabit Media Independent Interface (USGMII). However, in one embodiment, the control header 300 is modified relative to the known control header format specified for the media independent interface. In the illustrated embodiment, the control header 300 includes a packet type field 302, a subport identifier (Id) field 304, an extension field type indicator field 306, an extension field 308, and a cyclic redundancy check (CRC) field 310. In some embodiments, the control header 300 omits the Figure 3A One or more of the fields 302-310 shown, and / or including Figure 3A One or more additional fields not shown in .

[0041] In one embodiment, a PHY device (e.g., PHY device 108-1) is configured to generate a control header 300 for a received timing packet and insert the control header at a predetermined location within the timing packet. For example, PHY device 108-1 is configured to replace the preamble at the beginning of the timing packet with the control header 300. PHY device 108-1 is configured to include a timestamp corresponding to the time the packet was received in an extension field 308 of the control header 300. PHY device 108-1 is also configured to set the value of the extension field type field 306 to indicate that the extension field 308 includes a timestamp. In one embodiment, the timestamp included in the extension field 308 occupies 32 bits of the extension field 306. In another embodiment, the timestamp included in the extension field 307 occupies a number of bits other than 32 bits (e.g., 16 bits, 48 ​​bits, 64 bits, or any other suitable number of bits). In one embodiment, PHY device 108-1 is configured to include the timestamp as a 32-bit unsigned value (in nanoseconds) of the PHY clock 113 at the time the packet was received. In another embodiment, the PHY device 108-1 is configured to include the timestamp in another suitable format. For example, in one embodiment, where the PHY device 108-1 is configured to utilize the IEEE Time Application Interface (TAI) format, the PHY device 108-1 is configured to convert the nanosecond value of the PHY clock 113 upon packet reception into a 2-bit seconds value followed by a 29-bit nanosecond value including a two's complement of the nanosecond value.

[0042] The MAC processor 114 is configured to receive a timing packet and a control header 300 from the PHY device 108-1 and obtain a timestamp from the extension field 308 of the control header 300. In one embodiment, the MAC processor 114 is configured to pass the timestamp value to the host processor 116 in a suitable format. In one embodiment, the MAC processor 114 is configured to convert the timestamp value into a format suitable for transmission to the host processor 116. For example, the MAC processor 114 is configured to modify the timestamp value, for example, to subtract an ingress pipeline delay from the timestamp value, and pass the modified timestamp value to the host processor 116. In one embodiment, the MAC processor 114 is configured to generate a timestamp tag (TST) for the packet so that the timestamp value is included in the timestamp value in a suitable format and pass the timestamp tag along with the packet to the MAC processor 114. In one embodiment, the host processor 116 is configured to utilize the timestamp obtained from the control header 300 for synchronization with a master clock. In another embodiment, the MAC processor 114 is configured to internally utilize the timestamp obtained from the control header 300, for example, to update the correction field in the timing packet 119 to reflect the residence time of the timing packet 119, as described above.

[0043] Figure 3B is a diagram of a control header 350 according to one embodiment. Figure 1 In one embodiment, the MAC processor 114 is configured to insert a control header 350 into a timing packet received from the host controller 116 before transmitting the packet to the PHY device (e.g., PHY device 108-2) for transmission of the packet via the network port 104 (e.g., network port 104-2). In another embodiment, the MAC processor 114 is configured to modify a control header (e.g., control header 300) already present in the timing packet to generate the control header 350. In one embodiment, the control header 350 is inserted into the timing packet at a predetermined position within the timing packet. For example, in one embodiment, the control header 350 replaces the preamble at the beginning of the timing packet.

[0044] In one embodiment, the control header 350 is generally the same as the control header 300, and the extension field 308 of the control field 350 includes a PHY tag 314. In one embodiment, the PHY tag 314 corresponds to Figure 1In one embodiment, the MAC processor 114 is configured to generate a PHY tag 314 for the timing packet received from the host processor 116 and include the PHY tag 304 in the extension field 308 of the control header 350 generated for the packet. In one embodiment, the MAC processor 114 is further configured to include an indicator in the packet type field 302 of the control header 350 indicating that the timing packet is a type of packet into which the PHY device is to embed timing information. In one embodiment, the PHY device 108-2 is configured to determine, based on the packet type field 302, that the timing packet is a type of packet into which the PHY device is to embed timing information. In one embodiment, the PHY device 108-2 is configured to perform embedding of the timing information into the timing packet in response to determining, based on the packet type field 302, that the timing packet is a type of packet into which the PHY device is to embed timing information.

[0045] MAC processor 114 is configured to generate PHY tag 314 to include one or more indicators of one or more parameters required for PHY device 108-2 to embed timing information in the packet, the timing information indicating a time corresponding to transmission of the packet from network device 100 or a residence time of the timing packet in network device 100. In one embodiment, MAC processor 114 is configured to insert PHY tag 314 in place of a signature field of a control header format specified for a media independent interface.

[0046] In one embodiment, the PHY device 108-2 is configured to retrieve one or more indicators from the control header 350 and / or the PHY tag 314 that are used to embed timing information in the timing packet without parsing the timing packet to determine the location of the control header 320 and / or the PHY tag 314 in the timing packet. For example, in an embodiment in which the control header 350 is inserted into the timing packet at a predetermined location within the timing packet, such as at the beginning of the timing packet, the PHY device 108-2 is configured to retrieve the one or more indicators from the control header 350 at the beginning of the timing packet and / or from the PHY tag 314 located at the predetermined location within the control header 350. As described above, in at least some embodiments, the one or more indicators included in the control header 350 enable the PHY device 108-2 to efficiently apply a one-step timestamp to the packet with reduced hardware requirements compared to a system in which the PHY device implements one-step timestamps without receiving such one or more indicators from an upper layer processor, such as a MAC processor.

[0047] Figure 4 is a diagram of a PHY tag 400 according to one embodiment. In one embodiment, the PHY tag 400 corresponds to Figure 3BIn various embodiments, the MAC processor 114 is configured to generate a PHY tag 400 for a timing packet received from the host processor 116 or for a timing packet received from the PHY device 108. In the illustrated embodiment, the PHY tag 400 includes a reserved field 402, a correction field offset field 404, a TAI domain selection field 406, a checksum update field 408, and a timestamp least significant bit (LSB) field 410. In some embodiments, the PHY tag 400 omits the Figure 4 One or more of the fields 402-410 shown and / or including Figure 4 One or more additional fields not shown in .

[0048] The correction field offset field 404 of the PHY tag 400 is set to indicate the correction field in the timing packet (e.g., Figure 2 The correction field offset field 404 is set to an offset value (e.g., a number of bits, a number of bytes, or another suitable offset value) from the beginning of the timing packet or from the beginning of the start frame delimiter (SFD) field in the timing packet. In another embodiment, the correction field offset indicator field includes another suitable indicator of the position of the correction field in the timing packet. The TAI selection field 406 includes an indication of the TAI domain to be used by the PHY device 108-2 to timestamp the timing packet.

[0049] The checksum update indicator field 408 is set to indicate whether a checksum tail field update is to be performed by the PHY device 108-2 for the timing packet. For example, in one embodiment, if the timing packet is a UDP packet over IPv6, the MAC processor 114 sets the checksum update field 408 to a value (e.g., a logical 1) indicating that the PHY device 108-2 is to update the checksum tail field in the packet. Otherwise, in one embodiment, if the timing packet is not a UDP packet over IPv6, the MAC processor 114 sets the checksum update indicator field 408 to a value (e.g., a logical 0) indicating that a checksum tail field update is not required. In one embodiment, the PHY device 108-2 determines whether a checksum tail field update is required based on the checksum update indicator field 408, and in response to determining that a checksum tail field update is required, updates the checksum tail field (e.g., a logical 0) located at a predetermined location within the timing message in the timing packet (such as at the end of the timing message in the timing packet). Figure 2 The checksum tail field 210) performs an incremental update.

[0050] In one embodiment, the timestamp LSB field 410 includes the least significant bit of a timestamp in a timing packet, such as an ingress or start timestamp in the timing packet. In one embodiment, the least significant bit of the timestamp in the timing packet indicates to the PHY device 108-2 whether wraparound correction in the correction field of the timing packet is required by the PHY device 108-2. In one embodiment, the PHY device 108-2 is configured to compare the least significant bit of the current value of the PHY clock 113 with the value of the timestamp LSB field 410. In one embodiment, if the least significant bit of the current value of the PHY clock 113 is equal to the value of the timestamp LSB field 410, the PHY device 108-2 determines that wraparound correction is not required. In this case, the PHY device 108-2 (e.g., the egress timing module 110) determines a new value for the correction field in the timing packet by adding the nanosecond value of the PHY clock 113 to the current value of the correction field. On the other hand, in one embodiment, if the least significant bit of the current value of the PHY clock 113 is not equal to the value of the timestamp LSB field 410, the PHY device 108-2 determines that wraparound has occurred. In this case, in one embodiment, the PHY device 108-2 (e.g., the egress timing module 110) adds the nanosecond value of the PHY clock 113 and an additional second or 10 seconds. 9 The nanoseconds are added to the current value of the correction field to determine the new value of the correction field in the timing packet.

[0051] Figure 5 is a flow chart illustrating an example method 500 in a network device for processing timing packets for synchronizing the network device according to one embodiment. Figure 1 The network device 100 implements the method 500. For example, in one example, the MAC processor 114 of the network device 100 implements the method 500. For ease of explanation, refer to Figure 1 The method 500 is described with reference to the network device 100. In other embodiments, the method 500 is implemented by other suitable network devices.

[0052] At block 502, a timing packet to be transmitted by a network device is received at a MAC processor of the network device. In one embodiment, the timing packet is received by Figure 1 Received by the MAC processor 114. In one example, Figure 1 The timing packet 119 is received by the MAC processor. In another embodiment, the timing packet 119 is received by the MAC processor. Figure 1The timing packet received at block 502 is a timing packet different from the timing packet 119. In an embodiment where the network device 100 operates as an ordinary clock or boundary clock device, the timing packet received at block 502 is a timing packet generated by the host processor 116. In an embodiment where the network device 100 operates as a transparent clock device, the timing packet received at block 502 is a timing packet received by the MAC processor from a network port of the network device or from a PHY device coupled to the network port of the network device.

[0053] At block 504, the timing packet is processed by the MAC processor. In one embodiment, processing the timing packet by the MAC processor includes generating one or more indicators to be used by the PHY device for embedding timing information into one or more parameters in the timing packet provided from the MAC processor to the PHY device. In one embodiment, the one or more indicators enable the PHY device to dynamically and efficiently embed timing information into the timing packet as the timing packet is transmitted from the network device. In one embodiment, the one or more indicators include at least i) an indicator indicating that the timing packet is a type of packet into which the PHY device is to embed timing information, ii) an indicator of a position of a field in the timing packet at which the timing information is to be embedded in the timing packet by the PHY device, and iii) an indicator of whether the timing information in the timing packet needs to be updated by the PHY device. As a more specific example, in one embodiment, the one or more indicators include an indicator of the position of a timing field in the timing packet to be updated by the PHY device, such a correction field in the timing packet, an indicator of whether a checksum trailer field is present in the timing packet, and the like. In other embodiments, the one or more indicators additionally or alternatively include one or more other indicators of relevant information to enable the PHY device to efficiently embed timing information in timing packets dynamically as they are transmitted from the network device.

[0054] At block 506, the timing packet and one or more indicators are transmitted from the MAC processor to the PHY device. In one embodiment, the MAC processor transmits the timing packet and one or more indicators to the PHY device by including one or more parameters in the control header (e.g., Figure 3B The MAC processor may include a control header 350 (e.g., a control header 350) and insert the control header into the timing packet before transmitting the timing packet to the PHY device to transmit one or more indicators in the PHY device. In one embodiment, the control header 350 is inserted into the timing packet at a predetermined position within the timing packet. For example, in one embodiment, the control header replaces the preamble at the beginning of the timing packet. In another embodiment, the MAC processor provides the one or more indicators to the PHY device in another suitable manner, such as via a control signal or one or more tags provided by the MAC processor to the PHY device, which are separate from the timing packet provided by the MAC processor to the PHY device.

[0055] In various embodiments, providing one or more indicators from the MAC processor to the PHY device enables the PHY device to quickly and efficiently embed timing information into packets, such as by updating an initial value of a timing field of a timing packet, without parsing the timing packet to determine the location of a correction field in the timing packet and / or to determine whether a checksum trailer field is present in the timing packet. Thus, in at least some embodiments, providing one or more indicators from the MAC processor to the PHY device facilitates implementing the PHY device with reduced hardware, which reduces power consumption, cost, etc., compared to systems in which the PHY device is configured to dynamically perform one-step timestamping without such indicators being provided to the PHY device from the MAC processor and / or without initial timing information being embedded in timing packets by the MAC processor or a host processor.

[0056] Figure 6 is a flow chart illustrating an example method 600 for embedding timing information into a timing packet to be transmitted by a network device according to one embodiment. Figure 1 The network device 100 implements the method 600. For example, in one example, the PHY device 108 (eg, the PHY device 108-2) of the network device 100 implements the method 800. For ease of explanation, reference is made to Figure 1 The method 600 is described with reference to the device 100. In other embodiments, the method 600 is implemented by other suitable network devices.

[0057] At block 602, a PHY device of a network device receives a timing packet that is subsequently transmitted by the network device. In one embodiment, the timing packet is received at the PHY device from a MAC processor of the network device. In one embodiment, the timing packet includes initial timing information provided by one or both of i) the MAC processor and ii) a host processor of the network device.

[0058] At block 604, one or more indicators of one or more parameters to be used by the PHY device for embedding timing information in a timing packet are received at the PHY device. In one embodiment, the one or more indicators include at least i) an indicator indicating that the timing packet is a type of packet into which the PHY device is to embed timing information, ii) an indicator of a location of a field in the timing packet at which the timing information is to be embedded in the timing packet by the PHY device, and iii) an indicator of whether the timing information in the timing packet needs to be updated by the PHY device. In other embodiments, the one or more indicators additionally or alternatively include one or more other indicators of relevant information to enable the PHY device to dynamically and efficiently embed timing information in the timing packet as the timing packet is transmitted from the network device. In one embodiment, a control header (e.g., Figure 3B The control header 350 includes one or more indicators provided by the MAC processor to the PHY device. In other embodiments, the one or more indicators of the one or more parameters are received by the PHY device in other suitable ways, such as via a control signal or one or more tags provided by the MAC processor to the PHY device, separate from the timing packet provided by the MAC processor to the PHY device.

[0059] At block update 606, the PHY device updates the initial timing information in the timing packet to embed the final timing information in the timing packet. For example, receiving the timing packet at block 602 may include receiving a timing packet including i) a timestamp and ii) a correction field value generated based on a clock maintained by a host processor of the network device, and updating the timing information in the timing packet may include updating the initial correction field value in the timing packet based on the clock maintained by the PHY device. In one embodiment, the timing information is updated by the PHY device based on one or more indicators received by the PHY device from the MAC processor at block 604. For example, in one embodiment, the PHY device updates the initial value of the correction field based on an indicator of the location of the correction field received from the MAC processor at block 604, and does not parse the timing packet to determine the location of the correction field in the timing packet. As another example, the PHY device determines whether a checksum trailer field is present in the timing packet based on an indicator provided by the MAC processor, and updates the checksum trailer if the checksum trailer field is present in the timing packet.

[0060] At block 610 , the timing packets are forwarded by the PHY device to one or more network ports of the network device for transmission from the network device to one or more other devices on the network to allow the one or more other network devices to synchronize with a master clock in the network.

[0061] In various embodiments, timing information in a timing packet is updated by a PHY device based on one or more indicators received at the PHY device from a MAC processor, such that the PHY device can quickly and efficiently embed timing information in the packet by updating an initial value of a timing field of the timing packet without parsing the timing packet to determine the location of a correction field in the timing packet and / or determining whether a checksum trailer field is present in the timing packet. Thus, in at least some embodiments, the PHY device can be implemented with reduced hardware compared to a system in which the PHY device is configured to dynamically perform one-step timestamping without such indicators being provided to the PHY device from a MAC processor and / or without initial timing information being embedded in the timing packet by a MAC processor or a host processor, thereby reducing power consumption, cost, etc.

[0062] In one embodiment, a method for processing timing packets in a network device for synchronizing the network device comprises: receiving a timing packet to be transmitted by the network device at a media access control (MAC) processor of the network device; performing initial processing of the timing packet by the MAC processor, including generating one or more indicators of one or more parameters to be used by a PHY device of the network device for embedding timing information in the timing packet, the one or more indicators comprising at least i) an indicator indicating that the timing packet is a type of packet into which the timing information is to be embedded by the PHY device, ii) an indicator of a position of a field in the timing packet at which the timing information is to be embedded in the timing packet by the PHY device, and iii) an indicator of whether the timing information in the timing packet needs to be updated by the PHY device; and transmitting i) the timing packet and ii) the one or more indicators from the MAC processor to the PHY device for further processing of the timing packet based on the one or more indicators and subsequent transmission of the timing packet from the network device.

[0063] In other embodiments, the method includes any suitable combination of one or more of the following features.

[0064] The method also includes generating, by the MAC processor, a control header to include the one or more indicators generated for the timing packet, and inserting, by the MAC processor, the control header into the timing packet before transmitting the timing packet to the PHY device.

[0065] The method also includes generating, by the MAC processor, a PHY tag to be included in the control header, generating, by the MAC processor, the control header to include the PHY tag in an extension field of the control header, and inserting the control header at a predetermined position within the timing packet before transmitting the timing packet to the PHY device.

[0066] Inserting the control header at the predetermined position in the timing packet comprises replacing a preamble at the beginning of the timing packet with the control header.

[0067] Generating the PHY tag includes generating the PHY tag to include one or more of: i) an offset indicator field, the offset indicator field being set to indicate an offset of a correction field in the timing packet relative to a delimiter field of the timing packet, ii) a checksum update indicator field being set to indicate whether a checksum update is required for the timing packet, and iii) a timestamp least significant bit (LSB) field, wherein the timestamp LSB field indicates to the PHY device whether wrap-around of a correction field value is to be accounted for by the PHY device.

[0068] Receiving the timing packet includes receiving one of: i) a timing packet generated by a host processor of the network device, or ii) receiving a timing packet previously received by the network device, the timing packet previously received by the network device including a correction field for indicating a residence time of the timing packet in the network device.

[0069] The timing information to be embedded in the timing packet indicates one of: i) a time corresponding to a transmission of the timing packet from the network device, or ii) a residence time of the timing packet in the network device.

[0070] In another embodiment, a network device configured to operate in a network includes: a media access control (MAC) processor, configured to: receive a timing packet to be transmitted by the network device, generate one or more indicators of one or more parameters to be used by a PHY device of the network device for embedding timing information in the timing packet, the one or more indicators including at least i) an indicator indicating that the timing packet is a type of packet into which the PHY device is to embed timing information, ii) an indicator of the position of a field in the timing packet, where the timing information is to be embedded in the timing packet by the PHY device, and iii) an indicator of whether the timing information in the timing packet needs to be updated by the PHY device; and transmit i) the timing packet and ii) the one or more indicators to the PHY device for further processing of the timing packet based on the one or more indicators and subsequent transmission of the timing packet from the network device.

[0071] In other embodiments, the network device includes any suitable combination of one or more of the following features.

[0072] The MAC processor is further configured to generate a control header to include the one or more indicators and to insert the control header into the timing packet before transmitting the timing packet to the PHY device.

[0073] The MAC processor is further configured to generate a PHY tag to be included in the control header, generate the control header to include the PHY tag in an extension field of the control header, and insert the control header at a predetermined position within the timing packet before transmitting the timing packet to the PHY device.

[0074] The MAC processor is configured to replace a preamble at the beginning of the timing packet with the control header.

[0075] The MAC processor is configured to generate the PHY tag to include one or more of: i) an offset indicator field, the offset indicator field being set to indicate an offset of a correction field in the timing packet relative to a delimiter field of the timing packet, ii) a checksum update indicator field being set to indicate whether a checksum update is required for the timing packet, and iii) a timestamp least significant bit (LSB) field, wherein the timestamp LSB field is set to indicate to the PHY device whether wrap-around of a correction field value is to be accounted for by the PHY device.

[0076] The timing packet is one of: i) a timing packet generated by a host processor of the network device, or ii) a timing packet previously received by the network device, the timing packet previously received by the network device including a correction field for indicating a residence time of the timing packet in the network device.

[0077] The timing information to be embedded in the timing packet indicates one of: i) a time corresponding to a transmission of the timing packet from the network device, or ii) a residence time of the timing packet in the network device.

[0078] In yet another embodiment, a network device configured to operate in a network includes a media access control (MAC) processor coupled to a physical layer (PHY) device, wherein the MAC processor is configured to: receive a timing packet to be transmitted by the network device, generate one or more indicators of one or more parameters to be used by a PHY device of the network device for embedding timing information in the timing packet, the one or more indicators including at least i) an indicator indicating that the timing packet is a type of packet into which the PHY device is to embed timing information, ii) an indicator of a position of a field in the timing packet at which the timing information is to be embedded in the timing packet by the PHY device, and iii) an indicator of whether the timing information in the timing packet needs to be updated by the PHY device; and transmit i) the timing packet and ii) the one or more indicators to the PHY device. The PHY device is configured to: receive i) the timing packet from the MAC processor and ii) the one or more indicators from the MAC processor; embed timing information in the timing packet based on the one or more indicators; and forward the timing packet to one or more network ports of the network device for transmission of the timing packet from the network device.

[0079] In other embodiments, the network device includes any suitable combination of one or more of the following features.

[0080] The timing packet is one of: i) a timing packet generated by a host processor of the network device, or ii) a timing packet previously received by the network device, the timing packet previously received by the network device including a correction field for indicating a residence time of the timing packet in the network device.

[0081] The timing information to be embedded in the timing packet indicates one of: i) a time corresponding to a transmission of the timing packet from the network device, or ii) a residence time of the timing packet in the network device.

[0082] The MAC processor is configured to receive a timing packet comprising i) a timestamp, and ii) a value of a correction field generated based on a clock maintained by a host processor of the network device.

[0083] The PHY device is configured to embed the timing information in the timing packet at least by updating the value of the correction field based on a clock maintained by the PHY device of the network device.

[0084] The MAC processor is configured to generate a PHY tag to include an offset indicator field set to indicate an offset of a correction field in the timing packet relative to a delimiter field of the timing packet, generate a control header to include the PHY tag in an extension field of the control header, and replace a preamble at the beginning of the timing packet with the control header before transmitting the timing packet to the PHY device.

[0085] The PHY device is configured to update the correction field at the offset indicated by the offset indicator field and not parse the timing packet to locate the correction field within the timing packet.

[0086] The MAC processor is configured to generate the PHY tag to further include a checksum update indicator field, the checksum update indicator field being set to indicate whether the timing packet requires a checksum update.

[0087] The PHY device is configured to determine whether the timing packet requires a checksum update based on the checksum update indicator field, and in response to determining that the timing packet requires a checksum update, perform an incremental update of a checksum trailer field in the timing packet.

[0088] The MAC processor is configured to generate the PHY tag to further include a timestamp least significant bit (LSB) field, wherein the timestamp LSP field indicates whether wraparound of a correction field value is to be accounted for by the PHY device.

[0089] The PHY device is configured to determine, based on the timestamp LSB field, whether wraparound processing of the correction field value is to be accounted for by the PHY device, and in response to determining that the wraparound processing of the correction field value is to be accounted for by the PHY device, update the correction field to account for the wraparound processing in the correction field.

[0090] In another embodiment, a method for embedding timing information in a timing packet to be transmitted by a network device comprises: receiving, at a physical layer (PHY) device of the network device, a timing packet to be transmitted by the network device, the timing packet including initial timing information provided by one or both of i) a media access control (MAC) processor and ii) a host processor of the network device; receiving, at the PHY device, from the MAC processor, one or more indicators of one or more parameters to be used by the PHY device for embedding timing information in the timing packet, the one or more indicators including at least i) an indication that the timing packet is to be transmitted by the network device; The PHY device is configured to: provide a timing packet receiving device comprising: a first portion of a timing packet receiving device and a second portion of a timing packet receiving device; a second portion of a timing packet receiving device and a second portion of a timing packet receiving device; and a second portion of a timing packet receiving device and a second portion of a timing packet receiving device. The PHY device is configured to provide a timing packet receiving device and a second portion of a timing packet receiving device. The PHY device is configured to provide a timing packet receiving device and a second portion of a timing packet receiving device.

[0091] In other embodiments, the method includes any suitable combination of one or more of the following features.

[0092] Receiving the one or more indicators comprises: receiving a control header inserted into the timing packet by the MAC processor, wherein the control header includes the one or more indicators, and

[0093] Updating the timing information in the timing packet includes updating the timing information based on the one or more indicators included in the control header, and not classifying the timing packet as a timing packet by the PHY device.

[0094] Receiving the timing packet includes receiving a timing packet including: i) a timestamp and ii) a correction field value generated based on a clock maintained by a host processor of the network device.

[0095] Updating the timing information in the timing packet includes updating the correction field value in the timing packet based on a clock maintained by the PHY device.

[0096] Receiving the timing packet includes receiving one of: i) a timing packet generated by a host processor of the network device, or ii) receiving a timing packet previously received by the network device, the timing packet previously received by the network device including a correction field for indicating a residence time of the timing packet in the network device.

[0097] Updating the initial timing information in the timing packet to embed final timing information in the timing packet includes updating the initial timing information indicating one of: i) a time corresponding to transmission of the timing packet from the network device, or ii) a residence time of the timing packet in the network device.

[0098] Receiving the one or more indicators includes receiving a PHY tag included in a control header at a predetermined location within the timing packet, and the method further includes retrieving, by the PHY device, the PHY tag from the control header at the predetermined location within the timing packet of the PHY device.

[0099] Retrieving the PHY tag includes retrieving the PHY tag from the control header that replaces the preamble at the beginning of the timing packet.

[0100] The PHY tag includes an offset indicator field, the offset indicator field being arranged to indicate an offset of a correction field in the timing packet relative to a delimiter field of the timing packet, and

[0101] Updating the initial timing information in the timing packet to embed the final timing information includes updating the correction field at the offset indicated by the offset indicator field and without parsing the timing packet by the PHY device to locate the correction field within the timing packet.

[0102] The PHY further includes a checksum update indicator field, the checksum update indicator field being configured to indicate whether the timing packet requires a checksum update.

[0103] Updating the initial timing information in the timing packet to embed the final timing information includes: determining whether the timing packet requires a checksum update based on the checksum update indicator field, and in response to determining that the timing packet requires a checksum update, performing an incremental update of a checksum trailer field in the timing packet.

[0104] The PHY also includes a timestamp least significant bit (LSB) field, wherein the timestamp LSP field indicates whether wraparound of correction field values ​​is to be accounted for by the PHY device.

[0105] Updating the initial timing information in the timing packet to embed the final timing information includes determining whether wraparound of the correction field value is to be accounted for by the PHY device based on the timestamp LSB field, and in response to determining that the wraparound of the correction field value is to be accounted for by the PHY device, updating the correction field to account for the wraparound in the correction field.

[0106] In another embodiment, a network device configured to operate in a network includes a physical layer (PHY) device processor configured to: receive a timing packet to be transmitted by the network device, the timing packet including initial timing information provided by one or both of i) a media access control (MAC) processor and ii) a host processor of the network device; receive one or more indicators of one or more parameters to be used by the PHY device for embedding timing information in the timing packet, the one or more indicators including at least i) an indicator indicating that the timing packet is a type of packet into which the PHY device is to embed timing information, ii) an indicator of a position of a field in the timing packet at which the timing information is to be embedded in the timing packet by the PHY device, and iii) an indicator of whether the timing information in the timing packet needs to be updated by the PHY device; update the initial timing information in the timing packet based on the one or more indicators to embed final timing information in the timing packet; and forward the timing packet to one or more network ports of the network device for transmission of the timing packet from the network device.

[0107] In other embodiments, the network device includes any suitable combination of one or more of the following features.

[0108] The PHY device is configured to receive a timing packet comprising i) a timestamp and ii) a correction field value generated based on a clock maintained by a host processor of the network device, and update the correction field value in the timing packet based on the clock maintained by the PHY device.

[0109] The PHY device is configured to: receive one of: i) a timing packet generated by a host processor of the network device, or ii) receive a timing packet previously received by the network device, the timing packet previously received by the network device including a correction field for indicating a residence time of the timing packet in the network device.

[0110] The PHY device is configured to update the initial timing information in the timing packet to embed final timing information in the timing packet by at least updating initial timing information indicating one of the following: i) a time corresponding to a transmission of the timing packet from the network device, or ii) a residence time of the timing packet in the network device.

[0111] The PHY device is configured to: receive, from the MAC processor, a control header inserted into the timing packet by the MAC processor, wherein the control header includes the one or more indicators, and update the timing information based on the one or more indicators in the control header, and not classify, by the PHY device, the timing packet as a timing packet.

[0112] The control header i) is inserted into the timing packet at a predetermined position within the timing packet and ii) includes a PHY tag in an extension field of the control header, and the PHY device is configured to retrieve the PHY tag from the control header at the predetermined position within the timing packet of the PHY device.

[0113] The PHY device is configured to retrieve the PHY tag from the control header that replaces the preamble at the beginning of the timing packet.

[0114] The PHY tag includes an offset indicator field that is set to indicate an offset of a correction field in the timing packet relative to a delimiter field of the timing packet, and the PHY device is configured to update the correction field at the offset indicated by the offset indicator field and not parse the timing packet to locate the correction field within the timing packet.

[0115] The PHY tag also includes a checksum update indicator field, the checksum update indicator field being set to indicate whether the timing packet requires a checksum update, and the PHY device being configured to determine whether the timing packet requires a checksum update based on the checksum update indicator field, and in response to determining that the timing packet requires a checksum update, perform an incremental update of a checksum trailer field in the timing packet.

[0116] The PHY tag also includes a timestamp least significant bit (LSB) field, wherein the timestamp LSB field indicates whether wrap-around processing of the correction field value is to be accounted for by the PHY device, and the PHY device is configured to: determine whether wrap-around processing of the correction field value is to be accounted for by the PHY device based on the timestamp LSB field, and in response to determining that the wrap-around processing of the correction field value is to be accounted for by the PHY device, update the correction field to account for the wrap-around processing in the correction field.

[0117] At least some of the various blocks, operations, and techniques described above are suitably implemented using dedicated hardware, such as one or more of the following: discrete components, integrated circuits, application-specific integrated circuits (ASICs), programmable logic devices (PLDs), processors that execute firmware instructions, processors that execute software instructions, or any combination thereof. When implemented using a processor that executes software or firmware instructions, the software or firmware instructions may be stored in any suitable computer-readable memory, such as a magnetic disk, optical disk, or other storage medium. The software or firmware instructions may include machine-readable instructions that, when executed by one or more processors, cause the one or more processors to perform various actions.

[0118] Although the present invention has been described with reference to specific examples, these examples are intended to illustrate and not limit the invention. Changes, additions and / or deletions may be made to the disclosed embodiments without departing from the scope of the invention.

Claims

1. A method for processing a timing packet for synchronizing the network device in a network device, the method comprising: receiving, at a media access control (MAC) processor of the network device, a timing packet to be transmitted by the network device; performing, by the MAC processor, initial processing of the timing packet, including generating one or more indicators of parameters to be used by a PHY device of the network device for embedding timing information in the timing packet, the one or more indicators indicating at least i) a type of packet into which the timing packet is to be embedded by the PHY device, ii) a location of a field in the timing packet at which the timing information is to be embedded by the PHY device, and iii) whether the timing information in the timing packet needs to be updated by the PHY device; as well as i) the timing packet and ii) the one or more indicators are communicated from the MAC processor to the PHY device for further processing of the timing packet based on the one or more indicators and subsequent transmission of the timing packet from the network device.

2. The method according to claim 1, further comprising: generating, by the MAC processor, a control header to include the one or more indicators generated for the timing packet, and The control header is inserted into the timing packet by the MAC processor before transmitting the timing packet to the PHY device.

3. The method according to claim 2, further comprising: generating, by the MAC processor, a PHY tag to be included in the control header, generating, by the MAC processor, the control header to include a PHY tag in an extension field of the control header, and The control header is inserted at a predetermined position within the timing packet before transmitting the timing packet to the PHY device.

4. The method of claim 3, wherein inserting the control header at the predetermined position in the timing packet comprises: The preamble at the beginning of the timing packet is replaced with the control header.

5. The method of claim 4 , wherein generating the PHY tag comprises generating the PHY tag to include one or more of: i) an offset indicator field set to indicate an offset of a correction field in the timing packet relative to a delimiter field of the timing packet, ii) a checksum update indicator field set to indicate whether a checksum update is required for the timing packet, and iii) a timestamp least significant bit (LSB) field, wherein the timestamp LSB field indicates to the PHY device whether wraparound of a correction field value is to be accounted for by the PHY device.

6. The method of claim 1 , wherein receiving the timing packet comprises receiving one of: i) a timing packet generated by a host processor of the network device, or ii) receiving a timing packet previously received by the network device, the timing packet previously received by the network device comprising a correction field for indicating a residence time of the timing packet in the network device, and wherein the timing information to be embedded in the timing packet indicates one of: i) a time corresponding to a transmission of the timing packet from the network device, or ii) a residence time of the timing packet in the network device.

7. A network device configured to operate in a network, the network device comprising: Media Access Control (MAC) processor, configured as receiving a timing packet to be transmitted by said network device, generating one or more indicators of parameters to be used by a PHY device of the network device for embedding timing information in the timing packet, the one or more indicators indicating at least i) a type of packet into which the timing packet is to be embedded by the PHY device, ii) a position of a field in the timing packet at which the timing information is to be embedded by the PHY device, and iii) whether the timing information in the timing packet needs to be updated by the PHY device; as well as i) the timing packet and ii) the one or more indicators are communicated to the PHY device for further processing of the timing packet based on the one or more indicators and subsequent transmission of the timing packet from the network device.

8. The network device according to claim 7, wherein the MAC processor is further configured to generating a control header to include the one or more indicators, and The control header is inserted into the timing packet before transmitting the timing packet to the PHY device.

9. The network device according to claim 8, wherein the MAC processor is further configured to generating a PHY tag to be included in the control header, generating the control header to include the PHY tag in an extension field of the control header, and The control header is inserted at a predetermined position within the timing packet before transmitting the timing packet to the PHY device.

10. The network device of claim 9, wherein the MAC processor is configured to replace a preamble at the beginning of the timing packet with the control header.

11. The network device of claim 9, wherein the MAC processor is configured to generate the PHY tag to include one or more of: i) an offset indicator field, the offset indicator field being set to indicate an offset of a correction field in the timing packet relative to a delimiter field of the timing packet, ii) a checksum update indicator field being set to indicate whether a checksum update is required for the timing packet, and iii) a timestamp least significant bit (LSB) field, wherein the timestamp LSB field is set to indicate to the PHY device whether wraparound of a correction field value is to be accounted for by the PHY device.

12. The network device according to claim 7, wherein The timing packet is one of: i) a timing packet generated by a host processor of the network device, or ii) a timing packet previously received by the network device, the timing packet previously received by the network device including a correction field for indicating a residence time of the timing packet in the network device.

13. The network device of claim 7, wherein the timing information to be embedded in the timing packet indicates one of: i) a time corresponding to transmission of the timing packet from the network device, or ii) a residence time of the timing packet in the network device.

14. A network device configured to operate in a network, the network device comprising: A media access control (MAC) processor is coupled to a physical layer (PHY) device, wherein the MAC processor is configured to receiving a timing packet to be transmitted by said network device, generating one or more indicators of parameters to be used by a PHY device of the network device for embedding timing information in the timing packet, the one or more indicators indicating at least i) a type of packet into which the timing packet is to be embedded by the PHY device, ii) an indicator of a position of a field in the timing packet at which the timing information is to be embedded in the timing packet by the PHY device, and iii) whether the timing information in the timing packet needs to be updated by the PHY device; as well as transmitting i) the timing packet and ii) the one or more indicators to the PHY device; in The PHY device is configured as receiving i) the timing packet from the MAC processor and ii) the one or more indicators from the MAC processor; embedding timing information in the timing packet based on the one or more indicators; as well as The timing packets are forwarded to one or more network ports of the network device for transmission of the timing packets from the network device.

15. The network device according to claim 14, wherein The timing packet is one of: i) a timing packet generated by a host processor of the network device, or ii) a timing packet previously received by the network device, the timing packet previously received by the network device including a correction field for indicating a residence time of the timing packet in the network device, and The timing information to be embedded in the timing packet indicates one of: i) a time corresponding to a transmission of the timing packet from the network device, or ii) a residence time of the timing packet in the network device.

16. The network device according to claim 14, wherein The MAC processor is configured to receive a timing packet comprising i) a timestamp, and ii) a value of a correction field generated based on a clock maintained by a host processor of the network device, and The PHY device is configured to embed the timing information in the timing packet at least by updating the value of the correction field based on a clock maintained by the PHY device of the network device.

17. The network device according to claim 16, wherein The MAC processor is configured to generating a PHY tag to include an offset indicator field, the offset indicator field being set to indicate an offset of a correction field in the timing packet relative to a delimiter field of the timing packet, generating a control header to include the PHY tag in an extension field of the control header, and replacing the preamble at the beginning of the timing packet with the control header before transmitting the timing packet to the PHY device, and The PHY device is configured to update the correction field at the offset indicated by the offset indicator field and not parse the timing packet to locate the correction field within the timing packet.

18. The network device according to claim 17, wherein The MAC processor is configured to generate the PHY tag to further include a checksum update indicator field, the checksum update indicator field being set to indicate whether the timing packet requires a checksum update, and The PHY device is configured as determining whether the timing packet requires a checksum update based on the checksum update indicator field, and In response to determining that the timing packet requires a checksum update, an incremental update of a checksum trailer field in the timing packet is performed.

19. The network device according to claim 17, wherein The MAC processor is configured to generate the PHY tag to further include a timestamp least significant bit (LSB) field, wherein the timestamp LSB field indicates whether wraparound of a correction field value is to be interpreted by the PHY device, and The PHY device is configured as determining whether wraparound of the correction field value is to be accounted for by the PHY device based on the timestamp LSB field, and In response to determining that the wrap-around of the correction field value is to be accounted for by the PHY device, updating the correction field to account for the wrap-around in the correction field.

20. A method for embedding timing information in a timing packet to be transmitted by a network device, the method comprising: receiving, at a physical layer (PHY) device of the network device, a timing packet to be transmitted by the network device, the timing packet including initial timing information provided by one or both of i) a media access control (MAC) processor and ii) a host processor of the network device; receiving, at the PHY device, from the MAC processor, one or more indicators of parameters to be used by the PHY device for embedding timing information in the timing packet, the one or more indicators indicating at least i) a type of packet into which the timing packet is to be embedded by the PHY device, ii) a position of a field in the timing packet at which the timing information is to be embedded by the PHY device in the timing packet, and iii) whether the timing information in the timing packet needs to be updated by the PHY device; updating, by the PHY device, the initial timing information in the timing packet based on the one or more indicators to embed final timing information in the timing packet; as well as The timing packets are forwarded by the PHY device to one or more network ports of the network device for transmission of the timing packets from the network device.

21. The method according to claim 20, wherein Receiving the one or more indicators includes: receiving a control header inserted into the timing packet by the MAC processor, wherein the control header includes the one or more indicators, and Updating the timing information in the timing packet includes updating the timing information based on the one or more indicators included in the control header, and not classifying the timing packet as a timing packet by the PHY device.

22. The method according to claim 20, wherein Receiving the timing packet includes receiving a timing packet including: i) a timestamp and ii) a correction field value generated based on a clock maintained by a host processor of the network device, and Updating the timing information in the timing group includes: The correction field value in the timing packet is updated based on a clock maintained by the PHY device.

23. The method of claim 20, wherein receiving the timing packet comprises receiving one of: i) a timing packet generated by a host processor of the network device, or ii) receiving a timing packet previously received by the network device, the timing packet previously received by the network device including a correction field for indicating a residence time of the timing packet in the network device, and Updating the initial timing information in the timing packet to embed final timing information in the timing packet includes updating initial timing information indicating one of: i) a time corresponding to transmission of the timing packet from the network device, or ii) a residence time of the timing packet in the network device.

24. The method of claim 20, wherein Receiving the one or more indicators comprises receiving a PHY tag included in a control header at a predetermined location within the timing packet, and The method also includes retrieving, by the PHY device, the PHY tag from the control header at the predetermined location within the timing packet of the PHY device.

25. The method of claim 24, wherein retrieving the PHY tag comprises: The PHY tag is retrieved from the control header that replaces the preamble at the beginning of the timing packet.

26. The method of claim 24, wherein The PHY tag includes an offset indicator field, the offset indicator field being arranged to indicate an offset of a correction field in the timing packet relative to a delimiter field of the timing packet, and Updating the initial timing information in the timing packet to embed the final timing information comprises: The correction field is updated at the offset indicated by the offset indicator field, and the timing packet is not parsed by the PHY device to locate the correction field within the timing packet.

27. The method according to claim 26, wherein The PHY further includes a checksum update indicator field, the checksum update indicator field being configured to indicate whether the timing packet requires a checksum update. Updating the initial timing information in the timing packet to embed the final timing information comprises determining whether the timing packet requires a checksum update based on the checksum update indicator field, and In response to determining that the timing packet requires a checksum update, an incremental update of a checksum trailer field in the timing packet is performed.

28. The method of claim 26, wherein The PHY further includes a Timestamp LSB field, wherein the Timestamp LSB field indicates whether wraparound of a correction field value is to be accounted for by the PHY device. Updating the initial timing information in the timing packet to embed the final timing information comprises determining whether wraparound of the correction field value is to be accounted for by the PHY device based on the timestamp LSB field, and In response to determining that the wrap-around of the correction field value is to be accounted for by the PHY device, updating the correction field to account for the wrap-around in the correction field.

29. A network device configured to operate in a network, the network device comprising: Physical layer PHY device processor, configured as receiving a timing packet to be transmitted by the network device, the timing packet including initial timing information provided by one or both of i) a media access control (MAC) processor and ii) a host processor of the network device; receiving one or more indicators of parameters to be used by the PHY device for embedding timing information in the timing packet, the one or more indicators indicating at least i) a type of packet into which the timing packet is to be embedded by the PHY device, ii) a position of a field in the timing packet at which the timing information is to be embedded by the PHY device, and iii) whether the timing information in the timing packet needs to be updated by the PHY device; updating the initial timing information in the timing packet based on the one or more indicators to embed final timing information in the timing packet; as well as The timing packets are forwarded to one or more network ports of the network device for transmission of the timing packets from the network device.

30. The network device of claim 29, wherein the PHY device is configured to receiving a timing packet comprising i) a timestamp and ii) a correction field value generated based on a clock maintained by a host processor of the network device, and The correction field value in the timing packet is updated based on a clock maintained by the PHY device.

31. The network device of claim 29, wherein the PHY device is configured to receiving one of: i) a timing packet generated by a host processor of the network device, or ii) receiving a timing packet previously received by the network device, the timing packet previously received by the network device including a correction field for indicating a residence time of the timing packet in the network device, and The initial timing information in the timing packet is updated to embed final timing information in the timing packet by at least updating initial timing information indicating one of the following: i) a time corresponding to transmission of the timing packet from the network device, or ii) a residence time of the timing packet in the network device.

32. The network device of claim 29, wherein the PHY device is configured to receiving from the MAC processor a control header inserted into the timing packet by the MAC processor, wherein the control header includes the one or more indicators, and The timing information is updated based on the one or more indicators in the control header, and the timing packet is not classified as a timing packet by the PHY device.

33. The network device of claim 32, wherein The control header i) is inserted into the timing packet at a predetermined position within the timing packet, and ii) includes a PHY tag in an extension field of the control header, and The PHY device is configured to retrieve the PHY tag from the control header at the predetermined position within the timing packet of the PHY device.

34. The network device of claim 33, wherein the PHY device is configured to retrieve the PHY tag from the control header that replaces a preamble at the beginning of the timing packet.

35. The network device of claim 34, wherein The PHY tag includes an offset indicator field, the offset indicator field being arranged to indicate an offset of a correction field in the timing packet relative to a delimiter field of the timing packet, and The PHY device is configured to update the correction field at the offset indicated by the offset indicator field and not parse the timing packet to locate the correction field within the timing packet.

36. The network device of claim 35, wherein The PHY tag further includes a checksum update indicator field, the checksum update indicator field being configured to indicate whether the timing packet requires a checksum update, and The PHY device is configured as determining whether the timing packet requires a checksum update based on the checksum update indicator field, and In response to determining that the timing packet requires a checksum update, an incremental update of a checksum trailer field in the timing packet is performed.

37. The network device of claim 35, wherein The PHY tag further includes a Timestamp LSB field, wherein the Timestamp LSB field indicates whether wraparound of the correction field value is to be interpreted by the PHY device, and The PHY device is configured as determining whether wraparound of the correction field value is to be accounted for by the PHY device based on the timestamp LSB field, and In response to determining that the wrap-around of the correction field value is to be accounted for by the PHY device, updating the correction field to account for the wrap-around in the correction field.

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