Semiconductor structure, preparation method of semiconductor structure and electronic equipment

Abstract

The invention relates to a semiconductor structure and a preparation method thereof. The preparation method of the semiconductor structure comprises the following steps: forming a stack structure on a substrate, wherein the stack structure comprises a plurality of sacrificial layers and a plurality of interlayer dielectric layers which are alternately stacked along a direction vertical to the substrate; wherein the sacrificial layer comprises a non-metallic material; etching the stack structure to form an etching groove and a first word line definition hole; the etching groove penetrates through the stacking structure in the direction perpendicular to the substrate and extends in the first direction; the first word line defining hole is located on the side of the etching groove in the second direction, and a gap is formed between the first word line defining hole and the etching groove. According to the preparation method of the semiconductor structure, a sacrificial layer in a stack structure comprises a non-metal sacrificial layer, an etching groove and a first word line definition hole formed by etching the stack structure have side walls with relatively high steepness, and the surfaces of the side walls are flat and smooth, so that the production yield and the use reliability of the semiconductor structure are improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and particularly to a semiconductor structure, a method for manufacturing the semiconductor structure, and an electronic device. Background Art

[0002] With the development of integrated circuit technology, the critical dimensions of devices are increasingly reduced, and the types and quantities of devices included in a single chip increase accordingly, making any minor difference in the process production likely to affect the device performance.

[0003] In order to reduce the cost of products as much as possible, it is desired to fabricate as many device units as possible on a limited substrate. Since Moore's law came out, various semiconductor structure designs and process optimizations have been proposed in the industry to meet the requirements of current products. Summary of the Invention

[0004] Based on this, the present application provides a semiconductor structure, a method for manufacturing the semiconductor structure, and an electronic device, which are beneficial to improving the production yield and use reliability of the semiconductor structure.

[0005] To achieve the above object, on the one hand, the present application provides a method for manufacturing a semiconductor structure according to some embodiments. The semiconductor structure includes a first transistor and a second transistor. A first gate of the first transistor is connected to a first word line, a first source / drain of the first transistor is connected to a first bit line, and a second source / drain of the first transistor is connected to a storage gate; the storage gate also serves as a back gate of the second transistor;

[0006] The manufacturing method includes:

[0007] Providing a substrate; forming a stacked structure on the substrate, the stacked structure including multiple layers of sacrificial layers and multiple layers of interlayer dielectric layers alternately stacked in a direction perpendicular to the substrate; wherein, the sacrificial layer includes a non-metallic material;

[0008] Etching the stacked structure to form an etching groove and a first word line defining hole; the etching groove penetrates the stacked structure in a direction perpendicular to the substrate and extends in a first direction; the first word line defining hole is located beside the etching groove in a second direction and has a gap with the etching groove; the first direction intersects with the second direction and both are parallel to the substrate;

[0009] Etch each of the sacrificial layers laterally based on the etch groove and the first word line definition hole to form a first transistor accommodation groove and a first bit line accommodation groove; the first transistor accommodation groove is located in a first etch region of the sacrificial layer and surrounds the periphery of the first word line definition hole; the first bit line accommodation groove is located in a second etch region of the sacrificial layer and is located between the first transistor accommodation groove and the etch groove; the second etch region and the first etch region are connected;

[0010] Form a storage gate on a side of the first transistor accommodation groove facing away from the first bit line accommodation groove.

[0011] In some embodiments, forming the storage gate on a side of the first transistor accommodation groove facing away from the first bit line accommodation groove includes:

[0012] Form a conductive material layer filling the etch groove, the first word line definition hole, the first transistor accommodation groove, and the first bit line accommodation groove;

[0013] Remove a part of the conductive material layer to retain the conductive material layer formed on a side of the first transistor accommodation groove facing away from the first bit line accommodation groove; the retained conductive material layer serves as the storage gate.

[0014] In some embodiments, the conductive material layer filling the etch groove, the first word line definition hole, the first transistor accommodation groove, and the first bit line accommodation groove is formed by an atomic layer deposition process.

[0015] In some embodiments, the interlayer dielectric layer is formed at least of an oxide material, and the sacrificial layer is formed at least of one of a nitride material and a polysilicon material.

[0016] In some embodiments, the method for preparing the semiconductor structure further includes:

[0017] Form a gate dielectric layer and a first word line in the first word line definition hole in sequence;

[0018] Fill a first semiconductor layer in the first transistor accommodation groove; the first semiconductor layer surrounds the sidewall of the gate dielectric layer and covers the inner wall of the first bit line accommodation groove;

[0019] Form a first bit line in the first bit line accommodation groove that covers the first semiconductor layer and fills the first bit line accommodation groove.

[0020] In some embodiments, before etching the stacked structure to form an etch groove and a first word line definition hole, the method for preparing the semiconductor structure further includes:

[0021] Etching the stack structure to form first through holes and isolation grooves that are spaced apart and penetrate the stack structure; etching each sacrificial layer laterally based on the first through holes and the isolation grooves to form second transistor accommodating grooves and second bit line accommodating grooves;

[0022] An insulating dielectric layer and a second semiconductor layer are sequentially formed on the sidewalls of the second transistor receiving groove and the sidewalls of the second bit line receiving groove; wherein the insulating dielectric layer also covers the sidewalls of the first through hole and the sidewalls of the isolation groove;

[0023] A second bit line is formed in the second bit line receiving groove, covering the second semiconductor layer and filling the second bit line receiving groove; a second bit line isolation structure is formed in the isolation groove; and a second word line is formed in the first through hole;

[0024] The storage gate is formed on a side of the second semiconductor layer away from the second bit line, and the insulating dielectric layer is located between the second semiconductor layer and the storage gate.

[0025] On the other hand, the present application also provides a semiconductor structure according to some embodiments, including:

[0026] substrate;

[0027] A plurality of memory cells; the memory cells include a first transistor and a second transistor; the first transistor and the second transistor in the same memory cell are arranged and connected along a second direction; the second direction is parallel to the substrate; the second transistor includes a second semiconductor layer, a second word line dielectric layer, a storage gate and a second gate; the second semiconductor layer at least partially surrounds the second gate, the second semiconductor layer and the second word line dielectric layer are provided between the storage gate and the second gate, and the storage gate at least partially surrounds the second semiconductor layer.

[0028] In some embodiments, the semiconductor structure further includes a second bit line; the second bit line extends along a first direction; the first direction is parallel to the substrate and intersects with the second direction;

[0029] The second semiconductor layer at least partially surrounds the second bit line, and the second semiconductor layer is in contact with the second bit line.

[0030] In some embodiments, the semiconductor structure further includes a second word line;

[0031] The second word line extends in a direction perpendicular to the substrate; the second gate is a part of the second word line; the second word line includes a first main body portion perpendicular to the substrate, and a first protruding portion extending from the first main body portion in the second direction; both the top surface of the first protruding portion away from the substrate and the bottom surface close to the substrate are connected to the second semiconductor layer through the second word line dielectric layer.

[0032] In some embodiments, the semiconductor structure further includes a ground wire;

[0033] The ground wire includes a second main body portion perpendicular to the substrate, and a second protruding portion extending from the second main body portion in the second direction; the second protruding portion is at least partially surrounded and contacted by the second semiconductor layer.

[0034] In some embodiments, the semiconductor structure further includes a first through hole;

[0035] The first main body portion and the second main body portion are arranged in parallel in the first through hole, and the second word line dielectric layer is provided between the first main body portion and the second main body portion.

[0036] In some embodiments, the semiconductor structure further includes:

[0037] A first word line defining hole, perpendicular to the substrate; a first word line and a gate dielectric layer are provided in the first word line defining hole, and the gate dielectric layer is located between the first word line and the side wall of the first word line defining hole;

[0038] A first transistor accommodating groove, surrounding the periphery of the first word line defining hole; the first transistor accommodating groove is filled with a first semiconductor layer.

[0039] In some embodiments, the first word line defining hole and the first transistor accommodating groove are communicated.

[0040] In some embodiments, the first semiconductor layer surrounds the side wall of the gate dielectric layer.

[0041] In some embodiments, the semiconductor structure further includes:

[0042] A first bit line, extending in the first direction;

[0043] A first bit line accommodating groove, the first bit line is arranged in the first bit line accommodating groove; the first bit line accommodating groove and the first transistor accommodating groove are communicated.

[0044] In another aspect, the present application also provides an electronic device according to some embodiments, including some of the foregoing semiconductor structures.

[0045] The semiconductor structure, the manufacturing method of the semiconductor structure, and the electronic device provided by the present application can / at least have the following advantages:

[0046] In the embodiment of the present application, the stacked structure formed on the substrate includes multiple layers of sacrificial layers and multiple layers of interlayer dielectric layers alternately stacked in a direction perpendicular to the substrate; wherein, the sacrificial layer includes a non-metallic material. There is no significant difference in the chemical properties between the non-metallic sacrificial layer and the interlayer dielectric layer. Therefore, the etched grooves and the first word line defining holes formed by etching the above stacked structure have side walls with relatively high steepness, and the side wall surfaces are flat and smooth, which is beneficial to improving the production yield and use reliability of the semiconductor structure. The side walls of the etched grooves and the first word line defining holes are formed into a contour with relatively high steepness and a flat and smooth surface, which is also beneficial to the adhesion of the subsequent filling material, improving the filling quality, and further beneficial to improving the production yield and use reliability of the semiconductor structure.

[0047] In the semiconductor structure provided by the embodiment of the present application, by making the second semiconductor layer at least partially surround the second gate, a CAA structure can be formed to increase the gate control ability of the main gate; by making the storage gate at least partially surround the second semiconductor layer, a GAA structure can be formed to improve the control ability of the storage gate, and at the same time increase the voltage holding ability of the storage gate and the data storage ability of the semiconductor structure. Description of the Drawings

[0048] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0049] Figure 1 It is a schematic flowchart of the manufacturing method of the semiconductor structure provided in some embodiments of the present application;

[0050] Figure 2 It is a schematic flowchart of step S500 in the manufacturing method of the semiconductor structure provided in some embodiments of the present application;

[0051] Figure 3 It is a schematic flowchart of the manufacturing method of the semiconductor structure provided in some other embodiments of the present application;

[0052] Figure 4 It is a schematic flowchart of the manufacturing method of the semiconductor structure provided in some other embodiments of the present application;

[0053] Figure 5 Figure (a) in [reference] is a schematic top view structure diagram of the structure obtained after forming the stacked structure in some embodiments of the present application;Figure 5 Figure (a) in [[ ]] is also a top view structural schematic diagram of a semiconductor structure provided in some embodiments of the present application; Figure 5 Figure (b) in [[ ]] is Figure 5 a cross-sectional structural schematic diagram perpendicular to the substrate in the direction of AA' of the structure shown in Figure (a) in [[ ]];

[0054] Figure 6 Figure (a) in [[ ]] is a top view structural schematic diagram of the structure obtained after forming a separation structure in some embodiments of the present application; Figure 6 Figure (b) in [[ ]] is Figure 6 a cross-sectional structural schematic diagram perpendicular to the substrate in the direction of AA' of the structure shown in Figure (a) in [[ ]]; Figure 6 Figure (c) in [[ ]] is Figure 6 a cross-sectional structural schematic diagram perpendicular to the substrate in the direction of BB' of the structure shown in Figure (a) in [[ ]];

[0055] Figure 7 Figure (a) in [[ ]] is a top view structural schematic diagram of the structure obtained after forming a first through hole, an isolation groove, a second transistor accommodation groove, and a second bit line accommodation groove in some embodiments of the present application; Figure 7 Figure (b) in [[ ]] is Figure 7 a cross-sectional structural schematic diagram perpendicular to the substrate in the direction of AA' of the structure shown in Figure (a) in [[ ]]; Figure 7 Figure (c) in [[ ]] is Figure 7 a cross-sectional structural schematic diagram perpendicular to the substrate in the direction of BB' of the structure shown in Figure (a) in [[ ]];

[0056] Figure 8 Figure (a) in [[ ]] is a top view structural schematic diagram of the structure obtained after forming a sacrificial dielectric layer in some embodiments of the present application; Figure 8 Figure (b) in [[ ]] is Figure 8 a cross-sectional structural schematic diagram perpendicular to the substrate in the direction of AA' of the structure shown in Figure (a) in [[ ]]; Figure 8 Figure (c) in [[ ]] is Figure 8 a cross-sectional structural schematic diagram perpendicular to the substrate in the direction of BB' of the structure shown in Figure (a) in [[ ]];

[0057] Figure 9 Figure (a) in [[ ]] is a top view structural schematic diagram of the structure obtained after forming a second semiconductor layer in some embodiments of the present application; Figure 9 Figure (b) in [[ ]] is Figure 9 a cross-sectional structural schematic diagram perpendicular to the substrate in the direction of AA' of the structure shown in Figure (a) in [[ ]]; Figure 9 Figure (c) in [[ ]] is Figure 9 a cross-sectional structural schematic diagram perpendicular to the substrate in the direction of BB' of the structure shown in Figure (a) in [[ ]];

[0058] Figure 10Figure (a) in [this] shows a top - view structural schematic diagram of the structure obtained after forming the second bit - line material layer in some embodiments of the present application; Figure 10 Figure (b) in [this] shows Figure 10 a cross - sectional structural schematic diagram perpendicular to the substrate along the AA' direction of the structure shown in Figure (a) in [this]; Figure 10 Figure (c) in [this] shows Figure 10 a cross - sectional structural schematic diagram perpendicular to the substrate along the BB' direction of the structure shown in Figure (a) in [this];

[0059] Figure 11 Figure (a) in [this] shows a top - view structural schematic diagram of the structure obtained after forming the second bit - line in some embodiments of the present application; Figure 11 Figure (b) in [this] shows Figure 11 a cross - sectional structural schematic diagram perpendicular to the substrate along the AA' direction of the structure shown in Figure (a) in [this]; Figure 11 Figure (c) in [this] shows Figure 11 a cross - sectional structural schematic diagram perpendicular to the substrate along the BB' direction of the structure shown in Figure (a) in [this];

[0060] Figure 12 Figure (a) in [this] shows a top - view structural schematic diagram of the structure obtained after forming the ground - wire in some embodiments of the present application; Figure 12 Figure (b) in [this] shows Figure 12 a cross - sectional structural schematic diagram perpendicular to the substrate along the AA' direction of the structure shown in Figure (a) in [this]; Figure 12 Figure (c) in [this] shows Figure 12 a cross - sectional structural schematic diagram perpendicular to the substrate along the BB' direction of the structure shown in Figure (a) in [this];

[0061] Figure 13 Figure (a) in [this] shows a top - view structural schematic diagram of the structure obtained after forming the second word - line definition hole in some embodiments of the present application; Figure 13 Figure (b) in [this] shows Figure 13 a cross - sectional structural schematic diagram perpendicular to the substrate along the AA' direction of the structure shown in Figure (a) in [this]; Figure 13 Figure (c) in [this] shows Figure 13 a cross - sectional structural schematic diagram perpendicular to the substrate along the BB' direction of the structure shown in Figure (a) in [this];

[0062] Figure 14 Figure (a) in [this] shows a top - view structural schematic diagram of the structure obtained after forming the second word - line in some embodiments of the present application; Figure 14 Figure (b) in [this] shows Figure 14 a cross - sectional structural schematic diagram perpendicular to the substrate along the AA' direction of the structure shown in Figure (a) in [this]; Figure 14 Figure (c) in [this] shows Figure 14 a cross - sectional structural schematic diagram perpendicular to the substrate along the BB' direction of the structure shown in Figure (a) in [this];

[0063] Figure 15 Figure (a) in [reference] is a top view structural schematic diagram of the structure obtained after forming an etching groove and a first word line defining hole in some embodiments of the present application; Figure 15 Figure (b) in [reference] is Figure 15 a cross-sectional structural schematic diagram perpendicular to the substrate along the AA' direction of the structure shown in Figure (a) in [reference]; Figure 15 Figure (c) in [reference] is Figure 15 a cross-sectional structural schematic diagram perpendicular to the substrate along the BB' direction of the structure shown in Figure (a) in [reference];

[0064] Figure 16 Figure (a) in [reference] is a top view structural schematic diagram of the structure obtained after forming a conductive material layer in some embodiments of the present application; Figure 16 Figure (b) in [reference] is Figure 16 a cross-sectional structural schematic diagram perpendicular to the substrate along the AA' direction of the structure shown in Figure (a) in [reference]; Figure 16 Figure (c) in [reference] is Figure 16 a cross-sectional structural schematic diagram perpendicular to the substrate along the BB' direction of the structure shown in Figure (a) in [reference];

[0065] Figure 17 Figure (a) in [reference] is a top view structural schematic diagram of the structure obtained after forming a storage gate in some embodiments of the present application; Figure 17 Figure (b) in [reference] is Figure 17 a cross-sectional structural schematic diagram perpendicular to the substrate along the AA' direction of the structure shown in Figure (a) in [reference]; Figure 17 Figure (c) in [reference] is Figure 17 a cross-sectional structural schematic diagram perpendicular to the substrate along the BB' direction of the structure shown in Figure (a) in [reference];

[0066] Figure 18 Figure (a) in [reference] is a top view structural schematic diagram of the structure obtained after forming a sacrificial material layer in some embodiments of the present application; Figure 18 Figure (b) in [reference] is Figure 18 a cross-sectional structural schematic diagram perpendicular to the substrate along the AA' direction of the structure shown in Figure (a) in [reference]; Figure 18 Figure (c) in [reference] is Figure 18 a cross-sectional structural schematic diagram perpendicular to the substrate along the BB' direction of the structure shown in Figure (a) in [reference];

[0067] Figure 19 Figure (a) in [reference] is a top view structural schematic diagram of the structure obtained after forming a gate dielectric layer and a first word line in some embodiments of the present application; Figure 19 Figure (b) in [reference] is Figure 19 a cross-sectional structural schematic diagram perpendicular to the substrate along the AA' direction of the structure shown in Figure (a) in [reference]; Figure 19 Figure (c) in [reference] is Figure 19 a cross-sectional structural schematic diagram perpendicular to the substrate along the BB' direction of the structure shown in Figure (a) in [reference];

[0068] Figure 20 In the (a) figure, it is a top view structural schematic diagram of the structure obtained after exposing a part of the sidewall of the gate dielectric layer in some embodiments of the present application; Figure 20 In the (b) figure, it is Figure 20 a cross-sectional structural schematic diagram perpendicular to the substrate along the AA' direction of the structure shown in the (a) figure in Figure 20 In the (c) figure, it is Figure 20 a cross-sectional structural schematic diagram perpendicular to the substrate along the BB' direction of the structure shown in the (a) figure in

[0069] Figure 21 In the (a) figure, it is a top view structural schematic diagram of the structure obtained after forming the first bit line material layer in some embodiments of the present application; Figure 21 In the (b) figure, it is Figure 21 a cross-sectional structural schematic diagram perpendicular to the substrate along the AA' direction of the structure shown in the (a) figure in Figure 21 In the (c) figure, it is Figure 21 a cross-sectional structural schematic diagram perpendicular to the substrate along the BB' direction of the structure shown in the (a) figure in

[0070] Figure 22 In the (a) figure, it is a top view structural schematic diagram of the structure obtained after forming the first semiconductor layer and the first bit line in some embodiments of the present application; Figure 22 In the (b) figure, it is Figure 22 a cross-sectional structural schematic diagram perpendicular to the substrate along the AA' direction of the structure shown in the (a) figure in Figure 22 In the (c) figure, it is Figure 22 a cross-sectional structural schematic diagram perpendicular to the substrate along the BB' direction of the structure shown in the (a) figure in

[0071] Figure 23 In the (a) figure, it is a top view structural schematic diagram of the structure obtained after forming the first bit line isolation structure in some embodiments of the present application, Figure 23 In the (a) figure, it is also a top view structural schematic diagram of the semiconductor structure provided in some other embodiments of the present application; Figure 23 In the (b) figure, it is Figure 23 a cross-sectional structural schematic diagram perpendicular to the substrate along the AA' direction of the structure shown in the (a) figure in Figure 23 In the (c) figure, it is Figure 23 a cross-sectional structural schematic diagram perpendicular to the substrate along the BB' direction of the structure shown in the (a) figure in Figure 23 In the (d) figure, it is Figure 23 a cross-sectional structural schematic diagram parallel to the substrate along the CC' direction of the structure shown in the (b) figure;

[0072] Figure 24A schematic three-dimensional structure diagram of a semiconductor structure provided in some embodiments of the present application;

[0073] Figure 25 is Figure 24 the front view of the structure shown;

[0074] Figure 26 is Figure 24 a schematic cross-sectional structure diagram of a memory cell in the structure shown parallel to the substrate;

[0075] Figure 27 is Figure 23 the equivalent circuit diagram of the structure shown;

[0076] Figure 28 is Figure 26 the equivalent circuit diagram of the memory cell shown.

[0077] Explanation of reference numerals:

[0078] 1. Substrate; 11. Partition groove; 12. Partition structure; 13. Ground layer; 2. Stacked structure; 21. Sacrificial layer; 22. Interlayer dielectric layer; 23. Capping layer; 31. Gate dielectric layer; 32. First bit line isolation structure; 320. First bit line material layer; 33. Second word line dielectric layer; 331. First main body; 332. First protruding part; 34. Second bit line isolation structure; 340. Second bit line material layer; 35. First word line dielectric layer; 371. Second main body; 372. Second protruding part; 41. First semiconductor layer; 411. First semiconductor material layer; 42. Second semiconductor layer; 421. Second semiconductor material layer; 43. Memory gate; 431. Conductive material layer; 51. Sacrificial dielectric layer; 52. Insulating dielectric layer; 53. Filling dielectric layer; 54. Sacrificial material layer; U. Memory cell; T1. Second transistor; T2. First transistor; SN. Memory node; WWL. First word line; WBL. First bit line; RWL. Second word line; RBL. Second bit line; GND. Ground wire; E1. Isolation groove; E2. Etching groove; H1. First through hole; H2. First word line definition hole; H3. Second word line definition hole; H4. Second through hole; G1. Second transistor accommodation groove; G2. Second bit line accommodation groove; G3. First transistor accommodation groove; G4. First bit line accommodation groove; G5. Capacitor accommodation groove. Detailed implementation manners

[0079] To facilitate the understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. Preferred embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0080] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terms used herein in the specification of this application are for the purpose of describing particular embodiments only and are not intended to limit this application.

[0081] It should be understood that when an element or layer is referred to as being “on” another element or layer, it can be directly on the other element or layer or there can be intervening elements or layers. It should be understood that although the terms first, second, etc. may be used herein to describe various elements, components, regions, layers, etch regions, and / or portions, these elements, components, regions, layers, etch regions, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, etch region, or portion from another element, component, region, layer, etch region, or portion. Thus, without departing from the teachings of this application, a first element, component, region, layer, etch region, or portion discussed below could be denoted as a second element, component, region, layer, or portion; for example, a first etch region could be referred to as a second etch region, and similarly, a second etch region could be referred to as a first etch region; the first etch region and the second etch region are different etch regions.

[0082] Spatial relationship terms such as “on” etc. can be used herein to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientation shown in the figures, spatial relationship terms also include different orientations of the device during use and operation. For example, if the device in the figures is flipped, an element or feature described as being “on” another element will be oriented as “under” the other element or feature. Thus, the exemplary term “on” can include both an upper and a lower orientation. In addition, the device can also include additional orientations (such as, rotated 90 degrees or other orientations), and the spatial descriptors used herein are to be interpreted accordingly.

[0083] As used herein, the singular forms “a,” “an,” and “the” may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that when the terms “comprise” and / or “include” are used in this specification, the presence of the stated features, integers, steps, operations, elements, and / or components can be identified, but one or more other features, integers, steps, operations, elements, components, and / or groups may not be excluded. Also, as used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0084] It should be noted that the illustrations provided in this embodiment only schematically illustrate the basic concept of the present application. Although only the components related to the present application are shown in the illustrations and are not drawn according to the number, shape, and size of the components in actual implementation, the types, quantities, and proportions of the components in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0085] The present application provides a semiconductor structure, a method for manufacturing the semiconductor structure, and an electronic device, which are beneficial to improving the production yield and use reliability of the semiconductor structure. The detailed content will be elaborated in the subsequent embodiments.

[0086] On the one hand, according to some embodiments, the present application provides a method for manufacturing a semiconductor structure. The semiconductor structure includes a first transistor and a second transistor. The first gate of the first transistor is connected to a first word line, the first source / drain of the first transistor is connected to a first bit line, and the second source / drain of the first transistor is connected to a storage gate; the storage gate simultaneously serves as the back gate of the second transistor.

[0087] Please refer to Figure 1 , in some embodiments, the method for manufacturing the semiconductor structure may specifically include the following steps:

[0088] S100: Provide a substrate; form a stacked structure on the substrate, the stacked structure including multiple layers of sacrificial layers and multiple layers of interlayer dielectric layers alternately stacked in a direction perpendicular to the substrate; wherein, the sacrificial layer includes a non-metallic material.

[0089] S300: Etch the stacked structure to form an etch groove and a first word line definition hole; the etch groove penetrates the stacked structure in a direction perpendicular to the substrate and extends in a first direction; the first word line definition hole is located beside the etch groove in a second direction and has a gap with the etch groove; the first direction intersects with the second direction and both are parallel to the substrate.

[0090] S400: Transversely etch each sacrificial layer based on the etch groove and the first word line definition hole to form a first transistor accommodation groove and a first bit line accommodation groove; the first transistor accommodation groove is located in a first etching area of the sacrificial layer and surrounds the periphery of the first word line definition hole; the first bit line accommodation groove is located in a second etching area of the sacrificial layer and is located between the first transistor accommodation groove and the etch groove; the second etching area and the first etching area are connected.

[0091] S500: Form a storage gate on a side of the first transistor accommodation groove facing away from the first bit line accommodation groove.

[0092] In the method for manufacturing a semiconductor structure provided in the above embodiments, the stacked structure formed on the substrate includes multiple layers of sacrificial layers and multiple layers of interlayer dielectric layers alternately stacked in a direction perpendicular to the substrate; wherein, the sacrificial layer includes a non-metallic material. There is no significant difference in the chemical properties between the non-metallic sacrificial layer and the interlayer dielectric layer. Therefore, the etching grooves and the first word line definition holes formed by etching the above stacked structure have sidewalls with a relatively high steepness, and the sidewall surfaces are flat and smooth, which is beneficial to improving the production yield and use reliability of the semiconductor structure. The sidewalls of the etching grooves and the first word line definition holes are formed into a contour with a relatively high steepness and a flat and smooth surface, which is also beneficial to the adhesion of the subsequent filling material, improving the filling quality, and further beneficial to improving the production yield and use reliability of the semiconductor structure.

[0093] Please refer to Figure 2 , in some embodiments, step S500 forms a storage gate on a side of the first transistor accommodation groove away from the first bit line accommodation groove, and specifically may include the following steps:

[0094] S510: Form a conductive material layer filling the etching groove, the first word line definition hole, the first transistor accommodation groove, and the first bit line accommodation groove.

[0095] S520: Remove a part of the conductive material layer to retain the conductive material layer formed on a side of the first transistor accommodation groove away from the first bit line accommodation groove; the retained conductive material layer serves as the storage gate.

[0096] Please refer to Figure 3 , in some embodiments, the method for manufacturing the semiconductor structure may further include the following steps:

[0097] S610: Sequentially form a gate dielectric layer and a first word line in the first word line definition hole.

[0098] S620: Fill a first semiconductor layer in the first transistor accommodation groove; the first semiconductor layer surrounds the sidewalls of the gate dielectric layer and covers the inner wall of the first bit line accommodation groove.

[0099] S630: Form a first bit line in the first bit line accommodation groove, covering the first semiconductor layer and filling the first bit line accommodation groove.

[0100] It can be understood that in the method for manufacturing a semiconductor structure provided in the above embodiments, a gate dielectric layer and a first word line are sequentially formed in the first word line definition hole, and a first semiconductor layer surrounding the sidewalls of the gate dielectric layer is formed, so that the first semiconductor layer surrounds the first word line, making the first transistor have a Channel-All-Around (CAA) structure, which is beneficial to saving the structure size. Therefore, when the above semiconductor structure is applied to the manufacturing process of a memory, the storage density of the memory can be improved.

[0101] Please refer to Figure 4 , in some embodiments, before step S300 etches the stacked structure to form an etching groove and a first word line defining hole, the method for manufacturing the semiconductor structure may further include the following steps:

[0102] S210: Etch the stacked structure to form first through holes and isolation grooves that are spaced apart and penetrate the stacked structure; laterally etch each sacrificial layer based on the first through holes and the isolation grooves to form a second transistor accommodating groove and a second bit line accommodating groove.

[0103] S220: Sequentially form an insulating dielectric layer and a second semiconductor layer on the sidewalls of the second transistor accommodating groove and the sidewalls of the second bit line accommodating groove; wherein, the insulating dielectric layer also covers the sidewalls of the first through holes and the isolation grooves.

[0104] S230: Form a second bit line in the second bit line accommodating groove that covers the second semiconductor layer and fills the second bit line accommodating groove; fill the isolation groove to form a second bit line isolation structure; fill the first through hole to form a second word line.

[0105] It should be understood that although Figures 1 to 4 the steps in the flowchart are shown sequentially according to the indication of the arrows, these steps are not necessarily executed sequentially according to the order indicated by the arrows. Unless there is a clear description in this article, the execution of these steps has no strict order limitation, and these steps can be executed in other orders. Moreover, Figures 1 to 4 at least a part of the steps in

[0106] may include multiple steps or multiple stages. These steps or stages are not necessarily executed at the same moment, but can be executed at different moments, and the execution order of these steps or stages is not necessarily sequential, but can be executed alternately or in turn with at least a part of other steps or steps or stages in other steps.

[0106] To more clearly illustrate the method for manufacturing the semiconductor structure provided in the above-mentioned some embodiments, the following will be combined with Figures 5 to 23 to understand some embodiments of the present application.

[0107] It should be noted that the first direction and the second direction involved in the embodiments of the present application intersect. For the convenience of understanding, in the embodiments of the present application, the first direction is taken as the Y direction and the second direction is taken as the X direction for exemplary illustration.

[0108] It should also be noted that, as an example, the first transistor may be a write transistor, and the second transistor may be a read transistor; or, the first transistor may be a read transistor, and the second transistor may be a write transistor. In the embodiments of the present application, the first transistor is taken as a write transistor and the second transistor is taken as a read transistor for exemplary illustration.

[0109] In step S100, as shown in FIG. (a) of Figure 5 and FIG. (b) of Figure 5 , a substrate 1 is provided, and a stacked structure 2 is formed on the substrate 1. The stacked structure 2 may include multiple layers of sacrificial layers 21 and multiple layers of interlayer dielectric layers 22 alternately stacked in a direction perpendicular to the substrate 1. Among them, the sacrificial layer 21 includes a non-metallic material. In the embodiments of the present application, the direction perpendicular to the substrate 1 is taken as the Z direction for exemplary illustration.

[0110] The embodiments of the present application do not specifically limit the constituent material of the substrate 1. As an example, the substrate 1 may be composed of a semiconductor material, an insulating material, a conductor material, or any combination of their material types. The substrate 1 may be a single-layer structure or a multi-layer structure. For example, the substrate 1 may be a substrate such as a silicon (Si) substrate 1, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Or, for another example, the substrate 1 may be a layered substrate 1 including a stack such as Si and SiGe, a stack of Si and SiC, silicon on insulator (SOI), or silicon germanium on insulator.

[0111] As an example, the lowermost layer of the stacked structure 2 may be the sacrificial layer 21, and the topmost layer of the stacked structure 2 may be the interlayer dielectric layer 22; or, the lowermost layer of the stacked structure 2 may be the interlayer dielectric layer 22, and the topmost layer of the stacked structure 2 may be the sacrificial layer 21. Referring to Figure 5 FIG. (b) of, in the embodiments of the present application, the lowermost layer of the stacked structure 2 is the sacrificial layer 21, and the topmost layer of the stacked structure 2 is the interlayer dielectric layer 22 for exemplary illustration.

[0112] The embodiments of the present application do not specifically limit the materials of the sacrificial layer 21 and the interlayer dielectric layer 22. In some embodiments, the sacrificial layer 21 and the interlayer dielectric layer 22 may be formed of materials with the same or similar chemical properties.

[0113] As an example, the interlayer dielectric layer 22 may be formed of at least an oxide material; correspondingly, the sacrificial layer 21 may be formed of at least one of a nitride material and a polysilicon material, that is, the non-metallic sacrificial layer may be formed of a nitride material, or a polysilicon material, or a combination of a nitride material and a polysilicon material.

[0114] In addition, in some embodiments, as shown in FIG. (b) of Figure 5 , a capping layer 23 may also be formed on the stacked structure 2 in step S100 to provide electrical protection for the semiconductor structure.

[0115] In some embodiments, asFigure 6 as shown in Figure (a) of Figure 6 Figure (b) of Figure 6 and Figure (c) of

[0116] The method for preparing the semiconductor structure may further include the following steps: pattern the stacked structure 2 to form a plurality of partition grooves 11 arranged in columns along a first direction. Then, form a partition structure 12 in the partition grooves 11.

[0117] As an example, the partition structure 12 obtained in the above steps can be used to define the setting positions of the memory cells. Specifically, the partition structures 12 adjacent to each other in the first direction can be used to define the setting positions of the corresponding memory cells.

[0118] The embodiments of the present application do not specifically limit the material of the partition structure 12. As an example, the material of the partition structure 12 includes, but is not limited to, one or more of oxides, nitrides, oxynitrides, and carbides. Exemplarily, the oxide includes silicon dioxide (SiO2); the nitride includes silicon nitride (SiN); the oxynitride includes silicon oxynitride (SiON), and the carbide includes silicon carbide.

[0119] In some embodiments, as Figure 7 shown in Figure (a) of Figure 7 Figure (b) of Figure 7 and Figure (c) of

[0120]

[0121] In step S210, etch the stacked structure 2 to form first through holes H1 and isolation grooves E1 that are spaced apart and penetrate the stacked structure 2; then, laterally etch each sacrificial layer 21 based on the first through holes H1 and the isolation grooves E1 to form a second transistor accommodation groove G1 and a second bit line accommodation groove G2.

[0122] It can be understood that the sacrificial layer 21 located between the first through holes H1 and the isolation grooves E1 in step S210 can be completely removed.

[0123] Specifically, as shown in Figure 7 Figure (a) in Figure 7 Figure (b) in Figure 7 Figure (c) in , when the bottom layer of the stacking structure 2 is the sacrificial layer 21, the second transistor accommodating groove G1 close to the substrate 1 is located between the substrate 1 and the interlayer dielectric layer 22 of the bottom layer; that is, in the direction perpendicular to the substrate 1, the upper sidewall of the second transistor accommodating groove G1 exposes the lower surface of the interlayer dielectric layer 22 close to the substrate 1, and the lower sidewall of the second transistor accommodating groove G1 exposes the surface of the substrate 1, and the remaining second transistor accommodating grooves G1 are located between adjacent interlayer dielectric layers 22; that is, in the direction perpendicular to the substrate 1, the upper sidewall of the second transistor accommodating groove G1 exposes the lower surface of the upper adjacent interlayer dielectric layer 22, and the lower sidewall of the second transistor accommodating groove G1 exposes the upper surface of the lower adjacent interlayer dielectric layer 22.

[0124] Correspondingly, when the bottom layer of the stacking structure 2 is the interlayer dielectric layer 22, the second transistor accommodating grooves G1 are all located between adjacent interlayer dielectric layers 22; that is, in the direction perpendicular to the substrate 1, the upper sidewall of the second transistor accommodating groove G1 exposes the lower surface of the upper adjacent interlayer dielectric layer 22, and the lower sidewall of the second transistor accommodating groove G1 exposes the upper surface of the lower adjacent interlayer dielectric layer 22.

[0125] In step S220, please refer to Figures 8 to 9 , and an insulating dielectric layer 52 and a second semiconductor layer 42 are sequentially formed on the sidewalls of the second transistor accommodating groove G1 and the sidewalls of the second bit line accommodating groove G2; wherein, the insulating dielectric layer 52 also covers the sidewalls of the first through hole H1 and the sidewalls of the isolation groove E1.

[0126] The process of forming the insulating dielectric layer 52 and the second semiconductor layer 42 in step S220 can be specifically represented by the following steps, for example:

[0127] As Figure 8 Figure (a) in Figure 8 Figure (b) in Figure 8 Figure (c) in shows that an insulating dielectric layer 52 and a second semiconductor material layer 421 are sequentially formed on the sidewalls of the second transistor accommodating groove G1, the sidewalls of the first through hole H1, and the sidewalls of the isolation groove E1, and a sacrificial dielectric layer 51 for filling the second transistor accommodating groove G1, the first through hole H1, and the isolation groove E1 is formed.

[0128] As Figure 9 Figure (a) in Figure 9 Figure (b) in Figure 9As shown in Figure (c), the sacrificial dielectric layer 51 located in the first through hole H1 and the isolation groove E1, and the second semiconductor material layer 421 on the sidewalls of the first through hole H1 and the isolation groove E1 are removed to form the second semiconductor layer 42.

[0129] In step S230, please refer to Figures 9 to 11 , a second bit line RBL (such as a read bit line) that covers the second semiconductor layer 42 and fills the second bit line accommodation groove G2 is formed in the second bit line accommodation groove G2; a second bit line isolation structure 34 is filled and formed in the isolation groove E1; a second word line RWL (such as a read word line) is filled and formed in the first through hole H1.

[0130] The process of forming the second bit line RBL in step S230 can be specifically represented by the following steps, for example:

[0131] As Figure 9 shown in Figure (a), Figure 9 Figure (b), and Figure 9 Figure (c), a filling dielectric layer 53 that fills the exposed first through hole H1 and the isolation groove E1 is formed.

[0132] As Figure 10 shown in Figure (a), Figure 10 Figure (b), and Figure 10 Figure (c), the filling dielectric layer 53 located in the first trench E1 is removed to expose the first trench E1; then, based on the first trench E1, the sacrificial dielectric layer 51 in the second transistor accommodation grooves G1 on both sides of the first trench E1 is removed to expose the second bit line accommodation groove G2, and a second bit line material layer 340 that covers the second semiconductor layer 42 and fills the second bit line accommodation groove G2 is formed in the second bit line accommodation groove G2.

[0133] As Figure 11 shown in Figure (a), Figure 11 Figure (b), and Figure 11 Figure (c), the second bit line material layer 340 located in the first trench E1 is removed to expose the first trench E1, and the remaining second bit line material layer 340 serves as the second bit line RBL. Thereafter, exemplaryly, a second bit line isolation structure 34 can also be formed in the first trench E1. The second bit line isolation structure 34 can be used to achieve isolation between adjacent second bit lines RBL.

[0134] In step S230, the second word line RWL can be formed after the second bit line RBL and the second bit line isolation structure 32 are formed. In some embodiments, a ground wire GND can also be formed in the first through hole H1 and the second transistor accommodation groove G1. The following combines Figures 12 to 14, taking the formation of the ground wire GND and the second word line RWL in the first through hole H1 and the second transistor accommodation groove G1 as an example for illustration, it can be specifically manifested as the following steps, for example:

[0135] As shown in Figure 12 Figure (a) therein, Figure 12 Figure (b) therein, and Figure 12 Figure (c) therein, remove a part of the filling dielectric layer 53 located in the first through hole H1, and further remove the sacrificial dielectric layer 51 located outside the first through hole H1; form the ground wire GND in the exposed gap.

[0136] As shown in Figure 13 Figure (a) therein, Figure 13 Figure (b) therein, and Figure 13 Figure (c) therein, remove the remaining filling dielectric layer 53, and further remove the sacrificial dielectric layer 51 located outside the first through hole H1 to form the second word line definition hole H3.

[0137] As shown in Figure 14 Figure (a) therein, Figure 14 Figure (b) therein, and Figure 14 Figure (c) therein, form the second word line dielectric layer 33 covering the inner sidewall of the second word line definition hole H3, and the second word line RWL covering the second word line dielectric layer 33 and filling the second word line definition hole H3.

[0138] In step S300, as shown in Figure 15 Figure (a) therein, Figure 15 Figure (b) therein, and Figure 15 Figure (c) therein, etch the stacked structure 2 to form the etch groove E2 and the first word line definition hole H2. The etch groove E2 penetrates the stacked structure 2 in a direction perpendicular to the substrate 1 and extends in the first direction, and the first word line definition hole H2 is located beside the etch groove E2 in the second direction and has a gap with the etch groove E2.

[0139] As an example, the stacked structure 2 can be etched to form the etch groove E2 and the first word line definition hole H2 by using a dry etching process, but not limited to this. It can be understood that the etch groove E2 and the multiple first word line definition holes H2 can be formed simultaneously, that is, the etch groove E2 and the multiple first word line definition holes H2 can be formed by using a single etching process based on the same mask layer; or, the etch groove E2 and the multiple first word line definition holes H2 can also be formed separately, that is, the etch groove E2 and the multiple first word line definition holes H2 can be formed by using multiple etching processes based on different mask layers.

[0140] In step S400, please continue to refer to Figure 15 Figure (a) therein, Figure 15 Figure (b) therein, and Figure 15In FIG. (c), each sacrificial layer 21 is laterally etched based on the etching groove E2 and the first word line defining hole H2 to form a first transistor accommodating groove G3 and a first bit line accommodating groove G4.

[0141] The first transistor accommodating groove G3 is located in the first etching region of the sacrificial layer 21 and surrounds the periphery of the first word line defining hole H2. The first bit line accommodating groove G4 is located in the second etching region of the sacrificial layer 21 and is between the first transistor accommodating grooves G3. It should be noted that the second etching region and the first etching region are connected.

[0142] Specifically, as shown in FIG. (a) in Figure 15 , FIG. (b) in Figure 15 and FIG. (c) in Figure 15 , when the bottom layer of the stacked structure 2 is the sacrificial layer 21, the first transistor accommodating groove G3 close to the substrate 1 is located between the substrate 1 and the interlayer dielectric layer 22 of the bottom layer; that is, in the direction perpendicular to the substrate 1, the upper sidewall of the first transistor accommodating groove G3 exposes the lower surface of the interlayer dielectric layer 22 close to the substrate 1, and the lower sidewall of the first transistor accommodating groove G3 exposes the surface of the substrate 1. The remaining first transistor accommodating grooves G3 are located between adjacent interlayer dielectric layers 22; that is, in the direction perpendicular to the substrate 1, the upper sidewall of the first transistor accommodating groove G3 exposes the lower surface of the upper adjacent interlayer dielectric layer 22, and the lower sidewall of the first transistor accommodating groove G3 exposes the upper surface of the lower adjacent interlayer dielectric layer 22.

[0143] Correspondingly, when the bottom layer of the stacked structure 2 is the interlayer dielectric layer 22, the first transistor accommodating grooves G3 are all located between adjacent interlayer dielectric layers 22; that is, in the direction perpendicular to the substrate 1, the upper sidewall of the first transistor accommodating groove G3 exposes the lower surface of the upper adjacent interlayer dielectric layer 22, and the lower sidewall of the first transistor accommodating groove G3 exposes the upper surface of the lower adjacent interlayer dielectric layer 22.

[0144] As an example, step S400 can laterally etch each sacrificial layer 21 by using an anisotropic etching process. Anisotropic etching can selectively etch materials in a preset crystal orientation or crystal plane direction, and leave very little or almost no etching marks in other directions. Therefore, using anisotropic etching for back etching in the above steps can make the morphology of the obtained structure more precise and controllable.

[0145] As shown in Figure 15 FIG. (a) in Figure 15 , FIG. (b) in Figure 15As shown in Figure (c), the sacrificial layer 21 between the first transistor receiving groove G3 and the first bit line receiving groove G4 is completely removed, so that the first transistor receiving groove G3 and the first bit line receiving groove G4 are communicated. Specifically, a plurality of first transistor receiving grooves G3 are communicated with the first word line defining holes H2, and a plurality of first bit line receiving grooves G4 are communicated with the etching groove E2. Since the etching groove E2 and the plurality of first word line defining holes H2 both penetrate the stacked structure 2 and extend into the substrate 1, in some embodiments, the plurality of first transistor receiving grooves G3 and the plurality of first bit line receiving grooves G4 can be directly formed by a single etching process, thereby further simplifying the process flow of the manufacturing method to improve production efficiency.

[0146] In step S500, please refer to Figures 16 to 17 , a storage gate 43 is formed on the side of the first transistor receiving groove G3 facing away from the first bit line receiving groove G4. It can be understood that the storage gate 43 and the second semiconductor layer 42 can jointly form the second transistor T2.

[0147] It should be noted that the storage gate 43 is formed on the side of the second semiconductor layer 42 facing away from the second bit line RBL, and the insulating dielectric layer 52 is located between the second semiconductor layer 42 and the storage gate 43.

[0148] In some embodiments, step S500 forms a storage gate 43 on the side of the first transistor receiving groove G3 facing away from the first bit line receiving groove G4, which can be specifically manifested as the following steps S510 to S520.

[0149] In step S510, as shown in Figure (a) of Figure 16 , Figure (b) of Figure 16 , and Figure (c) of Figure 16 , a conductive material layer 431 is formed to fill the etching groove E2, the first word line defining holes H2, the first transistor receiving groove G3, and the first bit line receiving groove G4.

[0150] In step S520, as shown in Figure (a) of Figure 17 , Figure (b) of Figure 17 , and Figure (c) of Figure 17 , a part of the conductive material layer 431 is removed to retain the conductive material layer 431 formed on the side of the first transistor receiving groove G3 facing away from the first bit line receiving groove G4; the retained conductive material layer 431 serves as the storage gate 43.

[0151] The embodiments of the present application do not specifically limit the manner of forming the conductive material layer 431 in step S510. In some embodiments, the conductive material layer 431 for filling the etching groove E2, the first word line defining holes H2, the first transistor receiving groove G3, and the first bit line receiving groove G4 can be formed by an atomic layer deposition process.

[0152] In some embodiments, the method for preparing the semiconductor structure may further include the following steps S610 - S630 .

[0153] In step S610, refer to Figures 18 to 19 , a gate dielectric layer 31 and a first word line WWL (eg, a write word line) are sequentially formed in the first word line definition hole H2.

[0154] The process of forming the gate dielectric layer 31 and the first word line WWL in step S610 can be specifically performed as follows:

[0155] like Figure 18 Figure (a) in Figure 18 Figure (b) and Figure 18 As shown in FIG. (c), a sacrificial material layer 54 is formed to fill the first transistor accommodating groove G3, the first word line defining hole H2, the first bit line accommodating groove G4 and the etching groove E2. For example, the sacrificial material layer 54 may be formed by a deposition process, and the deposition process may include but is not limited to an atomic layer deposition process, a chemical vapor deposition process, and a molecular layer deposition process.

[0156] like Figure 19 Figure (a) in Figure 19 Figure (b) and Figure 19 As shown in FIG. 5( c ), the sacrificial material layer 54 in the first word line definition hole H2 is removed. Then, a gate dielectric layer 31 and a first word line WWL are sequentially formed in the first word line definition hole H2.

[0157] It can be understood that in the embodiment of the present application, the sacrificial material layer 54 has a certain etching selectivity with the sacrificial layer 21 , the interlayer dielectric layer 22 and the substrate 1 , so as to facilitate better removal of the sacrificial material layer 54 in subsequent processes.

[0158] For example, the constituent material of the first word line WWL includes, but is not limited to, one or more of conductive polysilicon, metal, conductive metal nitride, conductive metal oxide and metal silicide. For example, the metal may be tungsten (W), nickel (Ni), copper (Cu), aluminum (Al), molybdenum (Mo), ruthenium (Ru), tantalum (Ta) or titanium (Ti); the conductive metal nitride includes titanium nitride (TiN); the conductive metal oxide includes iridium oxide (IrO 2 ); Metal silicides include tungsten silicon (WSi).

[0159] For example, the material of the gate dielectric layer 31 may include, but is not limited to, silicon oxide (eg, silicon dioxide), silicon nitride (silicon oxynitride), nitride (eg, silicon nitride), metal oxide (eg, Al 2 O 3), metal oxynitrides (such as AlON), metal silicides, high-k dielectric materials (dielectric constant greater than 3.9), low-k dielectric materials (dielectric constant greater than or equal to 2.5 and less than 3.9), ultra-low-k dielectric materials (dielectric constant less than 2.5), ferroelectric materials, antiferroelectric materials, carbides (silicon carbide) or combinations thereof. Exemplarily, high-k materials may include hafnium oxide (HfO 2 ), zirconium oxide (ZrO 2 ), aluminum oxide (Al 2 O 3 ), lanthanum oxide (La 2 O 3 ), titanium oxide (TiO 2 ), tantalum oxide (Ta 2 O 5 ), niobium oxide (Nb 2 O 5 ), or strontium titanate (SrTiO3). The material of the first word line dielectric layer 35 may be the same as or different from the material of the gate dielectric layer 31.

[0160] The following is to be understood in conjunction with Figures 20 to 22 In step S620, the first semiconductor layer 41 is filled in the first transistor receiving groove G3. Specifically, the first semiconductor layer 41 may surround the sidewall of the gate dielectric layer 31 and cover the inner wall of the first bit line receiving groove G4. It can be understood that the first semiconductor layer 41 can be used to form the first transistor T1. In step S630, a first bit line WBL (such as a write bit line) that covers the first semiconductor layer 41 and fills the first bit line receiving groove G4 is formed in the first bit line receiving groove G4.

[0161] As an example, the above steps S620 to S630 may specifically be as follows:

[0162] As Figure 20 shown in the (a) figure of Figure 20 the (b) figure of Figure 20 and the (c) figure of

[0163] As Figure 21 shown in the (a) figure of Figure 21 the (b) figure of Figure 21As shown in FIG. (c), a first semiconductor material layer 411 is deposited on the removal region of the remaining sacrificial material layer 54, such that the first semiconductor material layer 411 fills the first transistor receiving groove G3 and covers the inner wall of the first bit line receiving groove G4 and the side walls of the interlayer dielectric layer 22 exposed in the etching groove E2. Thereafter, a first bit line material layer 320 is formed to cover the first semiconductor material layer 411 and fill the first bit line receiving groove G4 and the etching groove E2.

[0164] As Figure 22 shown in FIG. (a), Figure 22 FIG. (b), and Figure 22 FIG. (c), the first semiconductor material layer 411 and the first bit line material layer 320 in the etching groove E2 are removed to form the first semiconductor layer 41 and the first bit line WBL.

[0165] As an example, the material of the first semiconductor layer 41 may include at least one of polysilicon, amorphous silicon, oxide materials (e.g., IGZO, IZO, ITO, zinc oxide), and two-dimensional materials (e.g., graphene, molybdenum disulfide, etc.).

[0166] In some embodiments, the first semiconductor material layer 411 is formed of a metal oxide semiconductor material. Exemplarily, the material of the first semiconductor material layer 411 includes a metal oxide semiconductor of at least one of indium, gallium, zinc, or tin, such as indium gallium zinc oxide (Indium Gallium Zinc Oxide, abbreviated as IGZO), to facilitate reducing the leakage current of the first transistor T1, thereby ensuring the reliability of the first transistor T1 and reducing the refresh time of the first transistor T1.

[0167] Correspondingly, the second semiconductor layer 42 may also be formed of a metal oxide semiconductor material, and the material of the second semiconductor layer 42 and the material of the first semiconductor layer 41 may be the same or different. For example, the material of the second semiconductor layer 42 may also be an IGZO material to facilitate reducing the leakage current of the second transistor T2, thereby ensuring the reliability of the second transistor T2 and reducing the refresh time of the second transistor T2.

[0168] In addition, as an example, the first semiconductor material layer 411 and the first bit line material layer 320 may be formed by atomic layer deposition processes respectively to form the first semiconductor material layer 411 and the first bit line material layer 320 with better morphology.

[0169] Exemplarily, the material of the first bit line WBL may include, but is not limited to, metal materials such as metal tungsten, metal nickel, or metal titanium, etc.

[0170] In some embodiments, the first semiconductor material layer 411 and the first bit line material layer 320 in the etching groove E2 can be removed by a dry etching process.

[0171] In some embodiments, as Figure 23 shown in FIG. (a) in Figure 23 FIG. (b) in Figure 23 and FIG. (c) in

[0172] On the other hand, according to some embodiments, the present application also provides a semiconductor structure.

[0173] It can be understood that the semiconductor structure provided by the embodiments of the present application can be used as at least a part of a memory. In some embodiments, the semiconductor structure can be a memory. The following will be described by taking Figures 23 to 26 the memory with a 2T0C structure as the semiconductor structure as an example.

[0174] In some embodiments, the semiconductor structure may include a substrate 1 and a plurality of memory cells U.

[0175] Among them, the memory cells U are disposed on the substrate 1, and the memory cells U may include a first transistor T1 and a second transistor T2.

[0176] The first transistor T1 and the second transistor T2 in the same memory cell U are arranged and connected along a second direction; the second direction is parallel to the substrate 1; the second transistor T1 includes a second semiconductor layer 42, a second word line RWL dielectric layer 33, a storage gate 43 and a second gate; at least a part of the second semiconductor layer 42 surrounds the second gate, there is a second semiconductor layer 42 and a second word line RWL dielectric layer 33 between the storage gate 43 and the second gate, and at least a part of the storage gate 43 surrounds the second semiconductor layer 42.

[0177] In the semiconductor structure provided in the above embodiments, by making at least a part of the second semiconductor layer 42 surround the second gate, a CAA structure can be formed to increase the gate control ability of the main gate; by making at least a part of the storage gate 43 surround the second semiconductor layer 42, a GAA structure can be formed to improve the control ability of the storage gate 43, and at the same time, the voltage holding ability of the storage gate 43 can be increased, and the data storage ability of the semiconductor structure can be increased.

[0178] As an example, the second transistor T2 can be a single-gate structure or a double-gate structure. Please refer to Figures 23 to 26 the following embodiments in which the second transistor T2 is a double-gate structure for understanding.

[0179] In some embodiments, the semiconductor structure may further include a second bit line RBL, and the second bit line RBL may extend along a first direction parallel to the substrate 1; the first direction is parallel to the substrate and intersects with a second direction.

[0180] In some embodiments, the semiconductor structure may further include a second word line RWL, and the second word line RWL extends along a direction perpendicular to the substrate 1.

[0181] The second gate is a part of the second word line RWL; the second word line RWL includes a first main body portion perpendicular to the substrate 1, and a first protruding portion 332 protruding from the first main body portion 331 in the second direction; both the top surface of the first protruding portion away from the substrate 1 and the bottom surface close to the substrate 1 are connected to the second semiconductor layer 42 through the second word line RWL dielectric layer 33.

[0182] In some embodiments, the semiconductor structure may further include a first bit line WBL, and the first bit line WBL extends along the first direction parallel to the substrate 1.

[0183] In some embodiments, the semiconductor structure may further include a first word line WWL and a second word line RWL. The first word line WWL extends along a direction perpendicular to the substrate 1, and a gate dielectric layer 31 is provided on the sidewall of the first word line WWL. The second word line RWL extends along a direction perpendicular to the substrate 1, and a second word line dielectric layer 33 is provided on the sidewall of the second word line RWL.

[0184] Here, the second bit line RBL and the second word line RWL are insulated from each other. Among them, while the second word line RWL is used as the read word line of the semiconductor structure, it can also be used as the gate of the second transistor T2 in each memory cell U to control the on / off of the second transistor T2.

[0185] In some embodiments, the semiconductor structure may further include a ground wire GND. Specifically, the ground wire GND is located beside the second word line RWL and is parallel to the second word line RWL.

[0186] In some embodiments, the first transistor T1 may include a first semiconductor layer 41. The first semiconductor layer 41 is disposed around the sidewall of the gate dielectric layer 31 and covers the upper and lower surfaces of the first bit line WBL and the sidewall of the first bit line WBL close to the first word line WWL.

[0187] In some embodiments, the second transistor T2 may include a second semiconductor layer 42 and a storage gate 43. The second semiconductor layer 42 at least partially surrounds the second bit line RBL, and the second semiconductor layer 42 is in contact with the second bit line RBL.

[0188] As an example, the second semiconductor layer 42 is disposed on the sidewall of the insulating dielectric layer 52 along the first direction, and is disposed on the side of the ground wire GND away from the second word line RWL, and covers the upper and lower surfaces corresponding to the second bit line RBL; the storage gate 43 is located on the side of the second semiconductor layer 42 away from the second bit line RBL.

[0189] In the semiconductor structure provided in the above embodiment, the second transistor T2 adopts a double-gate structure, so that the gate control ability of the second transistor T2 is enhanced, thereby reducing the subthreshold swing and improving the switching ratio of the second transistor T2, and enhancing the electrical performance of the semiconductor structure in the above embodiment.

[0190] In some embodiments, the second word line RWL may include a first main body portion 331 and a first extending portion 332. The first main body portion 331 extends in a direction perpendicular to the substrate 1, and the first extending portion 332 is disposed on the side of the second bit line RBL close to the first main body portion 331. The second semiconductor layer 42 also surrounds and is disposed on the sidewall of the first word line dielectric layer 33 covering the first extending portion 332.

[0191] In some embodiments, the ground wire GND includes a second main body portion 371 and a second extending portion 372. The second main body portion 371 extends in a direction perpendicular to the substrate 1, and the second extending portion 372 is disposed on the side of the corresponding storage gate 43 close to the second main body portion 371, and the second extending portion 372 extends from the second main body portion 371 in the second direction.

[0192] Exemplarily, the second extending portion 372 is at least partially surrounded and contacted by the second semiconductor layer 42.

[0193] As an example, the first main body portion 331 and the first extending portion 332 may be an integrally formed structure; the second main body portion 371 and the second extending portion 372 may also be an integrally formed structure.

[0194] In some embodiments, the semiconductor structure may further include a first through hole H1. The first main body portion 331 and the second main body portion 371 may be disposed in the first through hole H1 in parallel, and there is a second word line dielectric layer 33 between the first main body portion 331 and the second main body portion 371.

[0195] In some embodiments, the semiconductor structure may further include a first bit line isolation structure 32 and a second bit line isolation structure 34. The first bit line isolation structure 32 is located on the side of the first bit line WBL away from the first word line WWL and extends along the first direction; the second bit line isolation structure 34 is located on the side of the second bit line RBL away from the second word line RWL and extends along the first direction.

[0196] In some embodiments, the semiconductor structure may further include an interlayer dielectric layer 22 located on the upper and lower surfaces of the memory cell U. The interlayer dielectric layer 22 can be used to separate adjacent memory cells U along a first direction.

[0197] In some embodiments, the semiconductor structure may further include a plurality of separation structures 12 arranged in columns along a first direction. The separation structures 12 can be used to separate adjacent memory cells U along the first direction.

[0198] In some embodiments, an insulating dielectric layer 52 is further disposed between the conductive structures of the semiconductor structure, which can avoid charge leakage and effectively reduce the leakage current.

[0199] As an example, the insulating dielectric layer 52 can cover the outer surface of the second semiconductor layer 42 and is located between the ground wire GND and the interlayer dielectric layer 22, between the ground wire GND and the substrate 1, between the second word line RWL and the interlayer dielectric layer 22, between the second word line dielectric layer 33 and the substrate 1, and between the second bit line isolation structure 34 and the substrate 1. For example, the insulating dielectric layer 52 located on the outer surface covering the second semiconductor layer 42 and between the second semiconductor layer 42 and the memory gate 43 can also serve as the gate dielectric layer of the memory gate 43.

[0200] In some embodiments, the semiconductor structure may further include a ground layer 13 located in the substrate 1. The second main body portion 371 of the ground wire GND penetrates the insulating dielectric layer 52 along a direction perpendicular to the substrate 1 and extends to the ground layer 13.

[0201] In some embodiments, the semiconductor structure may further include a first word line defining hole H2. The first word line defining hole H2 is perpendicular to the substrate 1.

[0202] The first word line defining hole H2 has a first word line WWL and a gate dielectric layer 31 therein, and the gate dielectric layer 31 is located between the first word line WWL and the sidewall of the first word line defining hole H2.

[0203] In some embodiments, the semiconductor structure may further include a first transistor receiving groove G3. The first transistor receiving groove G3 surrounds the periphery of the first word line defining hole H2.

[0204] Exemplarily, the first transistor receiving groove G3 may be filled with a first semiconductor layer 41.

[0205] In some embodiments, the first word line defining hole H2 and the first transistor receiving groove G3 may be connected.

[0206] In some embodiments, the semiconductor structure may further include a first bit line receiving groove G4. The first bit line WBL may be disposed in the first bit line receiving groove G4. Exemplarily, the first bit line receiving groove G4 and the first transistor receiving groove G3 may communicate with each other.

[0207] Figure 27 The equivalent circuit of the memory with a 2T0C structure for the semiconductor structure in this embodiment is shown. Figure 28 The equivalent circuit of a storage cell U is shown as an example. Please refer to Figures 23 to 26 for understanding. The storage gate 43 can be used to store charges. For example, the storage gate 43, the second semiconductor layer 42, and the insulating dielectric layer 52 therebetween can be equivalent to a capacitor, corresponding to the storage node SN in Figure 27 and Figure 28 The ground wire GND can be used to connect to the ground voltage G.

[0208] It should be noted that the semiconductor structures in the embodiments of the present application can all be prepared by using the preparation methods of the corresponding semiconductor structures. Therefore, the technical features between the structural embodiments and the method embodiments can be mutually replaced and supplemented without conflict, so that those skilled in the art can learn about the technical content of the present application.

[0209] On the other hand, according to some embodiments, the present application also provides an electronic device, which may include some of the foregoing semiconductor structures. The electronic device may include, but is not limited to, mobile phones, televisions, displays, tablets, computers, and the like. Due to the use of semiconductor structures with better performance and reliability, the electronic device in the embodiments of the present application has more beneficial performance and higher reliability.

[0210] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no conflict in the combination of these technical features, it should be considered as the scope described in this specification.

[0211] The above-described embodiments only represent several implementation manners of the present application. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, the semiconductor structure includes a first transistor and a second transistor, a first gate of the first transistor is connected to a first word line, a first source / drain of the first transistor is connected to a first bit line, and a second source / drain of the first transistor is connected to a storage gate; the storage gate simultaneously serves as a back gate of the second transistor; the fabrication method includes: providing a substrate; forming a stacked structure on the substrate, the stacked structure including multiple layers of sacrificial layers and multiple layers of interlayer dielectric layers alternately stacked in a direction perpendicular to the substrate; wherein, the sacrificial layer includes a non-metallic material; etching the stacked structure to form an etching groove and a first word line defining hole; the etching groove penetrates the stacked structure in a direction perpendicular to the substrate and extends in a first direction; the first word line defining hole is located beside the etching groove in a second direction and has a gap with the etching groove; the first direction intersects with the second direction and both are parallel to the substrate; transversely etching each of the sacrificial layers based on the etching groove and the first word line defining hole to form a first transistor accommodating groove and a first bit line accommodating groove; the first transistor accommodating groove is located in a first etching area of the sacrificial layer and surrounds the periphery of the first word line defining hole; the first bit line accommodating groove is located in a second etching area of the sacrificial layer and is located between the first transistor accommodating groove and the etching groove; the second etching area and the first etching area are connected; forming a storage gate on a side of the first transistor accommodating groove facing away from the first bit line accommodating groove.

2. The method for fabricating a semiconductor structure according to claim 1, characterized in that, the forming a storage gate on a side of the first transistor accommodating groove facing away from the first bit line accommodating groove includes: forming a conductive material layer filling the etching groove, the first word line defining hole, the first transistor accommodating groove and the first bit line accommodating groove; removing a part of the conductive material layer to retain the conductive material layer formed on a side of the first transistor accommodating groove facing away from the first bit line accommodating groove; the retained conductive material layer serves as the storage gate.

3. The method for fabricating a semiconductor structure according to claim 2, characterized in that, the conductive material layer filling the etching groove, the first word line defining hole, the first transistor accommodating groove and the first bit line accommodating groove is formed by an atomic layer deposition process.

4. The method for fabricating a semiconductor structure according to claim 1, characterized in that, the interlayer dielectric layer is formed at least by an oxide material, and the sacrificial layer is formed at least by one of a nitride material and a polysilicon material.

5. The method for fabricating a semiconductor structure according to any one of claims 1 to 4, characterized in that, the method for fabricating the semiconductor structure further includes: sequentially forming a gate dielectric layer and a first word line in the first word line defining hole; filling a first semiconductor layer in the first transistor accommodating groove; the first semiconductor layer surrounds the sidewall of the gate dielectric layer and covers the inner wall of the first bit line accommodating groove; A first bit line is formed in the first bit line receiving groove to cover the first semiconductor layer and fill the first bit line receiving groove.

6. The method for manufacturing a semiconductor structure according to any one of claims 1 to 4, wherein, before etching the stacked structure to form an etching groove and a first word line defining hole, the method for manufacturing the semiconductor structure further includes: etching the stacked structure to form first through holes and isolation grooves that are spaced apart and penetrate the stacked structure; laterally etching each of the sacrificial layers based on the first through holes and the isolation grooves to form a second transistor receiving groove and a second bit line receiving groove; forming an insulating dielectric layer and a second semiconductor layer on the side walls of the second transistor receiving groove and the second bit line receiving groove in sequence; wherein, the insulating dielectric layer also covers the side walls of the first through holes and the isolation grooves; forming a second bit line in the second bit line receiving groove to cover the second semiconductor layer and fill the second bit line receiving groove; filling the isolation groove to form a second bit line isolation structure; filling the first through hole to form a second word line; the storage gate is formed on a side of the second semiconductor layer facing away from the second bit line, and the insulating dielectric layer is located between the second semiconductor layer and the storage gate.

7. A semiconductor structure, wherein, comprising: a substrate; a plurality of memory cells; the memory cell includes a first transistor and a second transistor; the first transistor and the second transistor in the same memory cell are arranged and connected along a second direction; the second direction is parallel to the substrate; the second transistor includes a second semiconductor layer, a second word line dielectric layer, a storage gate, and a second gate; at least a part of the second semiconductor layer surrounds the second gate, and there are the second semiconductor layer and the second word line dielectric layer between the storage gate and the second gate, and the storage gate at least partially surrounds the second semiconductor layer.

8. The semiconductor structure according to claim 7, wherein, further comprising a second bit line; the second bit line extends along a first direction; the first direction is parallel to the substrate and intersects the second direction; at least a part of the second semiconductor layer surrounds the second bit line, and the second semiconductor layer is in contact with the second bit line.

9. The semiconductor structure according to claim 8, wherein, further comprising a second word line; the second word line extends in a direction perpendicular to the substrate; the second gate is a part of the second word line; the second word line includes a first main body portion perpendicular to the substrate, and a first extending portion extending from the first main body portion in the second direction; both the top surface of the first extending portion away from the substrate and the bottom surface close to the substrate are connected to the second semiconductor layer through the second word line dielectric layer.

10. The semiconductor structure according to claim 9, wherein, further comprising a ground wire; the ground wire includes a second main body portion perpendicular to the substrate, and a second extending portion extending from the second main body portion in the second direction; the second extending portion is at least partially surrounded and contacted by the second semiconductor layer.

11. The semiconductor structure according to claim 10, characterized in that, it further includes a first through hole; the first main body portion and the second main body portion that are parallel to each other are disposed in the first through hole, and a second word line dielectric layer is provided between the first main body portion and the second main body portion.

12. The semiconductor structure according to claim 7, characterized in that, it further includes: a first word line defining hole, perpendicular to the substrate; a first word line and a gate dielectric layer are provided in the first word line defining hole, and the gate dielectric layer is located between the first word line and the side wall of the first word line defining hole; a first transistor accommodating groove, surrounding the periphery of the first word line defining hole; the first transistor accommodating groove is filled with a first semiconductor layer.

13. The semiconductor structure according to claim 12, characterized in that, the first word line defining hole and the first transistor accommodating groove are communicated with each other.

14. The semiconductor structure according to claim 13, characterized in that, the first semiconductor layer is disposed around the side wall of the gate dielectric layer.

15. The semiconductor structure according to claim 14, characterized in that, it further includes: a first bit line, extending along the first direction; a first bit line accommodating groove, and the first bit line is disposed in the first bit line accommodating groove; the first bit line accommodating groove and the first transistor accommodating groove are communicated with each other.

16. An electronic device, characterized in that, it includes the semiconductor structure according to any one of claims 7 to 15.

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