Semiconductor structure and method of forming the same, memory

Abstract

The present disclosure relates to a semiconductor structure and a forming method thereof, a memory, the semiconductor structure comprising an active layer, a first gate dielectric layer, a first word line structure, a second gate dielectric layer, a second word line structure, a bit line structure, a common electrode, a dielectric layer and a conductive contact layer, the active layer comprising a first channel region, a second channel region, a source region, a first drain region and a second drain region of at least partially different lines, the first gate dielectric layer covering at least part of a surface of the first channel region; the first word line structure covering the first gate dielectric layer and extending along a first direction; the second gate dielectric layer covering at least part of a surface of the second channel region; the second word line structure covering the second gate dielectric layer and extending along the first direction; the bit line structure being electrically connected with the source region; in a second direction, the common electrode is located between the first channel region and the second channel region; the dielectric layer at least covering an outer periphery of the common electrode; the conductive contact layer covering a surface of the dielectric layer and being electrically connected with the second drain region.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor, and in particular, to a semiconductor structure, a forming method thereof and a memory. BACKGROUND

[0002] The memory is widely used in mobile devices such as mobile phones and tablet computers due to its small size, high integration level and fast transmission speed. However, the existing memory has a serious leakage phenomenon due to the structure, resulting in poor structural reliability.

[0003] It should be noted that the information disclosed in the above background section is only used to strengthen the understanding of the background of the present disclosure, and therefore can include information that does not constitute prior art known to those of ordinary skill in the art. SUMMARY

[0004] Therefore, the present disclosure provides a semiconductor structure, a forming method thereof and a memory, which can reduce leakage and improve device reliability.

[0005] According to one aspect of the present disclosure, a semiconductor structure is provided, comprising:

[0006] An active layer comprising a first channel region, a second channel region, a source region, a first drain region and a second drain region, the first channel region and the second channel region both extend along a first direction, and the first channel region and the second channel region are spaced apart along a second direction; the first direction intersects the second direction; the first drain region is connected to one end of the first channel region, and the second drain region is connected to an end of the second channel region close to the first drain region; the source region is connected between an end of the first channel region away from the first drain region along the first direction and an end of the second channel region away from the second drain region along the first direction, and the first drain region and the second drain region are insulated;

[0007] A first gate dielectric layer covering at least part of the surface of the first channel region;

[0008] A first word line structure covering the first gate dielectric layer and extending along the first direction;

[0009] A second gate dielectric layer covering at least part of the surface of the second channel region;

[0010] A second word line structure covering the second gate dielectric layer and extending along the first direction;

[0011] A bit line structure electrically connected to the source region;

[0012] A common electrode, in the second direction, the common electrode is located between the first channel region and the second channel region;

[0013] a dielectric layer covering at least an outer periphery of the common electrode;

[0014] a conductive contact layer covering a surface of the dielectric layer and electrically connected to the second drain region.

[0015] In an exemplary embodiment of the present disclosure, the conductive contact layer is located between the common electrode and the first channel region; or, the conductive contact layer is located between the common electrode and the second channel region.

[0016] In an exemplary embodiment of the present disclosure, when the conductive contact layer is located between the common electrode and the first channel region, the dielectric layer is further located between the conductive contact layer and the first drain region, the first channel region and the source region; when the conductive contact layer is located between the common electrode and the second channel region, the dielectric layer is further located between the conductive contact layer and the second drain region, the second channel region and the source region.

[0017] In an exemplary embodiment of the present disclosure, the material of the dielectric layer is a high dielectric constant material.

[0018] In an exemplary embodiment of the present disclosure, the first gate dielectric layer surrounds the first channel region, and the first word line structure surrounds the first gate dielectric layer;

[0019] and / or, the second gate dielectric layer surrounds the second channel region, and the second word line structure surrounds the second gate dielectric layer.

[0020] In an exemplary embodiment of the present disclosure, the first gate dielectric layer covers a surface of the first channel region away from the second channel region and surfaces of two sidewalls of the first channel region facing each other in a third direction, the third direction being perpendicular to the first direction and the second direction;

[0021] and / or, the second gate dielectric layer covers a surface of the second channel region away from the first channel region and surfaces of two sidewalls of the second channel region facing each other in the third direction.

[0022] In an exemplary embodiment of the present disclosure, the material of the first channel region is different from that of the second channel region.

[0023] In an exemplary embodiment of the present disclosure, the material of the first channel region includes at least one of indium gallium zinc oxide, indium gallium oxide or indium zinc oxide.

[0024] In an exemplary embodiment of the present disclosure, the material of the second channel region includes at least one of indium tin oxide, polysilicon, silicon or germanium silicon.

[0025] In an exemplary embodiment of the present disclosure, the semiconductor structure further comprises:

[0026] an insulating layer between the first drain region and the second drain region.

[0027] In an exemplary embodiment of the present disclosure, the semiconductor structure further comprises a ground electrode electrically connected with the first drain region to ground the first drain region.

[0028] According to an aspect of the present disclosure, there is provided a memory comprising a plurality of semiconductor structures as described in any one of the above embodiments, the number of the semiconductor structures being plural, the plurality of semiconductor structures constituting a plurality of semiconductor groups spaced apart along a first direction, each of the semiconductor groups comprising a plurality of semiconductor structures stacked along a third direction; each of the semiconductor structures in the same semiconductor group sharing the bit line structure, two semiconductor structures adjacent along the first direction in different semiconductor groups sharing the first gate dielectric layer, the second gate dielectric layer, the first word line structure and the second word line structure.

[0029] According to an aspect of the present disclosure, there is provided a method for forming a semiconductor structure, comprising:

[0030] forming an active layer comprising a first channel region, a second channel region, a source region, a first drain region and a second drain region, the first channel region and the second channel region extending along a first direction, and the first channel region and the second channel region being spaced apart along a second direction; the first direction intersecting the second direction; the first drain region connected with one end of the first channel region, the second drain region connected with an end of the second channel region close to the first drain region; the source region connected between an end of the first channel region away from the first drain region along the first direction and an end of the second channel region away from the second drain region along the first direction, the first drain region and the second drain region being insulated;

[0031] forming a first gate dielectric layer covering at least part of a surface of the first channel region;

[0032] forming a first word line structure covering the first gate dielectric layer and extending along the first direction;

[0033] forming a second gate dielectric layer covering at least part of a surface of the second channel region;

[0034] forming a second word line structure covering the second gate dielectric layer and extending along the first direction;

[0035] forming a bit line structure, the bit line structure electrically connected with the source region;

[0036] forming a common electrode, the common electrode located between the first channel region and the second channel region in the second direction;

[0037] forming a dielectric layer covering at least a periphery of the common electrode;

[0038] forming a conductive contact layer covering a surface of the dielectric layer, the conductive contact layer electrically connected with the second drain region.

[0039] In an exemplary embodiment of the present disclosure, the first channel region and the second channel region are different in material.

[0040] In an exemplary embodiment of the present disclosure, the forming method further comprises:

[0041] forming an insulating layer between the first drain region and the second drain region.

[0042] The semiconductor structure and the forming method thereof of the present disclosure, on one hand, the common electrode, the dielectric layer and the conductive contact layer can jointly constitute a structure similar to a capacitor, which can be used for storing electric charge; the structure can be read and written through current, compared with the traditional capacitor structure, the structure is not sensitive to various parasitic effects, the leakage phenomenon is obviously weakened, the data storage time is longer, and the refresh frequency can be reduced, the power consumption is reduced, the structure reliability is stronger, and the 3D stacking is facilitated. On the other hand, the active layer, the first gate dielectric layer, the first word line structure, the second gate dielectric layer and the second word line structure jointly constitute a double transistor structure, which can effectively improve the transistor distribution density, and the adjacent transistors can share the source region and the bit line structure, which helps to reduce the wiring density, save area and reduce the parasitic coupling effect; in addition, since the source region, the first drain region and the second drain region are all non-collinear with the first word line structure and / or the second word line structure, the wiring can be facilitated while the parasitic coupling effect is further reduced, thereby improving the device reliability.

[0043] The memory of the present disclosure, since the source region, the first drain region and the second drain region are all non-collinear with the first word line structure and / or the second word line structure, and each semiconductor structure in the same semiconductor group shares the bit line structure in the third direction, and two semiconductor structures adjacent in the first direction in different semiconductor groups share the first gate dielectric layer, the second gate dielectric layer, the first word line structure and the second word line structure, the 3D stacking of the first word line structure and / or the second word line structure and the bit line structure can be facilitated. Such design does not increase the height of the single-layer transistor in the third direction, is more conducive to 3D stacking, and the process technology is relatively simple and the manufacturing cost is relatively low.

[0044] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0045] The accompanying drawings, which are incorporated in and form a part of the specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the disclosure. It is appreciated that the accompanying drawings are only some embodiments of the present disclosure, and other drawings can be obtained by those of ordinary skill in the art without creative effort based on the drawings.

[0046] Figure 1 A schematic diagram of a semiconductor structure in an embodiment of the present disclosure.

[0047] Figure 2 A top view of a semiconductor structure in an embodiment of the present disclosure.

[0048] Figure 3 A schematic diagram of a semiconductor structure in an embodiment of the present disclosure.

[0049] Figure 4 A cross-sectional view of a second channel region, a second gate dielectric layer and a second word line structure along a second direction in an embodiment of the present disclosure.

[0050] Figure 5 A cross-sectional view of a second channel region, a second gate dielectric layer and a second word line structure along a second direction in another embodiment of the present disclosure.

[0051] Figure 6 A flow chart of a method of forming a semiconductor structure in an embodiment of the present disclosure.

[0052] Figure 7 A schematic diagram of a memory in an embodiment of the present disclosure.

[0053] Figure 8 A top view of a memory in an embodiment of the present disclosure.

[0054] REFERENCE SIGNS:

[0055] 100, memory; 1, active layer; 11, first channel region; 12, second channel region; 13, source region; 14, first drain region; 15, second drain region; 2, first gate dielectric layer; 3, first word line structure; 4, second gate dielectric layer; 5, second word line structure; 6, bit line structure; 7, common electrode; 8, dielectric layer; 9, conductive contact layer; 10, insulating layer; 20, ground electrode; 30, insulating protective layer; X, first direction; Y, second direction; Z, third direction. DETAILED DESCRIPTION

[0056] Example implementations will now be described more fully with reference to the accompanying drawings. Example implementations can be implemented in any

[0057] Although relative terms such as "upper," "lower," etc. are used herein to describe one component's relationship to another component of the icon, such terminology is used in this specification for convenience only and is not limiting of the relative position of the components in the icon. It is to be understood that if the icon were turned over, the component described as being "upper" would then be "lower". When a structure is "on" another structure, it can mean that the structure is formed integrally with the other structure, or that the structure is "directly" on the other structure, or that the structure is "indirectly" on the other structure via another structure.

[0058] The terms "a," "an," "the" and "at least one" are used to mean one or more elements / components / etc.; the terms "comprises", "comprising", "includes", "including" and the like are used to mean open-ended including and do not exclude additional elements / components / etc.; the term "or" is used to mean, and is used in the alternative (e.g., either, but not both) one or more of the enumerated possibilities are present. The terms "first," "second," and "third," etc. are used merely as labels, and are not intended to impose numerical requirements on their objects.

[0059] With the continuous development of mobile devices, mobile devices such as mobile phones, tablets, wearable devices, etc. are more and more widely used in life. As an essential element in mobile devices, people have great demand for the small size and integration of the memory. In the process of memory manufacturing, transistors and capacitors are increasingly difficult to shrink due to structural limitations. As the size of the capacitor decreases, the amount of stored charge decreases, and the leakage phenomenon is more serious. At the same time, when 3D stacking is performed, the 3D stacking of the capacitor is difficult, and various parasitic capacitances in the 3D structure seriously erode the read-write window, resulting in low device reliability.

[0060] Based on this, the semiconductor structure provided by the embodiments of the present disclosure includes an active layer 1, a first gate dielectric layer 2, a first word line structure 3, a second gate dielectric layer 4, a second word line structure 5, a bit line structure 6, a common electrode 7, a dielectric layer 8, and a conductive contact layer 9, as shown in FIGS. 1 and 2. Figure 1 Figure 2 The semiconductor structure includes an active layer 1, a first gate dielectric layer 2, a first word line structure 3, a second gate dielectric layer 4, a second word line structure 5, a bit line structure 6, a common electrode 7, a dielectric layer 8, and a conductive contact layer 9, as shown in FIGS. 1 and 2.

[0061] ​The active layer 1 comprises a first channel region 11, a second channel region 12, a source region 13, a first drain region 14 and a second drain region 15, the first channel region 11 and the second channel region 12 both extend along a first direction X, and the first channel region 11 and the second channel region 12 are spaced apart along a second direction Y; the first direction X intersects the second direction Y; the first drain region 14 is connected with an end portion of the first channel region 11, and the second drain region 15 is connected with an end portion of the second channel region 12 close to the first drain region 14; the source region 13 is connected between an end portion of the first channel region 11 away from the first drain region 14 along the first direction X and an end portion of the second channel region 12 away from the second drain region 15 along the first direction X, and the first drain region 14 and the second drain region 15 are insulatively arranged;

[0062] The first gate dielectric layer 2 covers at least part of a surface of the first channel region 11;

[0063] The first word line structure 3 covers the first gate dielectric layer 2 and extends along the first direction X;

[0064] The second gate dielectric layer 4 covers at least part of a surface of the second channel region 12;

[0065] The second word line structure 5 covers the second gate dielectric layer 4 and extends along the first direction X;

[0066] The bit line structure 6 is electrically connected with the source region 13;

[0067] In the second direction Y, the common electrode 7 is located between the first channel region 11 and the second channel region 12;

[0068] The dielectric layer 8 at least covers an outer periphery of the common electrode 7;

[0069] The conductive contact layer 9 covers a surface of the dielectric layer 8 and is electrically connected with the second drain region 15.

[0070] The semiconductor structure of the present disclosure, on the one hand, the common electrode 7, the dielectric layer 8 and the conductive contact layer 9 can jointly constitute a structure similar to a capacitor, which can be used for storing electric charge; the structure can be read and written by current, compared with the traditional capacitor structure, the structure is not sensitive to various parasitic effects, the leakage phenomenon is obviously weakened, the data storage time is longer, and the refresh frequency can be reduced, the power consumption is reduced, the structure reliability is stronger, and the 3D stacking is facilitated. On the other hand, the active layer 1, the first gate dielectric layer 2, the first word line structure 3, the second gate dielectric layer 4 and the second word line structure 5 jointly constitute a double transistor structure, which can effectively improve the transistor distribution density, and the adjacent transistors can share the source region 13 and the bit line structure 6, which helps to reduce the wiring density, save area and reduce the parasitic coupling effect; in addition, since the source region 13, the first drain region 14 and the second drain region 15 are non-collinear with the first word line structure 3 and / or the second word line structure 5, the parasitic coupling effect can be further reduced while facilitating wiring, thereby improving the device reliability.

[0071] The parts of the semiconductor structure of the present disclosure and their specific details will be described in detail below:

[0072] As shown in Figure 1 and Figure 2 The active layer 1 can include a first channel region 11, a second channel region 12, a source region 13, a first drain region 14 and a second drain region 15, wherein the first channel region 11 and the second channel region 12 can be distributed in parallel, the first channel region 11 and the second channel region 12 can extend along the first direction X, and the first channel region 11 can be distributed in parallel with the second channel region 12 along the second direction Y.

[0073] It should be noted that the first direction X can intersect the second direction Y, for example, the first direction X and the second direction Y can be perpendicular to each other. It should be noted that perpendicular can be absolute perpendicular, or can be approximately perpendicular. In the manufacturing process, there will inevitably be deviations. In the present disclosure, due to the limitation of the manufacturing process, the angle deviation may occur, so that the included angle between the first direction X and the second direction Y has a certain deviation. As long as the angle deviation between the first direction X and the second direction Y is within the preset range, the first direction X and the second direction Y can be considered perpendicular. For example, the preset range can be 10°, that is, the first direction X and the second direction Y can be considered perpendicular when the included angle is greater than or equal to 80° and less than or equal to 100°.

[0074] The first drain region 14 can be connected to an end portion of the first channel region 11 distributed along the first direction X, and the first drain region 14 can be non-collinear with the first channel region 11, for example, the first drain region 14 can extend along the second direction Y. The second drain region 15 is connected to an end portion of the second channel region 12 close to the first drain region 14, for example, the second drain region 15 can be connected to an end portion of the end portions of the second channel region 12 distributed along the first direction X close to the first drain region 14, and the second drain region 15 can be non-collinear with the second channel region 12, for example, the second drain region 15 can extend along the second direction Y. It should be noted that when the first drain region 14 and the second drain region 15 both extend along the second direction Y, the end portion of the first drain region 14 away from the first channel region 11 along the second direction Y can be distributed opposite to the end portion of the second drain region 15 away from the second channel region 12 along the second direction Y, and the end portion of the first drain region 14 away from the first channel region 11 along the second direction Y can be insulated from the end portion of the second drain region 15 away from the second channel region 12 along the second direction Y.

[0075] For example, an insulating layer 10 can be provided between the end portion of the first drain region 14 away from the first channel region 11 along the second direction Y and the end portion of the second drain region 15 away from the second channel region 12 along the second direction Y, and the material of the insulating layer 10 can be silicon nitride. In some embodiments of the present disclosure, the insulating layer 10 can be in a strip shape and can extend along a third direction Z, and the third direction Z can be perpendicular to both the first direction X and the second direction Y.

[0076] The source region 13 can be non-collinear with the first channel region 11 and / or the second channel region 12, and since the first drain region 14, the first channel region 11 and the source region 13 are non-collinear, and the second drain region 15, the second channel region 12 and the source region 13 are non-collinear, the parasitic coupling effect can be reduced while facilitating wiring, and the device reliability can be improved.

[0077] For example, the source region 13 can be connected between the end portion of the first channel region 11 away from the first drain region 14 along the first direction X and the end portion of the second channel region 12 away from the second drain region 15 along the first direction X. The source region 13 can be distributed parallel to the first drain region 14 and / or the second drain region 15, for example, the first drain region 14, the second drain region 15 and the source region 13 can all extend along the second direction Y. In some embodiments of the present disclosure, the first channel region 11, the second channel region 12, the first drain region 14, the second drain region 15, the source region 13 and the insulating layer 10 can form a ring structure similar to a rectangle.

[0078] In some embodiments of this disclosure, the first drain region 14, the second drain region 15, and the source region 13 have the same doping type, the first channel region 11 and the second channel region 12 have the same doping type, and the first drain region 14 and the first channel region 11 have different doping types. For example, the first drain region 14, the second drain region 15, and the source region 13 are all n-type doped, and the first channel region 11 and the second channel region 12 are both p-type doped. n-type ions can be implanted into the first drain region 14, the second drain region 15, and the source region 13 using an ion implantation process.

[0079] In one exemplary embodiment of this disclosure, please continue to refer to Figure 1 and Figure 2 As shown, the semiconductor structure of this disclosure may further include a ground electrode 20, which may be electrically connected to the first drain region 14 to ground the first drain region 14. For example, the ground electrode 20 may be disposed on the surface of the first drain region 14 away from the source region 13 along a first direction X; or, the ground electrode 20 may be at least partially embedded in the first drain region 14; or, the ground electrode 20 may be disposed between the first drain region 14 and the insulating layer 10. The ground electrode 20 may be strip-shaped and may extend along a third direction Z. For example, both the ground electrode 20 and the insulating layer 10 may extend along a third direction Z, and the ground electrode 20 and the insulating layer 10 may be distributed side by side in a second direction Y.

[0080] Please continue reading Figure 1 and Figure 2 As shown, the first gate dielectric layer 2 at least covers a portion of the surface of the first channel region 11. For example, the first gate dielectric layer 2 may at least cover the surface of the first channel region 11 that is away from the second channel region 12 along the second direction Y. The first gate dielectric layer 2 may be strip-shaped and may extend along the first direction X. The material of the first gate dielectric layer 2 may be silicon oxide, and the first gate dielectric layer 2 may be formed on the surface of the first channel region 11 by chemical vapor deposition, physical vapor deposition, atomic layer deposition, or in-situ water vapor oxidation. Of course, the first gate dielectric layer 2 may also be formed by other methods, and no special limitation is made here on the formation method of the first gate dielectric layer 2.

[0081] The first word line structure 3 may cover the surface of the first gate dielectric layer 2. The first word line structure 3 may also be strip-shaped and may extend along the first direction X. For example, the first word line structure 3 may cover the entire surface of the first gate dielectric layer 2. The first word line structure 3 may together with the first gate dielectric layer 2, the first channel region 11, the first drain region 14, and the source region 13 to form a transistor structure.

[0082] In some embodiments of the present disclosure, the first word line structure 3 can include a first conductive layer, a first barrier layer and a second conductive layer distributed in sequence along the second direction Y, wherein the first conductive layer can cover the surface of the first gate dielectric layer 2, the first barrier layer can be located between the first conductive layer and the second conductive layer, the material of the first conductive layer can be polysilicon, the material of the first barrier layer can be titanium nitride, and the material of the second conductive layer can be tungsten. The first barrier layer can prevent the diffusion of metal ions in the second conductive layer into the first conductive layer and / or the first gate dielectric layer 2, thereby helping to improve device reliability.

[0083] In some embodiments of the present disclosure, the first gate dielectric layer 2 can surround the periphery of the first channel region 11, i.e., the first gate dielectric layer 2 can cover the first channel region 11, and the first word line structure 3 can surround the first gate dielectric layer 2, i.e., the first word line structure 3 can cover the first gate dielectric layer 2, thereby forming a full-ring gate structure, which helps to enhance the gate control ability and reduce channel leakage.

[0084] In some embodiments of the present disclosure, the first gate dielectric layer 2 covers the surface of the first channel region 11 away from the second channel region 12 along the second direction Y and the surfaces of the two sidewalls of the first channel region 11 facing each other along the third direction Z. The first word line structure 3 can cover the entire surface of the first gate dielectric layer 2, thereby forming a fin field effect transistor structure with strong gate control ability.

[0085] The second gate dielectric layer 4 covers at least part of the surface of the second channel region 12. For example, the second gate dielectric layer 4 can cover at least the surface of the second channel region 12 away from the first channel region 11 along the second direction Y. The second gate dielectric layer 4 can be strip-shaped and can extend along the first direction X. The material of the second gate dielectric layer 4 can be silicon oxide. The second gate dielectric layer 4 can be formed on the surface of the second channel region 12 by chemical vapor deposition, physical vapor deposition, atomic layer deposition or in-situ water vapor oxidation, or other methods, which are not limited herein.

[0086] The second word line structure 5 can cover the surface of the second gate dielectric layer 4. The second word line structure 5 can be strip-shaped and can extend along the first direction X. For example, the second word line structure 5 can cover the entire surface of the second gate dielectric layer 4. The second word line structure 5, together with the second gate dielectric layer 4, the second channel region 12, the second drain region 15 and the source region 13, can form a transistor structure. It should be noted that the transistor structure formed by the first gate dielectric layer 2, the first channel region 11, the first drain region 14 and the source region 13 and the transistor structure formed by the second gate dielectric layer 4, the second channel region 12, the second drain region 15 and the source region 13 share the same source region 13, which helps to reduce the wiring density, save area and reduce the parasitic coupling effect.

[0087] In some embodiments of the present disclosure, the second word line structure 5 can include a third conductive layer, a second barrier layer and a fourth conductive layer distributed in sequence along the second direction Y, wherein the third conductive layer can cover the surface of the second gate dielectric layer 4, the second barrier layer is located between the third conductive layer and the fourth conductive layer, the material of the third conductive layer can be polysilicon, the material of the second barrier layer can be titanium nitride, and the material of the fourth conductive layer can be tungsten. The second barrier layer can prevent the diffusion of metal ions in the fourth conductive layer into the third conductive layer and / or the second gate dielectric layer 4, which can further improve the reliability of the device.

[0088] In some embodiments of the present disclosure, as shown in FIG. 2, the second gate dielectric layer 4 can surround the periphery of the second channel region 12, i.e., the second gate dielectric layer 4 can cover the second channel region 12, and the second word line structure 5 can surround the second gate dielectric layer 4, i.e., the second word line structure 5 can cover the second gate dielectric layer 4, thereby forming a full ring gate structure, which can enhance the gate control ability and reduce the channel leakage. Figure 4 In some embodiments of the present disclosure, as shown in FIG. 2, the second gate dielectric layer 4 can surround the periphery of the second channel region 12, i.e., the second gate dielectric layer 4 can cover the second channel region 12, and the second word line structure 5 can surround the second gate dielectric layer 4, i.e., the second word line structure 5 can cover the second gate dielectric layer 4, thereby forming a full ring gate structure, which can enhance the gate control ability and reduce the channel leakage.

[0089] Figure 5 In some embodiments of the present disclosure, as shown in FIG. 2, the second gate dielectric layer 4 can surround the periphery of the second channel region 12, i.e., the second gate dielectric layer 4 can cover the second channel region 12, and the second word line structure 5 can surround the second gate dielectric layer 4, i.e., the second word line structure 5 can cover the second gate dielectric layer 4, thereby forming a full ring gate structure, which can enhance the gate control ability and reduce the channel leakage.

[0090] In an exemplary embodiment of the present disclosure, the material of the first channel region 11 can be different from the material of the second channel region 12. For example, the material of the first channel region 11 can be a material with low electron mobility, such as a metal oxide with a large band gap. Specifically, the material of the first channel region 11 can include at least one of indium gallium zinc oxide, indium gallium oxide or indium zinc oxide, which can help reduce the leakage. The material of the second channel region 12 can be a material with high electron mobility, which can help improve the signal transmission speed. For example, the material of the second channel region 12 can include at least one of indium tin oxide, polysilicon, silicon or germanium silicon. It should be noted that at this time, the transistor composed of the first channel region 11, the first drain region 14, the source region 13, the first gate dielectric layer 2 and the first word line structure 3 can be used as a read transistor, and the transistor composed of the second channel region 12, the second drain region 15, the source region 13, the second gate dielectric layer 4 and the second word line structure 5 can be used as a write transistor.

[0091] ​The bit line structure 6 can be electrically connected with the source region 13. For example, the bit line structure 6 can be located on the surface of the source region 13 away from the first drain region 14 and the second drain region 15 in the first direction X. The bit line structure 6 can be formed on the surface of the source region 13 by chemical vapor deposition, physical vapor deposition, atomic layer deposition or other methods. Of course, the bit line structure 6 can also be formed by other methods, which are not particularly limited herein. Alternatively, at least part of the bit line structure 6 can be embedded in the source region 13. In some embodiments of the present disclosure, the bit line structure 6 can be in a strip shape, and the bit line structure 6 can be distributed parallel to the insulating layer 10 and / or the ground electrode 20. For example, the bit line structure 6 can extend in the third direction Z.

[0092] It should be noted that when two transistors share the same source region 13, the two transistors can also share the same bit line structure 6, which helps to reduce the wiring density, save area, reduce the size of the bit line structure, and reduce the parasitic coupling effect.

[0093] In the second direction Y, the common electrode 7 can be located between the first channel region 11 and the second channel region 12. For example, the common electrode 7 can be located within a rectangular ring structure surrounded by the first channel region 11, the second channel region 12, the first drain region 14, the second drain region 15, the source region 13 and the insulating layer 10. It should be noted that the common electrode 7 has a gap with the first channel region 11, the second channel region 12, the first drain region 14, the second drain region 15, the source region 13 and the insulating layer 10. The material of the common electrode 7 can be polysilicon and / or tungsten, etc. In some embodiments of the present disclosure, the common electrode 7 can be in a strip shape and can extend in the third direction Z. The cross section of the common electrode 7 can be in a rectangular shape, a circular shape, an elliptical shape, a polygonal shape or an irregular shape, which are not particularly limited herein.

[0094] The dielectric layer 8 can cover at least the surface of the common electrode 7. For example, the dielectric layer 8 can at least adhere to the outer periphery of the common electrode 7. The material of the dielectric layer 8 can be a high dielectric constant material, for example, it can be aluminum oxide, hafnium oxide, lanthanum oxide, titanium oxide, zirconium oxide, tantalum oxide, niobium oxide, strontium oxide or a mixture thereof. Of course, it can also be other high dielectric constant materials, which are not listed one by one herein.

[0095] The conductive contact layer 9 can cover the surface of the dielectric layer 8 and can be electrically connected with the second drain region 15. For example, the conductive contact layer 9 can be located between the common electrode 7 and the first channel region 11, for example, the conductive contact layer 9 can cover the surface of the dielectric layer 8 close to the first channel region 11 in the second direction Y and the surface of the dielectric layer 8 close to the first drain region 14 and the second drain region 15 in the first direction X. Alternatively, the conductive contact layer 9 can be located between the common electrode 7 and the second channel region 12, for example, the conductive contact layer 9 can cover the surface of the dielectric layer 8 close to the second channel region 12 in the second direction Y and the surface of the dielectric layer 8 close to the first drain region 14 and the second drain region 15 in the first direction X. It should be noted that when the insulating layer 10 is provided between the first drain region 14 and the second drain region 15, part of the conductive contact layer 9 can be located between the common electrode 7 and the insulating layer 10.

[0096] In an exemplary embodiment of the present disclosure, when the conductive contact layer 9 is located between the common electrode 7 and the first channel region 11, part of the dielectric layer 8 can also be located between the conductive contact layer 9, the first drain region 14, the first channel region 11 and the source region 13.

[0097] In an exemplary embodiment of the present disclosure, when the conductive contact layer 9 is located between the common electrode 7 and the second channel region 12, part of the dielectric layer 8 can also be located between the conductive contact layer 9, the second drain region 15, the second channel region 12 and the source region 13.

[0098] The common electrode 7, the dielectric layer 8 and the conductive contact layer 9 in the embodiments of the present disclosure can jointly constitute a structure similar to a capacitor, which can be used to store electric charges; the structure can be read and written by electric current, is not sensitive to various parasitic effects compared to traditional capacitor structures, the leakage phenomenon is significantly weakened, the data storage time is longer, and the refresh frequency and power consumption can be reduced, the structural reliability is strong, and 3D stacking is facilitated.

[0099] The embodiments of the present disclosure also include a forming method of a semiconductor structure, Figure 6 A flowchart of the forming method of the semiconductor structure of the present disclosure is shown in FIG. 1, and the forming method includes steps S110-S190, wherein: Figure 6

[0100] ​Step S110, forming an active layer, the active layer comprising a first channel region, a second channel region, a source region, a first drain region and a second drain region, the first channel region and the second channel region both extending along a first direction, and the first channel region and the second channel region being spaced apart along a second direction; the first direction and the second direction intersecting; the first drain region being connected to an end of the first channel region, and the second drain region being connected to an end of the second channel region close to the first drain region; the source region being connected between an end of the first channel region away from the first drain region and an end of the second channel region away from the second drain region along the first direction, the first drain region and the second drain region being insulated from each other;

[0101] Step S120, forming a first gate dielectric layer covering at least part of a surface of the first channel region;

[0102] Step S130, forming a first word line structure covering the first gate dielectric layer and extending along the first direction;

[0103] Step S140, forming a second gate dielectric layer covering at least part of a surface of the second channel region;

[0104] Step S150, forming a second word line structure covering the second gate dielectric layer and extending along the first direction;

[0105] Step S160, forming a bit line structure, the bit line structure being electrically connected to the source region;

[0106] Step S170, forming a common electrode, the common electrode being located between the first channel region and the second channel region along the second direction;

[0107] Step S180, forming a dielectric layer covering at least a periphery of the common electrode;

[0108] Step S190, forming a conductive contact layer covering a surface of the dielectric layer, the conductive contact layer being electrically connected to the second drain region.

[0109] In an example embodiment of the present disclosure, the material of the first channel region 11 can be different from the material of the second channel region 12. For example, the material of the first channel region 11 can be a material with lower electron mobility, such as a metal oxide with a larger band gap. Specifically, the material of the first channel region 11 can include at least one of indium gallium zinc oxide, indium gallium oxide or indium zinc oxide, which helps to reduce leakage current. The material of the second channel region 12 can be a material with higher electron mobility, so as to improve signal transmission speed. For example, the material of the second channel region 12 can include at least one of indium tin oxide, polysilicon, silicon or germanium silicon.

[0110] In some embodiments of the present disclosure, the forming method of the present disclosure can further comprise:

[0111] Step S200, forming an insulating layer between the first drain region and the second drain region.

[0112] The material of the insulating layer 10 can be silicon nitride. The insulating layer 10 can be in a strip shape and can extend along the third direction Z. The first channel region 11, the second channel region 12, the first drain region 14, the second drain region 15, the source region 13, and the insulating layer 10 can form a ring structure similar to a rectangle.

[0113] On one hand, the common electrode 7, the dielectric layer 8, and the conductive contact layer 9 can jointly form a structure similar to a capacitor, which can be used for storing electric charges. This structure can be read and written through current. Compared with a traditional capacitor structure, this structure is not sensitive to various parasitic effects, the leakage phenomenon is significantly weakened, the data storage time is longer, the refresh frequency can be reduced, the power consumption is reduced, the structural reliability is stronger, and the 3D stacking is facilitated. On the other hand, the active layer 1, the first gate dielectric layer 2, the first word line structure 3, the second gate dielectric layer 4, and the second word line structure 5 jointly form a double-transistor structure, which can effectively improve the transistor distribution density, and the adjacent transistors can share the source region 13 and the bit line structure 6, which helps to reduce the wiring density, save the area, and reduce the parasitic coupling effect. In addition, since the source region 13, the first drain region 14, and the second drain region 15 are not collinear with the first word line structure 3 and / or the second word line structure 5, the parasitic coupling effect can be further reduced while facilitating wiring, thereby improving the device reliability.

[0114] The specific details of the forming method of the semiconductor structure of the present disclosure have been described in detail in the corresponding embodiments of the semiconductor structure, and thus will not be repeated here.

[0115] It should be noted that although the steps of the forming method of the semiconductor structure of the present disclosure are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in this specific order, or that all the steps shown must be performed to achieve the desired results. In addition or alternatively, some steps can be omitted, a plurality of steps can be combined into one step, and / or one step can be divided into a plurality of steps, etc.

[0116] The present disclosure also provides a memory 100, as shown in Figure 7 and Figure 8As shown, the memory 100 comprises a plurality of semiconductor structures according to any of the above embodiments, the number of semiconductor structures is multiple, the multiple semiconductor structures form multiple semiconductor groups which are spaced along the first direction X, and the semiconductor group comprises multiple semiconductor structures which are stacked along the third direction Z; the semiconductor structures in the same semiconductor group share the bit line structure 6, and two semiconductor structures in different semiconductor groups which are adjacent along the first direction X share the first gate dielectric layer 2, the second gate dielectric layer 4, the first word line structure 3 and the second word line structure 5.

[0117] The memory 100 of the present disclosure, since the source region 13, the first drain region 14 and the second drain region 15 are all non-collinear with the first word line structure 3 and / or the second word line structure 5, and the semiconductor structures in the same semiconductor group share the bit line structure 6 along the third direction Z, and two semiconductor structures in different semiconductor groups which are adjacent along the first direction X share the first gate dielectric layer 2, the second gate dielectric layer 4, the first word line structure 3 and the second word line structure 5, the 3D stacking of the first word line structure 3 and / or the second word line structure 5 and the bit line structure 6 can be facilitated, such design does not increase the height of the single-layer transistor along the third direction Z, is more conducive to 3D stacking, and the process is relatively simple and the manufacturing cost is relatively low.

[0118] It should be noted that when the semiconductor structure further comprises the insulating layer 10, the semiconductor structures in the same semiconductor group can share the same insulating layer 10; when the semiconductor structure further comprises the ground electrode 20, the semiconductor structures in the same semiconductor group can share the same ground electrode 20.

[0119] In an exemplary embodiment of the present disclosure, please continue to refer to Figure 8 As shown, the memory of the present disclosure can further comprise an insulating protective layer 30, the insulating protective layer 30 can fill the remaining gaps in the semiconductor group and the gaps between adjacent semiconductor groups, and each part in the memory can be insulated and protected by the insulating protective layer 30 to prevent short circuit or coupling between structures, which helps to further improve the reliability of the device.

[0120] Other embodiments of the present disclosure will be apparent to those skilled in the art with the consideration of the specification and practice of the disclosure disclosed herein. The present disclosure is intended to cover any variations, uses or adaptive changes of the present disclosure which follow the general principles of the present disclosure and include common knowledge or conventional technical means in the art which are not disclosed by the present disclosure. The specification and examples are only regarded as exemplary, and the true scope and spirit of the present disclosure are indicated by the appended claims.

Claims

1. A semiconductor structure, characterized in that, include: An active layer includes a first channel region, a second channel region, a source region, a first drain region, and a second drain region. The first channel region and the second channel region both extend along a first direction, and the first channel region and the second channel region are spaced apart along a second direction. The first direction and the second direction intersect. The first drain region is connected to one end of the first channel region, and the second drain region is connected to the end of the second channel region closest to the first drain region. The source region is connected between the end of the first channel region away from the first drain region along the first direction and the end of the second channel region away from the second drain region along the first direction. The first drain region and the second drain region are insulated from each other. The first gate dielectric layer covers at least a portion of the surface of the first channel region; The first word line structure covers the first gate dielectric layer and extends along the first direction; Second gate A dielectric layer, at least covering a portion of the surface of the second channel region; The second word line structure covers the second gate dielectric layer and extends along the first direction; The bit line structure is electrically connected to the source region; A common electrode, in the second direction, is located between the first channel region and the second channel region; A dielectric layer, at least covering the outer periphery of the common electrode; A conductive contact layer covers the surface of the dielectric layer and is electrically connected to the second drain region.

2. The semiconductor structure according to claim 1, characterized in that, The conductive contact layer is located between the common electrode and the first channel region; or, the conductive contact layer is located between the common electrode and the second channel region.

3. The semiconductor structure according to claim 2, characterized in that, When the conductive contact layer is located between the common electrode and the first channel region, the dielectric layer is also located between the conductive contact layer and the first drain region, the first channel region, and the source region; when the conductive contact layer is located between the common electrode and the second channel region, the dielectric layer is also located between the conductive contact layer and the second drain region, the second channel region, and the source region.

4. The semiconductor structure according to claim 1, characterized in that, The dielectric layer is made of a material with a high dielectric constant.

5. The semiconductor structure according to claim 1, characterized in that, The first gate dielectric layer surrounds the first channel region, and the first word line structure surrounds the first gate dielectric layer. And / or, the second gate dielectric layer surrounds the second channel region, and the second word line structure surrounds the second gate dielectric layer.

6. The semiconductor structure according to claim 1, characterized in that, The first gate dielectric layer covers the surface of the first channel region that is away from the second channel region and the surfaces of two sidewalls that are opposite each other in the first channel region along a third direction, the third direction being perpendicular to the first direction and the second direction; And / or, the second gate dielectric layer covers the surface of the second channel region away from the first channel region and the surfaces of the two sidewalls of the second channel region that are opposite each other along the third direction.

7. The semiconductor structure according to any one of claims 1-6, characterized in that, The materials of the first channel region and the second channel region are different.

8. The semiconductor structure according to claim 7, characterized in that, The material of the first channel region includes at least one of indium gallium zinc oxide, indium gallium oxide, or indium zinc oxide.

9. The semiconductor structure according to claim 7, characterized in that, The material of the second channel region includes at least one of indium tin oxide, polycrystalline silicon, monocrystalline silicon, or germanium silicon.

10. The semiconductor structure according to any one of claims 1-6, characterized in that, The semiconductor structure also includes: An insulating layer is located between the first drain region and the second drain region.

11. The semiconductor structure according to any one of claims 1-6, characterized in that, The semiconductor structure further includes a ground electrode, which is electrically connected to the first drain region to ground the first drain region.

12. A memory, characterized in that, The invention includes a plurality of semiconductor structures as described in any one of claims 1-11, wherein the number of semiconductor structures is plurality of, and the plurality of semiconductor structures form a plurality of semiconductor groups spaced apart along a first direction, wherein the semiconductor group includes a plurality of semiconductor structures stacked along a third direction; each semiconductor structure in the same semiconductor group shares the bit line structure, and two adjacent semiconductor structures in different semiconductor groups along the first direction share the first gate dielectric layer, the second gate dielectric layer, the first word line structure and the second word line structure.

13. A method for forming a semiconductor structure, characterized in that, include: An active layer is formed, comprising a first channel region, a second channel region, a source region, a first drain region, and a second drain region. The first channel region and the second channel region both extend along a first direction, and the first channel region and the second channel region are spaced apart along a second direction. The first direction and the second direction intersect. The first drain region is connected to one end of the first channel region, and the second drain region is connected to the end of the second channel region closest to the first drain region. The source region is connected between the end of the first channel region away from the first drain region along the first direction and the end of the second channel region away from the second drain region along the first direction. The first drain region and the second drain region are insulated from each other. A first gate dielectric layer is formed that at least covers a portion of the surface of the first channel region; A first word line structure is formed that covers the first gate dielectric layer and extends along the first direction; A second gate dielectric layer is formed that at least covers a portion of the surface of the second channel region; A second word line structure is formed that covers the second gate dielectric layer and extends along the first direction; A bit line structure is formed, and the bit line structure is electrically connected to the source region; A common electrode is formed, wherein, in the second direction, the common electrode is located between the first channel region and the second channel region; A dielectric layer is formed that at least covers the outer periphery of the common electrode; A conductive contact layer is formed covering the surface of the dielectric layer, and the conductive contact layer is electrically connected to the second drain region.

14. The forming method according to claim 13, characterized in that, The materials of the first channel region and the second channel region are different.

15. The forming method according to claim 13 or 14, characterized in that, The forming method further includes: An insulating layer is formed between the first drain region and the second drain region.

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