Semiconductor structure and method of forming the same

Abstract

The present disclosure relates to a semiconductor structure and a method for forming the same. The semiconductor structure comprises a substrate, a memory cell on the substrate, the memory cell comprising a transistor region and a capacitor region, the memory cell further comprising an oxide semiconductor layer continuously distributed in the transistor region and the capacitor region, the oxide semiconductor layer in the transistor region serving as an active layer of a transistor, and the oxide semiconductor layer in the capacitor region serving as a lower electrode layer of a capacitor, the lower electrode layer having a lower resistance than the active layer. The present disclosure simplifies the manufacturing process of the semiconductor structure and improves the manufacturing yield of the semiconductor structure.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor manufacturing, and in particular, to a semiconductor structure and a forming method thereof. BACKGROUND

[0002] Dynamic Random Access Memory (DRAM) is a semiconductor device commonly used in electronic devices such as computers, which is composed of a plurality of memory cells, each of which usually includes a transistor and a capacitor. The gate of the transistor is electrically connected to the word line, the source is electrically connected to the bit line, and the drain is electrically connected to the capacitor. The word line voltage on the word line can control the opening and closing of the transistor, so that the data information stored in the capacitor can be read through the bit line, or the data information can be written into the capacitor.

[0003] DRAM and other semiconductor structures usually use a 6F2 arrangement and a buried word line manufacturing process. However, as the size of DRAM and other semiconductor structures is further miniaturized, the performance of the semiconductor structure will be greatly reduced. In order to meet the requirements of continuously reducing the size and increasing the storage capacity of DRAM and other semiconductor structures, DRAM and other semiconductor structures with three-dimensional stacked structure have emerged. However, the current process for manufacturing DRAM and other semiconductor structures with three-dimensional stacked structure is relatively complex. For example, the forming processes of the transistor and the capacitor in DRAM are carried out separately, which is relatively cumbersome and complex, thereby reducing the manufacturing yield and production efficiency of the semiconductor structure.

[0004] Therefore, how to simplify the manufacturing process of the semiconductor structure while improving the performance of the semiconductor structure is a technical problem to be solved at present. SUMMARY

[0005] Some embodiments of the present disclosure provide a semiconductor structure and a forming method thereof, which are used to simplify the manufacturing process of the semiconductor structure and improve the performance of the semiconductor structure.

[0006] According to some embodiments, the present disclosure provides a semiconductor structure, comprising:

[0007] a substrate;

[0008] a memory cell located on the substrate, comprising a transistor region and a capacitor region, the memory cell further comprising an oxide semiconductor layer continuously distributed in the transistor region and the capacitor region, the oxide semiconductor layer in the transistor region serving as an active layer of a transistor, and the oxide semiconductor layer in the capacitor region serving as a lower electrode layer of a capacitor, the resistance of the lower electrode layer being lower than the resistance of the active layer.

[0009] In some embodiments, the oxide semiconductor layer includes a first oxide semiconductor layer and a second oxide semiconductor layer, which are both extended along a first direction and are both spaced apart along a second direction, the first direction and the second direction are both parallel to the top surface of the substrate, and the first direction intersects the second direction.

[0010] The first oxide semiconductor layer of the transistor region serves as a first active layer, the second oxide semiconductor layer of the transistor region serves as a second active layer, and the first active layer and the second active layer collectively constitute the active layer.

[0011] The first oxide semiconductor layer of the capacitor region serves as a first lower electrode layer, the second oxide semiconductor layer of the capacitor region serves as a second lower electrode layer, and the first lower electrode layer and the second lower electrode layer collectively constitute the lower electrode layer.

[0012] In some embodiments, a projection of the first active layer on the top surface of the substrate, a projection of the second active layer on the top surface of the substrate, a projection of the first lower electrode layer on the top surface of the substrate, and a projection of the second lower electrode layer on the top surface of the substrate are all L-shaped.

[0013] In some embodiments, the transistor further includes a gate structure, the gate structure includes a first gate layer and a second gate layer, the first gate layer is located between the first active layer and the second active layer, and the second gate layer is located on a side of the first active layer away from the first gate layer and on a side of the second active layer away from the first gate layer.

[0014] The capacitor further includes a dielectric layer covering a surface of the lower electrode layer and an upper electrode layer covering a surface of the dielectric layer, the upper electrode layer includes a first upper electrode layer and a second upper electrode layer that are electrically connected to each other, the first upper electrode layer is located between the first lower electrode layer and the second lower electrode layer, and the second upper electrode layer is located on a side of the first lower electrode layer away from the first upper electrode layer and on a side of the second lower electrode layer away from the first upper electrode layer.

[0015] In some embodiments, the material of the second upper electrode layer is the same as the material of the second gate layer, and the second upper electrode layer is disposed in the same layer as the second gate layer.

[0016] In some embodiments, further comprising:

[0017] A word line lead-out structure is located above the transistor, and the word line lead-out structure includes a first lead-out plug, a second lead-out plug, and a word line lead wire, one end of the first lead-out plug is electrically connected with the first gate layer, the other end of the first lead-out plug is electrically connected with the word line lead wire, one end of the second lead-out plug is electrically connected with the second gate layer, the other end of the second lead-out plug is electrically connected with the word line lead wire.

[0018] In some embodiments, the first active layer includes a first channel region, and a first source region and a first drain region distributed on opposite sides of the first channel region along the first direction, the first lower electrode layer is in contact and electrically connected with the first drain region;

[0019] The second active layer includes a second channel region, and a second source region and a second drain region distributed on opposite sides of the second channel region along the first direction, the second lower electrode layer is in contact and electrically connected with the second drain region;

[0020] The semiconductor structure further includes a bit line, the bit line extends along the second direction, and the bit line is electrically connected with the first source region and the second source region.

[0021] In some embodiments, the number of the storage units is a plurality, and the plurality of the storage units are arranged in an array along the second direction and a third direction, the third direction is perpendicular to the top surface of the substrate;

[0022] A plurality of the bit lines are arranged at intervals along the third direction, and each of the bit lines is electrically connected with the active layer in the plurality of the storage units arranged at intervals along the second direction;

[0023] The gate structure in the plurality of the storage units arranged at intervals along the third direction is electrically connected.

[0024] In some embodiments, the concentration of oxygen vacancies in the lower electrode layer is greater than the concentration of oxygen vacancies in the active layer.

[0025] According to other embodiments, the disclosure further provides a forming method of a semiconductor structure, including the following steps:

[0026] Providing a substrate;

[0027] Forming a storage unit on the substrate, the storage unit includes a transistor region and a capacitor region, the storage unit further includes an oxide semiconductor layer continuously distributed in the transistor region and the capacitor region, the oxide semiconductor layer in the transistor region serves as an active layer of a transistor, and the oxide semiconductor layer in the capacitor region serves as a lower electrode layer of a capacitor, the resistance of the lower electrode layer is lower than the resistance of the active layer.

[0028] In some embodiments, the specific step of forming a memory cell on the substrate comprises:

[0029] forming a stack layer on the substrate, the stack layer comprising alternatingly stacked interlayer insulating layers and sacrificial layers along a third direction, and the stack layer comprising a transistor region and a capacitor region arranged along a first direction, the first direction being parallel to a top surface of the substrate;

[0030] forming a first trench through the transistor region and the capacitor region of the stack layer along the third direction;

[0031] forming an oxide semiconductor layer covering inner walls of the first trench;

[0032] reducing a resistance of the oxide semiconductor layer of the capacitor region, forming the active layer in the transistor region and the lower electrode layer in the capacitor region.

[0033] In some embodiments, the specific step of forming a first trench through the transistor region and the capacitor region of the stack layer along the third direction comprises:

[0034] removing the sacrificial layers of the capacitor region, forming a second trench between adjacent interlayer insulating layers in the capacitor region;

[0035] forming a first isolation layer filling the second trench;

[0036] etching the stack layer and the first isolation layer, forming a first trench through the transistor region and the capacitor region of the stack layer along the third direction and through the first isolation layer along the third direction.

[0037] In some embodiments, the specific step of reducing a resistance of the oxide semiconductor layer of the capacitor region comprises:

[0038] treating the oxide semiconductor layer of the capacitor region with plasma to increase oxygen vacancies in the oxide semiconductor layer of the capacitor region; or;

[0039] implanting doping ions into the oxide semiconductor layer of the capacitor region to enhance a conductivity of the oxide semiconductor layer of the capacitor region.

[0040] In some embodiments, the specific step of forming the active layer in the transistor region and the lower electrode layer in the capacitor region comprises:

[0041] removing the oxide semiconductor layer between adjacent ones of the sacrificial layers, the oxide semiconductor layer remaining in the capacitor region forming a plurality of initial lower electrode layers spaced apart along the third direction, and the oxide semiconductor layer remaining in the transistor region forming a plurality of initial active layers spaced apart along the third direction;

[0042] splitting the initial lower electrode layers and the initial active layers to form lower electrode layers including first lower electrode layers and second lower electrode layers spaced apart along a second direction, and to form active layers including first active layers and second active layers spaced apart along the second direction, the second direction being parallel to a top surface of the substrate and intersecting the first direction.

[0043] In some embodiments, after forming lower electrode layers including first lower electrode layers and second lower electrode layers spaced apart along a second direction, and forming active layers including first active layers and second active layers spaced apart along the second direction, the method further comprises:

[0044] forming a dielectric layer covering the first lower electrode layers and the second lower electrode layers, and forming a gate dielectric layer covering the first active layers and the second active layers;

[0045] forming an upper electrode layer covering the dielectric layer, and forming a gate structure covering the gate dielectric layer, to form the capacitor including the lower electrode layers, the dielectric layer, and the upper electrode layer, and to form the transistor including the first active layers, the second active layers, the gate dielectric layer, and the gate structure.

[0046] Some embodiments of the present disclosure provide a semiconductor structure and a method of forming the same. The oxide semiconductor layer is continuously distributed in the transistor region and the capacitor region in the memory cell. The oxide semiconductor layer in the transistor region is used as the active layer of the transistor, and the oxide semiconductor layer in the capacitor region is used as the lower electrode layer of the capacitor. The resistance of the lower electrode layer is lower than that of the active layer. Therefore, part of the manufacturing process of the transistor and part of the manufacturing process of the capacitor can be performed synchronously, which simplifies the manufacturing process of the semiconductor structure and improves the manufacturing efficiency of the semiconductor structure. Some other embodiments of the present disclosure improve the conductivity of the oxide semiconductor layer used to form the lower electrode layer by using a resistance reduction process. The lower electrode layer has good conductivity, and the resistance of the lower electrode layer can be adjusted flexibly. Therefore, the performance of the semiconductor structure is further improved, and the manufacturing yield of the semiconductor structure is improved. BRIEF DESCRIPTION OF DRAWINGS

[0047] ATTACHMENT Figure 1is a top view schematic diagram of a semiconductor structure in the specific embodiment of the present disclosure;

[0048] attached Figure 2 is a perspective schematic diagram of a semiconductor structure in the specific embodiment of the present disclosure;

[0049] attached Figure 3 is a flow chart of a forming method of a semiconductor structure in the specific embodiment of the present disclosure;

[0050] attached Figure 4 - attached Figure 18 is a main process structure schematic diagram in the process of forming a semiconductor structure in the specific embodiment of the present disclosure. DETAILED DESCRIPTION

[0051] The specific embodiments of the semiconductor structure and the forming method thereof provided by the present disclosure are described in detail below with reference to the accompanying drawings.

[0052] The specific embodiments provide a semiconductor structure, attached Figure 1 is a top view schematic diagram of a semiconductor structure in the specific embodiment of the present disclosure, attached Figure 2 is a perspective schematic diagram of a semiconductor structure in the specific embodiment of the present disclosure. As shown in Figure 1 and Figure 2 The semiconductor structure comprises:

[0053] a substrate 71;

[0054] a memory cell located on the substrate 71, comprising a transistor region and a capacitor region, the memory cell further comprising an oxide semiconductor layer 80 continuously distributed in the transistor region and the capacitor region, the oxide semiconductor layer 80 in the transistor region serving as an active layer 19 of a transistor 17, and the oxide semiconductor layer 80 in the capacitor region serving as a lower electrode layer 29 of a capacitor 18, the resistance of the lower electrode layer 29 being lower than the resistance of the active layer 19.

[0055] The semiconductor structure described in the present embodiment can be, but is not limited to, a DRAM, and the present embodiment takes the semiconductor structure as an example of a DRAM. The substrate 71 can be, but is not limited to, a silicon substrate, and the present embodiment takes the substrate 71 as an example of a silicon substrate. In other embodiments, the substrate 71 can also be a semiconductor substrate such as a gallium nitride, a gallium arsenide, a gallium carbide, a silicon carbide, or an SOI. The substrate 71 is used to support the device structure thereon, and a top surface of the substrate 71 is a surface of the substrate 71 facing the memory cell. The memory cell is located on the top surface of the substrate 71, and the memory cell includes the transistor 17 located in the transistor region and the capacitor 18 electrically connected with the transistor 17 and located in the capacitor region. In a write operation of the memory cell, data can be stored in the capacitor 18 by turning on the transistor 17, and in a read operation of the memory cell, data stored in the capacitor 18 can be read by turning on the transistor 17. The transistor 17 includes the active layer 19, and the active layer 19 includes a channel region and a source region and a drain region distributed on opposite sides of the channel region along a first direction D1. The capacitor 18 is located at an end of the transistor 17 along the first direction D1, and the lower electrode layer 29 is in contact with an end of the active layer 19 along the first direction D1 (for example, the drain region in the active layer 19) and is electrically connected. The first direction D1 is parallel to the top surface of the substrate 71. The material of the oxide semiconductor layer 80 includes an oxide semiconductor material.

[0056] The present embodiment can synchronize the manufacturing process of the active layer 19 in the transistor 17 and the manufacturing process of the lower electrode layer 29 in the capacitor 18 by continuously distributing the oxide semiconductor layer 80 in the transistor region and the capacitor region, and using the oxide semiconductor layer 80 in the transistor region as the active layer 19 of the transistor 17 and using the oxide semiconductor layer 80 in the capacitor region as the lower electrode layer 29 of the capacitor 18, thereby simplifying the manufacturing process of the memory cell and the semiconductor structure and improving the manufacturing efficiency of the semiconductor structure. Moreover, the present embodiment uses the oxide semiconductor layer 80 as the lower electrode layer 29 and the active layer 19, and the resistance of the lower electrode layer 29 is lower than the resistance of the active layer 19, so that the anti-leakage characteristics of the transistor 17 are improved and the lower electrode layer 29 has good conductive performance, thereby further improving the performance of the semiconductor structure and improving the manufacturing yield of the semiconductor structure. The material of the oxide semiconductor layer 80 in the present embodiment is any one of In2O3 (indium oxide), ZnO (zinc oxide), IZO (indium zinc oxide), IGZO (indium gallium zinc oxide), IZTO (indium tin zinc oxide), ZnON (zinc oxynitride), or a combination of two or more thereof. In an example, the material of the oxide semiconductor layer 80 is IGZO.

[0057] In an example, the semiconductor structure includes a plurality of memory cells, and the plurality of memory cells are arranged in a three-dimensional array on the substrate 71 along the first direction D1, the second direction D2, and the third direction D3, thereby further improving the storage capacity of the semiconductor structure and further miniaturizing the semiconductor structure. The second direction D2 is parallel to the top surface of the substrate 71, and the second direction D2 intersects (e.g., obliquely intersects or perpendicularly intersects) the first direction D1, and the third direction D3 is perpendicular to the top surface of the substrate 71.

[0058] In some embodiments, the oxide semiconductor layer 80 includes a first oxide semiconductor layer and a second oxide semiconductor layer, which are both extended along a first direction D1 and are arranged at intervals along a second direction D2, the first direction D1 and the second direction D2 are both parallel to the top surface of the substrate 71, and the first direction D1 intersects the second direction D2;

[0059] The first oxide semiconductor layer in the transistor region is used as a first active layer 101, the second oxide semiconductor layer in the transistor region is used as a second active layer 102, and the first active layer 101 and the second active layer 102 together constitute the active layer 19;

[0060] The first oxide semiconductor layer of the capacitor region serves as a first lower electrode layer 111, and the second oxide semiconductor layer of the capacitor region serves as a second lower electrode layer 112, and the first lower electrode layer 111 and the second lower electrode layer 112 together constitute the lower electrode layer 29.

[0061] In particular, the first active layer 101 is in contact with the first lower electrode layer 111 and is electrically connected therewith, the second active layer 102 is in contact with the second lower electrode layer 112 and is electrically connected therewith, and the material of the first active layer 101, the material of the second active layer 102, the material of the first lower electrode layer 111, and the material of the second lower electrode layer 112 are all constituted by the oxide semiconductor layer 80 including an oxide semiconductor material, so that the first active layer 101, the second active layer 102, the first lower electrode layer 111, and the second lower electrode layer 112 are arranged in the same layer. By constituting the first active layer 101 and the second active layer 102 arranged at intervals along the second direction D2 and the first electrode layer 111 and the second electrode layer 112 arranged at intervals along the second direction D2 by the oxide semiconductor layer 80, on the one hand, the surface area of the lower electrode layer 29 can be increased, and thus the area of the capacitor 18 including the lower electrode layer 29, i.e., the storage capacity of the capacitor 18, can be increased; on the other hand, the channel length of the transistor 17 can be shortened, and thus the response speed of the transistor 17 can be improved. In an example, the material and composition of the first active layer 101 are the same as those of the second active layer 102, and the material and composition of the first lower electrode layer 111 are the same as those of the second lower electrode layer 112.

[0062] In some embodiments, the projection of the first active layer 101 on the top surface of the substrate 71, the projection of the second active layer 102 on the top surface of the substrate 71, the projection of the first lower electrode layer 111 on the top surface of the substrate 71, and the projection of the second lower electrode layer 112 on the top surface of the substrate 71 are all L-shaped.

[0063] For example, as Figure 1As shown, the projection of the first active layer 101 on the top surface of the substrate 71 and the projection of the second active layer 102 on the top surface of the substrate 71 are both L-shaped, so as to increase the contact area of the first active layer 101 and the second active layer 102 with the bit line 14, reduce the contact resistance between the transistor 17 and the bit line 14, and further improve the performance of the semiconductor structure. The projection of the first lower electrode layer 111 on the top surface of the substrate 71 and the projection of the second lower electrode layer 112 on the top surface of the substrate 71 are both L-shaped, so as to further increase the area of the capacitor 18, and achieve further improvement of the storage capacity of the capacitor 18. In an example, as shown in FIG. 1, the corner of the L-shaped first active layer 101 is located on the side of the first active layer 101 away from the first lower electrode layer 111, and the corner of the L-shaped first lower electrode layer 111 is located on the side of the first lower electrode layer 111 away from the first active layer 101. The corner of the L-shaped second active layer 102 is located on the side of the second active layer 102 away from the second lower electrode layer 112, and the corner of the L-shaped second lower electrode layer 112 is located on the side of the second lower electrode layer 112 away from the second active layer 102, so as to further simplify the manufacturing process of the semiconductor structure. Figure 1 As shown, the corner of the L-shaped first active layer 101 is located on the side of the first active layer 101 away from the first lower electrode layer 111, and the corner of the L-shaped first lower electrode layer 111 is located on the side of the first lower electrode layer 111 away from the first active layer 101. The corner of the L-shaped second active layer 102 is located on the side of the second active layer 102 away from the second lower electrode layer 112, and the corner of the L-shaped second lower electrode layer 112 is located on the side of the second lower electrode layer 112 away from the second active layer 102, so as to further simplify the manufacturing process of the semiconductor structure.

[0064] In some embodiments, the transistor 17 further includes a gate structure, the gate structure including a first gate layer 131 and a second gate layer 133, the first gate layer 131 being located between the first active layer 101 and the second active layer 102, and the second gate layer 133 being located on the side of the first active layer 101 away from the first gate layer 131 and on the side of the second active layer 102 away from the first gate layer 131.

[0065] The capacitor 18 further includes a dielectric layer 16 covering the surface of the lower electrode layer 29 and an upper electrode layer covering the surface of the dielectric layer 16, the upper electrode layer including a first upper electrode layer 151 and a second upper electrode layer 152 electrically connected to each other, the first upper electrode layer 151 being located between the first lower electrode layer 111 and the second lower electrode layer 112, and the second upper electrode layer 112 being located on the side of the first lower electrode layer 111 away from the first upper electrode layer 111 and on the side of the second lower electrode layer 112 away from the first upper electrode layer 111.

[0066] For example, as shown in FIG. 1, the first active layer 101 and the second active layer 102 are both L-shaped, and the first lower electrode layer 111 and the second lower electrode layer 112 are both L-shaped. Figure 1 and Figure 2As shown, the semiconductor structure further includes a first gate dielectric layer 121 covering the first active layer 101 and the second active layer 102, a gate contact layer 132 covering the first gate dielectric layer 121, the first gate layer 131 covering the gate contact layer 132, a second gate dielectric layer 122 covering the first active layer 101 and the second active layer 102, and the second gate layer 133 covering the second gate dielectric layer 122, the first gate dielectric layer 121 and the second gate dielectric layer 122 are distributed on opposite sides of the first active layer 101 and the second active layer 102 along the second direction D2. The present embodiment helps to further improve the gate control performance of the transistor 17 by dividing the gate structure into the first gate layer 131 and the second gate layer 133. In an example, the material of the first gate dielectric layer 121 and the material of the second gate dielectric layer 122 are the same, for example, both are oxide materials (e.g., silicon dioxide). The material of the gate contact layer 132 can be polysilicon material, and the gate contact layer 132 is in contact with the first gate layer 131 for electrical connection, so as to further reduce the contact resistance inside the transistor 17. The first upper electrode layer 151 and the second upper electrode layer 152 in the capacitor are electrically connected.

[0067] In some embodiments, the material of the second upper electrode layer 152 is the same as the material of the second gate layer 133, and the second upper electrode layer 152 is arranged in the same layer as the second gate layer 133, so that the second upper electrode layer 152 and the second gate layer 133 can be formed synchronously, thereby further simplifying the manufacturing process of the semiconductor structure.

[0068] In some embodiments, the semiconductor structure further includes:

[0069] A word line lead-out structure is located above the transistor 17, and the word line lead-out structure includes a first lead-out plug, a second lead-out plug 26, and a word line lead wire 28, one end of the first lead-out plug is electrically connected with the first gate layer 131, and the other end is electrically connected with the word line lead wire 28, one end of the second lead-out plug 26 is electrically connected with the second gate layer 133, and the other end is electrically connected with the word line lead wire 28.

[0070] Specifically, as Figure 1 and Figure 2As shown, the word line lead-out structure is located above the storage unit along a third direction D3, the word line lead-out structure includes the first lead-out plug electrically connected with the first gate layer 131, the second lead-out plug electrically connected with the second gate layer 133, a word line bridge line 27 electrically connecting the first lead-out plug and the second lead-out plug 26, and the word line lead wire 28 electrically connected with the word line bridge line 27. The word line control signal from the outside is transmitted to the first lead-out plug and the second lead-out plug 26 through the word line lead wire 28 and the word line bridge line 27 in sequence, and then transmitted to the first gate layer 131 by the first lead-out plug and to the second gate layer 133 by the second lead-out plug 26 synchronously. The third direction D3 is perpendicular to the top surface of the substrate 71.

[0071] In some embodiments, the first active layer 101 includes a first channel region, and a first source region and a first drain region distributed on opposite sides of the first channel region along the first direction D1, and the first lower electrode layer 111 is in contact with the first drain region for electrical connection;

[0072] The second active layer 102 includes a second channel region, and a second source region and a second drain region distributed on opposite sides of the second channel region along the first direction D1, and the second lower electrode layer 112 is in contact with the second drain region for electrical connection;

[0073] The semiconductor structure further includes a bit line 14, the bit line 14 extends along the second direction D2, and the bit line 14 is electrically connected with the first source region and the second source region.

[0074] Specifically, the bit line 14 extends along the second direction D2, and is electrically connected with the first source region and the second source region in the storage unit at the same time. A bit line lead-out structure is further included above the bit line 14, the bit line lead-out structure includes a bit line plug 24 and a bit line lead wire 25, one end of the bit line plug 24 is electrically connected with the bit line 14, and the other end is electrically connected with the bit line lead wire 25. In an example, the bit line lead wire 25 and the word line lead wire 28 both extend along the first direction D1.

[0075] In some embodiments, the number of the storage units is a plurality, and a plurality of the storage units are arranged in an array along the second direction D2 and a third direction D3, the third direction D3 is perpendicular to the top surface of the substrate 71;

[0076] A plurality of the bit lines 14 are arranged at intervals along the third direction D3, and each of the bit lines 14 is electrically connected with the active layer 19 in a plurality of the storage units arranged at intervals along the second direction D2;

[0077] The gate structures in the plurality of memory cells arranged along the third direction D3 are electrically connected.

[0078] For example, the semiconductor structure includes a plurality of memory cells arranged in a three-dimensional array along the second direction D2 and the third direction D3. A plurality of bit lines 14 are arranged along the third direction D3, and each of the bit lines 14 is electrically connected to the active layer 19 in the plurality of memory cells arranged along the second direction D2. A plurality of bit line lead-out structures are electrically connected to the plurality of bit lines 14, respectively, for leading out signals of the plurality of bit lines 14. The first gate layer 131 in the plurality of memory cells arranged along the third direction D3 is electrically connected, and the second gate layer 133 in the plurality of memory cells arranged along the third direction D3 is also electrically connected.

[0079] In an example, the semiconductor structure further includes an upper electrode lead-out structure, which includes a third lead-out plug 21, a fourth lead-out plug 22, an upper electrode bridge line 20, and an upper electrode lead line 23. One end of the third lead-out plug 21 is electrically connected to the first upper electrode layer 151, and the other end is electrically connected to the upper electrode bridge line 20. One end of the fourth lead-out plug 22 is electrically connected to the second upper electrode layer 152, and the other end is electrically connected to the upper electrode bridge line 20. The upper electrode bridge line 20 is electrically connected to the upper electrode lead line 23.

[0080] In some embodiments, the concentration of oxygen vacancies in the lower electrode layer 29 is greater than the concentration of oxygen vacancies in the active layer 19. In an example, the metal-oxygen bond in the oxide semiconductor material in the oxide semiconductor layer 80 (i.e., the lower electrode layer 29) in the capacitor region can be broken by plasma treatment or the like, thereby increasing the oxygen vacancies in the lower electrode layer 29, and further reducing the resistance of the lower electrode layer 29 and increasing the conductivity of the lower electrode layer 29. In other embodiments, the conductivity of the lower electrode layer 29 can also be increased by ion doping. The present specific embodiment increases the conductivity of the lower electrode layer 29 by increasing the concentration of oxygen vacancies or ion doping, so that the resistance of the lower electrode layer can be flexibly adjusted while ensuring good conductivity of the lower electrode layer, thereby helping to further improve the performance of the semiconductor structure and improve the manufacturing yield of the semiconductor structure.

[0081] The present specific embodiment also provides a method for forming a semiconductor structure, and the method includes the steps of: Figure 3 is a flowchart of a method for forming a semiconductor structure in the present specific embodiment, and the method includes the steps of: Figure 4 -attached Figure 18is a schematic diagram of a main process structure in a process of forming a semiconductor structure according to an embodiment of the present disclosure. The schematic diagram of the semiconductor structure formed according to the embodiment of the present disclosure can be seen from Figure 1 and Figure 2 . As shown in Figures 1-18 , the method for forming the semiconductor structure includes the following steps:

[0082] Step S31, providing a substrate 71;

[0083] Step S32, forming a memory cell on the substrate 71, the memory cell including a transistor region PT and a capacitor region PC, the memory cell further including an oxide semiconductor layer 80 continuously distributed in the transistor region PT and the capacitor region PC, the oxide semiconductor layer 80 of the transistor region PT serving as an active layer 19 of a transistor 17, and the oxide semiconductor layer 80 of the capacitor region PC serving as a lower electrode layer 29 of a capacitor 18, the lower electrode layer 29 having a resistance lower than that of the active layer 19.

[0084] In some embodiments, the specific step of forming the memory cell on the substrate 71 includes:

[0085] forming a stack layer on the substrate 71, the stack layer including interlayer isolation layers 40 and sacrificial layers 41 alternately stacked along a third direction D3, and the stack layer including the transistor region PT and the capacitor region PC arranged along a first direction D1, the first direction D1 being parallel to a top surface of the substrate 71, as shown in Figure 4 ;

[0086] forming a first trench 70 penetrating the transistor region PT and the capacitor region PC of the stack layer along the third direction D3, as shown in Figure 7 , wherein, Figure 7 (a) in FIG. 4 is a schematic top view after the first trench 70 is formed, Figure 7 (b) in FIG. 4 is a schematic cross-sectional view of (a) in FIG. 4 at a position of A-A; Figure 7

[0087] forming an oxide semiconductor layer 80 covering inner walls of the first trench 70, as shown in Figure 8 , wherein, Figure 8 (a) in FIG. 5 is a schematic top view after the oxide semiconductor layer 80 is formed, Figure 8 (b) in FIG. 5 is a schematic cross-sectional view of (a) in FIG. 5 at a position of A-A; Figure 8

[0088] ​​reducing the resistance of the oxide semiconductor layer 80 of the capacitor region PC, forming the active layer 19 of the transistor region PT and the lower electrode layer 29 of the capacitor region PC.

[0089] In some embodiments, the specific step of forming the first trench 70 through the transistor region PT and the capacitor region PC of the stack layer along the third direction D3 comprises:

[0090] removing the sacrificial layer 41 of the capacitor region PC, forming the second trench 50 between the adjacent ILDs 40 in the capacitor region PC, as shown in Figure 5 ;

[0091] forming the first isolation layer 60 filling the second trench 50, as shown in Figure 6 ;

[0092] etching the stack layer and the first isolation layer 60, forming the first trench 70 through the transistor region PT and the capacitor region PC of the stack layer along the third direction D3 and through the first isolation layer 60 along the third direction D3, as shown in Figure 7 .

[0093] For example, the ILDs 40 and the sacrificial layers 41 can be alternately deposited on the top surface of the substrate 71 by a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process, forming the stack layer, as shown in Figure 4 . In an example, the material of the ILDs 40 can be an oxide material, such as silicon dioxide. The material of the sacrificial layers 41 can be a polysilicon material including doped ions (e.g. P-type ions), such as a polysilicon material with an ion doping concentration of 1 x 1010 21 / cm 3 ~ 1 x 1010 23 / cm 3 , to enhance the conductivity of the sacrificial layers 41. In an example, after forming the stack layer, a protection layer 42 is formed above the stack layer to protect the topmost polysilicon in the stack layer. In an example, the material of the protection layer 42 is a nitride material, such as silicon nitride. In an example, the stack layer further includes a bit line region PB, which is distributed along the first direction D1 on opposite sides of the transistor region PT with the capacitor region PC. Then, a lateral etching process can be used to selectively remove the sacrificial layers 41 of the capacitor region PC in the stack layer, forming the second trench 50 between the adjacent ILDs 40 in the capacitor region PC, as shown in Figure 5The second dielectric material is filled in the second trench 50 to form the first isolation layer 60 between the adjacent ILDs 40 in the capacitor region PC, as shown in FIG. 1G. Figure 6 Then, a dry etching process can be used to etch the stack and the first isolation layer 60 to form a first trench 70 through the stack in the transistor region PT and the capacitor region PC along the third direction D3 and through the first isolation layer 60 along the third direction D3, as shown in FIG. 1H. Figure 7

[0094] In an example, after the first trench 70 is formed, the exposed portion of the sacrificial layer 41 on the sidewall of the first trench 70 is exposed, and thus a second dielectric layer 72 covering the sidewall of the first trench 70 can be formed by an in-situ steam generation (ISSG) or deposition process to avoid the impact of subsequent processes on the sacrificial layer 41. In an example, the material of the second dielectric layer 72 is an oxide material, such as silicon dioxide.

[0095] In some embodiments, the specific step of reducing the resistance of the oxide semiconductor layer 80 in the capacitor region PC includes:

[0096] treating the oxide semiconductor layer 80 in the capacitor region PC by a plasma process to increase the oxygen vacancies in the oxide semiconductor layer 80 in the capacitor region PC; or

[0097] implanting dopant ions into the oxide semiconductor layer 80 in the capacitor region PC to enhance the conductivity of the oxide semiconductor layer 80 in the capacitor region PC.

[0098] In an example, after the first trench 70 and the second dielectric layer 72 in the first trench 70 are formed, an oxide semiconductor material can be deposited on the inner wall of the first trench 70 by a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, or an atomic layer deposition (ALD) process to form the oxide semiconductor layer 80, as shown in FIG. 1I. Figure 8 Then, a first fill layer 90 filling the first trench 70 and covering the oxide semiconductor layer 80 is formed, as shown in FIG. 1J. Figure 9 wherein, Figure 9 (a) in FIG. 1J is a top view schematic diagram after the first fill layer 90 is formed, Figure 9 (b) in FIG. 1J is a cross-sectional view along the line A-A’ in FIG. 1J. Figure 9 ​Fig. 2 shows a cross-sectional view of the capacitor region PC at position A-A in Fig. 1. In one example, the first fill layer 90 can be a low-K dielectric material. Thereafter, the first fill layer 90 of the capacitor region PC is removed to expose the oxide semiconductor layer 80 of the capacitor region PC. Next, the exposed oxide semiconductor layer 80 of the capacitor region PC is subjected to a resistance reduction treatment. In one example, the resistance reduction treatment is to treat the oxide semiconductor layer 80 of the capacitor region PC with plasma so that at least part of the metal-oxygen bonds in the oxide semiconductor layer 80 of the capacitor region PC are broken, thereby reducing the oxygen content in the oxide semiconductor layer 80 of the capacitor region PC, increasing the oxygen vacancies in the oxide semiconductor layer 80 of the capacitor region PC, thereby enhancing the conductivity of the oxide semiconductor layer 80 of the capacitor region PC, forming a first oxide semiconductor layer 100 in the capacitor region PC. In another example, the resistance reduction treatment is to implant dopant ions into the oxide semiconductor layer 80 of the capacitor region PC, thereby enhancing the conductivity of the oxide semiconductor layer 80 of the capacitor region PC, forming a first oxide semiconductor layer 100 in the capacitor region PC. The oxide semiconductor layer 80 of the transistor region PT that remains unsubjected to the resistance reduction treatment serves as a second oxide semiconductor layer 103, as shown in Fig. 3. Figure 10

[0099] In one example, when the first fill layer 90 of the capacitor region PC is removed, the ILD layer 40 and the first isolation layer 60 between the first trenches 70 in the capacitor region PC are also removed, thereby exposing two opposite sidewalls of the oxide semiconductor layer 80 in the capacitor region PC along the second direction D2, which helps to increase the storage capacity of the capacitor 18 formed in the capacitor region PC while enhancing the resistance reduction effect of the oxide semiconductor layer 80 of the capacitor region PC.

[0100] After the resistance reduction treatment of the oxide semiconductor layer 80 in the capacitor region PC, the first trenches 70 in the capacitor region PC and the gaps between the first trenches 70 are filled with a low-K material to form a second fill layer 110. Next, the first fill layer 90 and the second fill layer 110 in the first trenches 70 are removed, leaving only the second fill layer 110 between the first trenches 70 in the capacitor region PC, as shown in Fig. 4. Figure 11 Figure 11 Fig. 4(a) is a top view of the structure after the second fill layer 110 between the first trenches 70 in the capacitor region PC is left by etching, Figure 11 Fig. 4(b) is a cross-sectional view of the structure at position A-A in Fig. 4(a). Figure 11 Fig. 4(a) is a top view of the structure after the second fill layer 110 between the first trenches 70 in the capacitor region PC is left by etching,​​

[0101] Next, a lateral etching process can be employed to remove the first oxide semiconductor layer 100 between adjacent sacrificial layers 41, the remaining first oxide semiconductor layer 100 in the capacitor region PC forms a plurality of initial lower electrode layers 201 spaced apart along the third direction D3, and the remaining second oxide semiconductor layer 103 in the transistor region PT forms a plurality of initial active layers 202 spaced apart along the third direction D3, see Figure 12 .

[0102] In some embodiments, the specific step of forming the active layers 19 in the transistor region PT and the lower electrode layers 29 in the capacitor region PC comprises:

[0103] removing the oxide semiconductor layer 80 between adjacent sacrificial layers 41, the remaining oxide semiconductor layer 80 in the capacitor region PC forms a plurality of initial lower electrode layers 201 spaced apart along the third direction D3, and the remaining oxide semiconductor layer 80 in the transistor region PT forms a plurality of initial active layers 202 spaced apart along the third direction D3, as shown in Figure 12 .

[0104] splitting the initial lower electrode layers 201 and the initial active layers 202 to form lower electrode layers 29 comprising first lower electrode layers 111 and second lower electrode layers 112 spaced apart along a second direction D2, and to form active layers 19 comprising first active layers 101 and second active layers 102 spaced apart along the second direction D2, the second direction D2 being parallel to the top surface of the substrate 71, and the second direction D2 intersecting the first direction D1.

[0105] In some embodiments, the specific step of splitting the initial lower electrode layers 201 and the initial active layers 202 comprises:

[0106] forming a first dielectric layer 120 covering the initial lower electrode layers 201 and the initial active layers 202 in the first trench 70, as shown in Figure 12 .

[0107] forming a first conductive material layer 130 filling the first trench 70 and covering the first dielectric layer 120, as shown in Figure 13 .

[0108] forming a second isolation layer 142 through the first dielectric layer 120 and the first conductive material layer 130 along the first direction D1, and forming a third isolation layer 141 through the first dielectric layer 120 and the first conductive material layer 130 along the second direction D2, the second isolation layer 142 separating the initial active layer 202 into a first active layer 101 and a second active layer 102, the second isolation layer 142 also separating the initial lower electrode layer 201 into a first lower electrode layer 111 and a second lower electrode layer 112, the third isolation layer 141 separating the first dielectric layer 120 into a second gate dielectric layer 122 covering the first active layer and a dielectric layer 16 covering the first lower electrode layer 111, the third isolation layer 141 also separating the first conductive material layer 130 into a second gate layer 133 on the second gate dielectric layer 122 and a second upper electrode layer 152 on the dielectric layer 16, as shown in Figure 14

[0109] In some embodiments, after forming the lower electrode layer 29 including the first lower electrode layer 111 and the second lower electrode layer 112 spaced apart along the second direction D2, and forming the active layer 19 including the first active layer 101 and the second active layer 102 spaced apart along the second direction D2, the method further comprises the following steps:

[0110] forming a dielectric layer covering the first lower electrode layer 111 and the second lower electrode layer 112, and forming a gate dielectric layer covering the first active layer 101 and the second active layer 102;

[0111] forming an upper electrode layer covering the dielectric layer, and forming a gate structure covering the gate dielectric layer, to form the capacitor 28 including the lower electrode layer 29, the dielectric layer and the upper electrode layer, and to form the transistor 17 including the first active layer 101, the second active layer 102, the gate dielectric layer and the gate structure.

[0112] ​Specifically, the initial active layer 202 in each of the first trenches 70 is divided into the first active layer 101 and the second active layer 102 arranged along the second direction D2, and the initial lower electrode layer 201 in each of the first trenches 70 is divided into the first lower electrode layer 111 and the second lower electrode layer 112 arranged along the second direction D2, and the first conductive material layer 130 in each of the first trenches 70 is divided into the first upper electrode layer and the second gate layer 133 arranged along the second direction D2. In two of the first trenches 70 adjacent along the second direction D2, the first active layer 101 in one of the first trenches 70 and the second active layer 102 in the other of the first trenches 70 together form the active layer 19 of the transistor 17 in one of the memory cells, and the first lower electrode layer 111 in one of the first trenches 70 and the second lower electrode layer 112 in the other of the first trenches 70 together form the lower electrode layer 29 of the capacitor 18 in one of the memory cells, see Figure 18 .

[0113] In some embodiments, after forming the second isolation layer 142 penetrating the first dielectric layer 120 and the first conductive material layer 130 along the first direction D1, and forming the third isolation layer 141 penetrating the first dielectric layer 120 and the first conductive material layer 130 along the second direction D2, the method further comprises the following steps:

[0114] A first gate layer 131 is formed in the gap between two of the first trenches 70 adjacent in the transistor region PT, and the first gate layer 131 and the second gate layer 133 distributed on opposite sides of the first gate layer 131 along the second direction D2 and adjacent to the first gate layer 131 together form a gate structure of one of the transistors 17, as shown in Figure 16 .

[0115] A first upper electrode layer 151 is formed in the gap between two of the first trenches 70 adjacent in the capacitor region PC, and the first upper electrode layer 151 and the second upper electrode layer 152 distributed on opposite sides of the first upper electrode layer 151 along the second direction D2 and adjacent to the first upper electrode layer 151 together form an upper electrode layer of one of the capacitors 18, as shown in Figure 18 .

[0116] For example, a dry etching process can be used to etch the gap between two of the first trenches 70 adjacent in the transistor region PT to form a third trench 150 penetrating the stack, as shown in Figure 15As shown. A conductive material such as tungsten is filled into the third trench 150 to form the first gate layer 131, as shown. Figure 16 As shown. The remaining sacrificial layer 41 on the surface of the first gate layer 131 serves as the gate contact layer 132, and the remaining second dielectric layer 72 on the surface of the gate contact layer 132 serves as the first gate dielectric layer 121 of the transistor 17. Then, the second fill layer 110 between adjacent first trenches 70 in the capacitor region PC is removed to form a fourth trench 170 exposing the first lower electrode layer 111 and the second lower electrode layer 112, as shown. Figure 17 As shown. Next, a dielectric layer covering the inner wall of the fourth trench 170 and a first upper electrode layer 151 covering the dielectric layer are formed again, as shown. Figure 18 As shown.

[0117] In the formation of such Figure 18 Following the structure shown, the sacrificial layer 41 of the bit line region PB in the stacked layers can be removed, forming a bit line trench in the bit line region PB located between adjacent interlayer isolation layers 40. A conductive material such as metal is filled into the bit line trench to form a bit line 14, as shown. Figure 1 and Figure 2 As shown.

[0118] The semiconductor structure and its formation method provided in some embodiments of this specific implementation provide a method for forming a semiconductor structure by setting oxide semiconductor layers continuously distributed in transistor regions and capacitor regions in a memory cell, using the oxide semiconductor layer in the transistor region as the active layer of the transistor, and using the oxide semiconductor layer in the capacitor region as the lower electrode layer of the capacitor, and making the resistance of the lower electrode layer lower than the resistance of the active layer. This allows for the simultaneous execution of the manufacturing processes of part of the transistor and part of the capacitor, simplifying the semiconductor structure manufacturing process and improving the manufacturing efficiency. Other embodiments of this specific implementation improve the conductivity of the oxide semiconductor layer used to form the lower electrode layer by employing a resistance reduction process. This allows for flexible adjustment of the resistance value of the lower electrode layer while ensuring good conductivity, thereby further improving the performance of the semiconductor structure and increasing its manufacturing yield.

[0119] The above description is only a preferred embodiment of this disclosure. It should be noted that those skilled in the art can make several improvements and modifications without departing from the principles of this disclosure, and these improvements and modifications should also be considered within the scope of protection of this disclosure.

Claims

1. A semiconductor structure, characterized in that, include: Substrate; A memory cell, located on the substrate, includes a transistor region and a capacitor region. The memory cell also includes an oxide semiconductor layer continuously distributed in the transistor region and the capacitor region. The oxide semiconductor layer in the transistor region serves as the active layer of the transistor, and the oxide semiconductor layer in the capacitor region serves as the lower electrode layer of the capacitor. The resistance of the lower electrode layer is lower than the resistance of the active layer.

2. The semiconductor structure according to claim 1, characterized in that, The oxide semiconductor layer includes a first oxide semiconductor layer and a second oxide semiconductor layer that both extend along a first direction and are spaced apart along a second direction. The first direction and the second direction are both parallel to the top surface of the substrate, and the first direction intersects the second direction. The first oxide semiconductor layer in the transistor region serves as the first active layer, and the second oxide semiconductor layer in the transistor region serves as the second active layer. The first active layer and the second active layer together constitute the active layer. The first oxide semiconductor layer in the capacitor region serves as the first lower electrode layer, and the second oxide semiconductor layer in the capacitor region serves as the second lower electrode layer. The first lower electrode layer and the second lower electrode layer together constitute the lower electrode layer.

3. The semiconductor structure according to claim 2, characterized in that, The projections of the first active layer, the second active layer, the first lower electrode layer, and the second lower electrode layer on the top surface of the substrate are all L-shaped.

4. The semiconductor structure according to claim 2, characterized in that, The transistor further includes a gate structure, which includes a first gate layer and a second gate layer. The first gate layer is located between the first active layer and the second active layer, and the second gate layer is located on the side of the first active layer away from the first gate layer and on the side of the second active layer away from the first gate layer. The capacitor further includes a dielectric layer covering the surface of the lower electrode layer and an upper electrode layer covering the surface of the dielectric layer. The upper electrode layer includes a first upper electrode layer and a second upper electrode layer that are electrically connected to each other. The first upper electrode layer is located between the first lower electrode layer and the second lower electrode layer. The second upper electrode layer is located on the side of the first lower electrode layer away from the first upper electrode layer and on the side of the second lower electrode layer away from the first upper electrode layer.

5. The semiconductor structure according to claim 4, characterized in that, The material of the second upper electrode layer is the same as that of the second gate layer, and the second upper electrode layer and the second gate layer are disposed in the same layer.

6. The semiconductor structure according to claim 4, characterized in that, Also includes: A word line lead structure is located above the transistor. The word line lead structure includes a first lead plug, a second lead plug, and a word line lead. One end of the first lead plug is electrically connected to the first gate layer and the other end is electrically connected to the word line lead. One end of the second lead plug is electrically connected to the second gate layer and the other end is electrically connected to the word line lead.

7. The semiconductor structure according to claim 4, characterized in that, The first active layer includes a first channel region, and a first source region and a first drain region distributed on opposite sides of the first channel region along the first direction. The first lower electrode layer is electrically connected to the first drain region. The second active layer includes a second channel region, and a second source region and a second drain region distributed on opposite sides of the second channel region along the first direction. The second lower electrode layer is in contact with and electrically connected to the second drain region. The semiconductor structure further includes a bit line extending along the second direction and electrically connected to the first source region and the second source region.

8. The semiconductor structure according to claim 7, characterized in that, The number of the storage cells is multiple, and the multiple storage cells are arranged in an array along the second direction and the third direction, wherein the third direction is perpendicular to the top surface of the substrate; The multiple bit lines are spaced apart along the third direction, and each bit line is electrically connected to the active layer in the multiple memory cells spaced apart along the second direction. The gate structures in the plurality of memory cells arranged at intervals along the third direction are electrically connected.

9. The semiconductor structure according to claim 1, characterized in that, The concentration of oxygen vacancies in the lower electrode layer is greater than the concentration of oxygen vacancies in the active layer.

10. A method for forming a semiconductor structure, characterized in that, Includes the following steps: Provide substrate; A memory cell is formed on the substrate. The memory cell includes a transistor region and a capacitor region. The memory cell also includes an oxide semiconductor layer continuously distributed in the transistor region and the capacitor region. The oxide semiconductor layer in the transistor region serves as the active layer of the transistor, and the oxide semiconductor layer in the capacitor region serves as the lower electrode layer of the capacitor. The resistance of the lower electrode layer is lower than the resistance of the active layer.

11. The method for forming a semiconductor structure according to claim 10, characterized in that, The specific steps for forming memory cells on the substrate include: A stacked layer is formed on the substrate, the stacked layer including an interlayer isolation layer and a sacrificial layer alternately stacked along a third direction, and the stacked layer including a transistor region and a capacitor region arranged along a first direction, the first direction being parallel to the top surface of the substrate; A first trench is formed along the third direction, penetrating the transistor region and the capacitor region of the stacked layer; An oxide semiconductor layer is formed covering the inner wall of the first trench; The resistance of the oxide semiconductor layer in the capacitor region is reduced to form the active layer in the transistor region and the lower electrode layer in the capacitor region.

12. The method for forming a semiconductor structure according to claim 11, characterized in that, The specific steps for forming a first trench extending along the third direction through the transistor region and the capacitor region of the stacked layer include: Remove the sacrificial layer in the capacitor region and form a second trench in the capacitor region between adjacent interlayer isolation layers; A first isolation layer is formed, filling the second trench; The stacked layer and the first isolation layer are etched to form the transistor region and the capacitor region that penetrate the stacked layer in a third direction, and a first trench that penetrates the first isolation layer in a third direction.

13. The method for forming a semiconductor structure according to claim 11, characterized in that, The specific steps for reducing the resistance of the oxide semiconductor layer in the capacitor region include: The oxide semiconductor layer in the capacitor region is treated with plasma to increase the number of oxygen vacancies in the oxide semiconductor layer in the capacitor region; or... Doping ions are implanted into the oxide semiconductor layer of the capacitor region to enhance the conductivity of the oxide semiconductor layer in the capacitor region.

14. The method for forming a semiconductor structure according to claim 11, characterized in that, The specific steps for forming the active layer located in the transistor region and the lower electrode layer located in the capacitor region include: Remove the oxide semiconductor layer between adjacent sacrificial layers, and the remaining oxide semiconductor layer in the capacitor region forms a plurality of initial lower electrode layers spaced apart along the third direction, and the remaining oxide semiconductor layer in the transistor region forms a plurality of initial active layers spaced apart along the third direction. The initial lower electrode layer and the initial active layer are separated to form a lower electrode layer including a first lower electrode layer and a second lower electrode layer spaced apart along a second direction, and an active layer including a first active layer and a second active layer spaced apart along a second direction, wherein the second direction is parallel to the top surface of the substrate and intersects with the first direction.

15. The method for forming a semiconductor structure according to claim 14, characterized in that, After forming a lower electrode layer comprising a first lower electrode layer and a second lower electrode layer spaced apart along a second direction, and forming an active layer comprising a first active layer and a second active layer spaced apart along a second direction, the process further includes the following steps: A dielectric layer is formed covering the first lower electrode layer and the second lower electrode layer, and a gate dielectric layer is formed covering the first active layer and the second active layer; An upper electrode layer covering the dielectric layer is formed, and a gate structure covering the gate dielectric layer is formed to form the capacitor including the lower electrode layer, the dielectric layer and the upper electrode layer, and the transistor including the first active layer, the second active layer, the gate dielectric layer and the gate structure is formed.

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