Semiconductor memory device and manufacturing method thereof

Abstract

Provided herein are a semiconductor memory device and a method of manufacturing the same. The semiconductor memory device includes: a plurality of interlayer insulating structures; a plurality of conductive layers alternately laminated with the plurality of interlayer insulating structures; a plurality of data storage patterns spaced apart from each other in a direction in which the plurality of interlayer insulating structures and the plurality of conductive layers are alternately stacked; and a barrier insulating layer or a barrier insulating pattern interposed between each data storage pattern and the corresponding conductive layer.

Description

Technical Field

[0001] Various embodiments of the present disclosure generally relate to semiconductor memory devices and methods of manufacturing the semiconductor memory devices. More particularly, the present disclosure relates to a three-dimensional (3D) semiconductor memory device and a method of manufacturing the 3D semiconductor memory device. Background Art

[0002] Semiconductor memory devices can be applied to small electronic devices and electronic systems in various fields, such as the automotive, medical fields, or data centers. Therefore, the demand for semiconductor memory devices is increasing.

[0003] Semiconductor memory devices may include memory cells for storing data. 3D semiconductor memory devices include memory cells arranged three-dimensionally. Compared with 2D semiconductor memory devices, 3D semiconductor memory devices have an advantage in achieving a large capacity.

[0004] As the integration degree of the memory cells in the 3D semiconductor memory device increases, the distance between the memory cells decreases in the stacking direction of the memory cells. Therefore, the operation reliability of the semiconductor memory device may deteriorate. Summary of the Invention

[0005] Embodiments of the present disclosure may provide a semiconductor memory device. The semiconductor memory device may include: a channel layer extending in a first direction; a tunnel insulating layer extending along an outer wall of the channel layer in the first direction; a plurality of interlayer insulating structures arranged along the outer wall of the tunnel insulating layer, the plurality of interlayer insulating structures being spaced apart from each other in the first direction; a plurality of conductive layers arranged alternately with the plurality of interlayer insulating structures in the first direction; a plurality of data storage patterns interposed between the plurality of conductive layers and the tunnel insulating layer in a second direction, the plurality of data storage patterns being spaced apart from each other in the first direction, wherein the plurality of data storage patterns respectively correspond to the plurality of conductive layers, and wherein the second direction is perpendicular to the first direction; a pad insulating pattern extending to cover a first surface of each of the plurality of data storage patterns facing the first direction, a second surface of each of the plurality of data storage patterns facing a direction opposite to the first surface, and a third surface of each of the plurality of data storage patterns facing the second direction; and a barrier insulating layer interposed between each of the plurality of conductive layers and the pad insulating pattern, wherein the pad insulating pattern includes a crystalline insulating layer.

[0006] Embodiments of the present disclosure may provide a semiconductor memory device. The semiconductor memory device may include: a channel layer extending in a first direction; a tunnel insulating layer extending along an outer wall of the channel layer in the first direction; a plurality of interlayer insulating structures arranged along the outer wall of the tunnel insulating layer, the plurality of interlayer insulating structures being spaced apart from each other in the first direction; a plurality of conductive layers arranged alternately with the plurality of interlayer insulating structures in the first direction; a plurality of data storage patterns interposed between the plurality of conductive layers and the tunnel insulating layer in a second direction, the plurality of data storage patterns being spaced apart from each other in the first direction, wherein the plurality of data storage patterns respectively correspond to the plurality of conductive layers, and wherein the second direction is perpendicular to the first direction; a sacrificial insulating pattern covering a first surface of each of the plurality of data storage patterns facing the first direction and a second surface of each of the plurality of data storage patterns facing a direction opposite to the first surface; and a blocking insulating pattern interposed between each of the plurality of data storage patterns and a corresponding conductive layer among the plurality of conductive layers. The blocking insulating pattern may be thicker than the sacrificial insulating pattern.

[0007] Embodiments of the present disclosure may provide a method of manufacturing a semiconductor memory device. The method may include the steps of: alternately stacking a plurality of first interlayer insulating layers and a plurality of sacrificial layers in a first direction; forming a hole through the plurality of first interlayer insulating layers and the plurality of sacrificial layers; forming a plurality of second interlayer insulating layers on sidewalls of the plurality of first interlayer insulating layers facing the hole to define uneven portions on the sidewalls of the hole; forming a blocking insulating layer along the uneven portions to cover the sidewalls of the plurality of second interlayer insulating layers and the sidewalls of the plurality of sacrificial layers; forming a crystalline insulating layer on an inner wall of the blocking insulating layer to have a plurality of grooves corresponding to the plurality of sacrificial layers; forming a plurality of data storage patterns on the inner wall of the crystalline insulating layer to respectively fill the plurality of grooves of the crystalline insulating layer; etching a portion of the crystalline insulating layer exposed between the plurality of data storage patterns to separate the crystalline insulating layer into a plurality of pad insulating patterns; forming a tunnel insulating layer inside the hole to cover the etched area of the crystalline insulating layer and the plurality of data storage patterns; forming a channel layer along an inner wall of the tunnel insulating layer; and replacing the plurality of sacrificial layers with a plurality of conductive layers.

[0008] Embodiments of the present disclosure may provide a method of manufacturing a semiconductor memory device. The method may include the steps of: alternately stacking a plurality of first interlayer insulating layers and a plurality of sacrificial layers in a first direction; forming holes through the plurality of first interlayer insulating layers and the plurality of sacrificial layers; forming a plurality of second interlayer insulating layers on sidewalls of the plurality of first interlayer insulating layers facing the holes to define uneven portions on sidewalls of the holes; forming a sacrificial insulating layer along the uneven portions to cover sidewalls of the plurality of second interlayer insulating layers and sidewalls of the plurality of sacrificial layers and having a plurality of grooves corresponding to the plurality of sacrificial layers; forming a plurality of data storage patterns on inner walls of the sacrificial insulating layer to respectively fill the plurality of grooves of the sacrificial insulating layer; forming a tunnel insulating layer inside the holes to cover the plurality of data storage patterns and the sacrificial insulating layer; forming a channel layer along an inner wall of the tunnel insulating layer; removing the plurality of sacrificial layers to define a plurality of openings exposing the sacrificial insulating layer; removing exposed portions of the sacrificial insulating layer such that the plurality of data storage patterns are exposed through the plurality of openings; selectively depositing a preliminary layer on an exposed surface of each of the plurality of data storage patterns; forming a blocking insulating pattern by modifying the preliminary layer; and forming a plurality of conductive layers inside the plurality of openings opened by the blocking insulating pattern. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a circuit diagram showing a memory cell array of a semiconductor memory device according to an embodiment of the present disclosure.

[0010] Figure 2A and Figure 2B is a diagram showing a semiconductor memory device according to an embodiment of the present disclosure.

[0011] Figures 3A to 3D is a cross-sectional view showing a stacked structure of a plurality of memory cells according to an embodiment of the present disclosure.

[0012] Figures 4A to 4H is a cross-sectional view showing a method of manufacturing a semiconductor memory device according to an embodiment of the present disclosure.

[0013] Figure 5A and Figure 5B is a cross-sectional view showing a method of manufacturing a semiconductor memory device according to an embodiment of the present disclosure.

[0014] Figures 6A to 6I is a cross-sectional view showing a method of manufacturing a semiconductor memory device according to an embodiment of the present disclosure.

[0015] Figure 7 is a cross-sectional view showing a process of forming a preliminary layer according to an embodiment of the present disclosure.

[0016] Figures 8A to 8CIt is a cross-sectional view showing a method of manufacturing a semiconductor memory device according to an embodiment of the present disclosure.

[0017] Figure 9 It is a block diagram showing an electronic system according to an embodiment of the present disclosure. Detailed Embodiments

[0018] The specific structures and function descriptions disclosed herein are merely illustrative and are for describing embodiments according to the concepts of the present disclosure. Embodiments according to the concepts of the present disclosure can be modified in various forms and replaced with other equivalent embodiments. Therefore, the present disclosure should not be construed as being limited to the embodiments set forth herein.

[0019] It will be understood that although terms such as "first" and "second" may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another, and the order or number of components is not limited by the terms.

[0020] Various embodiments of the present disclosure relate to a semiconductor memory device capable of improving operation reliability and a method of manufacturing a semiconductor memory device capable of improving operation reliability.

[0021] Figure 1 It is a circuit diagram showing a memory cell array of a semiconductor memory device according to an embodiment of the present disclosure.

[0022] Referring to Figure 1 , the memory cell array of the semiconductor memory device may include a plurality of memory cell strings CS. The plurality of memory cell strings CS may be connected to a gate array GE1 and GE2, a bit line array structure BAS, and a common source layer CSR.

[0023] Each memory cell string CS may include at least one source selection transistor SST, a plurality of memory cells MC, and at least one drain selection transistor DST. The plurality of memory cells MC may be connected in series between the source selection transistor SST and the drain selection transistor DST. The source selection transistor SST, the plurality of memory cells MC, and the drain selection transistor DST may be connected in series through a channel layer.

[0024] The gate array may include a plurality of gate groups. Figure 1 The first gate group GE1 and the second gate group GE2 of the gate array are shown. Each gate group GE1 or GE2 may include a source selection line SSL, a plurality of word lines WL, and a drain selection line DSL. The source selection line SSL may be used as a gate electrode of the source selection transistor SST, each word line WL may be used as a gate electrode of the corresponding memory cell MC, and the drain selection line DSL may be used as a gate electrode of the drain selection transistor DST.

[0025] The bit line array structure BAS may include a plurality of bit lines BL. A voltage for pre-charging the channel layer of the corresponding memory cell string CS may be applied to each bit line BL. A voltage may be applied to the common source layer CSR to discharge the channel layer potential of the memory cell string CS.

[0026] A plurality of memory cell strings CS may be connected in parallel to the common source layer CSR. The plurality of memory cell strings CS may be divided into a plurality of columns and a plurality of rows. The memory cell strings on the column corresponding to the bit line may be connected in parallel to each bit line BL. The memory cell strings on the row corresponding to the gate group may be connected in parallel to each gate group GE1 or GE2.

[0027] Figure 2A and Figure 2B is a diagram showing a semiconductor memory device according to an embodiment of the present disclosure.

[0028] Referring to Figure 2A and Figure 2B a semiconductor memory device may include the bit line array structure BAS and the doped semiconductor structure DPS described with reference to Figure 1 Each gate group GE1 or GE2 described with reference to Figure 1 may be composed of a plurality of conductive layers CL of the corresponding gate stack ST among the plurality of gate stacks ST. Each conductive layer CL may include various conductive materials such as a doped semiconductor layer and a metal layer. The doped semiconductor layer may include a doped silicon layer. The metal layer may include tungsten, copper, molybdenum, etc. The conductive layer CL may further include a conductive metal nitride layer. The conductive metal nitride layer may include titanium nitride, tantalum nitride, etc.

[0029] Each gate stack ST may further include a plurality of interlayer insulating structures IL alternately laminated with the plurality of conductive layers CL between the bit line array structure BAS and the doped semiconductor structure DPS. Each interlayer insulating structure IL may include an insulating material such as a silicon oxide layer or a silicon nitride layer. For example, the silicon nitride layer may include a silicon oxynitride layer.

[0030] The doped semiconductor structure DPS may include at least one doped semiconductor layer. The doped semiconductor structure DPS may include at least one of an n-type impurity and a p-type impurity. The doped semiconductor structure DPS may be used as at least one of a well region and the common source layer CSR, which is described with reference to Figure 1 The doped semiconductor structure DPS may include at least one of a first conductive type doped region containing an n-type impurity as a majority carrier and a second conductive type doped region containing a p-type impurity as a majority carrier. The first conductive type doped region may be provided as the common source layer, and the second conductive type doped region may be provided as the well region.

[0031] Multiple bit lines BL of the bit line array structure BAS may be disposed within the bit line insulating structure BIS. Figure 2A and Figure 2B FIG. is a perspective view showing the bit line insulating structure BIS for easy identification. Multiple bit lines BL may be spaced apart from the gate stack ST and the bit line insulating structure BIS may be interposed therebetween.

[0032] The bit line insulating structure BIS may include a plurality of insulating layers having two or more layers. A plurality of bit line connection structures BCC may be further disposed within the bit line insulating structure BIS. The plurality of bit line connection structures BCC may be disposed between the bit line array structure BAS and the gate stack ST. Each bit line connection structure BCC may be a conductive pattern connected to a corresponding bit line BL and may be formed in various structures.

[0033] Adjacent gate stacks ST may be spaced apart from each other by a slit SI. The filler disposed in the slit SI may be designed in various ways. According to an embodiment, the filler may include an insulating layer. According to another embodiment, in addition to the insulating layer, the filler may further include at least one of a conductive layer and a semiconductor layer.

[0034] The plurality of conductive layers CL of the gate stack ST may extend in a direction intersecting the multiple bit lines BL. At least one layer of the plurality of conductive layers CL adjacent to the doped semiconductor structure DPS may be used as a Figure 1 source selection line SSL as shown, at least one layer adjacent to the bit line array structure BAS may be used as a Figure 1 drain selection line DSL as shown, and the remaining layers may be used as a Figure 1 plurality of word lines WL as shown.

[0035] The plurality of conductive layers CL and the plurality of interlayer insulating structures IL of the gate stack ST may extend to surround the plurality of channel pillars CHP. Each channel pillar CHP may include a channel layer of the memory cell string CS described with reference to Figure 1 The channel layer of the channel pillar CHP may be electrically connected to the corresponding bit line BL through the bit line connection structure BCC. The channel layer of the channel pillar CHP may include a contact surface contacting the doped semiconductor structure DPS. The contact surface may be defined as a part of the sidewall of the channel pillar CHP, an end of the channel pillar CHP, etc. According to an embodiment, with reference to Figure 2B , the doped semiconductor structure DPS may include a groove into which an end of the channel pillar CHP is inserted, and the contact surface between the doped semiconductor structure DPS and the channel layer may be defined as the end of the channel pillar CHP.

[0036] With reference to Figure 2A and Figure 2B, a memory cell string of a semiconductor memory device may be defined along a channel pillar CHP. The semiconductor memory device may further include a peripheral circuit structure to control the operation of the memory cell string. The peripheral circuit structure may include an input / output circuit, a control circuit, a voltage generation circuit, a row decoder, a column decoder, a page buffer, etc. More specifically, the peripheral circuit structure may include a plurality of transistors PTR, capacitors, resistors, etc. Although Figure 2A and Figure 2B representatively show a plurality of transistors PTR constituting a page buffer connected to a bit line array structure BAS, the peripheral circuit structure is not limited to these drawings.

[0037] The peripheral circuit structure including a plurality of transistors PTR may be adjacent to a doped semiconductor structure DPS as Figure 2A shown, or may be adjacent to a bit line array structure BAS as Figure 2B shown.

[0038] The peripheral circuit structure may be connected to the memory cell string through a plurality of conductive layers CL, a bit line array structure BAS, and a doped semiconductor structure DPS. According to an embodiment, the transistors PTR of the page buffer may be connected to the channel layer of the channel pillar CHP through corresponding bit lines BL.

[0039] Each transistor PTR may be disposed on an active region of a semiconductor substrate SUB separated by an isolation layer ISO. A peripheral insulating structure PIS may cover the transistor PTR and the semiconductor substrate SUB on which the transistor PTR is disposed. The transistor PTR may be connected to the bit line BL through a corresponding interconnect IC. The interconnect IC may be formed in the peripheral insulating structure PIS. The interconnect IC may include at least one of a plurality of wires and a plurality of conductive contacts for providing an electrical connection.

[0040] Referring to Figure 2A , a doped semiconductor structure DPS may be disposed above the peripheral insulating structure PIS. Although not shown in the figure, the interconnect IC may be electrically connected to the bit line BL through a peripheral circuit contact between the bit line BL and the interconnect IC.

[0041] Referring to Figure 2B, a first conductive bonding structure BP1 and a second conductive bonding structure BP2 can be disposed between a bit line array structure BAS and an interconnect IC. The first conductive bonding structure BP1 can be disposed in a first intermediate insulating structure IS1 between a bit line insulating structure BIS and a peripheral insulating structure PIS. The first conductive bonding structure BP1 can be coupled to a corresponding bit line BL. The second conductive bonding structure BP2 can be disposed in a second intermediate insulating structure IS2 between the first intermediate insulating structure IS1 and the peripheral insulating structure PIS. The second conductive bonding structure BP2 can be coupled to a corresponding interconnect IC. The first conductive bonding structure BP1 and the second conductive bonding structure BP2 can be bonded to each other, which allows the interconnect IC and the bit line BL to be electrically connected through the first conductive bonding structure BP1 and the second conductive bonding structure BP2.

[0042] Referring to Figure 2A or Figure 2B , a data storage layer serving as a data storage region of a memory cell can be disposed between a conductive layer serving as a word line among a plurality of conductive layers CL and a channel pillar CHP. According to an embodiment of the present disclosure, by separating the data storage layer into a plurality of data storage patterns corresponding to a plurality of memory cells of a memory cell string, interference between adjacent memory cells in the stacking direction of the conductive layers CL can be reduced. Hereinafter, referring to Figures 3A to 3D a cross-section of a gate stack ST and a cross-section of a channel pillar CHP shown in

[0043] Figures 3A to 3D FIG. is a cross-sectional view showing a stacked structure of a plurality of memory cells according to an embodiment of the present disclosure.

[0044] Referring to Figures 3A to 3D , a channel layer 133 of the channel pillar CHP can extend in a first direction +DR1. The channel layer 133 can be formed of a semiconductor material such as silicon (Si), germanium (Ge), or a mixture thereof, which can be used for a channel region of a memory cell string.

[0045] The channel pillar CHP may further include a core insulating layer 135. The channel layer 133 can surround sidewalls of the core insulating layer 135.

[0046] Multiple memory cells MC may be stacked along the channel layer 133 in a first direction +DR1. Each conductive layer 151 of the gate stack ST may be used as a word line connected to a corresponding memory cell MC. Each memory cell MC may include a data storage pattern 125P between the corresponding conductive layer 151 and the channel layer 133. The data storage pattern 125P may be formed of a material layer capable of storing data that can be changed using Fowler-Nordheim tunneling. According to an embodiment, the data storage pattern 125P may be formed of a charge trapping insulating layer, a floating gate layer, or an insulating layer containing conductive nanodots. The charge trapping insulating layer may include a silicon nitride layer.

[0047] Multiple data storage patterns 125P corresponding to the multiple memory cells MC may be arranged to be spaced apart from each other in the first direction +DR1. Accordingly, since interference between adjacent memory cells MC in the first direction +DR1 may be reduced, the operational reliability of the semiconductor memory device may be improved.

[0048] A tunnel insulating layer 131 may be provided between each data storage pattern 125P and the channel layer 133. The tunnel insulating layer 131 may extend along the outer wall of the channel layer 133 in the first direction +DR1. The tunnel insulating layer 131 may include an insulating material such as a silicon oxide layer.

[0049] Multiple data storage patterns 125P may respectively correspond to multiple conductive layers 151. Each data storage pattern 125P may be interposed between the corresponding conductive layer 151 and the tunnel insulating layer 131. The inner wall of the data storage pattern 125P may contact the tunnel insulating layer 131. In addition to the above inner wall, the data storage pattern 125P may further include a first surface S1, a second surface S2, and a third surface S3. The first surface S1 may face the first direction +DR1, and the second surface S2 may face a direction -DR1 opposite to the first surface S1. The third surface S3 may face the corresponding conductive layer 151. In other words, the third surface S3 may face a second direction DR2 perpendicular to the first direction +DR1. A blocking insulating layer 121 or a blocking insulating pattern 141 may be provided between the data storage pattern 125P and the conductive layer 151.

[0050] A plurality of interlayer insulation structures 101 of the gate stack ST may be arranged along an outer wall of the tunnel insulation layer 131. The plurality of interlayer insulation structures 101 may be set to be spaced apart from each other in a first direction +DR1. The plurality of interlayer insulation structures 101 and the plurality of conductive layers 151 may be alternately arranged in the first direction +DR1. Each interlayer insulation structure 101 may include a first interlayer insulation layer 101A and a second interlayer insulation layer 101B or 101B'. The plurality of first interlayer insulation layers 101A of the plurality of interlayer insulation structures 101 and the plurality of conductive layers 151 may be alternately arranged in the first direction +DR1. In other words, each conductive layer 151 may be arranged between the first interlayer insulation layers 101A adjacent in the first direction +DR1. The plurality of second interlayer insulation layers 101B or 101B' of the plurality of interlayer insulation structures 101 may be arranged on sidewalls of the plurality of first interlayer insulation layers 101A. Each second interlayer insulation layer 101B or 101B' may be arranged between a corresponding first interlayer insulation layer 101A and the tunnel insulation layer 131. Each of the first interlayer insulation layer 101A and the second interlayer insulation layer 101B or 101B' may have a thickness extending in the first direction +DR1. The thickness of the second interlayer insulation layer 101B or 101B' may have a maximum value at a point where the first interlayer insulation layer 101A contacts the second interlayer insulation layer 101B or 101B’.

[0051] Referring to Figure 3A and Figure 3B , the barrier insulation layer 121 may extend in the first direction +DR1 and may be shaped by the profiles of the data storage pattern 125P, the conductive layer 151, the second interlayer insulation layer 101B or 101B’, and the first interlayer insulation layer 101A. Specifically, the barrier insulation layer 121 may extend from a space between each of a first surface S1 and a second surface S2 of the data storage pattern 125P and the corresponding second interlayer insulation layer 101B. The second interlayer insulation layer 101B may include a convex sidewall facing the tunnel insulation layer 131. The barrier insulation layer 121 may extend into a space between the convex sidewall of the second interlayer insulation layer 101B and the tunnel insulation layer 131. A portion of the barrier insulation layer 121 between the convex sidewall of the second interlayer insulation layer 101B and the tunnel insulation layer 131 may include sidewalls 121FSW or 121RSW that contact the tunnel insulation layer 131 between the data storage patterns 125P adjacent in the first direction +DR1. According to an embodiment, as Figure 3A shown, the sidewall 121FSW of the barrier insulation layer 121 may be flat. According to an embodiment, as Figure 3B shown, the sidewall 121RSW of the barrier insulation layer 121 may be circular.

[0052] Referring to Figure 3A and Figure 3B, a plurality of data storage patterns 125P can be formed by etching a part of the data storage layer before forming the tunnel insulating layer 131. In order to protect the barrier insulating layer 121 during the process of etching a part of the data storage layer, a crystalline insulating layer with a higher etching selectivity to the data storage layer than the barrier insulating layer 121 can be deposited before forming the data storage layer. The crystalline insulating layer can be separated into a plurality of pad insulating patterns 123P. Therefore, leakage current due to the crystalline insulating layer can be reduced or prevented. Due to a plurality of contact areas between the barrier insulating layer 121 and the tunnel insulating layer 131, the plurality of pad insulating patterns 123P can be spaced apart from each other in the first direction +DR1. The plurality of pad insulating patterns 123P can correspond to the plurality of data storage patterns 125P. The plurality of pad insulating patterns 123P can face the plurality of conductive layers 151 and the plurality of interlayer insulating structures 101, and the barrier insulating layer 121 is interposed therebetween. In other words, the barrier insulating layer 121 can be interposed between each of the plurality of conductive layers 151 and the plurality of interlayer insulating structures 101 and the corresponding pad insulating pattern 123P.

[0053] The gate stack ST can include an inner wall facing the channel layer 133. The inner wall of the gate stack ST can have an uneven structure defined by the plurality of conductive layers 151 and the plurality of interlayer insulating structures 101. The barrier insulating layer 121 can be deposited to a first thickness 121TH on the uneven structure formed on the inner wall of the gate stack ST. The pad insulating pattern 123P can remain on the inner wall of the barrier insulating layer 121 with a second thickness 123TH. The second thickness 123TH can be less than the first thickness 121TH. The maximum thickness of the second interlayer insulating layer 101B in the first direction +DR1 can be formed to be less than the thickness of the first interlayer insulating layer 101A. Therefore, a space for disposing the barrier insulating layer 121, the pad insulating pattern 123P, and the data storage pattern 125P can be ensured between the second interlayer insulating layers 101B adjacent in the first direction +DR1.

[0054] The pad insulating pattern 123P can include a crystalline high-k layer having a higher dielectric constant than a silicon dioxide (SiO 2 ) layer. According to an embodiment, the pad insulating pattern 123P can include a crystalline aluminum oxide layer, a crystalline hafnium oxide layer, etc.

[0055] Referring to Figure 3C and Figure 3D , the plurality of conductive layers 151 can be alternately disposed with the plurality of first interlayer insulating layers 101A of the plurality of interlayer insulating structures 101 in the first direction +DR1. The plurality of data storage patterns 125P can be alternately disposed with the plurality of second interlayer insulating layers 101B' of the plurality of interlayer insulating structures 101 in the first direction +DR1.

[0056] After the plurality of data storage patterns 125P are separated from each other, a plurality of barrier insulating patterns 141 may be formed. Accordingly, damage to the plurality of barrier insulating patterns 141 due to an etching process for separating the plurality of data storage patterns 125P may be prevented.

[0057] Each of the barrier insulating patterns 141 may be formed before forming the conductive layer 151 and may be formed by modifying a preliminary layer selectively deposited on a third surface S3 of a corresponding data storage pattern 125P. The preliminary layer may include silicon oxycarbide (SiOC) or the same material as the data storage pattern 125P. The barrier insulating pattern 141 formed from the modified preliminary layer may include a low dielectric layer having a dielectric constant lower than that of a silicon dioxide layer. According to an embodiment, the barrier insulating pattern 141 may include silicon oxycarbide or an oxide of the same material as the data storage pattern 125P.

[0058] Before forming the plurality of data storage patterns 125P, a sacrificial insulating layer may be deposited on a surface of an uneven structure defined by a plurality of second interlayer insulating layers 101B' of the gate stack ST. The sacrificial insulating layer may be separated into a plurality of sacrificial insulating patterns 121P' or 121P". Each of the sacrificial insulating patterns 121P' or 121P" may be formed to expose a third surface S3 of the data storage pattern 125P. The sacrificial insulating pattern 121P' or 121P" may cover each of a first surface S1 and a second surface S2 of the data storage pattern 125P. The sacrificial insulating pattern 121P' or 121P" may be interposed between the data storage pattern 125P and the second interlayer insulating layer 101B' adjacent to each other in a first direction +DR1 and may extend along a surface of the second interlayer insulating layer 101B'.

[0059] The barrier insulating pattern 141 may be formed on the third surface S3 of the data storage pattern 125P with a first thickness 141TH. The sacrificial insulating pattern 121P' or 121P" may be formed on the surface of the second interlayer insulating layer 101B' with a second thickness 121TH'. The first thickness 141TH may be greater than the second thickness 121TH'.

[0060] Refer to Figure 3C and Figure 3D, a blocking insulating pattern 141 may be disposed between adjacent first interlayer insulating layers 101A along a first direction +DR1. The blocking insulating pattern 141 may not extend into the space between the second interlayer insulating layer 101B' and the data storage pattern 125P. Therefore, even if the maximum thickness of the second interlayer insulating layer 101B' in the first direction +DR1 is substantially the same as that of the first interlayer insulating layer 101A, a space for disposing the data storage pattern 125P can be ensured between adjacent second interlayer insulating layers 101B' along the first direction +DR1. According to an embodiment, the second interlayer insulating layer 101B' may contact the sacrificial insulating pattern 121P' or 121P", and the sacrificial insulating pattern 121P' may contact the data storage pattern 125P.

[0061] Referring to Figure 3C , the second interlayer insulating layer 101B' may include a convex circular sidewall facing the tunnel insulating layer 131. The sacrificial insulating pattern 121P' may extend into the space between the circular sidewall of the second interlayer insulating layer 101B' and the tunnel insulating layer 131. The sacrificial insulating pattern 121P' may have a circular sidewall 121RSW' facing the tunnel insulating layer 131. The circular sidewall 121RSW' may contact the tunnel insulating layer 131.

[0062] Referring to Figure 3D , at least one of the sidewalls of the sacrificial insulating pattern 121P" and the second interlayer insulating layer 101B' may be planarized. According to an embodiment, the second interlayer insulating layer 101B' may include a planar sidewall 101FSW facing the tunnel insulating layer 131. The planar sidewall 101FSW may contact the tunnel insulating layer 131.

[0063] Referring to Figures 3A to 3D , the conductive layer 151, the interlayer insulating structure 101, the channel layer 133, etc. are shown as being separated into adjacent first and second structures in a second direction DR2 with respect to the core insulating layer 135. Although not shown in the figure, the first and second structures may not be separated from each other, but may be coupled to each other through portions extending along the periphery of the channel pillar CHP as in the interlayer insulating structure IL shown Figure 2A .

[0064] Figures 4A to 4H is a cross-sectional view showing a method of manufacturing a semiconductor memory device according to an embodiment of the present disclosure.

[0065] Referring to Figure 4A , a plurality of first interlayer insulating layers 201A and a plurality of sacrificial layers 203 may be alternately stacked above a lower structure (not shown) in a first direction DR1. Each of the plurality of first interlayer insulating layers 201A and the plurality of sacrificial layers 203 may have a plate shape extending in a second direction DR2 intersecting the first direction DR1.

[0066] Although not shown in the figures, according to an embodiment, the following structure may include a semiconductor substrate SUB, which includes Figure 2A the plurality of transistors PTR shown and Figure 2A the doped semiconductor structure DSP shown. According to an embodiment, the following structure may be a sacrificial substrate formed of a silicon wafer or the like.

[0067] The plurality of sacrificial layers 203 may be formed of a material having an etching selectivity with respect to the plurality of first interlayer insulating layers 201A. According to an embodiment, each of the first interlayer insulating layers 201A may include an insulating material such as a silicon oxide layer or a silicon oxynitride layer, and each of the sacrificial layers 203 may include a sacrificial insulating material such as a silicon nitride (Si x N y , for example, Si 3 N 4 ) layer.

[0068] Subsequently, holes 211 extending in the first direction DR1 may be formed to pass through the plurality of first interlayer insulating layers 201A and the plurality of sacrificial layers 203. Accordingly, sidewalls of the plurality of first interlayer insulating layers 201A facing the holes 211 may be exposed.

[0069] Thereafter, a plurality of second interlayer insulating layers 201B may be formed on the exposed sidewalls of the plurality of first interlayer insulating layers 201A to define an uneven portion on the sidewalls of the holes 211. According to an embodiment, the plurality of second interlayer insulating layers 201B may be formed by selectively depositing an insulating material on the sidewalls of the plurality of first interlayer insulating layers 201A. At this time, each of the second interlayer insulating layers 201B may have a sidewall protruding with respect to the holes 211. Subsequently, by selectively etching each of the second interlayer insulating layers 201B, the maximum thickness of the second interlayer insulating layers 201B in the first direction DR1 may be controlled to be less than that of the first interlayer insulating layers 201A. The first interlayer insulating layers 201A and the second interlayer insulating layers 201B connected to each other may form an interlayer insulating structure 201.

[0070] A barrier insulating layer 221 may be formed along the uneven portion of the sidewalls of the holes 211 defined by the plurality of second interlayer insulating layers 201B. The barrier insulating layer 221 may extend to cover the sidewalls of the plurality of second interlayer insulating layers 201B and the sidewalls of the plurality of sacrificial layers 203. The barrier insulating layer 221 may be deposited on the uneven portion of the sidewalls of the holes 211 to have a first thickness TH1. The barrier insulating layer 221 may include an inner wall facing the holes 211. An uneven structure may be defined on the inner wall of the barrier insulating layer 221. The barrier insulating layer 221 may include an insulating material such as a silicon oxide layer, an aluminum oxide layer, or a hafnium oxide layer.

[0071] Refer to Figure 4B, a crystalline insulating layer 223 may be formed on the inner wall of the barrier insulating layer 221. The crystalline insulating layer 223 may be deposited on the inner wall of the barrier insulating layer 221 to have a second thickness TH2. The second thickness TH2 may be less than the first thickness TH1.

[0072] The crystalline insulating layer 223 may include a crystalline high-k layer having a dielectric constant higher than that of a silicon dioxide layer. According to an embodiment, the formation of the crystalline insulating layer 223 may include steps of forming a high-k layer (e.g., an aluminum oxide layer or a hafnium oxide layer) and performing heat treatment and crystallization on the high-k layer.

[0073] The crystalline insulating layer 223 may include an inner wall facing the hole 211. Uneven portions defined by the plurality of second interlayer insulating layers 201B may define a plurality of grooves 223GV in the inner wall of the crystalline insulating layer 223. The plurality of grooves 223GV may respectively correspond to the plurality of sacrificial layers 203.

[0074] Referring to Figure 4C , a data storage layer 225 may be formed on the inner wall of the crystalline insulating layer 223. The data storage layer 225 may fill the plurality of grooves 223GV. The data storage layer 225 may be formed on the convex inner wall of the crystalline insulating layer 223 to have a first thickness t1 in a second direction DR2, and may be formed to have a second thickness t2 inside each of the grooves 223GV, where the second thickness t2 is greater than the first thickness t1. The data storage layer 225 may be formed of a charge trapping insulating layer (e.g., a silicon nitride layer), a floating gate layer (e.g., polysilicon), or an insulating layer including conductive nanodots.

[0075] Subsequently, a portion of the data storage layer 225 may be etched using a first etchant 301. Accordingly, the thickness of the data storage layer 225 may be reduced. According to an embodiment, hydrofluoric acid (HF) may be used as the first etchant 301. The crystalline insulating layer 223 may reduce or prevent fluorine generated during the etching process using hydrofluoric acid (HF) from penetrating into the barrier insulating layer 221. Accordingly, damage to the barrier insulating layer 221 may be prevented or mitigated.

[0076] Referring to Figure 4D , by selectively etching the data storage layer using a second etchant 303, the data storage layer may be separated into a plurality of data storage patterns 225P. Each of the data storage patterns 225P may be retained in the corresponding groove 223GV.

[0077] Compared with the first etchant 301, the second etchant 303 may have a higher etching selectivity to avoid etching the barrier insulating layer 221 and the crystalline insulating layer 223 while etching the data storage layer 225. According to an embodiment, the second etchant 303 may be highly selective phosphoric acid (HSP). By using Figure 4CAfter the thickness of the data storage layer 225 is reduced by the first etchant 301 shown, the second etchant 303 is used to selectively etch the data storage layer 225, and the concentration of by-products generated during the etching process using the second etchant 303 can be controlled to be lower than the critical value. Therefore, when the concentration of by-products in the highly selective second etchant 303 (such as phosphoric acid (H 3 PO 4 )) exceeds the critical value, the phenomenon of oxide regrowth can be prevented or alleviated.

[0078] During the etching process of the data storage layer using the second etchant 303, a part of the crystalline insulating layer 223 may be exposed. This part of the crystalline insulating layer 223 may be exposed between the data storage patterns 225P adjacent in the first direction DR1.

[0079] Referring to Figure 4E , by etching the exposed part of the crystalline insulating layer, the crystalline insulating layer can be separated into a plurality of pad insulating patterns 223P. Therefore, a part of the barrier insulating layer 221 may be exposed between the pad insulating patterns 223P adjacent in the first direction DR1. The exposed part of the barrier insulating layer 221 may correspond to the circular sidewall facing the hole 211.

[0080] Subsequently, the circular sidewall of the barrier insulating layer 221 can be planarized by a trimming process. The trimming process may include an etching process using a third etchant 305. Hydrofluoric acid (HF) can be used as the third etchant 305. A part of the data storage pattern 225P can be etched by hydrofluoric acid (HF). The phenomenon of the barrier insulating layer 221 between the fluorine penetration sacrificial layer 203 and the data storage pattern 225P generated during the etching process using hydrofluoric acid (HF) can be prevented or alleviated by the pad insulating pattern 223P.

[0081] Through the trimming process, the barrier insulating layer 221 can have a planar sidewall 221FSW.

[0082] Referring to Figure 4F , a tunnel insulating layer 231 can be formed in the hole 211 (see Figure 4E ). The tunnel insulating layer 231 may include an insulating material such as a silicon oxide layer. The tunnel insulating layer 231 may extend in the first direction DR1 to cover the planar sidewall 221FSW of the barrier insulating layer 221, a plurality of data storage patterns 225P, and a plurality of pad insulating patterns 223P.

[0083] Subsequently, a channel layer 233 can be formed along the inner wall of the tunnel insulating layer 231. The channel layer 233 can be formed of a semiconductor material such as silicon (Si), germanium (Ge), or a mixture thereof. Thereafter, a core insulating layer 235 can be formed in the hole 211 (see Figure 4E ).

[0084] Reference Figure 4G , a plurality of sacrificial layers 203 as shown in Figure 4F can be removed to define a plurality of openings 311. To this end, a slit SI as shown in Figure 2A or Figure 2B can be formed to pass through the plurality of sacrificial layers 203 and the plurality of first interlayer insulating layers 201A as shown in Figure 4F . The plurality of sacrificial layers 203 as shown in Figure 4F can be selectively removed through the slit. Each opening 311 can be defined between the first interlayer insulating layers 201A adjacent in the first direction DR1.

[0085] Reference Figure 4H , a plurality of conductive layers 251 can be formed inside the plurality of openings 311 as shown in Figure 4G . To this end, the plurality of openings 311 as shown in Figure 4G can be filled with a conductive material through the slit, and a part of the conductive material in the slit can be removed so that the conductive material is separated into a plurality of conductive layers 251.

[0086] Using the process described with reference to Figures 4A to 4H , a semiconductor memory device as shown in Figure 3A can be provided.

[0087] Figure 5A and Figure 5B are cross-sectional views showing a method of manufacturing a semiconductor memory device according to an embodiment of the present disclosure.

[0088] Before performing the process shown in Figure 5A , a process of forming a stacked structure of the plurality of first interlayer insulating layers 201A and the plurality of sacrificial layers 203 described with reference to Figure 4A , a process of forming holes 211 passing through the plurality of first interlayer insulating layers 201A and the plurality of sacrificial layers 203, and a process of forming the plurality of second interlayer insulating layers 201B can be performed. In addition, before performing the process shown in Figure 5A , a process of forming a crystalline insulating layer described with reference to Figure 4B , a process of forming a data storage layer described with reference to Figure 4C , a process of etching a part of the data storage layer using a first etchant described with reference to Figure 4C , and a process of selectively etching the data storage layer using a second etchant described with reference to Figure 4D can be performed. Therefore, as shown in Figure 5A , a plurality of data storage patterns 225P can be provided between the plurality of interlayer insulating structures 201 defined by the plurality of first interlayer insulating layers 201A and the plurality of second interlayer insulating layers 201B.

[0089] Subsequently, as referred to Figure 4DAs described, a portion of the etchable crystalline insulating layer that is exposed between the data storage patterns 225P. Thus, as Figure 5A shown, the crystalline insulating layer can be separated into a plurality of pad insulating patterns 223P.

[0090] Referring to Figure 5A , the circular sidewall 221RSW of the blocking insulating layer 221 can be exposed between adjacent pad insulating patterns 223P along the first direction DR1.

[0091] Referring to Figure 5B , a tunnel insulating layer 231 can be formed inside the hole 211 (see Figure 5A ). The tunnel insulating layer 231 can extend in the first direction DR1 to cover the circular sidewall 221RSW of the blocking insulating layer 221, the plurality of data storage patterns 225P, and the plurality of pad insulating patterns 223P. Subsequently, a channel layer 233 and a core insulating layer 235 can be formed in sequence.

[0092] Subsequently, by performing the processes shown in Figure 4G and Figure 4H , a semiconductor memory device as shown in Figure 3B can be provided.

[0093] Figures 6A to 6I is a cross-sectional view showing a method of manufacturing a semiconductor memory device according to an embodiment of the present disclosure.

[0094] Referring to Figure 6A , as described with reference to Figure 4A , a plurality of first interlayer insulating layers 201A and a plurality of sacrificial layers 203 can be alternately stacked above a lower structure (not shown) in the first direction DR1. Each of the plurality of first interlayer insulating layers 201A and the plurality of sacrificial layers 203 can have the shape of a flat plate extending in the second direction DR2 that intersects the first direction DR1.

[0095] Subsequently, a hole 211 can be formed that extends in the first direction DR1 to pass through the plurality of first interlayer insulating layers 201A and the plurality of sacrificial layers 203. Thus, the sidewalls of the plurality of first interlayer insulating layers 201A facing the hole 211 can be exposed.

[0096] Thereafter, a plurality of second interlayer insulating layers 201B' can be formed on the exposed sidewalls of the plurality of first interlayer insulating layers 201A to define an uneven portion on the sidewall of the hole 211. According to an embodiment, the plurality of second interlayer insulating layers 201B' can be formed by selectively depositing an insulating material on the sidewalls of the plurality of first interlayer insulating layers 201A. At this time, each of the second interlayer insulating layers 201B' can have a sidewall that protrudes with respect to the hole 211. The first interlayer insulating layer 201A and the second interlayer insulating layer 201B' that are connected to each other can form an interlayer insulating structure 201.

[0097] Subsequently, a sacrificial insulating layer 221' may be formed along the uneven portions of the sidewalls of the hole 211 defined by the plurality of second interlayer insulating layers 201B'. The sacrificial insulating layer 221' may extend to cover the sidewalls of the plurality of second interlayer insulating layers 201B' and the sidewalls of the plurality of sacrificial layers 203. The sacrificial insulating layer 221' may be deposited on the uneven portions of the sidewalls of the hole 211 to a third thickness TH3. The third thickness TH3 may be less than the first thickness TH1 of the barrier insulating layer 221 described with reference to Figure 4A The sacrificial insulating layer 221' may include an insulating material such as a silicon oxide layer.

[0098] The sacrificial insulating layer 221' may include an inner wall facing the hole 211. The uneven portions defined by the plurality of second interlayer insulating layers 201B' may define a plurality of grooves 221GV on the inner wall of the sacrificial insulating layer 221'. The plurality of grooves 221GV may respectively correspond to the plurality of sacrificial layers 203.

[0099] With reference to Figure 6B , a data storage layer 225 may be formed on the inner wall of the sacrificial insulating layer 221'. The data storage layer 225 may fill the plurality of grooves 221GV. Similar to Figure 4C , inside the grooves 221GV, the data storage layer 225 may have a greater thickness in the second direction DR2 than along the convex inner wall of the sacrificial insulating layer 221'. The data storage layer 225 may be formed of a charge trapping insulating layer (e.g., a silicon nitride layer), a floating gate layer (e.g., polysilicon), or an insulating layer containing conductive nanodots.

[0100] Subsequently, a portion of the data storage layer 225 may be etched using a first etchant 301. Accordingly, the thickness of the data storage layer 225 may be reduced. According to an embodiment, hydrofluoric acid (HF) may be used as the first etchant 301.

[0101] With reference to Figure 6C , by selectively etching the data storage layer using a second etchant 303, the data storage layer may be separated into a plurality of data storage patterns 225P. Each data storage pattern 225P may be retained in the corresponding groove 223GV.

[0102] The second etchant 303 may have a higher etching selectivity than the first etchant 301 to avoid etching the sacrificial insulating layer 221' while etching the data storage layer 225. According to an embodiment, the second etchant 303 may be highly selective phosphoric acid (HSP). By performing the process as in Figure 6BAs shown, after the first etchant 301 is used to reduce the thickness of the data storage layer 225, the second etchant 303 is used to selectively etch the data storage layer 225, and the concentration of the by-products generated during the etching process using the second etchant 303 can be controlled to be lower than a critical value. 3 PO 4 When the concentration of by-products in )) exceeds the critical value, the phenomenon of oxide regrowth can be prevented or alleviated.

[0103] During the etching process of the data storage layer using the second etchant 303, a portion of the sacrificial insulating layer 221' may be exposed. The portion of the sacrificial insulating layer 221' may be exposed between the data storage patterns 225P adjacent in the first direction DR1. The exposed portion of the sacrificial insulating layer 221' may be a rounded sidewall 221RSW' facing the hole 211.

[0104] Reference Figure 6D , can be in hole 211 (see Figure 6C ) is formed inside. The tunnel insulating layer 231 may extend in the first direction DR1 to cover the circular sidewalls 221RSW' of the sacrificial insulating layer 221' and the plurality of data storage patterns 225P. The tunnel insulating layer 231 may include an insulating material such as a silicon oxide layer.

[0105] Then, refer to Figure 4F It is described that the channel layer 233 and the core insulating layer 235 are sequentially formed.

[0106] Reference Figure 6E , by referring to Figure 4G Described removal Figure 6D The plurality of sacrificial layers 203 shown may define a plurality of openings 311 . At this time, the plurality of data storage patterns 225P may be protected by the sacrificial insulating layer 221 ′. A portion of the sacrificial insulating layer 221 ′ may be exposed through the plurality of openings 311 .

[0107] Reference Figure 6F By removing a portion of the sacrificial insulating layer exposed through the plurality of openings 311 , the sacrificial insulating layer may be separated into a plurality of sacrificial insulating patterns 221P′. As a portion of the sacrificial insulating layer is removed, a plurality of data storage patterns 225P may be exposed through the plurality of openings 311 .

[0108] Reference Figure 6G , a preliminary layer 331 may be selectively deposited on an exposed surface of each of the plurality of data storage patterns 225P. According to an embodiment, the preliminary layer 331 may be deposited using area selective atomic layer deposition (ASD) and may include silicon oxycarbide (SiOC).

[0109] ReferenceFigure 6H , the preliminary layer 331 can be modified as shown in Figure 6G to form the barrier insulating pattern 241. According to an embodiment, the barrier insulating pattern 241 can be formed by annealing silicon oxycarbide. Here, carbon can be removed from the annealed silicon oxycarbide, and the dielectric constant and thickness can increase compared to the silicon oxycarbide before annealing. The barrier insulating pattern 241 including the annealed silicon oxycarbide can have a dielectric constant lower than that of the silicon dioxide layer and can be thicker than the sacrificial insulating pattern 221P'. Since the barrier insulating pattern 241 is formed after separating the data storage layer into a plurality of data storage patterns 225P by an etching process, fluorine generated during the etching process of the data storage layer can be prevented or reduced from penetrating into the barrier insulating pattern 241.

[0110] Referring to 6I, a plurality of conductive layers 251 can be formed in a plurality of openings 311 as shown in Figure 6H . Each conductive layer 251 can face a corresponding data storage pattern 225P and the barrier insulating pattern 241 is interposed therebetween.

[0111] Figure 7 is a cross-sectional view showing a process of forming a preliminary layer according to an embodiment of the present disclosure.

[0112] Instead of Figure 6G the preliminary layer 331 shown, a preliminary layer 333 as shown in Figure 7 can be formed. Figure 7 The preliminary layer 333 shown in Figure 6H can include the same material as the plurality of data storage patterns 225P. The preliminary layer 333 can be selectively formed on the surfaces of the plurality of data storage patterns 225P exposed through the plurality of openings 311. The preliminary layer 333 can be modified to the barrier insulating pattern 241 as shown in

[0113] Figure 7 The reference numerals "201A", "201B'", "201", "221P'", "231", "233", and "235" not described in Figures 6A to 6I can refer to the first interlayer insulating layer, the second interlayer insulating layer, the interlayer insulating structure, the sacrificial insulating pattern, the tunnel insulating layer, the channel layer, and the core insulating layer described with reference to

[0114] can be provided using the processes described with reference to Figures 6A to 6I and Figure 7 to provide the semiconductor memory device as shown in Figure 3C .

[0115] Figures 8A to 8C is a cross-sectional view showing a method of manufacturing a semiconductor memory device according to an embodiment of the present disclosure.

[0116] During the execution ofFigure 8A Before the process shown, you can perform the following steps as shown in the reference Figure 6A The process of forming a structure in which a plurality of first interlayer insulating layers 201A and a plurality of sacrificial layers 203 are alternately stacked is described as referring to Figure 6A The process of forming the hole 211, the process of selectively forming a plurality of second interlayer insulating layers 201B' on the sidewalls of the plurality of first interlayer insulating layers 201A to define a plurality of interlayer insulating structures 201, and the process described with reference to FIG. Figure 6A The process of forming the sacrificial insulating layer 221' is described. Figure 8A Before the process shown, the following steps can be performed in sequence: Figure 6B The process of forming the data storage layer is described as follows Figure 6B The process described herein using a first etchant to reduce the thickness of a data storage layer and the ... Figure 6C The process of forming a plurality of data storage patterns 225P is described. Figure 6C As shown, the rounded sidewalls 221RSW' of the sacrificial insulating layer 221' may be exposed between the data storage patterns 225P adjacent to each other in the first direction DR1.

[0117] Through the trimming process Figure 6C The circular sidewall 221RSW' or Figure 6C The convex sidewall of the second interlayer insulating layer 201B' is flattened. Figure 8A As shown, Figure 6C The convex sidewalls of the second interlayer insulating layer 201B' shown may be planarized by a trimming process. Here, the sacrificial insulating layer 221' may be a plurality of preliminary sacrificial insulating patterns 221PP", and the second interlayer insulating layer 201B' may have a flat sidewall 201FSW. The trimming process may include an etching process using a third etchant 305. Hydrofluoric acid (HF) may be used as the third etchant 305. A portion of the data storage pattern 225P may be etched by hydrofluoric acid (HF).

[0118] Reference Figure 8B , can be in hole 211 (see Figure 8A ) is formed inside. The tunnel insulating layer 231 may extend in the first direction DR1 to cover the flat sidewall 201FSW of the second interlayer insulating layer 201B', a plurality of data storage patterns 225P, and a plurality of preliminary sacrificial insulating patterns 221PP". Subsequently, a channel layer 233 and a core insulating layer 235 may be sequentially formed.

[0119] Reference Figure 8C , by removing Figure 8B The plurality of sacrificial layers 203 are used to form a plurality of openings 311 to expose Figure 8BThe multiple preliminary sacrificial insulation patterns 221PP" shown. Thereafter, by removing Figure 8B a part of the multiple preliminary sacrificial insulation patterns 221PP" shown, the multiple sacrificial insulation patterns 221P" can be retained. Each sacrificial insulation pattern 221P" can be retained between the data storage pattern 225P adjacent to each other in the first direction DR1 and the second interlayer insulation layer 201B'.

[0120] Subsequently, the process described with reference to Figure 6G and Figure 6H can be executed, or the process described with reference to Figure 7 can be executed, and then the process described with reference to Figure 6I can be executed. Thus, the semiconductor memory device shown in Figure 3D can be provided.

[0121] Figure 9 is a block diagram showing an electronic system according to an embodiment of the present disclosure.

[0122] With reference to Figure 9 , the electronic system 1000 can be a computing system, a medical device, a communication device, a wearable device, a memory system, etc. The electronic system 1000 may include a host 1100 and a storage device 1200.

[0123] The host 1100 can store data in the storage device 1200 or read data stored in the storage device 1200 based on an interface. The interface may include at least one of a double data rate (DDR) interface, a universal serial bus (USB) interface, a multimedia card (MMC) interface, an embedded MMC (eMMC) interface, a peripheral component interconnect (PCI) interface, a high-speed PCI (PCI-E) interface, an advanced technology attachment (ATA) interface, a serial ATA interface, a parallel ATA interface, a small computer system interface (SCSI), an enhanced small disk interface (ESDI), an integrated drive electronics (IDE) interface, a Firewire interface, a universal flash storage (UFS) interface, and a high-speed non-volatile memory (NVMe) interface.

[0124] The storage device 1200 may include a storage controller 1210 and a semiconductor memory device 1220. According to an embodiment, the storage device 1200 may include a semiconductor memory device 1220 such as a solid state drive (SSD) or a universal serial bus (USB) memory.

[0125] The storage controller 1210 can store data in the semiconductor memory device 1220 or read data stored in the semiconductor memory device 1220 under the control of the host 1100.

[0126] The semiconductor memory device 1220 may include one memory chip or multiple memory chips. The semiconductor memory device 1220 may store data or output the stored data under the control of the storage controller 1210.

[0127] The semiconductor memory device 1220 may be a non-volatile memory device. As described with reference to Figures 3A to 3D the semiconductor memory device 1220 may include a plurality of interlayer insulating structures, a plurality of conductive layers alternately stacked with the plurality of interlayer insulating structures, a plurality of data storage patterns spaced apart from each other in a direction in which the plurality of interlayer insulating structures and the plurality of conductive layers are stacked, and a barrier insulating layer or a barrier insulating pattern interposed between each data storage pattern and the corresponding conductive layer. The semiconductor memory device 1220 may also include a crystalline insulating layer interposed between the barrier insulating layer and the data storage pattern as described with reference to Figure 3A and Figure 3B or a sacrificial insulating pattern interposed between each interlayer insulating structure and the corresponding data storage pattern as described with reference to Figure 3C and Figure 3D This application claims priority to Korean Patent Application No. 10-2023-0167749, filed with the Korean Intellectual Property Office on November 28, 2023, the entire disclosure of which is incorporated herein by reference.

[0128] According to an embodiment of the present disclosure, since the data storage patterns are spaced apart from each other in the stacking direction of the conductive layers, interference between memory cells can be reduced, so that the operational reliability of the semiconductor memory device can be improved.

[0129] Cross-reference to related applications

[0130] This application claims priority to Korean Patent Application No. 10-2023-0167749, filed with the Korean Intellectual Property Office on November 28, 2023, the entire disclosure of which is incorporated herein by reference.

Claims

1. A semiconductor memory device, the semiconductor memory device comprising: a channel layer extending in a first direction; a tunnel insulating layer extending along an outer wall of the channel layer in the first direction; a plurality of interlayer insulating structures, the plurality of interlayer insulating structures being arranged along an outer wall of the tunnel insulating layer, the plurality of interlayer insulating structures being spaced apart from each other in the first direction; a plurality of conductive layers, the plurality of conductive layers being arranged alternately with the plurality of interlayer insulating structures in the first direction; a plurality of data storage patterns, the plurality of data storage patterns being interposed between the plurality of conductive layers and the tunnel insulating layer in a second direction, the plurality of data storage patterns being spaced apart from each other in the first direction, wherein the plurality of data storage patterns respectively correspond to the plurality of conductive layers, and wherein the second direction is perpendicular to the first direction; a pad insulating pattern extending to cover a first surface of each of the plurality of data storage patterns facing the first direction, a second surface of each of the plurality of data storage patterns facing a direction opposite to the first surface, and a third surface of each of the plurality of data storage patterns facing the second direction; and a blocking insulating layer interposed between each of the plurality of conductive layers and the pad insulating pattern, Wherein, the pad insulating pattern includes a crystalline insulating layer.

2. The semiconductor memory device according to claim 1, wherein The liner insulation pattern is thinner than the blocking insulation layer.

3. The semiconductor memory device according to claim 1, wherein: The pad insulating pattern has a dielectric constant higher than that of the silicon dioxide SiO 2 layer.

4. The semiconductor memory device according to claim 1, wherein: The plurality of interlayer insulating structures include: a plurality of first interlayer insulating layers, the plurality of first interlayer insulating layers being arranged alternately with the plurality of conductive layers in the first direction; and A plurality of second interlayer insulating layers are interposed between the plurality of first interlayer insulating layers and the tunnel insulating layer, and each of the second interlayer insulating layers has a sidewall protruding with respect to the tunnel insulating layer.

5. The semiconductor memory device according to claim 4, wherein: The blocking insulating layer extends to a space between the plurality of second interlayer insulating layers and the tunnel insulating layer and has a flat sidewall facing the tunnel insulating layer.

6. The semiconductor memory device according to claim 4, wherein: The blocking insulating layer extends to a space between the plurality of second interlayer insulating layers and the tunnel insulating layer and has a rounded sidewall facing the tunnel insulating layer.

7. A semiconductor memory device, the semiconductor memory device comprising: a channel layer extending in a first direction; a tunnel insulating layer extending along an outer wall of the channel layer in the first direction; a plurality of interlayer insulating structures, the plurality of interlayer insulating structures being arranged along an outer wall of the tunnel insulating layer, the plurality of interlayer insulating structures being spaced apart from each other in the first direction; a plurality of conductive layers, the plurality of conductive layers being arranged alternately with the plurality of interlayer insulating structures in the first direction; a plurality of data storage patterns, the plurality of data storage patterns being interposed between the plurality of conductive layers and the tunnel insulating layer in a second direction, the plurality of data storage patterns being spaced apart from each other in the first direction, wherein the plurality of data storage patterns respectively correspond to the plurality of conductive layers, and wherein the second direction is perpendicular to the first direction; a sacrificial insulating pattern covering a first surface of each of the plurality of data storage patterns facing the first direction and a second surface of each of the plurality of data storage patterns facing a direction opposite to the first surface; and a blocking insulating pattern interposed between each of the plurality of data storage patterns and a corresponding conductive layer among the plurality of conductive layers, Wherein, the blocking insulating pattern is thicker than the sacrificial insulating pattern.

8. The semiconductor memory device according to claim 7, wherein: The sacrificial insulating pattern is formed to open a third surface of each of the plurality of data storage patterns facing the second direction.

9. The semiconductor memory device according to claim 7, wherein: The blocking insulating pattern has a dielectric constant lower than that of the silicon dioxide layer.

10. The semiconductor memory device according to claim 7, wherein: The blocking insulating pattern includes silicon oxycarbide SiOC or an oxide including the same material as the plurality of data storage patterns.

11. The semiconductor memory device according to claim 7, wherein: The plurality of interlayer insulating structures include: a plurality of first interlayer insulating layers, the plurality of first interlayer insulating layers being arranged alternately with the plurality of conductive layers in the first direction; and A plurality of second interlayer insulating layers are interposed between the plurality of first interlayer insulating layers and the tunnel insulating layer and are alternately arranged with the plurality of data storage patterns in the first direction.

12. The semiconductor memory device according to claim 11, wherein The sacrificial insulating pattern is interposed between second interlayer insulating layers and data storage patterns adjacent to each other in the first direction among the plurality of second interlayer insulating layers and the plurality of data storage patterns.

13. The semiconductor memory device according to claim 11, in, Each of the plurality of second interlayer insulating layers has a rounded sidewall facing the tunnel insulating layer, and The sacrificial insulating pattern extends to a space between the circular sidewall and the tunnel insulating layer.

14. The semiconductor memory device according to claim 11, wherein: Each of the plurality of second interlayer insulating layers has a flat sidewall contacting the tunnel insulating layer.

15. A method for manufacturing a semiconductor memory device, the method comprising the steps of: alternately stacking a plurality of first interlayer insulating layers and a plurality of sacrificial layers in a first direction; forming holes through the plurality of first interlayer insulating layers and the plurality of sacrificial layers; forming a plurality of second interlayer insulating layers on sidewalls of the plurality of first interlayer insulating layers facing the hole to define uneven portions on the sidewalls of the hole; forming a blocking insulating layer along the uneven portion to cover sidewalls of the plurality of second interlayer insulating layers and sidewalls of the plurality of sacrificial layers; forming a crystalline insulating layer on an inner wall of the blocking insulating layer to have a plurality of grooves corresponding to the plurality of sacrificial layers; forming a plurality of data storage patterns on an inner wall of the crystalline insulating layer to respectively fill the plurality of grooves of the crystalline insulating layer; etching a portion of the crystalline insulating layer exposed between the plurality of data storage patterns so that the crystalline insulating layer is separated into a plurality of pad insulating patterns; forming a tunnel insulating layer inside the hole to cover the etched region of the crystalline insulating layer and the plurality of data storage patterns; forming a channel layer along an inner wall of the tunnel insulating layer; as well as The plurality of sacrificial layers are replaced with a plurality of conductive layers.

16. The method according to claim 15, wherein: The crystalline insulating layer is thinner than the blocking insulating layer.

17. The method according to claim 15, wherein: The crystalline insulating layer has a dielectric constant higher than that of the silicon dioxide layer.

18. The method according to claim 15, wherein: The step of forming the plurality of data storage patterns comprises the following steps: forming a data storage layer on the inner wall of the crystalline insulating layer to fill the plurality of grooves of the crystalline insulating layer; removing a portion of the data storage layer using hydrofluoric acid (HF) to reduce the thickness of the data storage layer; and A portion of the data storage layer is removed using phosphoric acid H 3 PO 4 so that the data storage layer having a reduced thickness is separated into the plurality of data storage patterns.

19. The method according to claim 15, wherein: The step of etching the portion of the crystalline insulating layer is performed to expose the blocking insulating layer.

20. The method according to claim 19, in, The sidewalls of the plurality of second interlayer insulating layers protrude with respect to the hole, wherein the exposed area of ​​the blocking insulating layer corresponds to a circular sidewall on the sidewalls of the plurality of second interlayer insulating layers facing the hole, and Wherein, the circular sidewall of the blocking insulating layer is planarized through a trimming process.

21. The method according to claim 19, in, The sidewalls of the plurality of second interlayer insulating layers protrude with respect to the hole, wherein the exposed area of ​​the blocking insulating layer corresponds to a circular sidewall on the sidewalls of the plurality of second interlayer insulating layers facing the hole, and Wherein, the tunnel insulation layer extends to cover the circular side wall.

22. A method for manufacturing a semiconductor memory device, the method comprising the steps of: alternately stacking a plurality of first interlayer insulating layers and a plurality of sacrificial layers in a first direction; forming holes through the plurality of first interlayer insulating layers and the plurality of sacrificial layers; forming a plurality of second interlayer insulating layers on sidewalls of the plurality of first interlayer insulating layers facing the hole to define uneven portions on the sidewalls of the hole; forming a sacrificial insulating layer along the uneven portion to cover sidewalls of the plurality of second interlayer insulating layers and sidewalls of the plurality of sacrificial layers and to have a plurality of grooves corresponding to the plurality of sacrificial layers; forming a plurality of data storage patterns on the inner wall of the sacrificial insulating layer to respectively fill the plurality of grooves of the sacrificial insulating layer; forming a tunnel insulating layer inside the hole to cover the plurality of data storage patterns and the sacrificial insulating layer; forming a channel layer along an inner wall of the tunnel insulating layer; removing the plurality of sacrificial layers to define a plurality of openings exposing the sacrificial insulating layers; removing the exposed portion of the sacrificial insulating layer so that the plurality of data storage patterns are exposed through the plurality of openings; selectively depositing a preliminary layer on an exposed surface of each of the plurality of data storage patterns; forming a blocking insulating pattern by modifying the preliminary layer; as well as A plurality of conductive layers are formed inside the plurality of openings opened by the blocking insulating pattern.

23. The method according to claim 22, wherein: The step of forming the plurality of data storage patterns comprises the following steps: forming a data storage layer on the inner wall of the sacrificial insulating layer to fill the plurality of grooves of the sacrificial insulating layer; removing a portion of the data storage layer using hydrofluoric acid (HF) to reduce the thickness of the data storage layer; and A portion of the data storage layer is removed using phosphoric acid H 3 PO 4 so that the data storage layer having a reduced thickness is separated into the plurality of data storage patterns.

24. The method according to claim 22, in, The sidewalls of the plurality of second interlayer insulating layers protrude with respect to the hole, wherein the sacrificial insulating layer comprises a circular sidewall between the plurality of data storage patterns facing the hole, and Wherein, the tunnel insulation layer extends to cover the circular side wall.

25. The method according to claim 22, in, The sidewalls of the plurality of second interlayer insulating layers protrude with respect to the hole, wherein the sacrificial insulating layer comprises a circular sidewall between the plurality of data storage patterns facing the hole, and The circular sidewall of the sacrificial insulating layer or the sidewalls of the plurality of second interlayer insulating layers are planarized by a trimming process.

26. The method of claim 22, wherein: The blocking insulating pattern has a dielectric constant lower than that of the silicon dioxide layer.

27. The method of claim 22, wherein: The blocking insulating pattern is thicker than the sacrificial insulating pattern.

28. The method according to claim 22, in, The preliminary layer includes silicon oxycarbide, and The preliminary layer is modified into the blocking insulating pattern by annealing the silicon oxycarbide.

29. The method according to claim 22, in, The preliminary layer includes the same material as the plurality of data storage patterns, and The preliminary layer is modified into the blocking insulating pattern by oxidizing the preliminary layer.

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