Junction field effect transistor based on ZnO thin film heterojunction and preparation method thereof
By etching grooves on the P-type silicon substrate and growing an N-type zinc oxide film, the conductive channel width is regulated by piezoelectric effect, the problem of insufficient current regulation of traditional junction field effect transistors is solved, and effective piezoelectric regulation of current and mechanical stability is achieved.
Patent Information
- Application Number
- CN202510234204.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-28
- Publication Date
- 2025-05-30
AI Technical Summary
Traditional junction field effect transistors are overly dependent on voltage in current regulation and have insufficient mechanical stability, which limits their application in high sensitivity and complex scenarios.
Using a junction-type field effect transistor based on ZnO film heterojunction, by etching grooves on a P-type silicon substrate and growing an N-type zinc oxide film, the width of the conductive channel is regulated by piezoelectric effect, thereby realizing piezoelectric regulation of current.
Effective control of current is achieved through piezoelectric effect, which significantly improves the mechanical stability of the device and is suitable for high-sensitivity applications in complex environments.
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Figure CN120076382A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the fields of microelectronics and piezoelectric electronics, and particularly relates to a preparation method of a junction field effect transistor based on a ZnO thin film heterojunction. Background Art
[0002] As a group II-VI compound semiconductor material, ZnO has excellent piezoelectric properties. Its piezoelectric constant can be optimized through doping and structure regulation, making it suitable for manufacturing high-performance piezoelectric devices and showing excellent semiconductor properties. ZnO has a hexagonal wurtzite structure, with high tensile strength, capable of withstanding large mechanical deformations and not affected by temperature changes. It has a direct bandgap of 3.37 eV and a free exciton binding energy of 60 meV, and has thermal and chemical stability at ambient temperature. Most of the existing heterojunction devices utilizing the piezoelectric effect of ZnO are based on zinc oxide in the form of nanowires. The small junction area leads to limited regulation effects, and the mechanical stability of the piezoelectric material in the form of nanowires is insufficient, making it prone to failure under mechanical stress, which limits its application in complex environments.
[0003] The heterojunction field effect transistor (JFET) is one of the most common semiconductor devices. Its channel can be of two types, N-type and P-type, and the most commonly used is the N-channel JFET. The junction field effect transistor has the advantages of small device size, low-frequency noise, and high input impedance, and has broad application prospects in fields such as piezoelectric detection. The heterojunction field effect transistor controls the conduction between the source and drain of the transistor by forming a PN junction between the gate and the source-drain. Specifically, it is through controlling the width of the depletion region of the PN junction formed between the gate and the source-drain. However, traditional heterojunction field effect transistors have the problem of over-relying on voltage in current regulation and lacking other regulation mechanisms. This limitation restricts their application in high-sensitivity scenarios. For example, in emerging fields such as pressure detection, traditional JFETs are difficult to convert mechanical energy into electrical signals due to the lack of sensitive response to external forces, which limits their application scope. Moreover, the single surface structure of existing JFETs limits performance improvement, and the mechanical stability is insufficient, making them prone to failure under mechanical stress, which restricts their application in complex environments. Summary of the Invention
[0004] Aiming at the defects of the existing technology, the present invention provides a preparation method of a junction field effect transistor based on a ZnO thin film heterojunction, aiming to solve the problems that traditional junction field effect transistors over-rely on voltage in current regulation and have insufficient mechanical stability, thus restricting their application in high-sensitivity and complex scenarios.
[0005] To solve the above technical problems, according to the first aspect of the present invention, a junction field effect transistor based on a ZnO thin film heterojunction is provided. The transistor includes a P-type silicon substrate, an N-type zinc oxide thin film, a source electrode, a drain electrode, and a gate electrode; first grooves and second grooves are symmetrically arranged on the upper surface and the lower surface of the P-type silicon substrate respectively, and the N-type zinc oxide thin film covers the interiors of both the first grooves and the second grooves; the N-type zinc oxide thin film is covered by the gate electrode; the source electrode and the drain electrode are located on the upper surface of the P-type silicon substrate, and the source electrode and the drain electrode are separated by the first grooves; the source electrode, the drain electrode, and the gate electrode do not contact each other.
[0006] Preferably, the source electrode, the drain electrode, and the gate electrode are each independently selected from aluminum or a titanium-aluminum composite material, and the titanium-aluminum composite material is specifically composed of a metal titanium layer and a metal aluminum layer.
[0007] Preferably, the thickness of the N-type zinc oxide thin film is 1 - 2 μm.
[0008] Preferably, the value obtained by subtracting the depths of the first grooves and the second grooves from the thickness of the P-type silicon substrate is the channel width, and the channel width is 30 - 50 μm.
[0009] According to another aspect of the present invention, a preparation method of the above-mentioned junction field effect transistor based on a ZnO thin film heterojunction is provided, including the following steps:
[0010] (1) Prepare a P-type silicon substrate;
[0011] (2) Use a metal mask plate to cover the four peripheral edges of the upper surface and the lower surface of the P-type silicon substrate, so that the middle area of the P-type silicon substrate is not covered by the metal mask plate; perform deep plasma etching on both the uncovered upper surface and the lower surface of the P-type silicon substrate to respectively obtain first grooves and second grooves on the upper surface and the lower surface of the P-type silicon substrate;
[0012] (3) Grow an N-type zinc oxide thin film inside both the first grooves and the second grooves;
[0013] (4) Prepare a gate electrode on the surface of the N-type zinc oxide thin film;
[0014] (5) Prepare a source electrode and a drain electrode on the upper surface of the P-type silicon substrate respectively, so that the source electrode and the drain electrode are separated by the first grooves;
[0015] (6) Finally, perform annealing treatment on the prepared sample.
[0016] Preferably, in step (3), the N-type zinc oxide thin film is prepared by magnetron sputtering.
[0017] Preferably, the sputtering power of the magnetron sputtering method is 130-180 w, the sputtering time is 1-2 h, and the sputtering gas pressure is 1-2.5 Pa.
[0018] Preferably, in steps (4) and (5), the gate electrode, source electrode, and drain electrode are all prepared by electron beam evaporation.
[0019] Preferably, in step (1), the P-type silicon substrate is also cleaned. The specific cleaning steps are as follows: first, ultrasonically clean with an acetone solution to remove organic dirt, then ultrasonically clean with alcohol to remove acetone, and finally ultrasonically clean with deionized water, and then blow dry with nitrogen.
[0020] Preferably, the annealing temperature is 400-600 °C, and the annealing time is 10-20 min.
[0021] Generally speaking, compared with the prior art, the above technical solutions conceived by the present invention mainly have the following technical advantages:
[0022] (1) By introducing a zinc oxide thin film to form a heterojunction with silicon, the fabricated junction field-effect heterojunction transistor structure can regulate the width of the conductive channel between the source and drain through the piezoelectric charge change caused by an external force and the spatially extended region formed by the piezoelectric effect, thereby realizing the regulation of the current of the piezoelectric device through piezoelectric regulation. Therefore, the present invention can effectively regulate the current of the junction device by using the piezoelectric effect of the ZnO thin film.
[0023] (2) By etching grooves on the silicon substrate, compared with grinding the entire silicon substrate to make it thinner, the present invention can significantly improve the mechanical stability of the device, effectively resist external stress and mechanical shock, and can better balance the thermal stress that may occur during the operation of the device, thereby improving the reliability of the device in a complex environment; by setting grooves on both the upper and lower surfaces of the silicon substrate, on the one hand, piezoelectric charges can be generated on the ZnO thin films on the upper and lower surface grooves, so as to more effectively regulate the width of the conductive channel and achieve a more significant current regulation effect. On the other hand, by setting grooves on both the upper and lower surfaces of the silicon substrate, the ZnO thin films on the upper and lower surface grooves can receive signals from different directions for signal detection from different external sources, realizing the multifunctional integration of the device. Therefore, the present invention etches grooves on the upper and lower surfaces of the silicon wafer respectively to reduce the channel width, greatly improving the piezoelectric regulation effect while ensuring the mechanical strength of the device.
[0024] (3) The present invention adopts magnetron sputtering technology. By adjusting the sputtering gas pressure, the microstructure and c-axis preferred orientation growth of the ZnO thin film can be affected. Moreover, the ZnO thin film prepared on the Si substrate exhibits better orientation growth characteristics, making the crystallinity and electrical properties of the prepared ZnO thin film better. By adjusting the sputtering gas pressure, the intensity of the ZnO diffraction peak can be increased and the crystallinity can be improved, thereby maximizing the piezoelectric regulation effect.
[0025] (4) In the present invention, for the heterojunction formed by the zinc oxide thin film and silicon, by adjusting the area of the groove to adjust the cross-sectional area of the heterojunction, the cross-sectional area of the heterojunction can be regulated, thereby realizing a large-area heterojunction and having a better piezoelectric regulation effect. Description of the Drawings
[0026] Figure 1 It is a schematic structural diagram of a junction field-effect transistor based on a ZnO thin film heterojunction provided by an embodiment of the present invention.
[0027] Figure 2 It is a process flow diagram of a junction field-effect transistor based on a ZnO thin film heterojunction provided by an embodiment of the present invention.
[0028] In the figure, 1 is a P-type silicon substrate; 2 is an N-type zinc oxide thin film; 3 is a source electrode; 4 is a drain electrode; 5 is a gate electrode; 6 is a first groove; 7 is a second groove; 8 is a mask plate. Detailed Embodiments
[0029] In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.
[0030] A junction field-effect transistor based on a ZnO thin film heterojunction provided by the present invention, specifically, as Figure 1 shown, includes: a P-type silicon substrate 1, an N-type zinc oxide thin film 2, a source electrode 3, a drain electrode 4 and a gate electrode 5; a first groove 6 and a second groove 7 are symmetrically arranged on the upper surface and the lower surface of the P-type silicon substrate 1 respectively, and the N-type zinc oxide thin film 2 is covered in both the first groove 6 and the second groove 7; the gate electrode 5 is covered on the N-type zinc oxide thin film 2; the source electrode 3 and the drain electrode 4 are respectively covered on the upper surface of the P-type silicon substrate 1 at both ends of the first groove 6, and the source electrode 3, the drain electrode 4 and the gate electrode 5 do not contact each other.
[0031] The present invention provides a method for preparing a junction field-effect transistor based on a ZnO thin film heterojunction: specifically including the following steps:
[0032] (1) Prepare a P-type silicon substrate 1;
[0033] (2) Use a metal mask plate 8 to block the four peripheral edges of the upper and lower surfaces of the P-type silicon substrate 1, so that the middle area of the P-type silicon substrate is not blocked by the metal mask plate 8; perform deep plasma etching on both the unblocked upper and lower surfaces of the P-type silicon substrate 1 to obtain a first groove 6 and a second groove 7 on the upper and lower surfaces of the P-type silicon substrate respectively;
[0034] (3) Grow an N-type zinc oxide thin film 2 in both the first groove 6 and the second groove 7;
[0035] (4) Prepare gate electrodes 5 on the surfaces of the N-type zinc oxide thin films 2;
[0036] (5) Prepare a source electrode 3 and a drain electrode 4 on the upper surface of the P-type silicon substrate 1 respectively, so that the source electrode 3 and the drain electrode 4 are separated by the first groove 6;
[0037] (6) Finally, perform annealing treatment on the prepared sample.
[0038] Specifically, it includes the following steps:
[0039] (1) Select a 2-inch silicon wafer with a thickness of 150 um ± 10.0 nm, a doping type of P-type, and a doping concentration of 10 15 -10 16 cm -3 . First, clean the silicon wafer. The specific steps are as follows: first, ultrasonically clean with acetone solution for 2 - 5 min to remove organic dirt, then ultrasonically clean with alcohol for 2 - 5 min to remove acetone, and finally ultrasonically clean with deionized water for 3 - 5 min, and then dry with nitrogen.
[0040] (2) Use deep reactive ion etching (DRIE) on the upper and lower surfaces of the silicon wafer, use a metal mask plate to block the parts that do not need to be etched, the etched area is 25 mm × 10 mm, the etching rate is controlled at 1 - 3 μm / min, and the etching time is 15 - 50 min. The flow rates of SF 6 and O 2 are 36 cm 3 / s and 6 cm 3 / s respectively, the radio frequency power is 120 - 360 W, and the reaction pressure is 240 - 350 torr.
[0041] (3) The sample obtained in step (2) is subjected to magnetron sputtering to grow a ZnO thin film at the groove. The sputtering gas pressure is 1 - 2.5 Pa, the substrate temperature is 25 - 250 °C, the sputtering power is 130 - 180 W, the sputtering time is 60 - 120 min, and the thickness of the zinc oxide thin film is 1 - 2 μm.
[0042] (4) The sample obtained in step (3) is subjected to electron beam evaporation. Using a metal mask plate to block, source electrodes, drain electrodes, and gate electrodes of a titanium-aluminum composite material are evaporated on the upper surface of the sample. The thickness of Ti is 10 - 30 nm, and the thickness of Al is 1 - 2 μm. The obtained sample is annealed in a hydrogen-nitrogen mixed gas with a hydrogen volume fraction of 3%, the annealing temperature is 400 - 600 °C, and the annealing time is 10 - 20 min. 2 Volume fraction of hydrogen is 3% in the hydrogen-nitrogen mixed gas, annealing temperature is 400 - 600 °C, annealing for 10 - 20 min.
[0043] Example 1
[0044] A junction field effect transistor based on a ZnO thin film heterojunction. Specifically, as Figure 1 shown, it includes: a P-type silicon substrate 1, an N-type zinc oxide thin film 2, a source electrode 3, a drain electrode 4, and a gate electrode 5; first grooves 6 and second grooves 7 are symmetrically arranged on the upper surface and the lower surface of the P-type silicon substrate 1 respectively, and the N-type zinc oxide thin film 2 is covered in both the first grooves 6 and the second grooves 7; the N-type zinc oxide thin film 2 is covered by the gate electrode 5; the source electrode 3 and the drain electrode 4 are located on the upper surface of the P-type silicon substrate 1, and the source electrode 3 and the drain electrode 4 are separated by the first groove 6, and the source electrode 3, the drain electrode 4, and the gate electrode 5 do not contact each other. The materials of the source electrode 3, the drain electrode 4, and the gate electrode 5 are all selected from titanium-aluminum composite materials. The titanium-aluminum composite material specifically consists of a metal titanium layer and a metal aluminum layer. The thickness of the metal titanium layer is 30 nm, and the thickness of the metal aluminum layer is 1 μm. The thickness of the N-type zinc oxide thin film 2 is 1 μm. The value obtained by subtracting the depths of the first groove 6 and the second groove 7 from the thickness of the P-type silicon substrate 1 is the channel width, and the channel width is 30 μm.
[0045] Example 2
[0046] A preparation method of a junction field effect transistor based on a ZnO thin film heterojunction specifically includes the following preparation steps:
[0047] (1) Select a 2-inch silicon wafer with a thickness of 150 μm, a doping type of P-type, and a doping concentration of 10 16 cm -3 . First, clean the silicon wafer. The specific steps are as follows: First, ultrasonically clean with an acetone solution for 3 min to remove organic dirt, then ultrasonically clean with alcohol for 3 min to remove acetone, and finally ultrasonically clean with deionized water for 3 min, and then dry with nitrogen.
[0048] (2) Deep reactive ion etching (DRIE) is used for the upper and lower surfaces of the silicon wafer. A metal mask plate is used to shield the parts that do not need to be etched. The etched area is 25 mm × 10 mm, the etching rate is controlled at 1 μm / min, and the etching time is 50 min. SF 6 and O 2 flow rates are 36 cm 3 / s and 6 cm 3 / s respectively, the radio frequency power is 300 W, the reaction pressure is 240 torr, and the channel width is 50 μm.
[0049] (3) For the sample obtained in step (2), ZnO thin films are grown at the grooves by magnetron sputtering. The sputtering gas pressure is 1 Pa, the substrate temperature is 250 °C, the sputtering power is 180 W, the sputtering time is 2 h, and the thickness of the zinc oxide thin film is 20 μm.
[0050] (4) Electron beam evaporation is carried out on the sample obtained in step (3). Using a metal mask plate to shield, source electrodes, drain electrodes, and gate electrodes of a titanium-aluminum composite material are evaporated on the upper surface of the sample. The titanium-aluminum composite material is specifically composed of a metal titanium layer and a metal aluminum layer. The thickness of Ti in each electrode is 30 nm, and the thickness of Al is 1 μm. Al is evaporated on the lower surface as the gate electrode with a thickness of 1 μm. The obtained sample is annealed in a hydrogen-nitrogen mixed gas with a hydrogen volume fraction of 3%, the annealing temperature is 450 °C, and the annealing time is 15 min. 2 The annealing temperature is 450 °C, and the annealing time is 15 min.
[0051] Example 3
[0052] A preparation method of a junction field effect transistor based on a ZnO thin film heterojunction specifically includes the following preparation steps: (1) A 2-inch silicon wafer is selected. The thickness of the silicon wafer is 150 μm, the doping type is P-type, and the doping concentration is 10 16 cm -3 . First, the silicon wafer is cleaned. The specific steps are as follows: First, ultrasonically clean with acetone solution for 3 min to remove organic dirt, then ultrasonically clean with alcohol for 3 min to remove acetone, and finally ultrasonically clean with deionized water for 3 min, and then blow dry with nitrogen.
[0053] (2) DRIE is used to etch the upper and lower surfaces of the silicon wafer. A metal mask plate is used to shield the parts that do not need to be etched. The etched area is 25 mm × 10 mm, the etching rate is controlled at 2 μm / min, and the etching time is 25 min. SF 6 and O 2 flow rates are 36 cm 3 / s and 6 cm 3 / s respectively, the radio frequency power is 120, the reaction pressure is 350 torr, and the channel width is 30 μm.
[0054] (3) The sample obtained in step (2) is subjected to magnetron sputtering to grow a ZnO thin film at the groove. The sputtering gas pressure is 2.5 Pa, the substrate temperature is 150 °C, the sputtering power is 130 W, the sputtering time is 120 min, and the thickness of the zinc oxide thin film is 15 μm.
[0055] (4) The sample obtained in step (3) is subjected to electron beam evaporation. Using a metal mask plate to block, source electrodes, drain electrodes, and gate electrodes of a titanium-aluminum composite material are evaporated on the upper surface of the sample. The titanium-aluminum composite material specifically consists of a metal titanium layer and a metal aluminum layer. The thickness of Ti in each electrode is 20 nm, and the thickness of Al is 1 μm. Al is evaporated on the lower surface as the gate electrode with a thickness of 1 μm. The obtained sample is annealed in a hydrogen-nitrogen mixed gas with a hydrogen volume fraction of 3% at an annealing temperature of 450 °C for 15 min. 2 The annealing is carried out in a hydrogen-nitrogen mixed gas with a hydrogen volume fraction of 3% at an annealing temperature of 450 °C for 15 min.
[0056] Example 4
[0057] A preparation method of a junction field effect transistor based on a ZnO thin film heterojunction specifically includes the following preparation steps: (1) A 2-inch silicon wafer is selected. The thickness of the silicon wafer is 150 μm, the doping type is P-type, and the doping concentration is 10 15 cm -3 . First, the silicon wafer is cleaned. The specific steps are as follows: First, ultrasonically clean with acetone solution for 3 min to remove organic dirt, then ultrasonically clean with alcohol for 3 min to remove acetone, and finally ultrasonically clean with deionized water for 3 min, and then dry with nitrogen.
[0058] (2) The upper and lower surfaces of the silicon wafer are etched by DRIE. A metal mask plate is used to block the parts that do not need to be etched. The etched area is 25 mm × 10 mm, the etching rate is controlled at 3 μm / min, and the etching time is 16 min. The flow rates of SF 6 and O 2 are 36 cm 3 / s and 6 cm 3 / s respectively, the radio frequency power is 200 W, and the reaction pressure is 300 torr.
[0059] (3) The sample obtained in step (2) is subjected to magnetron sputtering to grow a ZnO thin film at the groove. The sputtering gas pressure is 1.5 Pa, the substrate temperature is 100 °C, the sputtering power is 150 W, the sputtering time is 100 min, and the thickness of the zinc oxide thin film is 15 μm.
[0060] (4) Electron beam evaporation is performed on the sample obtained in step (3). Using a metal mask plate to block, source electrodes, drain electrodes, and gate electrodes of a titanium-aluminum composite material are evaporated on the upper surface of the sample. The titanium-aluminum composite material is specifically composed of a metal titanium layer and a metal aluminum layer. The thickness of Ti in each electrode is 25 nm, and the thickness of Al is 1 μm. Al is evaporated on the lower surface as the gate electrode with a thickness of 1 μm. The obtained sample is annealed in a hydrogen-nitrogen mixed gas with a hydrogen volume fraction of 3% at an annealing temperature of 600 °C for 15 min. 2 Anneal in a hydrogen-nitrogen mixed gas with a volume fraction of 3% hydrogen at an annealing temperature of 600 °C for 15 minutes.
[0061] In a junction JFET of a heterojunction based on ZnO disclosed in the present invention, a P-type Si is used as the channel, and a ZnO thin film is grown on the substrate by magnetron sputtering; the width of the conductive channel is regulated by piezoelectric charges caused by external forces, thereby realizing a JFET for piezoelectrically regulating current; electrodes are prepared by electron beam evaporation. The JFET has a simple structure, and its preparation process is controllable, and it has broad application prospects in the fields of integrated circuits, pressure detectors, etc.
[0062] It is easy for those skilled in the art to understand that the above are only preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.
Claims
1. A junction field effect transistor based on a ZnO thin film heterojunction, characterized in that: The transistor comprises a P-type silicon substrate (1), an N-type zinc oxide film (2), a source electrode (3), a drain electrode (4) and a gate electrode (5); the upper surface and the lower surface of the P-type silicon substrate (1) are symmetrically provided with a first groove (6) and a second groove (7), and the inside of the first groove (6) and the second groove (7) are both covered with the N-type zinc oxide film (2); the N-type zinc oxide film (2) is covered by the gate electrode (5); the source electrode (3) and the drain electrode (4) are located on the upper surface of the P-type silicon substrate (1), and the source electrode (3) and the drain electrode (4) are separated by the first groove (6); the source electrode (3), the drain electrode (4) and the gate electrode (5) are not in contact with each other.
2. A junction field effect transistor based on ZnO thin film heterojunction according to claim 1, characterized in that: The source electrode (3), the drain electrode (4) and the gate electrode (5) are each independently selected from aluminum or a titanium-aluminum composite material, and the titanium-aluminum composite material is specifically composed of a metal titanium layer and a metal aluminum layer.
3. A junction field effect transistor based on ZnO thin film heterojunction according to claim 1, characterized in that: The thickness of the N-type zinc oxide film (2) is 1-2 μm.
4. A junction field effect transistor based on ZnO thin film heterojunction according to claim 1, characterized in that: The value obtained by subtracting the depths of the first groove (6) and the second groove (7) from the thickness of the P-type silicon substrate (1) is the channel width, and the channel width is 30-50 um.
5. A method for preparing a junction field effect transistor based on a ZnO thin film heterojunction according to any one of claims 1 to 4, characterized in that: The following steps are involved: (1) Preparing a P-type silicon substrate; (2) using a metal mask plate to cover the edges of the upper surface and the lower surface of the P-type silicon substrate so that the middle area of the P-type silicon substrate is not covered by the metal mask plate; Performing deep plasma etching on the unshielded upper surface and lower surface of the P-type silicon substrate to obtain a first groove and a second groove on the upper surface and the lower surface of the P-type silicon substrate respectively; (3) growing an N-type zinc oxide thin film inside the first groove and the second groove; (4) preparing gate electrodes on the surface of the N-type zinc oxide film; (5) preparing a source electrode and a drain electrode on the upper surface of the P-type silicon substrate respectively, so that the source electrode and the drain electrode are separated by the first groove; (6) Finally, the prepared samples are annealed.
6. A method for preparing a junction field effect transistor based on a ZnO thin film heterojunction according to claim 5, characterized in that: In step (3), the N-type zinc oxide thin film is prepared by magnetron sputtering.
7. The method for preparing a junction field effect transistor based on a ZnO thin film heterojunction according to claim 6, characterized in that: The sputtering power of the magnetron sputtering method is 130-180W, the sputtering time is 1-2h, and the sputtering gas pressure is 1-2.5Pa.
8. A method for preparing a junction field effect transistor based on a ZnO thin film heterojunction according to claim 5, characterized in that: In step (4) and step (5), the gate electrode, source electrode and drain electrode are all prepared by electron beam evaporation.
9. A method for preparing a junction field effect transistor based on a ZnO thin film heterojunction according to claim 5, characterized in that: Step (1) also includes cleaning the P-type silicon substrate, and the specific steps of cleaning are: first use acetone solution to ultrasonically clean and remove organic dirt, then use alcohol to ultrasonically clean and remove acetone, and finally use deionized water to ultrasonically clean and then blow dry with nitrogen.
10. A method for preparing a junction field effect transistor based on a ZnO thin film heterojunction according to claim 5, characterized in that: The annealing temperature is 400-600° C., and the annealing time is 10-20 minutes.