Method of forming a semiconductor structure

Abstract

A method for forming a semiconductor structure, the method comprising: providing a substrate, the substrate comprising a device region and a dummy device region adjacent to the device region, a top of the substrate of the device region and the dummy device region being formed with a stacked gate structure, the stacked gate structure comprising a first gate structure and a second gate structure located above the first gate structure; forming an interlayer dielectric layer covering sidewalls of the stacked gate structure on the substrate of the device region and the dummy device region; removing the second gate structure; after removing the second gate structure, removing the first gate structure of the device region, forming an opening in the device region, the opening being enclosed by sidewalls of the adjacent interlayer dielectric layer and a top surface of the substrate; forming a device gate structure in the opening, a top of the device gate structure being flush with a top of the first gate structure in the dummy device region. The top surface flatness of the device gate structure and the thickness uniformity of the device gate structure are improved, and thus the performance of the semiconductor structure is improved.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the field of semiconductor manufacturing, and in particular, to a method for forming a semiconductor structure. BACKGROUND

[0002] With the gradual development of semiconductor process technology, the semiconductor process node is constantly reduced following the development trend of Moore's law. In order to adapt to the reduction of the process node, the channel length of the MOSFET field effect transistor has to be shortened. However, as the device channel length is shortened, the distance between the source and the drain of the device is also shortened, so the control ability of the gate to the channel is poor, and the subthreshold leakage phenomenon, i.e. the so-called short channel effect (SCE) is more likely to occur.

[0003] Therefore, in order to better adapt to the requirement of device size scaling, non-planar MOS transistors have emerged, such as gate-all-around (GAA) transistors or fin field effect transistors (FinFET). In the FinFET, the gate can at least control the ultra-thin body (fin) from two sides, and the control ability of the gate to the channel is stronger than that of the planar MOSFET device, which can well suppress the short channel effect; and the FinFET has better compatibility with existing integrated circuit manufacturing than other devices. SUMMARY

[0004] The problem solved by embodiments of the present application is to provide a method for forming a semiconductor structure, which is beneficial to further improve the performance of the semiconductor structure.

[0005] To solve the above problems, embodiments of the present application provide a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a device region and a pseudo-device region adjacent to the device region, a top of the substrate of the device region and the pseudo-device region being formed with a stacked gate structure, the stacked gate structure comprising a first gate structure and a second gate structure located above the first gate structure; forming an interlayer dielectric layer covering the sidewalls of the stacked gate structure on the substrate of the device region and the pseudo-device region; removing the second gate structure; after removing the second gate structure, removing the first gate structure of the device region to form an opening in the device region, the opening being surrounded by the top surface of the substrate and the sidewalls of the adjacent interlayer dielectric layer; forming a device gate structure in the opening, a top of the device gate structure being flush with a top of the first gate structure in the pseudo-device region.

[0006] Optionally, the step of forming the stacked gate structure comprises: forming a first gate material layer on top of the substrate in the device region and the dummy device region; forming a second gate material layer on top of the first gate material layer; forming a patterned hard mask layer on top of the second gate material layer; performing patterning on the second gate material layer and the first gate material layer in sequence with the hard mask layer as a mask, the remaining second gate material layer serving as the second gate structure, and the remaining first gate material layer serving as the first gate structure, the first gate structure and the second gate structure constituting the stacked gate structure; and removing the hard mask layer.

[0007] Optionally, the step of forming the first gate material layer on top of the substrate in the device region and the dummy device region comprises: forming a first gate film on top of the substrate in the device region and the dummy device region; and performing planarization on the first gate film with a partial thickness until the remaining first gate film reaches a target thickness, and taking the remaining first gate film as the first gate material layer.

[0008] Optionally, the process of performing patterning on the second gate material layer and the first gate material layer in sequence comprises a dry etching process.

[0009] Optionally, in the step of providing the substrate, a dielectric layer is formed on top of the substrate in the device region and the dummy device region, the dielectric layer being located between the first gate structure and the second gate structure; in the step of forming the stacked gate structure, the dielectric layer is used as an etching stop layer; after the step of removing the second gate structure, before the step of removing the first gate structure in the device region, the method further comprises: removing the dielectric layer.

[0010] Optionally, the material of the dielectric layer comprises one or both of silicon oxide and aluminum oxide.

[0011] Optionally, the process of removing the dielectric layer comprises a wet etching process.

[0012] Optionally, before the step of forming the interlayer dielectric layer, the method of forming the semiconductor structure further comprises: forming a sidewall layer on sidewalls of the stacked gate structure; after forming the sidewall layer, forming a source-drain doped layer in the substrate on both sides of the stacked gate structure; in the step of forming the interlayer dielectric layer, the interlayer dielectric layer also covers top of the source-drain doped layer.

[0013] Optionally, the step of forming the sidewall layer comprises: forming a sidewall material layer on top of and sidewalls of the stacked gate structure, and on top of the substrate exposed by the stacked gate structure; removing the sidewall material layer on top of the stacked gate structure and on top of the substrate, the remaining sidewall material layer on sidewalls of the stacked gate structure serving as the sidewall layer.

[0014] Optionally, the step of forming the interlayer dielectric layer comprises: forming an interlayer dielectric material layer covering the gate stack structure on the top of the substrate in the device region and the dummy device region; and planarizing the interlayer dielectric material layer above the top of the second gate structure with the top of the second gate structure as a stop position, and the remaining interlayer dielectric material layer as the interlayer dielectric layer.

[0015] Optionally, the process of removing the second gate structure comprises a wet etching process.

[0016] Optionally, after the second gate structure is removed, the step of removing the first gate structure in the device region comprises: forming a mask layer covering the first gate structure and the interlayer dielectric layer in the dummy device region, the mask layer exposing the first gate structure in the device region; removing the first gate structure in the device region with the mask layer as a mask; and removing the mask layer.

[0017] Optionally, the process of removing the first gate structure in the device region comprises a dry etching process.

[0018] Optionally, the step of forming the device gate structure in the opening comprises: forming a gate dielectric layer on the top and sidewall of the interlayer dielectric layer in the dummy device region, the top of the first gate structure, the top of the interlayer dielectric layer in the device region, and the bottom and sidewall of the opening; forming a gate electrode layer covering the gate dielectric layer on the top of the substrate in the device region and the dummy device region, the gate electrode layer also filling the remaining space in the opening; and planarizing the interlayer dielectric layer, the gate dielectric layer and the gate electrode layer above the top of the first gate structure with the top of the first gate structure as a stop position, the remaining gate dielectric layer and gate electrode layer in the opening as the device gate structure.

[0019] Optionally, the process of planarizing the interlayer dielectric layer, the gate dielectric layer and the gate electrode layer above the top of the first gate structure comprises a chemical mechanical polishing process.

[0020] Optionally, the material of the gate dielectric layer comprises one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2 and La2O3; and the material of the gate electrode layer comprises one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN and TiAlC.

[0021] Compared with the prior art, the technical scheme of the embodiment of the present application has the following advantages:

[0022] The embodiment of the present application provides a semiconductor structure forming method, a substrate includes a device area and a pseudo device area adjacent to the device area, a top of the substrate of the device area and the pseudo device area is formed with a laminated gate structure, the laminated gate structure includes a first gate structure and a second gate structure above the first gate structure, an interlayer dielectric layer covering sidewalls of the laminated gate structure is formed on the substrate of the device area and the pseudo device area, the second gate structure is removed, the first gate structure of the device area is removed, an opening surrounded by the top surface of the substrate and the sidewalls opposite to the adjacent interlayer dielectric layer is formed in the device area, correspondingly, in the process of forming a device gate structure in the opening, the top of the first gate structure in the pseudo device area can be used as a stop position, so that the top surface flatness of the device gate structure and the thickness uniformity of the device gate structure are improved, and the performance of the semiconductor structure is improved. BRIEF DESCRIPTION OF DRAWINGS

[0023] Figures 1 to 4 It is a semiconductor structure forming method corresponding structure diagram;

[0024] Figures 5 to 20 It is a semiconductor structure forming method corresponding structure diagram in the embodiment of the present application. DETAILED DESCRIPTION

[0025] At present, the performance of the semiconductor structure needs to be improved. The reason why the performance needs to be improved is analyzed in combination with a semiconductor structure forming method corresponding structure diagram.

[0026] Figures 1 to 4 It is a semiconductor structure forming method corresponding structure diagram.

[0027] REFERENCE Figure 1 A substrate 90 is provided, the substrate 90 includes a substrate 10 and a fin 12 standing on the substrate 10, a gate structure 13 is formed on the top of the substrate 10 and covers part of the top and part of the sidewall of the fin 12, a sidewall of the gate structure 13 is formed with a side wall layer 16, and an interlayer dielectric layer 15 covering the sidewall of the side wall layer 16 is formed on the exposed substrate 10 of the gate structure 13.

[0028] REFERENCE Figure 2 The gate structure 13 is removed, and a gate opening 20 is formed in the interlayer dielectric layer 15.

[0029] REFERENCE Figure 3 A device gate material layer 26 is formed in the gate opening 20 and on the top of the interlayer dielectric layer 15.

[0030] REFERENCE Figure 4The device gate material layer 26 is planarized until the height of the remaining device gate material layer 26 reaches a target height, and the remaining device gate material layer 26 is taken as the device gate layer 22.

[0031] It is found through research that, in the process of planarizing the device gate material layer 26, the device gate material layer 26 is planarized by using a chemical mechanical polishing process. Since no top of any film layer can be taken as a stop position for planarization, the top surface flatness of the device gate layer 22 is low, and accordingly, the height uniformity of the device gate layer 22 cannot be improved.

[0032] To solve the technical problem, an embodiment of the present application provides a method for forming a semiconductor structure, which comprises the following steps: providing a substrate, the substrate comprising a device region and a pseudo-device region adjacent to the device region, a top of the substrate of the device region and the pseudo-device region being formed with a stacked gate structure, the stacked gate structure comprising a first gate structure and a second gate structure above the first gate structure; forming an interlayer dielectric layer covering sidewalls of the stacked gate structure on the substrate of the device region and the pseudo-device region; removing the second gate structure; after the second gate structure is removed, removing the first gate structure of the device region, and forming an opening in the device region, the opening being surrounded by sidewalls of the adjacent interlayer dielectric layer and a top surface of the substrate; and forming a device gate structure in the opening, a top of the device gate structure being flush with a top of the first gate structure in the pseudo-device region.

[0033] An embodiment of the present application provides a method for forming a semiconductor structure, the substrate comprising a device region and a pseudo-device region adjacent to the device region, a top of the substrate of the device region and the pseudo-device region being formed with a stacked gate structure, the stacked gate structure comprising a first gate structure and a second gate structure above the first gate structure, an interlayer dielectric layer covering sidewalls of the stacked gate structure being formed on the substrate of the device region and the pseudo-device region, the second gate structure being removed, the first gate structure of the device region being removed, and an opening being formed in the device region, the opening being surrounded by sidewalls of the adjacent interlayer dielectric layer and a top surface of the substrate. Accordingly, in the process of forming the device gate structure in the opening, the top of the first gate structure in the pseudo-device region can be taken as a stop position, so that the top of the device gate structure in the device region is flush with the top of the first gate structure in the pseudo-device region, thereby improving the top surface flatness of the device gate structure and the thickness uniformity of the device gate structure, and further improving the performance of the semiconductor structure.

[0034] In order to make the above objectives, characteristics and advantages of the present application more obvious and easy to understand, specific embodiments of the present application are described in detail below with reference to the drawings.

[0035] Figures 5 to 20 is a structure diagram corresponding to each step in an embodiment of the method for forming a semiconductor structure of the present application.

[0036] Reference Figures 5 to 11 wherein, Figure 5 is a top view, Figure 6 is Figure 5 is a sectional view along AA direction, Figure 9 is a top view, Figure 10 is Figure 9 is a sectional view along BB direction, a substrate 105 is provided, the substrate 105 includes a device area 100A and a dummy device area 100B adjacent to the device area 100A, a top of the substrate 105 of the device area 100A and the dummy device area 100B is formed with a stacked gate structure 122, the stacked gate structure 122 includes a first gate structure 120 and a second gate structure 121 located above the first gate structure 120.

[0037] The substrate 105 provides a process platform for a subsequent semiconductor structure forming process.

[0038] In this embodiment, the substrate 105 includes a substrate 100 and a plurality of fin structures 102 separated on the substrate 100

[0039] In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate can also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, or other materials, and the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates.

[0040] The fin structure 102 is used to provide a channel for device operation.

[0041] In this embodiment, the material of the fin structure 102 is the same as that of the substrate 100, and the material of the fin structure 102 is silicon.

[0042] In this embodiment, the substrate 105 includes a device area 100A and a dummy device area 100B adjacent to the device area 100A.

[0043] Specifically, the device area 100A is a device operation area of the semiconductor structure, and the dummy device area 100B is a non-operation area of the semiconductor structure.

[0044] In this embodiment, the method for forming the semiconductor structure further includes: after forming the fin structure 102, forming an isolation layer 106 on the substrate 100 exposed by the fin structure 102, the isolation layer 106 covers part of the sidewall of the fin structure 102, and a top of the isolation layer 106 is lower than a top of the fin structure 102.

[0045] The isolation layer 106 is used to isolate adjacent devices. The material of the isolation layer 106 can be silicon oxide, silicon nitride or silicon oxynitride.

[0046] As an example, the material of the isolation layer 106 is silicon nitride.

[0047] It should be noted that the stack gate structure 122 provides a process basis for subsequent formation of a sidewall layer and an interlayer dielectric layer, occupies a space position in advance for subsequent formation of a device gate structure, and at the same time, the top of the first gate structure 120 in the dummy device region 100B can be used as a stop position in a process of subsequently forming a device gate structure in an opening, so that the device gate structure in the device region 100A is leveled with the top of the first gate structure 120 in the dummy device region 100B, which means that the thickness of the first gate structure 120 is controlled in the step of forming the first gate structure 120, so that the height of the subsequently formed device gate structure is controlled, thereby improving the controllability of the height of the device gate structure.

[0048] It should also be noted that the top of the second gate structure 121 can be used as a stop position for planarization processing in a process of subsequently forming an interlayer dielectric layer, so that the flatness of the top surface of the interlayer dielectric layer is improved.

[0049] In this embodiment, the stack gate structure 122 is a dummy gate structure.

[0050] In combination with Figures 5 to 11 The step of forming the stack gate structure 122 is described in detail.

[0051] Reference is made to Figures 5 to 7 The first gate material layer 107 is formed on the top of the substrate 105 in the device region 100A and the dummy device region 100B.

[0052] Specifically, the first gate material layer 107 is used as a material layer for forming the first gate structure 120, and at the same time, by forming the first gate material layer 107, the thickness of the remaining first gate material layer 107 can be controlled in the subsequent step of forming the first gate structure 120, so that the thickness of the first gate structure 120 reaches the target thickness.

[0053] In this embodiment, the step of forming the first gate material layer 107 on the top of the substrate 105 in the device region 100A and the dummy device region 100B includes: forming the first gate film 101 on the top of the substrate 105 in the device region 100A and the dummy device region 100B; and performing planarization processing on the first gate film 101 with a partial thickness until the thickness of the remaining first gate film 101 reaches a target thickness, and taking the remaining first gate film 101 as the first gate material layer 107.

[0054] The first gate film 101 is used as a material layer for forming the first gate material layer 107.

[0055] It should be noted that, since the fin part 102 has a relatively uniform distribution density, the distribution density of the fin part 102 has a relatively small influence on the planarization process during the planarization process of the first gate film 101 with a partial thickness, and accordingly, the flatness of the top surface of the first gate material layer 107 is improved. At the same time, by planarizing the first gate film 101 with a partial thickness until the thickness of the remaining first gate film 101 reaches the target thickness, it means that the thickness of the first gate structure 120 is controlled by controlling the thickness of the first gate material layer 107, which is beneficial to controlling the height of the device gate structure formed subsequently by the first gate structure 120, thereby improving the controllability of the height of the device gate structure.

[0056] In this embodiment, the process of forming the first gate film 101 includes one or both of a chemical vapor deposition process and an atomic layer deposition process.

[0057] As an example, the material of the first gate material layer 107 includes polysilicon.

[0058] Referring to Figure 8 The second gate material layer 110 is formed on the top of the first gate material layer 107.

[0059] Specifically, the second gate material layer 110 is used as a material layer for forming the second gate structure 121, and at the same time, by forming the second gate material layer 110, the top of the second gate structure 121 can be used as a stop position for planarization during the subsequent formation of the interlayer dielectric layer, so that the flatness of the top surface of the interlayer dielectric layer is improved.

[0060] It should be noted that, during the formation of the interlayer dielectric layer, the top of the second gate structure 121 can be used as a stop position for planarization, and compared with the scheme of using the top of the single-layer gate structure as a stop position for planarization, the top of the second gate structure 121 only performs a stop position during the planarization process, so that the flatness of the top surface of the interlayer dielectric layer is higher.

[0061] In this embodiment, the process of forming the second gate material layer 110 includes one or both of a chemical vapor deposition process and an atomic layer deposition process.

[0062] As an example, the material of the second gate material layer 110 includes polysilicon.

[0063] Referring to Figures 9 to 10 The patterned hard mask layer 113 is formed on the top of the second gate material layer 110.

[0064] It should be noted that the hard mask layer 113 is used as an etching mask for subsequently forming the first gate structure 120 and the second gate structure 121.

[0065] In this embodiment, the material of the hard mask layer 113 includes one or more of silicon oxide, silicon nitride and silicon oxynitride.

[0066] Referring to Figure 11 The second gate material layer 110 and the first gate material layer 107 are sequentially patterned with the hard mask layer 113 as a mask, the remaining second gate material layer 110 serves as a second gate structure 121, and the remaining first gate material layer 107 serves as a first gate structure 120. The first gate structure 120 and the second gate structure 121 constitute a laminated gate structure 122.

[0067] It should be noted that by sequentially patterning the second gate material layer 110 and the first gate material layer 107, the side wall morphology of the first gate structure 120 and the second gate structure 121 can be controlled, and at the same time, the probability of over-etching in the process of forming the first gate structure 120 and the second gate structure 121 is reduced, and the probability of damage to the fin 102 and the substrate 105 is reduced.

[0068] It should be further noted that in the subsequent process of forming a device gate structure in the opening, the top of the first gate structure 120 in the dummy device region 100B can serve as a stop position, so that the device gate structure in the device region 100A is flush with the top of the first gate structure 120 in the dummy device region 100B, thereby improving the flatness of the top surface of the device gate structure and the thickness uniformity of the device gate structure, and further improving the performance of the semiconductor structure.

[0069] As an example, the process of sequentially patterning the second gate material layer 110 and the first gate material layer 107 includes a dry etching process.

[0070] Specifically, the dry etching process is an anisotropic dry etching process, which has the characteristics of anisotropic etching, and the longitudinal etching rate is much greater than the lateral etching rate. By using the dry etching process to pattern the second gate material layer 110 and the first gate material layer 107, it is beneficial to improve the side wall morphology quality of the first gate structure 120 and the second gate structure 121, and to reduce the process difficulty of subsequently depositing a side wall layer on the side wall of the laminated gate structure 122.

[0071] It should be noted that after the laminated gate structure 122 is formed, before the subsequent formation of the side wall layer, the method for forming the semiconductor structure further includes: removing the hard mask layer 113.

[0072] The removal of the hard mask layer 113 provides a process basis for the subsequent formation of the side wall layer and the interlayer dielectric layer.

[0073] In this embodiment, the process of removing the hard mask layer 113 includes a wet etching process.

[0074] As an example, in the step of providing the substrate 105, the top of the substrate 105 of the device region 100A and the dummy device region 100B is formed with a dielectric layer 111, which is located between the first gate structure 120 and the second gate structure 121.

[0075] Specifically, the dielectric layer 111 is used to isolate the first gate structure 120 and the second gate structure 121, and in the step of forming the stacked gate structure 122, after the first gate material layer 107 is formed, the dielectric layer 111 is formed on the top of the first gate material layer 107, and the second gate material layer 110 is formed on the top of the dielectric layer 111. Accordingly, in the process of sequentially patterning the second gate material layer 110 and the first gate material layer 107, the dielectric layer 111 on the top of the first gate material layer 107 is used as an etching stop layer, which reduces the probability of over-etching of the first gate material layer 107 and makes the thickness uniformity of the second gate structure 121.

[0076] As an example, in the step of forming the stacked gate structure 122, the dielectric layer 111 is used as an etching stop layer to reduce the probability of over-etching of the first gate material layer 107.

[0077] It should be noted that in the process of sequentially patterning the second gate material layer 110 and the first gate material layer 107, the dielectric layer 111 exposed on both sides of the second gate structure 121 is also patterned, so as to expose the top surface of the first gate material layer 107, which facilitates the patterning of the first gate material layer 107 to form the first gate structure 120.

[0078] In this embodiment, the material of the dielectric layer 111 includes one or both of silicon oxide and aluminum oxide.

[0079] Both silicon oxide and aluminum oxide are commonly used materials for the dielectric layer 111, which have the characteristics of low process cost. At the same time, silicon oxide and aluminum oxide have a high etching selectivity with the materials selected for the second gate structure 121 and the first gate structure 120, which reduces the process difficulty of forming the stacked gate structure 122.

[0080] Reference Figure 12 Before the subsequent formation of the interlayer dielectric layer, the method for forming the semiconductor structure further includes: forming a sidewall layer 126 on the sidewall of the stacked gate structure 122; after the formation of the sidewall layer 126, forming a source-drain doped layer 190 in the substrate 105 on both sides of the stacked gate structure 122.

[0081] The sidewall layer 126 is used to protect the sidewall of the stack gate structure 122, and is also used to define the forming position of the source / drain doping layer 190.

[0082] The sidewall layer 126 can be a single layer structure or a stack structure, and the material of the sidewall layer 126 can be one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbon nitride, silicon carbon nitrogen oxide, silicon nitrogen oxide, boron nitride and boron carbon nitride.

[0083] In this embodiment, the sidewall layer 126 is a single layer structure, and the material of the sidewall layer 126 is silicon nitride.

[0084] In this embodiment, the step of forming the sidewall layer 126 includes: forming a sidewall material layer on the top and sidewall of the stack gate structure 122, and on the top of the substrate 105 exposed by the stack gate structure 122; removing the sidewall material layer on the top of the stack gate structure 122, and on the top of the substrate 105, and the remaining sidewall material layer on the sidewall of the stack gate structure 122 serves as the sidewall layer 126.

[0085] As an example, the process of forming the sidewall material layer includes an atomic layer deposition process.

[0086] The source / drain doping region is used as a source region or a drain region of a transistor.

[0087] In this embodiment, the source / drain doping layer 190 is formed by an in-situ self-doping process.

[0088] When forming an NMOS transistor, the source / drain doping layer 190 includes a stress layer doped with N-type ions, i.e., the first type of ions is N-type ions.

[0089] Specifically, the material of the stress layer is Si or SiC, the stress layer provides a tensile stress effect for the channel region of the NMOS transistor, thereby facilitating the improvement of the carrier mobility of the NMOS transistor, and the N-type ions are P ions, As ions or Sb ions.

[0090] When forming a PMOS transistor, the source / drain doping layer 190 includes a stress layer doped with P-type ions, i.e., the second type of ions is P-type ions.

[0091] The material of the stress layer is Si or SiGe, the stress layer provides a compressive stress effect for the channel region of the PMOS transistor, thereby facilitating the improvement of the carrier mobility of the PMOS transistor, and the P-type ions are B ions, Ga ions or In ions.

[0092] Reference Figures 13 to 14 An interlayer dielectric layer 129 covering the sidewall of the stack gate structure 122 is formed on the substrate 105 of the device region 100A and the dummy device region 100B.

[0093] The interlayer dielectric layer 129 is used for electrically isolating adjacent devices.

[0094] The material of the interlayer dielectric layer 129 is an insulating material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride. In this embodiment, the material of the interlayer dielectric layer 129 is silicon oxide.

[0095] In this embodiment, the step of forming the interlayer dielectric layer 129 includes: forming an interlayer dielectric material layer 128 on the top of the base 105 of the device region 100A and the dummy device region 100B, covering the stacked gate structure 122; and planarizing the interlayer dielectric material layer 128 above the top of the second gate structure 121 as a stop position, and leaving the remaining interlayer dielectric material layer 128 as the interlayer dielectric layer 129.

[0096] Specifically, the interlayer dielectric layer 129 is formed by using a deposition process and a planarization process (for example, a chemical mechanical polishing process) in sequence.

[0097] It should be noted that, since the interlayer dielectric material layer 128 above the top of the second gate structure 121 is planarized, the top of the interlayer dielectric layer 129 is flush with the top of the stacked gate structure 122.

[0098] As an example, in the step of forming the interlayer dielectric layer 129, the interlayer dielectric layer 129 also covers the top of the source-drain doped layer 190.

[0099] Specifically, the interlayer dielectric layer 129 covers the top of the source-drain doped layer 190, which can reduce the probability of damage to the source-drain doped layer 190 caused by the process of removing the second gate structure 121, thereby improving the electrical connection performance between the source-drain doped layer 190 and the subsequently formed interconnection structure (for example, a source-drain plug).

[0100] Reference Figure 15 The second gate structure 121 is removed.

[0101] Specifically, the second gate structure 121 is removed to provide a spatial position for subsequently forming a device gate structure.

[0102] In this embodiment, the process of removing the second gate structure 121 includes a wet etching process.

[0103] Specifically, the wet etching process is an isotropic etching process, in which the lateral etching rate is close to the vertical etching rate. By using the wet etching process to remove the second gate structure 121, the second gate structure 121 can be completely removed.

[0104] As an example, the etching solution used in the wet etching process is TMAH (tetramethylammonium hydroxide).

[0105] It should be noted that, in the process of removing the second gate structure 121, the dielectric layer 111 on the top of the first gate structure 120 protects the first gate structure 120, reducing the probability of damage to the first gate structure 120 caused by the process of removing the second gate structure 121.

[0106] Reference Figure 16 After the step of removing the second gate structure 121, before the subsequent removal of the first gate structure 120 of the device region 100A, further comprising: removing the dielectric layer 111.

[0107] It should be noted that, by removing the dielectric layer 111, the first gate structure 120 is exposed, which is beneficial for providing a spatial position for forming a device gate structure after the subsequent removal of the first gate structure 120.

[0108] In this embodiment, the process of removing the dielectric layer 111 includes a wet etching process.

[0109] Specifically, the wet etching process is an isotropic etching process, in which the lateral etching rate is close to the longitudinal etching rate. By using a wet etching process to remove the dielectric layer 111, the dielectric layer 111 can be completely removed.

[0110] As an example, the etching solution used in the wet etching process is NH4OH (ammonium hydroxide) solution.

[0111] Reference Figures 17 to 18 After removing the second gate structure 121, the first gate structure 120 of the device region 100A is removed, and an opening 180 is formed in the device region 100A. The opening 180 is surrounded by the top surface of the substrate 105 and the side walls of the adjacent interlayer dielectric layer 129.

[0112] Specifically, the opening 180 provides a spatial position for the subsequent formation of a device gate structure.

[0113] In this embodiment, the step of removing the first gate structure 120 of the device region 100A includes: forming a mask layer 132 covering the first gate structure 120 and the interlayer dielectric layer 129 in the pseudo device region 100B, the mask layer 132 exposing the first gate structure 120 of the device region 100A; removing the first gate structure 120 of the device region 100A with the mask layer 132 as a mask; and removing the mask layer 132.

[0114] Specifically, the mask layer 132 is used to shield the first gate structure 120 in the dummy device region 100B which is not desired to be removed by etching, and is also used as an etching mask for removing the first gate structure 120 in the device region 100A.

[0115] In this embodiment, the mask layer 132 includes an organic material layer (not shown in the figure), an anti-reflective coating layer (not shown in the figure) on the organic material layer, and a photoresist layer (not shown in the figure) on the anti-reflective coating layer.

[0116] The material of the organic material layer includes an organic material. In this embodiment, the material of the organic material layer is spin-on carbon (SOC).

[0117] In other embodiments, the material of the organic material layer can also be other organic materials, such as one or more of ODL (organic dielectric layer) material, DUO (Deep UV Light Absorbing Oxide) material, and APF (Advanced Patterning Film) material.

[0118] The material of the anti-reflective coating layer includes BARC (bottom anti-reflective coating) material. As an example, the BARC material is Si-ARC (silicon-containing anti-reflective coating) material.

[0119] In this embodiment, the process of removing the first gate structure 120 in the device region 100A includes a dry etching process.

[0120] Specifically, the dry etching process is an anisotropic dry etching process, which has the characteristic of anisotropic etching, that is, the longitudinal etching rate is much greater than the lateral etching rate. By using the dry etching process to remove the first gate structure 120 in the device region 100A, the probability of residual first gate structure 120 on the top of the substrate 105 is reduced, and the performance of the semiconductor structure is improved after the subsequent formation of the device gate structure.

[0121] It should be noted that after removing the first gate structure 120 in the device region 100A, the method for forming the semiconductor structure further includes removing the mask layer 132.

[0122] Removing the mask layer 132 provides a spatial position for the subsequent formation of the device gate structure.

[0123] Reference Figures 19 to 20The device gate structure 160 is formed in the opening 180, and the top of the device gate structure 160 is flush with the top of the first gate structure 120 in the dummy device region 100B.

[0124] Specifically, the device gate structure 160 is used to control the turn-on and turn-off of the channel in the device region 100A.

[0125] In this embodiment, the step of forming the device gate structure 160 in the opening 180 includes: forming a gate dielectric layer (not shown in the figure) on the top and sidewall of the interlayer dielectric layer 129 of the dummy device region 100B, the top of the first gate structure 120, the top of the interlayer dielectric layer 129 of the device region 100A, and the bottom and sidewall of the opening 180; continuing to form a gate electrode layer (not shown in the figure) covering the gate dielectric layer on the top of the substrate 105 of the device region 100A and the dummy device region 100B, the gate electrode layer also filling the remaining space in the opening 180; and planarizing the interlayer dielectric layer 129, the gate dielectric layer and the gate electrode layer higher than the top of the first gate structure 120 with the top of the first gate structure 120 as the stop position, so that the remaining gate dielectric layer and the gate electrode layer in the opening 180 become the device gate structure 160. Figure 19 Figure 19 Figure 20

[0126] Specifically, the top of the first gate structure 120 in the dummy device region 100B can be used as the stop position, so that the device gate structure 160 in the device region 100A is flush with the top of the first gate structure 120 in the dummy device region 100B, thereby improving the flatness of the top surface of the device gate structure 160 and the thickness uniformity of the device gate structure 160, and further improving the performance of the semiconductor structure.

[0127] In this embodiment, the process of planarizing the interlayer dielectric layer 129, the gate dielectric layer and the gate electrode layer higher than the top of the first gate structure 120 includes a chemical mechanical polishing process.

[0128] In this embodiment, the material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2 and La2O3.

[0129] Specifically, the gate dielectric layer includes a gate oxide layer conformally covering part of the top, part of the sidewall and part of the bottom of the fin 102, and a high-k gate dielectric layer conformally covering the gate oxide layer. The material of the high-k gate dielectric layer is a high-k dielectric material, which refers to a dielectric material with a relative dielectric constant greater than that of silicon oxide.

[0130] ​​​The gate electrode layer is used to electrically connect with an external structure. In this embodiment, the material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN and TiAlC. Specifically, the gate electrode layer can include a work function layer and an electrode layer covering the work function layer, or the gate electrode layer can also only include a work function layer.

[0131] Although the present application has been disclosed with reference to the above embodiments, the present application is not limited to the above embodiments. Any person skilled in the art can make various modifications and changes without departing from the spirit and scope of the present application. The scope of protection of the present application should be limited by the scope of the claims.

Claims

1. A method of forming a semiconductor structure, characterized by, The method comprises the following steps: providing a substrate, the substrate comprising a device region and a dummy device region adjacent to the device region, a top of the substrate of the device region and the dummy device region being formed with a stacked gate structure, the stacked gate structure comprising a first gate structure and a second gate structure above the first gate structure; forming an interlayer dielectric layer on the substrate of the device region and the dummy device region, the interlayer dielectric layer covering sidewalls of the stacked gate structure; removing the second gate structure; after removing the second gate structure, removing the first gate structure of the device region, forming an opening in the device region, the opening being surrounded by sidewalls opposite to the interlayer dielectric layer and a top surface of the substrate; forming a device gate structure in the opening, a top of the device gate structure being flush with a top of the first gate structure in the dummy device region.

2. The method of forming a semiconductor structure of claim 1, wherein, The step of forming the stacked gate structure comprises: forming a first gate material layer on a top of the substrate of the device region and the dummy device region; forming a second gate material layer on a top of the first gate material layer; forming a patterned hard mask layer on a top of the second gate material layer; sequentially performing patterning treatment on the second gate material layer and the first gate material layer with the hard mask layer as a mask, the remaining second gate material layer serving as the second gate structure, and the remaining first gate material layer serving as the first gate structure, the first gate structure and the second gate structure constituting the stacked gate structure; and removing the hard mask layer.

3. The method of forming a semiconductor structure of claim 2, wherein, The step of forming the first gate material layer on the top of the substrate of the device region and the dummy device region comprises: forming a first gate film on the top of the substrate of the device region and the dummy device region; and performing planarization treatment on part of the thickness of the first gate film until the thickness of the remaining first gate film reaches a target thickness, and taking the remaining first gate film as the first gate material layer.

4. The method of forming a semiconductor structure of claim 2, wherein, The process of sequentially performing patterning treatment on the second gate material layer and the first gate material layer comprises a dry etching process.

5. The method of forming a semiconductor structure of claim 1, wherein, In the step of providing the substrate, a dielectric layer is formed on the top of the substrate of the device region and the dummy device region, the dielectric layer being between the first gate structure and the second gate structure; In the step of forming the stacked gate structure, the dielectric layer is used as an etching stop layer; After the step of removing the second gate structure, before the step of removing the first gate structure of the device region, the method further comprises: removing the dielectric layer.

6. The method of forming a semiconductor structure of claim 5, wherein, The material of the dielectric layer comprises one or both of silicon oxide and aluminum oxide.

7. The method of forming a semiconductor structure of claim 5, wherein, The process of removing the dielectric layer comprises a wet etching process.

8. The method of forming a semiconductor structure of claim 1, wherein, Before forming the interlayer dielectric layer, the method of forming the semiconductor structure further comprises: forming a sidewall layer on sidewalls of the stacked gate structure; and after forming the sidewall layer, forming a source-drain doped layer in the substrate on both sides of the stacked gate structure. In the step of forming the interlayer dielectric layer, the interlayer dielectric layer also covers a top of the source-drain doped layer.

9. The method of forming a semiconductor structure of claim 8, wherein, The step of forming the side wall layer comprises: forming a side wall material layer on the top and sidewall of the stack gate structure and the top of the substrate exposed by the stack gate structure; removing the side wall material layer on the top of the stack gate structure and the top of the substrate, and the side wall material layer remaining on the sidewall of the stack gate structure as the side wall layer.

10. The method of forming a semiconductor structure of claim 1, wherein, The step of forming the interlayer dielectric layer comprises: forming an interlayer dielectric material layer covering the stack gate structure on the top of the substrate of the device region and the dummy device region; and planarizing the interlayer dielectric material layer higher than the top of the second gate structure to leave the interlayer dielectric material layer remaining as the interlayer dielectric layer.

11. The method of forming a semiconductor structure of claim 1, wherein, The process of removing the second gate structure comprises a wet etching process.

12. The method of forming a semiconductor structure of claim 1, wherein, After removing the second gate structure, the step of removing the first gate structure of the device region comprises: forming a mask layer covering the first gate structure and the interlayer dielectric layer in the dummy device region, the mask layer exposing the first gate structure of the device region; removing the first gate structure of the device region with the mask layer as a mask; and removing the mask layer.

13. The method of forming a semiconductor structure of claim 1 or 12, wherein, The process of removing the first gate structure of the device region comprises a dry etching process.

14. The method of forming a semiconductor structure of claim 1, wherein, The step of forming the device gate structure in the opening comprises: forming a gate dielectric layer on the top and sidewall of the interlayer dielectric layer of the dummy device region, the top of the first gate structure, the top of the interlayer dielectric layer of the device region, and the bottom and sidewall of the opening; forming a gate electrode layer covering the gate dielectric layer on the top of the substrate of the device region and the dummy device region, the gate electrode layer also filling the remaining space in the opening; and planarizing the interlayer dielectric layer, the gate dielectric layer and the gate electrode layer higher than the top of the first gate structure to leave the gate dielectric layer and the gate electrode layer remaining in the opening as the device gate structure.

15. The method of forming a semiconductor structure of claim 14, wherein, The process of planarizing the interlayer dielectric layer, the gate dielectric layer and the gate electrode layer higher than the top of the first gate structure comprises a chemical mechanical polishing process.

16. The method of forming a semiconductor structure of claim 14, wherein, The material of the gate dielectric layer comprises one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2 and La2O3. The material of the gate electrode layer comprises one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN and TiAlC.

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