Semiconductor device and method of manufacturing semiconductor device

Abstract

The present disclosure provides a semiconductor device and a method of manufacturing a semiconductor device, the method including: forming a stack pattern including active layers and a sacrificial layer stacked on a substrate, in which the active layers include two active layers vertically adjacent to each other, and the sacrificial layer is interposed between the two active layers; forming a recess by etching the stack pattern; forming an indentation by etching a portion of the sacrificial layer exposed by the recess; forming a silicon layer on the inner surface of the recess; forming an inner spacer in the indentation; forming an inner region by removing the sacrificial layer; and forming a gate insulating layer in the inner region, in which forming the gate insulating layer includes forming an oxide layer by performing an oxidation process on the silicon layer exposed through the inner region.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method of manufacturing a semiconductor device, and more particularly, to a semiconductor device including a field effect transistor and a method of manufacturing such a semiconductor device. Background Art

[0002] Semiconductor devices may include integrated circuits having metal oxide semiconductor field effect transistors (MOSFETs). As the size and design rules of semiconductor devices have been continuously reduced, the size of MOSFETs has also been continuously reduced. The operating characteristics of semiconductor devices may deteriorate due to the reduction in the size of MOSFETs. Therefore, various studies are being conducted on semiconductor devices that can overcome the limitations caused by high integration density and improve performance. Summary of the Invention

[0003] The present disclosure provides a semiconductor device with improved reliability and electrical characteristics. The present disclosure provides a method of manufacturing a semiconductor device with improved reliability and electrical characteristics.

[0004] According to one aspect of the present disclosure, a method of manufacturing a semiconductor device includes: forming a stacked pattern including an active layer and a sacrificial layer stacked on a substrate, wherein the active layer includes two active layers vertically adjacent to each other, and the sacrificial layer is interposed between the two active layers; forming a recess by etching the stacked pattern; forming an indentation by etching a part of the sacrificial layer exposed through the recess; forming a silicon layer on an inner surface of the recess; forming an inner spacer in the indentation; forming an inner region by removing the sacrificial layer; and forming a gate insulating layer in the inner region, wherein forming the gate insulating layer includes forming an oxide layer by performing an oxidation process on the silicon layer exposed through the inner region.

[0005] According to one aspect of the present disclosure, a method of manufacturing a semiconductor device includes: forming a stacked pattern including a semiconductor pattern and a sacrificial layer stacked on a substrate; forming a recess by etching the stacked pattern; forming an indentation by etching a part of the sacrificial layer exposed through the recess; forming a silicon layer on an inner surface of the recess, the silicon layer including a first part on the semiconductor pattern and a second part on the sacrificial layer; forming an inner spacer in the indentation; and forming a source / drain pattern in the recess, wherein the semiconductor pattern includes a main body part and a protrusion protruding from the main body part toward the source / drain pattern, and wherein a highest horizontal height of the main body part is equal to a highest horizontal height of the first part covering the protrusion.

[0006] According to one aspect of the present disclosure, a semiconductor device includes: a substrate including an active pattern; a first semiconductor pattern and a second semiconductor pattern stacked on the active pattern and spaced apart from each other perpendicularly; a source / drain pattern connected to the first semiconductor pattern and the second semiconductor pattern; a silicon layer positioned between the first semiconductor pattern and the source / drain pattern; a gate electrode positioned between the first semiconductor pattern and the second semiconductor pattern; a gate insulating layer positioned between the gate electrode and the source / drain pattern; a high-k dielectric layer surrounding the gate electrode and including a high-k dielectric material having a dielectric constant higher than that of a silicon oxide layer; and an inner spacer positioned between the gate insulating layer and the source / drain pattern, wherein the first semiconductor pattern includes a main body portion and a protrusion protruding from the main body portion toward the source / drain pattern, and wherein a first highest horizontal height of the main body portion is equal to a second highest horizontal height of the silicon layer covering the protrusion. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The above and other aspects, features, and advantages of certain embodiments of the present disclosure will be more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0008] Figures 1 to 3 is a diagram for illustrating a logic unit of a semiconductor device according to some embodiments of the present disclosure;

[0009] Figure 4 is a top view for illustrating a semiconductor device according to some embodiments of the present disclosure;

[0010] Figures 5A to 5D are cross-sectional views taken along lines A-A', B-B', C-C', and D-D' of Figure 4 respectively;

[0011] Figure 6 is an enlarged view illustrating an example of a region “M” of Figure 5A ;

[0012] Figures 7A to 12D is a cross-sectional view for illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure; and

[0013] Figures 13 to 17 is a diagram illustrating a method of manufacturing a semiconductor device according to Figure 6 and is an enlarged view for illustrating a method of forming a region “M” of Figure 5A ; DETAILED DESCRIPTION

[0014] In the following, in order to describe the present disclosure in detail, embodiments according to the present disclosure will be described with reference to the accompanying drawings.

[0015] The terms “comprising” and “including” and their derivatives mean including but not limiting. The term “or” is an inclusive term meaning “and / or”. The phrase “at least one of...” when used in conjunction with a list of items means that different combinations of one or more of the listed items can be used and only one item in the list may be required. For example, “at least one of A, B, and C” includes any of the following combinations: A; B; C; A and B; A and C; B and C; and A, B, and C; and any variations thereof. As an additional example, the expression “at least one of a, b, or c” may indicate: only a; only b; only c; both a and b; both a and c; both b and c; or all of a, b, and c; or variations thereof. Similarly, the term “set” means one or more. Thus, a set of items can be a single item or a collection of two or more items.

[0016] The description merely illustrates the principles of the present disclosure. Those skilled in the art will be able to design one or more arrangements that, although not explicitly described herein, embody the principles of the present disclosure. In addition, all examples recited herein are primarily and explicitly intended for illustrative purposes only to assist the reader in understanding the principles of the present disclosure and the concepts of the inventors for contributing to the art, and are to be construed as not limited to such specifically recited examples and conditions. Furthermore, all statements herein reciting the principles, aspects, and embodiments of the present disclosure and their specific examples are intended to encompass their equivalents.

[0017] The terms used in the present disclosure are only for describing specific embodiments and are not intended to limit the scope of another embodiment. Singular expressions may include plural expressions unless clearly having a different meaning in the context. The terms used herein (including technical or scientific terms) may have the same meaning as commonly understood by those of ordinary skill in the technical field described in the present disclosure. Terms defined in a general dictionary among the terms used in the present disclosure may be interpreted with a meaning identical or similar to the context meaning of the related art, and unless explicitly defined in the present disclosure, it is not interpreted in an ideal or overly formal meaning. In some cases, even the terms defined in the present disclosure cannot be interpreted as excluding embodiments of the present disclosure.

[0018] In one or more embodiments of the present disclosure described below, hardware methods are described as examples. However, since one or more embodiments of the present disclosure include technologies using both hardware and software, various embodiments of the present disclosure do not exclude software-based methods.

[0019] In addition, in the present disclosure, to determine whether a specific condition is satisfied or fulfilled, expressions such as greater than or less than may be used, but this is merely a description for illustrative purposes and does not exclude descriptions of greater than or equal to or less than or equal to. A condition described as "greater than or equal to" may be replaced with "greater than", a condition described as "less than or equal to" may be replaced with "less than", and a condition described as "greater than or equal to and less than" may be replaced with "greater than and less than or equal to".

[0020] Figures 1 to 3 is a diagram for illustrating a logic unit of a semiconductor device according to some embodiments of the present disclosure.

[0021] Figure 1 Illustrates a single-height cell SHC. In an embodiment, a first power wiring M1_R1 and a second power wiring M1_R2 may be disposed on a substrate 100. The first power wiring M1_R1 may be a path through which a source voltage VSS (e.g., a ground voltage) is provided. The second power wiring M1_R2 may be a channel through which a drain voltage VDD (e.g., a power supply voltage) is provided.

[0022] The single-height cell SHC may be defined between the first power wiring M1_R1 and the second power wiring M1_R2. The single-height cell SHC may include a first active region AR1 and a second active region AR2. One of the first active region AR1 and the second active region AR2 may be a p-type metal oxide semiconductor field effect transistor (PMOSFET) region, and the other of the first active region AR1 and the second active region AR2 may be an n-type MOSFET (NMOSFET) region. That is, the single-height cell SHC may have a complementary metal oxide semiconductor (CMOS) structure disposed between the first power wiring M1_R1 and the second power wiring M1_R2. For example, the first active region AR1 may be an NMOSFET region, and the second active region AR2 may be a PMOSFET region.

[0023] Each of the first active region AR1 and the second active region AR2 may have a first width W_SHC in a first direction D1. The length of the single-height cell SHC in the first direction D1 may be defined as a first height HE1. The first height HE1 may be substantially equal to the distance (e.g., pitch) between the first power wiring M1_R1 and the second power wiring M1_R2.

[0024] A single-height cell SHC can form a logic cell. In this specification, a logic cell may refer to a logic element that performs a specific function (e.g., AND, OR, XOR, XNOR, inverter, etc.). That is to say, a logic cell may include transistors that make up a logic device and wirings that connect the transistors to each other.

[0025] Reference Figure 2 , a double-height cell DHC can be provided. In an embodiment, a first power wiring M1_R1, a second power wiring M1_R2, and a third power wiring M1_R3 may be disposed on a substrate 100. The first power wiring M1_R1 may be disposed between the second power wiring M1_R2 and the third power wiring M1_R3. The third power wiring M1_R3 may be a path through which a source voltage VSS is provided.

[0026] A double-height cell DHC can be defined between the second power wiring M1_R2 and the third power wiring M1_R3. In an embodiment, as Figure 2 shown, the double-height cell DHC may include two first active regions AR1 (above M1_R1), AR1 (below M1_R1), and two second active regions AR2 (above M1_R2), AR2 (below M1_R3).

[0027] One of the two second active regions AR2 may be adjacent to the second power wiring M1_R2. The other of the two second active regions AR2 may be adjacent to the third power wiring M1_R3. The two first active regions AR1 may be adjacent to the first power wiring M1_R1. When observed in a top view, the first power wiring M1_R1 may be disposed between the two first active regions AR1.

[0028] The length of the double-height cell DHC in a first direction D1 may be defined as a second height HE2. The second height HE2 may be Figure 1 approximately twice the first height HE1 in

[0029] In the present disclosure, Figure 2 the double-height cell DHC shown can be defined as a multi-height cell. In an embodiment, a multi-height cell may include a triple-height cell whose cell height is approximately three times the height of a single-height cell SHC.

[0030] Reference Figure 3, the first single-height cell SHC1, the second single-height cell SHC2, and the double-height cell DHC can be two-dimensionally arranged on the substrate 100. The first single-height cell SHC1 can be arranged between the first power wiring M1_R1 and the second power wiring M1_R2. The second single-height cell SHC2 can be arranged between the first power wiring M1_R1 and the third power wiring M1_R3. The second single-height cell SHC2 can be adjacent to the first single-height cell SHC1 in the first direction D1.

[0031] The double-height cell DHC can be arranged between the second power wiring M1_R2 and the third power wiring M1_R3. The double-height cell DHC can be adjacent to the first single-height cell SHC1 and the second single-height cell SHC2 in the second direction D2.

[0032] The separation structure DB can be arranged between the first single-height cell SHC1 and the double-height cell DHC and between the second single-height cell SHC2 and the double-height cell DHC. Through the separation structure DB, the active region of the double-height cell DHC can be electrically separated from the active region of each of the first single-height cell SHC1 and the second single-height cell SHC2.

[0033] Figure 4 is a top view for illustrating a semiconductor device according to some embodiments of the present disclosure. Figures 5A to 5D are respectively cross-sectional views taken along Figure 4 the lines A-A', B-B', C-C', and D-D'. Figure 4 and Figures 5A to 5D The semiconductor device shown is an example representing Figure 1 the single-height cell SHC.

[0034] Refer to Figure 4 and Figures 5A to 5D , the single-height cell SHC can be arranged on the substrate 100. Logic transistors constituting a logic circuit can be arranged on the single-height cell SHC. The substrate 100 can be a semiconductor substrate including silicon, germanium, silicon-germanium, etc. or a compound semiconductor substrate. For example, the substrate 100 can be a silicon substrate.

[0035] The substrate 100 can include a first active region AR1 and a second active region AR2. Each of the first active region AR1 and the second active region AR2 can extend in the second direction D2. In an embodiment, the first active region AR1 can be an NMOSFET region, while the second active region AR2 can be a PMOSFET region.

[0036] The first active pattern AP1 and the second active pattern AP2 may be defined by a trench TR formed in a substrate 100. The first active pattern AP1 may be disposed on a first active region AR1, and the second active pattern AP2 may be disposed on a second active region AR2. The first active pattern AP1 and the second active pattern AP2 may extend in a second direction D2. The first active pattern AP1 and the second active pattern AP2 may be part of the substrate 100 and may be portions protruding vertically.

[0037] A device isolation layer ST may be disposed on the substrate 100. The device isolation layer ST may fill the trench TR. The device isolation layer ST may include a silicon oxide layer. The device isolation layer ST may not cover a first channel pattern CH1 and a second channel pattern CH2 that will be described later.

[0038] The first channel pattern CH1 may be disposed on the first active pattern AP1. The second channel pattern CH2 may be disposed on the second active pattern AP2. Each of the first channel pattern CH1 and the second channel pattern CH2 may include a first semiconductor pattern SP1, a second semiconductor pattern SP2, and a third semiconductor pattern SP3 stacked in sequence. The first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 may be spaced apart from each other in a vertical direction (i.e., a third direction D3).

[0039] Each of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 may include silicon germanium (SiGe). For example, each of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 may include crystalline silicon. According to an embodiment, each of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 may be stacked as nanosheets.

[0040] A plurality of first source / drain patterns SD1 may be disposed on the first active pattern AP1. A plurality of first recesses RS1 may be formed in the first active pattern AP1. The first source / drain patterns SD1 may be respectively disposed in the first recesses RS1. The first source / drain patterns SD1 may be impurity regions of a first conductivity type (e.g., n-type). The first channel pattern CH1 may be interposed between a pair of first source / drain patterns SD1. That is, the stacked first semiconductor pattern SP1, second semiconductor pattern SP2, and third semiconductor pattern SP3 may connect the pair of first source / drain patterns SD1 to each other.

[0041] A plurality of second source / drain patterns SD2 may be disposed on a second active pattern AP2. A plurality of second recesses RS2 may be formed on the second active pattern AP2. The second source / drain patterns SD2 may be respectively disposed in the second recesses RS2. The second source / drain patterns SD2 may be impurity regions of a second conductivity type (e.g., p-type). A second channel pattern CH2 may be interposed between pairs of the second source / drain patterns SD2. That is, the stacked first semiconductor pattern SP1, second semiconductor pattern SP2, and third semiconductor pattern SP3 may connect the pairs of second source / drain patterns SD2 to each other.

[0042] The first source / drain pattern SD1 and the second source / drain pattern SD2 may be epitaxial patterns formed by a selective epitaxial growth (SEG) process. For example, the top surface of each of the first source / drain pattern SD1 and the second source / drain pattern SD2 may be higher than the top surface of the third semiconductor pattern SP3. As another example, the top surface of at least one of the first source / drain pattern SD1 and the second source / drain pattern SD2 may be positioned at substantially the same level as the top surface of the third semiconductor pattern SP3.

[0043] In an embodiment, the first source / drain pattern SD1 may include the same semiconductor element (e.g., Si) as the substrate 100. The second source / drain pattern SD2 may include a semiconductor element (e.g., SiGe) having a lattice constant larger than the lattice constant of the semiconductor element of the substrate 100. Thus, the pairs of second source / drain patterns SD2 may provide compressive stress to the second channel pattern CH2 therebetween.

[0044] The sidewall of each of the first source / drain pattern SD1 and the second source / drain pattern SD2 may have a rough embossing form. That is, the sidewall of each of the first source / drain pattern SD1 and the second source / drain pattern SD2 may have a wavy profile. The sidewall of each of the first source / drain pattern SD1 and the second source / drain pattern SD2 may protrude toward a first inner gate electrode IGE1, a second inner gate electrode IGE2, and a third inner gate electrode IGE3 of a gate electrode GE to be described later.

[0045] The gate electrode GE may be disposed on the first channel pattern CH1 and the second channel pattern CH2. Each gate electrode GE may cross the first channel pattern CH1 and the second channel pattern CH2 and may extend in a first direction D1. Each gate electrode GE may overlap the first channel pattern CH1 and the second channel pattern CH2 perpendicularly. The gate electrodes GE may be arranged at a first pitch along a second direction D2.

[0046] The gate electrode GE may include a first inner gate electrode IGE1 between the active pattern AP1 or AP2 and the first semiconductor pattern SP1, a second inner gate electrode IGE2 between the first semiconductor pattern SP1 and the second semiconductor pattern SP2, a third inner gate electrode IGE3 between the second semiconductor pattern SP2 and the third semiconductor pattern SP3, and an outer gate electrode OGE on the third semiconductor pattern SP3.

[0047] Reference Figure 5D , the gate electrode GE may be disposed on the top surface TS, the bottom surface BS, and the two sidewalls SW of each of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3. That is, the transistor according to the present disclosure may be a three-dimensional field-effect transistor (e.g., NMCFET or gate-all-around field-effect transistor (GAAFET)) in which the gate electrode GE surrounds the channel three-dimensionally.

[0048] In an embodiment, an inner spacer ISP (e.g., see Figure 6 ) may be respectively between the first inner gate electrode IGE1, the second inner gate electrode IGE2, and the third inner gate electrode IGE3 of the gate electrode GE and the first source / drain pattern SD1 on the first active region AR1. In an embodiment, the inner spacer ISP may be respectively between the first inner gate electrode IGE1, the second inner gate electrode IGE2, and the third inner gate electrode IGE3 of the gate electrode GE and the second source / drain pattern SD2 on the second active region AR2. A detailed description of the inner spacer ISP according to the present disclosure will be described later with reference to Figure 6 .

[0049] Return reference Figure 4 and Figures 5A to 5D , paired gate spacers GS may be respectively disposed on the two sidewalls of the outer gate electrode OGE of the gate electrode GE. The gate spacers GS may extend along the gate electrode GE in the first direction D1. The top surface of the gate spacers GS may be higher than the top surface of the gate electrode GE. The top surface of the gate spacers GS may be coplanar with the top surface of the first interlayer insulating layer 110 to be described later. In an embodiment, the gate spacers GS may include at least one of SiCN, SiCON, and SiN. In another embodiment, the gate spacers GS may include a multi-layer structure having at least two of SiCN, SiCON, and SiN.

[0050] The gate insulating layer GI can be interposed between the gate electrode GE and the first channel pattern CH1, and between the gate electrode GE and the second channel pattern CH2. The gate insulating layer GI can cover the top surface TS, the bottom surface BS, and the two sidewalls SW of each of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3. The gate insulating layer GI can cover the top surface of the device isolation layer ST under the gate electrode GE. The gate insulating layer GI can include an inner gate insulating layer IIL located between the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 and the first inner gate electrode IGE1, the second inner gate electrode IGE2, and the third inner gate electrode IGE3, and an outer gate insulating layer OIL located between the third semiconductor pattern SP3 and the outer gate electrode OGE.

[0051] In one embodiment, the gate insulating layer GI can include a silicon oxide layer. Refer to Figure 6 , a high-k dielectric layer HK can be interposed between the gate electrode GE and the gate insulating layer GI. The high-k dielectric layer HK can surround the inner gate electrodes IGE1, IGE2, and IGE3 of the gate electrode GE with a uniform thickness. The high-k dielectric layer HK can extend from the bottom surface of the outer gate electrode OGE of the gate electrode GE to the side surface. For example, the gate insulating layer GI can have a structure stacked on the high-k dielectric layer HK.

[0052] The high-k dielectric layer HK (e.g., refer to Figure 6 ) can include a high-k dielectric material having a dielectric constant higher than that of the silicon oxide layer. As an example, the high-k dielectric material can include at least one of hafnium oxide, hafnium silicon oxide, hafnium zirconium oxide, hafnium tantalum oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanate, barium titanate, strontium titanate, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

[0053] In another embodiment, the semiconductor device can include a negative capacitance (NC) FET using a negative capacitor. For example, the gate insulating layer GI can include a ferroelectric material layer having ferroelectric properties and a paraelectric material layer having paraelectric properties.

[0054] The ferroelectric material layer can have a negative capacitance, while the paraelectric material layer can have a positive capacitance. For example, when two or more capacitors are connected in series and the capacitance of each capacitor has a positive value, the total capacitance decreases to be less than the capacitance of each individual capacitor. On the other hand, when at least one of the capacitances of two or more capacitors connected in series has a negative value, the total capacitance can have a positive value and be greater than the absolute value of each individual capacitance.

[0055] When a ferroelectric material layer having a negative capacitance is connected in series with a paraelectric material layer having a positive capacitance, the total capacitance of the series-connected ferroelectric material layer and paraelectric material layer can be increased. By using the increase in the total capacitance value, a transistor including the ferroelectric material layer can have a subthreshold swing (SS) of less than 60 mV / decade at room temperature.

[0056] The ferroelectric material layer can have ferroelectric properties. The ferroelectric material layer can include, for example, at least one of hafnium oxide, hafnium zirconium oxide, barium strontium titanium oxide, barium titanium oxide, and lead zirconium titanate. Here, as an example, hafnium zirconium oxide can be a material in which hafnium oxide is doped with zirconium (Zr). As another example, hafnium zirconium oxide is a compound of hafnium (Hf), zirconium (Zr), and oxygen (O).

[0057] The ferroelectric material layer can also include a doped dopant. For example, the dopant can include at least one of aluminum (Al), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr), and tin (Sn). The type of dopant included in the ferroelectric material layer can vary differently depending on which ferroelectric material the ferroelectric material layer includes.

[0058] When the ferroelectric material layer includes hafnium oxide, the dopant included in the ferroelectric material layer can include, for example, at least one of gadolinium (Gd), silicon (Si), zirconium (Zr), aluminum (Al), and yttrium (Y).

[0059] When the dopant is aluminum (Al), the ferroelectric material layer can include 3 atomic percent (at%) to 8 at% of aluminum. Here, the ratio of the dopant can be the ratio of aluminum to the sum of hafnium and aluminum.

[0060] When the dopant is silicon (Si), the ferroelectric material layer can include approximately 2 at% to approximately 10 at% of silicon. When the dopant is yttrium (Y), the ferroelectric material layer can include approximately 2 at% to approximately 10 at% of yttrium. When the dopant is gadolinium (Gd), the ferroelectric material layer can include approximately 1 at% to approximately 7 at% of gadolinium. When the dopant is zirconium (Zr), the ferroelectric material layer can include approximately 50 at% to approximately 80 at% of zirconium.

[0061] The paraelectric material layer can have paraelectric properties. The paraelectric material layer can include, for example, at least one of silicon oxide and metal oxides having a high dielectric constant. The metal oxides included in the paraelectric material layer can include, for example, at least one of hafnium oxide, zirconium oxide, and aluminum oxide, but are not limited thereto.

[0062] The ferroelectric material layer and the paraelectric material layer may include the same material. The ferroelectric material layer may have ferroelectric properties, but the paraelectric material layer may not have ferroelectric properties. For example, when the ferroelectric material layer and the paraelectric material layer include hafnium oxide, the crystal structure of the hafnium oxide included in the ferroelectric material layer is different from the crystal structure of the hafnium oxide included in the paraelectric material layer.

[0063] The ferroelectric material layer may have a thickness exhibiting ferroelectric properties. The thickness of the ferroelectric material layer may be, for example, about 0.5 nm to about 10 nm, but is not limited thereto. The critical thickness indicating ferroelectric properties may vary differently for each ferroelectric material, and the thickness of the ferroelectric material layer may vary depending on the ferroelectric material.

[0064] As an example, the gate insulating layer GI may include a ferroelectric material layer. As another example, the gate insulating layer GI may include a plurality of ferroelectric material layers spaced apart from each other. The gate insulating layer GI may have a stacked structure in which a plurality of ferroelectric material layers and a plurality of paraelectric material layers are alternately stacked.

[0065] Return reference Figure 4 and Figures 5A to 5D , the gate electrode GE may include a first metal pattern and a second metal pattern located on the first metal pattern. The first metal pattern may be disposed on the gate insulating layer GI and may be adjacent to the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3. The first metal pattern may include a work function metal for adjusting the threshold voltage of the transistor. The desired threshold voltage of the transistor may be achieved by adjusting the thickness and composition of the first metal pattern. For example, the first inner gate electrode IGE1, the second inner gate electrode IGE2, and the third inner gate electrode IGE3 of the gate electrode GE may be formed of the first metal pattern as a work function metal.

[0066] The first metal pattern may include a metal nitride layer. For example, the first metal pattern may include nitrogen (N) and at least one metal selected from the group consisting of titanium (Ti), tantalum (Ta), aluminum (Al), tungsten (W), and molybdenum (Mo). In addition, the first metal pattern may further include carbon (C). The first metal pattern may include a plurality of stacked work function metal layers.

[0067] The second metal pattern may include a metal having a lower resistance than the resistance of the first metal pattern. For example, the second metal pattern may include at least one metal selected from the group consisting of tungsten (W), aluminum (Al), titanium (Ti), and tantalum (Ta). For example, the outer gate electrode OGE of the gate electrode GE may include a first metal pattern and a second metal pattern located on the first metal pattern.

[0068] The first interlayer insulating layer 110 may be disposed on the substrate 100. The first interlayer insulating layer 110 may cover the gate spacer GS and the first source / drain pattern SD1 and the second source / drain pattern SD2. The top surface of the first interlayer insulating layer 110 may be substantially coplanar with the top surface of the gate covering pattern GP and the top surface of the gate spacer GS. The second interlayer insulating layer 120 covering the gate covering pattern GP may be disposed on the first interlayer insulating layer 110. The third interlayer insulating layer 130 may be disposed on the second interlayer insulating layer 120. The fourth interlayer insulating layer 140 may be disposed on the third interlayer insulating layer 130. For example, the first to fourth interlayer dielectric layers 110 to 140 may include silicon oxide layers.

[0069] The single-height cell SHC may have a first boundary BD1 and a second boundary BD2 that face each other in the second direction D2. The first boundary BD1 and the second boundary BD2 may extend in the first direction D1. The single-height cell SHC may have a third boundary BD3 and a fourth boundary BD4 that face each other in the first direction D1. The third boundary BD3 and the fourth boundary BD4 may extend in the second direction D2.

[0070] The separation structure DB may pass through the first interlayer insulating layer 110 and the second interlayer insulating layer 120 and extend into the first active pattern AP1 and the second active pattern AP2. The separation structure DB may pass through each of the first active pattern AP1 and the second active pattern AP2. The separation structure DB may electrically isolate the active region of the single-height cell SHC from the active region of an adjacent other cell.

[0071] The active contacts AC may be disposed through the first interlayer insulating layer 110 and the second interlayer insulating layer 120 and are electrically connected to the first source / drain pattern SD1 and the second source / drain pattern SD2, respectively. Pairs of active contacts AC may be disposed on both sides of the gate electrode GE. When observed in a top view, the active contacts AC may be in a strip shape extending in the first direction D1.

[0072] The active contacts AC may be self-aligned contacts. That is, the active contacts AC may be formed in a self-aligned manner using the gate covering pattern GP and the gate spacer GS. For example, the active contacts AC may cover at least a part of the sidewall of the gate spacer GS. In an embodiment, the active contacts AC may partially cover the top surface of the gate covering pattern GP.

[0073] A metal-semiconductor compound layer SC, such as a silicide layer, can be interposed between the active contact AC and the first source / drain pattern SD1 and between the active contact AC and the second source / drain pattern SD2, respectively. The active contact AC can be electrically connected to the source / drain patterns SD1 and SD2 through the metal-semiconductor compound layer SC. For example, the metal-semiconductor compound layer SC can include at least one of titanium silicide, tantalum silicide, tungsten silicide, nickel silicide, and cobalt silicide.

[0074] The gate contact GC can be disposed through the second interlayer insulating layer 120 and the gate covering pattern GP to be electrically connected to the gate electrode GE, respectively. When observed in a top view, the gate contact GC can be disposed to overlap with the first active region AR1 and the second active region AR2, respectively. For example, the gate contact GC can be disposed on the second active pattern AP2 (refer to Figure 5B ).

[0075] In an embodiment, referring to Figure 5B , the upper portion of the active contact AC adjacent to the gate contact GC can be filled with an upper insulating pattern UIP. The bottom surface of the upper insulating pattern UIP can be lower than the bottom surface of the gate contact GC. That is, the top surface of the active contact AC adjacent to the gate contact GC can be lowered below the bottom surface of the gate contact GC through the upper insulating pattern UIP. Therefore, the problem that the gate contact GC contacts the adjacent active contact AC and a short circuit occurs can be reduced or prevented.

[0076] Each of the active contact AC and the gate contact GC can include a conductive pattern FM and a barrier pattern BM surrounding the conductive pattern FM. For example, the conductive pattern FM can include at least one of aluminum, copper, tungsten, molybdenum, and cobalt. The barrier pattern BM can cover the sidewalls and the bottom surface of the conductive pattern FM. The barrier pattern BM can include a metal layer / metal nitride layer. The metal layer can include at least one of titanium, tantalum, tungsten, nickel, cobalt, and platinum. The metal nitride layer can include at least one of a titanium nitride (TiN) layer, a tantalum nitride (TaN) layer, a tungsten nitride (WN) layer, a nickel nitride (NiN) layer, a cobalt nitride (CoN) layer, or a platinum nitride (PtN) layer.

[0077] The first metal layer M1 can be disposed in the third interlayer insulating layer 130. For example, the first metal layer M1 can include a first power wiring M1_R1, a second power wiring M1_R2, and a first wiring M1_I. Each of the wirings M1_R1, M1_R2, and M1_I of the first metal layer M1 can extend parallel to each other in the second direction D2.

[0078] In an embodiment, the first power wiring M1_R1 and the second power wiring M1_R2 may be respectively disposed on the third boundary BD3 and the fourth boundary BD4 of the single-height cell SHC. The first power wiring M1_R1 may extend in the second direction D2 along the third boundary BD3. The second power wiring M1_R2 may extend in the second direction D2 along the fourth boundary BD4.

[0079] The first wiring M1_I of the first metal layer M1 may be disposed between the first power wiring M1_R1 and the second power wiring M1_R2. The first wiring M1_I of the first metal layer M1 may be arranged at a second pitch in the first direction D1. The second pitch may be smaller than the first pitch. The line width of each first wiring M1_I may be smaller than the line width of each of the first power wiring M1_R1 and the second power wiring M1_R2.

[0080] The first metal layer M1 may further include first vias VI1. The first vias VI1 may be respectively disposed below the wirings M1_R1, M1_R2, and M1_I of the first metal layer M1. The active contacts AC and the wirings of the first metal layer M1 may be electrically connected to each other through the first vias VI1. The gate contacts GC and the wirings of the first metal layer M1 may be electrically connected to each other through the first vias VI1.

[0081] The wirings of the first metal layer M1 and the first vias VI1 disposed below the wirings of the first metal layer M1 may be formed by separate processes. That is, each of the wirings of the first metal layer M1 and the first vias VI1 may be formed by a single damascene process. The semiconductor device according to the present disclosure may be formed using a process of less than 20 nm.

[0082] The second metal layer M2 may be disposed in the fourth interlayer insulating layer 140. The second metal layer M2 may include a plurality of second wirings M2_I. Each second wiring M2_I of the second metal layer M2 may be in a line shape or a strip shape extending in the first direction D1. That is, the second wirings M2_I may extend parallel to each other in the first direction D1.

[0083] The second metal layer M2 may further include second vias VI2 respectively disposed below the second wirings M2_I. The wirings of the first metal layer M1 and the wirings of the second metal layer M2 may be electrically connected to each other through the second vias VI2. For example, the wirings of the second metal layer M2 and the second vias VI2 disposed below the wirings of the second metal layer M2 may be formed together by a dual damascene process.

[0084] The wirings of the first metal layer M1 and the wirings of the second metal layer M2 may include the same or different conductive materials. For example, the wirings of the first metal layer M1 and the wirings of the second metal layer M2 may include at least one metal material selected from aluminum, copper, tungsten, molybdenum, ruthenium, and cobalt. In an embodiment, metal layers (e.g., M3, M4, M5...) stacked on the fourth interlayer insulating layer 140 may be additionally provided. Each of the stacked metal layers may include wirings for routing between cells.

[0085] Figure 6 is an enlarged view of an example of the region “M” that Figure 5A illustrates. Referring to Figure 6 , the gate insulating layer GI, the inner spacer ISP, the high-k dielectric layer HK, and the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 will be described.

[0086] The gate electrode GE may include a first inner gate electrode IGE1, a second inner gate electrode IGE2, a third inner gate electrode IGE3, and an outer gate electrode OGE. The gate insulating layer GI may include a silicon oxide layer. The gate insulating layer GI may include an inner gate insulating layer IIL on each of the first inner gate electrode IGE1, the second inner gate electrode IGE2, and the third inner gate electrode IGE3, and an outer gate insulating layer OIL on the outer gate electrode OGE. The outer gate insulating layer OIL may be provided on the bottom surface and the side surface of the outer gate electrode OGE. The outer gate insulating layer OIL may extend to a gate capping pattern GP (e.g., see Figure 5A ) that covers the top surface of the outer gate electrode OGE.

[0087] The inner gate insulating layer IIL may be provided between the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 and the first inner gate electrode IGE1, the second inner gate electrode IGE2, and the third inner gate electrode IGE3. For example, the inner gate insulating layer IIL may surround the first inner gate electrode IGE1, the second inner gate electrode IGE2, and the third inner gate electrode IGE3.

[0088] In an embodiment, the inner gate insulating layer IIL may include an upper insulating layer IILT between the first inner gate electrode IGE1 and the first semiconductor pattern SP1, a lower insulating layer IILB between the first inner gate electrode IGE1 and the first active pattern AP1, and a side insulating layer IILS between the first inner gate electrode IGE1 and the inner spacer ISP.

[0089] The inner gate insulating layer IIL may include an upper insulating layer IILT positioned between the second inner gate electrode IGE2 and the second semiconductor pattern SP2, a lower insulating layer IILB positioned between the second inner gate electrode IGE2 and the first semiconductor pattern SP1, and a side insulating layer IILS positioned between the second inner gate electrode IGE2 and the inner spacer ISP.

[0090] The inner gate insulating layer IIL may include an upper insulating layer IILT positioned between the third inner gate electrode IGE3 and the third semiconductor pattern SP3, a lower insulating layer IILB positioned between the third inner gate electrode IGE3 and the second semiconductor pattern SP2, and a side insulating layer IILS positioned between the third inner gate electrode IGE3 and the inner spacer ISP.

[0091] The inner gate insulating layer IIL may include a material different from the inner spacer ISP. The inner gate insulating layer IIL may have an etching selectivity with respect to the inner spacer ISP. For example, the inner gate insulating layer IIL may include silicon oxide (SiO), and the inner spacer ISP may include silicon nitride (SiN). The interface between the inner gate insulating layer IIL and the inner spacer ISP may be identified.

[0092] Each of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 may include a body portion BDP and a protrusion PTP protruding from the body portion BDP toward the first source / drain pattern SD1 in the second direction D2. A silicon layer GL may be formed to cover the outer wall of the protrusion PTP. The silicon layer GL may be interposed between the protrusion PTP and the first source / drain pattern SD1. The silicon layer GL may be an epitaxial pattern formed from the protrusion PTP by an epitaxial growth process.

[0093] The silicon layer GL may also be interposed between the first active pattern AP1 and the first source / drain pattern SD1. The silicon layer GL may be in contact with the inner spacer ISP and the inner gate insulating layer IIL. The thickness of the silicon layer GL may be constant. A first thickness TH1 of the side insulating layer IILS of the inner gate insulating layer IIL may be equal to a second thickness TH2 of the silicon layer GL. The first thickness TH1 may be defined as the shortest distance between a side surface of the side insulating layer IILS and a side surface of the inner spacer ISP. The second thickness TH2 may be defined as the shortest distance between a side surface of the first source / drain pattern SD1 and the protrusion PTP. The first thickness TH1 and the second thickness TH2 may be distances in the second direction D2.

[0094] The highest level height of the main body portion BDP can be substantially the same as the highest level height of the silicon layer GL. For example, the highest part of the main body portion BDP can be positioned at the same level height as the highest part of the silicon layer GL. The lowest level height of the main body portion BDP can be substantially the same as the lowest level height of the silicon layer GL. For example, the lowest part of the main body portion BDP can be positioned at the same level height as the lowest part of the silicon layer GL.

[0095] The main body portion BDP can have a main body thickness BDH in the third direction D3. The protrusion PTP can have a protrusion thickness PTH in the third direction D3. The main body thickness BDH can be greater than the protrusion thickness PTH. The main body thickness BDH can be equal to the sum of the protrusion thickness PTH and the thickness GLH of the silicon layer GL covering the protrusion. The thickness GLH of the silicon layer GL can be the length in the third direction D3. By forming the silicon layer GL on the protrusion PTP, the thicknesses of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 in the third direction D3 can be constant.

[0096] The high dielectric layer HK can be interposed between the inner gate electrodes IGE1, IGE2, and IGE3 and the inner gate insulating layer IIL or between the outer gate electrode OGE and the outer gate insulating layer OIL. The high dielectric layer HK can be disposed on the inner gate electrodes IGE1, IGE2, and IGE3, and the inner gate insulating layer IIL can be disposed on the high dielectric layer HK. The high dielectric layer HK can be conformally formed.

[0097] According to the semiconductor device manufacturing method described later, before forming the inner spacer ISP, a silicon layer GL can be formed on the first recess RS1 (for example, see Figure 12A ) and the second recess RS2 (for example, see Figure 12B ). The silicon layer GL can include a first portion GLa located on the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 and a second portion GLb located on the sacrificial layer. The second portion GLb can be oxidized through the oxidation process described later to form the side insulating layer IILS of the inner gate insulating layer IIL. The inner gate insulating layer IIL can prevent leakage current together with the inner spacer ISP.

[0098] According to the present disclosure, by disposing the silicon layer GL on the protrusion PTP, the thickness difference between the main body portion BDP and the protrusion PTP can be minimized. By forming the silicon layer GL, the thicknesses of the semiconductor patterns SP1, SP2, and SP3 can be constant. Therefore, the resistance caused by the reduction in the thicknesses of the semiconductor patterns SP1, SP2, and SP3 can be minimized. As a result, the electrical characteristics of the semiconductor device according to the present disclosure can be improved.

[0099] Figures 7A to 12Dis a cross-sectional view for illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure. In the embodiment, Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A and Figure 12A are cross-sectional views corresponding to the line A-A' in Figure 4 . Figure 9B , Figure 10B , Figure 11B and Figure 12B are cross-sectional views corresponding to the line B-B' in Figure 4 . Figure 9C , Figure 10C , Figure 11C and Figure 12C are cross-sectional views corresponding to the line C-C' in Figure 4 . Figure 7B , Figure 8B , Figure 11D and Figure 12D are cross-sectional views corresponding to the line D-D' of Figure 4 . Hereinafter, a manufacturing method according to an embodiment of the present disclosure will be described with reference to Figures 7A to 12D .

[0100] Referring to Figure 7A and Figure 7B , the substrate 100 includes a first active region AR1 and a second active region AR2. An active layer ACL and a sacrificial layer SAL may be alternately stacked on the substrate 100. The active layer ACL may include one of silicon (Si), germanium (Ge), and silicon germanium (SiGe), and the sacrificial layer SAL may include another one of silicon (Si), germanium (Ge), and silicon germanium (SiGe).

[0101] The sacrificial layer SAL may include a material having an etching selectivity with respect to the active layer ACL. For example, the active layer ACL may include silicon (Si), while the sacrificial layer SAL may include silicon germanium (SiGe). The concentration of germanium (Ge) in each sacrificial layer SAL may be 10 at% to 30 at%.

[0102] Mask patterns may be formed on the first active region AR1 and the second active region AR2 of the substrate 100, respectively. The mask patterns may be in a line shape or a strip shape extending in the second direction D2.

[0103] A patterning process may be performed using the mask patterns as an etching mask to form trenches TR defining a first active pattern AP1 and a second active pattern AP2. The first active pattern AP1 may be formed on the first active region AR1. The second active pattern AP2 may be formed on the second active region AR2.

[0104] A stacked pattern STP can be formed on each of the first active pattern AP1 and the second active pattern AP2. The stacked pattern STP can include an active layer ACL and a sacrificial layer SAL stacked alternately. The stacked pattern STP can be formed together with the first active pattern AP1 and the second active pattern AP2 during a patterning process.

[0105] A device isolation layer ST filling the trench TR can be formed. In an embodiment, an insulating layer covering the first active pattern AP1, the second active pattern AP2, and the stacked pattern STP can be formed on the entire surface of the substrate 100. The insulating layer can be recessed until the stacked pattern STP is exposed to form the device isolation layer ST.

[0106] The device isolation layer ST can include an insulating material such as a silicon oxide layer. The stacked pattern STP can be exposed on the device isolation layer ST. That is, the stacked pattern STP can vertically protrude above the device isolation layer ST.

[0107] Reference Figure 8A and Figure 8B , a sacrificial pattern PP intersecting the stacked pattern STP can be formed on the substrate 100. Each sacrificial pattern PP can be formed in a line shape or a strip shape extending in a first direction D1. The sacrificial patterns PP can be arranged at a first pitch along a second direction D2.

[0108] In an embodiment, forming the sacrificial pattern PP can include forming a sacrificial layer on the entire surface of the substrate 100, forming a hard mask pattern MP on the sacrificial layer, and patterning the sacrificial layer using the hard mask pattern MP as an etching mask. The sacrificial layer can include polysilicon.

[0109] A pair of gate spacers GS can be formed on two sidewalls of each sacrificial pattern PP. Forming the gate spacers GS includes conformally forming a gate spacer layer on the entire surface of the substrate 100 and anisotropically etching the gate spacer layer. In an embodiment, the gate spacers GS can be a multi-layer structure including at least two layers.

[0110] Reference Figures 9A to 9C , a first recess RS1 can be formed in the stacked pattern STP on the first active pattern AP1. A second recess RS2 can be formed in the stacked pattern STP on the second active pattern AP2. When forming the first recess RS1 and the second recess RS2, the device isolation layer ST located on both sides of each of the first active pattern AP1 and the second active pattern AP2 can be further recessed (reference Figure 9B ).

[0111] In an embodiment, the stacked pattern STP located on the first active pattern AP1 may be etched using the hard mask pattern MP and the gate spacer GS as an etch mask to form the first recess RS1. The first recess RS1 may be formed between pairs of sacrificial patterns PP.

[0112] In an embodiment, forming the first recess RS1 may include additionally performing a selective etching process on the exposed sacrificial layer SAL. Each sacrificial layer SAL may be imprinted by the selective etching process to form an imprinted area IDE. Accordingly, the first recess RS1 may have a wavy inner wall. The sidewalls of the sacrificial layer SAL may be concave due to the imprinted area IDE. The second recess RS2 in the stacked pattern STP located on the second active pattern AP2 may be formed in the same manner as the first recess RS1.

[0113] The first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 sequentially stacked between adjacent first recesses RS1 may be formed from the active layer ACL, respectively. The first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 located between adjacent first recesses RS1 may form the first channel pattern CH1. The first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 located between adjacent second recesses RS2 may form the second channel pattern CH2.

[0114] Reference Figures 10A to 10C may be made to form a silicon layer GL in the first recess RS1. Later, reference will be made to Figures 13 to 17 for a detailed description of the silicon layer GL.

[0115] Reference Figures 11A to 11D may be made to selectively remove the exposed sacrificial pattern PP and to form a gate insulating layer GI. The gate insulating layer GI may be formed on the exposed first semiconductor pattern SP1, second semiconductor pattern SP2, and third semiconductor pattern SP3. The gate insulating layer GI may be formed to surround each of the first semiconductor pattern SP1, second semiconductor pattern SP2, and third semiconductor pattern SP3. An inner gate insulating layer IIL may be formed in the first inner region IRG1, second inner region IRG2, and third inner region IRG3, which will be described later. An outer gate insulating layer OIL may be formed in the outer region ORG. Reference will be made to Figures 13 to 17 for a detailed description of the formation of the gate insulating layer GI.

[0116] Reference Figures 12A to 12D, a gate electrode GE may be formed on a gate insulating layer GI. The gate electrode GE may include a first inner gate electrode IGE1, a second inner gate electrode IGE2, and a third inner gate electrode IGE3 respectively formed in a first inner region IRG1, a second inner region IRG2, and a third inner region IRG3, and an outer gate electrode OGE formed in an outer region ORG. The gate electrode GE may be recessed to reduce its height. A gate capping pattern GP may be formed on the recessed gate electrode GE.

[0117] Referring again to Figures 5A to 5D , a second interlayer insulating layer 120 may be formed on a first interlayer insulating layer 110. The second interlayer insulating layer 120 may include a silicon oxide layer. An active contact AC electrically connected to a first source / drain pattern SD1 and a second source / drain pattern SD2 may be formed through the second interlayer insulating layer 120 and the first interlayer insulating layer 110. A gate contact GC electrically connected to the gate electrode GE may be formed through the second interlayer insulating layer 120 and the gate capping pattern GP.

[0118] The formation of each of the active contact AC and the gate contact GC may include forming a barrier pattern BM and forming a conductive pattern FM on the barrier pattern BM. The barrier pattern BM may be conformally formed and may include a metal layer / metal nitride layer. The conductive pattern FM may include a low-resistance metal.

[0119] A separation structure DB may be formed on a first boundary BD1 and a second boundary BD2 of a single-height cell SHC, respectively. The separation structure DB may extend from the second interlayer insulating layer 120 through the gate electrode GE into a first active pattern AP1 or a second active pattern AP2. The separation structure DB may include an insulating material such as a silicon oxide layer or a silicon nitride layer.

[0120] A third interlayer insulating layer 130 may be formed on the active contact AC and the gate contact GC. A first metal layer M1 may be formed in the third interlayer insulating layer 130. A fourth interlayer insulating layer 140 may be formed on the third interlayer insulating layer 130. A second metal layer M2 may be formed in the fourth interlayer insulating layer 140.

[0121] Hereinafter, reference will be made to Figures 13 to 17 to describe a formation process of the gate insulating layer GI. For simplicity of illustration, descriptions overlapping with the above are omitted. Figures 13 to 17 is a diagram illustrating a method of manufacturing a semiconductor device according to Figure 6 , and is an enlarged view for illustrating a method of forming a region “M” of Figure 5A .

[0122] Referring to Figure 13, a silicon layer GL may be formed in the first recess RS1. The silicon layer GL may be formed in the imprint area IDE. The silicon layer GL may be formed on the first active pattern AP1 of the substrate 100.

[0123] The silicon layer GL may include a first portion GLa located on the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3, and a second portion GLb located on the sacrificial layer SAL. The first portion GLa may cover the outer walls of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 exposed through the first recess RS1. The second portion GLb may cover the outer wall of the sacrificial layer SAL exposed through the imprint area IDE. The silicon layer GL may not be formed on the gate spacer GS.

[0124] Forming the silicon layer GL may include performing an epitaxial growth process on the first semiconductor pattern SP1, the second semiconductor pattern SP2, the third semiconductor pattern SP3, the first active pattern AP1, and the sacrificial layer SAL. The silicon layer GL may be grown using the first semiconductor pattern SP1, the second semiconductor pattern SP2, the third semiconductor pattern SP3, the first active pattern AP1, and the sacrificial layer SAL as seed layers.

[0125] As another example, forming the silicon layer GL may include selectively growing silicon on the sacrificial layer SAL. For example, the silicon layer GL may be formed only on the outer wall of the sacrificial layer SAL exposed through the first recess RS1.

[0126] Reference Figure 14 , an inner spacer ISP may be formed on the second portion GLb in the imprint area IDE. The inner spacer ISP may partially fill the imprint area IDE. Forming the inner spacer ISP may include forming an insulating layer that fills the imprint area IDE through the first recess RS1 and performing wet etching on the insulating layer exposed outside the imprint area IDE. The insulating layer may include at least one of a silicon oxynitride layer and a silicon nitride layer.

[0127] The inner spacer ISP may include one side surface in contact with the silicon layer GL and the other side surface exposed through the first recess RS1. The curvature of one side surface may be smaller than the curvature of the other side surface. The inner spacer ISP may be in a half-moon shape.

[0128] Reference Figure 15, a first source / drain pattern may be formed in the first recess RS1. In an embodiment, the SEG process may be performed using the first part GLa of the first recess RS1 and the substrate 100 that is exposed as a seed layer to form an epitaxial layer filling the first recess RS1. The epitaxial layer may be grown using the first part GLa of the first recess RS1 and the substrate 100 that is exposed as a seed layer. As an example, the SEG process may include a chemical vapor deposition (CVD) process or a molecular beam epitaxy (MBE) process.

[0129] In an embodiment, the first source / drain pattern SD1 may include the same semiconductor element (e.g., Si) as the substrate 100. When the first source / drain pattern SD1 is being formed, impurities (e.g., phosphorus, arsenic, or antimony) may be in-situ implanted so that the first source / drain pattern SD1 has an n-type. As another example, after the first source / drain pattern SD1 is formed, impurities may be implanted into the first source / drain pattern SD1.

[0130] A second source / drain pattern SD2 may be respectively formed in the second recess RS2. In an embodiment, the SEG process may be performed using the inner wall of the second recess RS2 as a seed layer, and thus the second source / drain pattern SD2 may be formed.

[0131] In one embodiment, the second source / drain pattern SD2 may include a semiconductor element (e.g., SiGe) whose lattice constant is larger than that of the semiconductor element of the substrate 100. When the second source / drain pattern SD2 is formed, impurities (e.g., boron, gallium, or indium) may be in-situ implanted so that the second source / drain pattern SD2 has a p-type. As another example, after the second source / drain pattern SD2 is formed, impurities may be implanted into the second source / drain pattern SD2.

[0132] Reference Figure 16 , a first interlayer insulating layer 110 may be formed to cover the first source / drain pattern SD1, the second source / drain pattern SD2, the hard mask pattern MP, and the gate spacer GS. As an example, the first interlayer insulating layer 110 may include a silicon oxide layer.

[0133] The first interlayer insulating layer 110 may be planarized until the top surface of the sacrificial pattern PP is exposed. The planarization of the first interlayer insulating layer 110 may be performed using an etch-back process or a chemical mechanical polishing (CMP) process. During the planarization process, all the hard mask patterns MP may be removed. As a result, the top surface of the first interlayer insulating layer 110 may be coplanar with the top surface of the sacrificial pattern PP and the top surface of the gate spacer GS.

[0134] The exposed sacrificial pattern PP can be selectively removed. As the sacrificial pattern PP is removed, an outer region ORG exposing the first channel pattern CH1 and the second channel pattern CH2 can be formed (refer to Figure 11C ). The removal of the sacrificial pattern PP may include wet etching using an etchant that selectively etches polysilicon.

[0135] The sacrificial layer SAL exposed through the outer region ORG can be selectively removed to form an inner region IRG (refer to Figure 11C ). In an embodiment, an etching process that selectively etches the sacrificial layer SAL can be performed, so that only the sacrificial layer SAL can be removed while the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 are left. The etching process may have a high etching rate with respect to silicon germanium having a relatively high germanium concentration. For example, for silicon germanium with a germanium concentration greater than 10 at%, the etching process may have a high etching rate.

[0136] During the etching process, the sacrificial layer SAL located on the first active region AR1 and the second active region AR2 can be removed. The etching process may be wet etching. The etching material used in the etching process can quickly remove the sacrificial layer SAL having a relatively high germanium concentration.

[0137] In an embodiment, a first inner region IRG1 can be formed between the first active pattern AP1 or the second active pattern AP2 and the first semiconductor pattern SP1, a second inner region IRG2 can be formed between the first semiconductor pattern SP1 and the second semiconductor pattern SP2, and a third inner region IRG3 can be formed between the second semiconductor pattern SP2 and the third semiconductor pattern SP3.

[0138] The top and bottom surfaces of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 can be exposed through the outer region ORG and the inner regions IRG1, IRG2, and IRG3. A second portion GLb of the silicon layer GL can be exposed through the inner regions IRG1, IRG2, and IRG3. For example, the top surface ITW of the first semiconductor pattern SP1, the bottom surface IBW of the second semiconductor pattern SP2, and a side surface ISW of the second portion GLb can be exposed.

[0139] Refer to Figure 17, an inner gate insulating layer IIL may be formed on the exposed first semiconductor pattern SP1, second semiconductor pattern SP2, and third semiconductor pattern SP3. Forming the inner gate insulating layer IIL may include forming an oxide layer by performing an oxidation process on a first inner region IRG1, a second inner region IRG2, and a third inner region IRG3, and the oxide layer may be in direct contact with the inner spacer ISP. For example, oxidation may be performed on a second portion GLb exposed through the first inner region IRG1, the second inner region IRG2, and the third inner region IRG3, as well as on the top and bottom surfaces of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3. Through the oxidation process, an inner gate insulating layer IIL containing silicon oxide may be formed. As an example, the inner gate insulating layer IIL may include SiO 2 .

[0140] For example, a lower insulating layer IILB may be formed on the top surface of the first semiconductor pattern SP1 exposed through the second inner region IRG2. An upper insulating layer IILT may be formed on the bottom surface of the second semiconductor pattern SP2 exposed through the second inner region IRG2. The second portion GLb (e.g., see Figure 16 ) exposed through the second inner region IRG2 may be oxidized by an oxidation process to form a side insulating layer IILS. The oxidation process may be selectively performed only on the second portion GLb. Thus, only the first portion GLa may remain.

[0141] Through the oxidation process, the thicknesses of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 in the third direction D3 may be reduced. For example, Figure 16 the thickness H1 of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 may be greater than Figure 17 the thickness H2 of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3.

[0142] Referring back to Figure 6 , a high-k dielectric layer HK and a gate electrode GE may be sequentially formed on the inner gate insulating layer IIL and the outer gate insulating layer OIL, respectively. As described above, the high-k dielectric layer HK may include a high-k dielectric material having a dielectric constant higher than that of a silicon oxide layer. For example, the high-k dielectric layer HK may be formed by performing an atomic layer deposition (ALD) process.

[0143] According to the present disclosure, a silicon layer GL may be formed before forming the inner spacer ISP. The silicon layer GL may be formed in the imprint region IDE, thereby preventing the thicknesses of the semiconductor patterns SP1, SP2, and SP3 from decreasing due to the inner spacer ISP. Additionally, the inner gate insulating layer IIL may be formed by selectively performing an oxidation process only on the second portion GLb of the silicon layer GL. As a result, the inner gate insulating layer IIL may be formed between the gate electrode GE and the inner spacer ISP.

[0144] According to the present disclosure, a silicon layer may be formed before forming the inner spacer, so that the thickness of the semiconductor pattern may be constant. The thickness of the silicon layer may be adjusted to minimize the resistance caused by the decrease in the thickness of the semiconductor pattern. Additionally, an oxidation process may be performed on the formed silicon layer to form a gate insulating layer. As a result, the electrical characteristics of the semiconductor device according to the present disclosure may be improved.

[0145] Although embodiments have been described above, those skilled in the art will understand that many modifications and variations can be made without departing from the spirit and scope of the present disclosure defined in the appended claims. Therefore, the exemplary embodiments of the present disclosure should be considered illustrative rather than restrictive in all respects, and the spirit and scope of the present disclosure are indicated by the appended claims.

Claims

1. A method for manufacturing a semiconductor device, the method comprising: forming a stacking pattern, the stacking pattern comprising an active layer and a sacrificial layer stacked on a substrate, wherein the active layer comprises two active layers vertically adjacent to each other, and the sacrificial layer is interposed between the two active layers; forming a recess by etching the stacked pattern; forming an indentation by etching a portion of the sacrificial layer exposed by the recess; forming a silicon layer on an inner surface of the recess; forming an inner spacer in the indentation; forming an inner region by removing the sacrificial layer; and forming a gate insulating layer in the inner region, Wherein, forming the gate insulating layer includes forming an oxide layer by performing an oxidation process on the silicon layer exposed through the inner region.

2. The method according to claim 1, wherein: The oxide layer is in direct contact with the inner spacer.

3. The method according to claim 1, wherein: Forming the silicon layer includes performing an epitaxial growth process on the sacrificial layer and the semiconductor pattern exposed by the recess.

4. The method according to claim 1, further comprising forming a semiconductor pattern from the active layer, in, The silicon layer includes a first portion located on the semiconductor pattern and a second portion located on the sacrificial layer, and wherein the oxidation process is selectively performed in the second portion through the inner region.

5. The method according to claim 4, further comprising: oxidizing the top and bottom surfaces of the semiconductor pattern by the oxidation process; as well as The gate insulating layer is formed on the top surface and the bottom surface of the semiconductor pattern.

6. The method according to claim 4, wherein: The thickness of the semiconductor pattern in a vertical direction is reduced by the oxidation process. 7 . The method according to claim 1 , further comprising forming the inner spacer and forming a source / drain pattern in the recess. 8 . The method according to claim 1 , further comprising sequentially forming a gate electrode and a high dielectric layer in the inner region, the high dielectric layer comprising a high dielectric constant material having a higher dielectric constant than that of a silicon oxide layer.

9. The method according to claim 1, wherein: Forming the silicon layer includes selectively growing silicon on the sacrificial layer exposed by the recess.

10. A method for manufacturing a semiconductor device, the method comprising: forming a stacked pattern, the stacked pattern comprising a semiconductor pattern and a sacrificial layer stacked on a substrate; forming a recess by etching the stacked pattern; forming an indentation by etching a portion of the sacrificial layer exposed by the recess; forming a silicon layer on an inner surface of the recess, the silicon layer comprising a first portion located on the semiconductor pattern and a second portion located on the sacrificial layer; forming an inner spacer in the indentation; as well as forming a source / drain pattern in the recess, wherein the semiconductor pattern includes a main body portion and a protrusion protruding from the main body portion toward the source / drain pattern, and Wherein, a highest level height of the main body portion and a highest level height of the first portion covering the protrusion are equal to each other.

11. The method according to claim 10, wherein: Forming the first portion includes performing an epitaxial growth process on the protrusion.

12. The method according to claim 10, further comprising: forming an inner region by removing the sacrificial layer and exposing the second portion through the inner region; as well as A gate insulating layer is formed by performing an oxidation process on the exposed second portion.

13. The method according to claim 12, wherein: Forming the gate insulating layer includes performing an oxidation process on top and bottom surfaces of the semiconductor pattern exposed through the inner region. 14 . The method according to claim 12 , further comprising sequentially forming a gate electrode and a high dielectric layer in the inner region, the high dielectric layer comprising a high dielectric constant material having a higher dielectric constant than that of the silicon oxide layer.

15. The method according to claim 12, wherein: The thickness of the semiconductor pattern in a vertical direction is reduced by the oxidation process.

16. A semiconductor device, comprising: a substrate comprising an active pattern; a first semiconductor pattern and a second semiconductor pattern, the first semiconductor pattern and the second semiconductor pattern being stacked on the active pattern and vertically spaced apart from each other; a source / drain pattern connected to the first semiconductor pattern and the second semiconductor pattern; a silicon layer, the silicon layer being located between the first semiconductor pattern and the source / drain pattern; a gate electrode, the gate electrode being located between the first semiconductor pattern and the second semiconductor pattern; a gate insulating layer, the gate insulating layer being located between the gate electrode and the source / drain pattern; a high dielectric layer surrounding the gate electrode and comprising a high dielectric constant material having a dielectric constant higher than that of the silicon oxide layer; as well as an inner spacer, the inner spacer being located between the gate insulating layer and the source / drain pattern, wherein the first semiconductor pattern includes a main body portion and a protrusion protruding from the main body portion toward the source / drain pattern, and Wherein, a first highest level height of the main body portion is equal to a second highest level height of the silicon layer covering the protrusion.

17. The semiconductor device according to claim 16, wherein: The gate insulating layer includes a side insulating layer between the high dielectric layer and the inner spacer, and Wherein, the first thickness of the side insulating layer is equal to the second thickness of the silicon layer.

18. The semiconductor device according to claim 16, wherein: The gate insulating layer includes a silicon oxide layer.

19. The semiconductor device according to claim 16, wherein: A first lowest level of the body portion is equal to a second lowest level of the silicon layer covering the protrusion.

20. The semiconductor device according to claim 16, wherein The gate insulating layer includes a first material different from a second material of the inner spacer.

Images