Photoelectric synapse device and modulation method and application thereof

Abstract

The invention provides a photoelectric synapse device and a modulation method and application thereof, and belongs to the technical field of artificial synapses. The photoelectric synaptic device comprises a substrate; a floating gate layer; a tunneling layer; the channel layer is located on the tunneling layer, the channel layer comprises a rhenium disulfide two-dimensional material layer, the channel layer generates photo-generated electron-hole pairs under the action of light pulses, and meanwhile, the floating gate layer is suitable for receiving photo-generated holes to regulate and control conductivity of the channel layer; the source electrode and the drain electrode are respectively positioned on the channel layer; wherein the initial state of the channel layer presents the write-in state of the first conductance, and the photoelectric synapse device presents a plurality of erase states respectively corresponding to the plurality of erase conductance by regulating and controlling the parameters of the optical pulse incident to the channel layer; after the channel layer is in the erasing state of the second conductance, forward electric pulses are applied to the substrate, so that the photoelectric synapse device recovers the writing state of the first conductance; wherein the first conductance is smaller than the second conductance, and the second conductance is the largest erasing conductance in the multiple erasing conductance.

Description

Technical Field

[0001] The present invention belongs to the technical field of artificial synapses. At least one embodiment of the present invention relates to an optoelectronic synaptic device, and particularly to an optoelectronic synaptic device, its modulation method, and application. Background Art

[0002] Due to the physical separation of the storage unit and the computing unit in traditional von Neumann computers, there are problems of an inherent upper limit on the computing speed and a sharp increase in energy consumption, making it difficult to meet the demand for efficient computing in the era of artificial intelligence. Inspired by the information processing mechanism of biological neural structures, neuromorphic computing effectively breaks through the limitations of the von Neumann bottleneck by integrating sensing, storage, and computing functions at the hardware level. The basic unit of a biological neural structure is a synapse. Therefore, developing artificial synaptic devices that can simulate the functions of biological synapses is the key to realizing neuromorphic computing. Currently, researchers have developed various artificial synaptic devices, including all-electric synapses, all-optical synapses, and optoelectronic synapses. Among them, optoelectronic synapses are closest to the hybrid signal processing mechanism of biological synapses and can achieve complex functions such as associative learning and optoelectronic neural computing. However, the optical synaptic weight accuracy of existing devices is limited, restricting their recognition accuracy in image classification tasks. Summary of the Invention

[0003] In view of this, the present invention provides an optoelectronic synaptic device, its modulation method, and application, aiming to solve the problem of insufficient optical weight accuracy of existing optoelectronic synaptic devices.

[0004] According to an embodiment of one aspect of the present invention, an optoelectronic synaptic device is provided, including:

[0005] A substrate; a floating gate layer located on the substrate; a tunneling layer located on the floating gate layer; a channel layer located on the tunneling layer, the channel layer includes a two-dimensional molybdenum disulfide material layer, the channel layer generates photo-generated electron-hole pairs under the action of a light pulse, and at the same time the floating gate layer is adapted to receive photo-generated holes to regulate the conductance of the channel layer; and a source electrode and a drain electrode, respectively located on the channel layer;

[0006] Wherein, the initial state of the channel layer presents a write state with a first conductance, and by regulating the parameters of the light pulse incident on the channel layer, the optoelectronic synaptic device presents multiple erase states corresponding to multiple erase conductances respectively; after the channel layer presents an erase state with a second conductance, by applying a positive electric pulse on the substrate, the optoelectronic synaptic device is restored to the write state with the first conductance; wherein the first conductance is less than the second conductance, and the second conductance is the largest erase conductance among the multiple erase conductances.

[0007] According to an embodiment of another aspect of the present invention, a modulation method of an optoelectronic synaptic device is provided, including:

[0008] Set the initial state of the channel layer to a write state with a first conductivity; adjust the parameters of the optical pulse incident on the channel layer to make the optoelectronic synaptic device present multiple erase states corresponding to multiple erase conductivities respectively; and after the channel layer presents an erase state with a second conductivity, by applying a positive electrical pulse on the substrate, make the optoelectronic synaptic device restore the write state with the first conductivity; wherein the first conductivity is less than the second conductivity, and the second conductivity is the largest erase conductivity among the multiple erase conductivities.

[0009] According to an embodiment of another aspect of the present invention, there is provided an application of the above optoelectronic synaptic device in a reconfigurable logic gate. Under the dual-mode cooperative modulation of light and electricity, the above optoelectronic synaptic device is suitable for respectively performing logic functions of "AND", "OR" and "non-material implication".

[0010] According to an embodiment of another aspect of the present invention, there is provided an application of the above optoelectronic synaptic device in associative learning bionics. Under the dual-mode cooperative modulation of light and electricity, the above optoelectronic synaptic device is suitable for simulating an extended version of the Pavlov experiment and paired associations in the monkey brain.

[0011] According to an embodiment of another aspect of the present invention, there is provided an application of an optoelectronic synaptic device array constructed by using multiple above optoelectronic synaptic devices in neuromorphic computing. Under the dual-mode cooperative modulation of light and electricity, the above optoelectronic synaptic device array is suitable for constructing a simulated neural network to realize the image classification function of a color blindness and color weakness map.

[0012] Based on the positive optoelectronic response characteristics in the ultraviolet to visible light band and the dependence of the postsynaptic current on the light source parameters, the optoelectronic synaptic device provided by the above embodiment of the present invention realizes the simulation of light-tunable synaptic plasticity. Light-tunable synaptic plasticity not only improves the energy efficiency of information processing, but also provides the possibility for realizing a more flexible and efficient optoelectronic system. Specifically, compared with an overly large erase voltage, a low-power optical input directly acts on the channel material, which can reduce the energy input of the computing system.

[0013] The optoelectronic synaptic device provided by the above embodiment of the present invention can adaptively adjust its operating state according to environmental conditions and task requirements under the dual-mode cooperative modulation of light and electricity, so as to realize a more realistic multi-modal signal processing ability for the real environment. And, based on the floating gate layer with an ultra-large storage capacity, the finely adjustable optical input and the highly sensitive channel material, the above device exhibits significant multi-bit storage characteristics. The multi-bit storage ability enables the artificial synaptic device to express more states, so as to more finely simulate the weight dynamics in the neural network and significantly improve the learning ability and generalization performance of the network. Description of the Drawings

[0014] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings of the embodiments will be briefly introduced below. Obviously, the accompanying drawings in the following description only relate to some embodiments of the present invention and do not limit the present invention.

[0015] Figure 1 3D schematic diagram of the optoelectronic synaptic device provided by the embodiment of the present invention;

[0016] Figure 2 Cross-sectional schematic diagram of the optoelectronic synaptic device provided by the embodiment of the present invention;

[0017] Figure 3 Flow schematic diagram of the preparation method of the optoelectronic synaptic device provided by the embodiment of the present invention;

[0018] Figure 4A Principle schematic diagram of the pure electronic synaptic device provided by the embodiment of the present invention during electronic writing and electronic erasing;

[0019] Figure 4B Principle schematic diagram of the optoelectronic synaptic device provided by the embodiment of the present invention during electronic writing and optical erasing;

[0020] Figure 5 Postsynaptic current of the optoelectronic synaptic device provided by the embodiment of the present invention under the irradiation of light pulses with different wavelengths;

[0021] Figure 6 Double-pulse facilitation characteristic curve of the optoelectronic synaptic device provided by the embodiment of the present invention under the irradiation of 405nm light pulses;

[0022] Figure 7A Postsynaptic current of the optoelectronic synaptic device provided by the embodiment of the present invention under the irradiation of light pulses with different light power densities;

[0023] Figure 7B Postsynaptic current of the optoelectronic synaptic device provided by the embodiment of the present invention under the irradiation of light pulses with different pulse widths;

[0024] Figure 8A Postsynaptic current of the optoelectronic synaptic device provided by the embodiment of the present invention under the irradiation of light pulses with different pulse frequencies;

[0025] Figure 8B Decay curve of the normalized postsynaptic current of the optoelectronic synaptic device provided by the embodiment of the present invention under the irradiation of different numbers of light pulses;

[0026] Figure 9 Weight change of the optoelectronic synaptic device provided by the embodiment of the present invention after electrical stimulation and optical stimulation with different intervals;

[0027] Figure 10AThe synaptic weights of the pure electro-synaptic device of Comparative Example 1 during electrical enhancement and electrical inhibition;

[0028] Figure 10B The synaptic weights of the optoelectronic synaptic device provided in Embodiment 1 of the present invention during optical enhancement and electrical inhibition;

[0029] Figure 11A The "AND" logic function realized by the optoelectronic synaptic device provided in Embodiment 1 of the present invention based on dual-mode collaborative modulation of light and electricity;

[0030] Figure 11B The "OR" logic function realized by the optoelectronic synaptic device provided in Embodiment 1 of the present invention based on dual-mode collaborative modulation of light and electricity;

[0031] Figure 11C The "non-material implication" logic function realized by the optoelectronic synaptic device provided in Embodiment 1 of the present invention based on dual-mode collaborative modulation of light and electricity;

[0032] Figures 12A to 12F The process of simulating associative learning bionics by the optoelectronic synaptic device provided in Embodiment 1 of the present invention; and

[0033] Figures 13A to 13D The learning effect of the simulated neural network constructed by the optoelectronic synaptic device array provided in the embodiments of the present invention when performing an image classification task.

[0034] Explanation of reference numerals:

[0035] 1 - Substrate;

[0036] 11 - Dielectric layer;

[0037] 12 - Insulating layer;

[0038] 2 - Floating gate layer;

[0039] 3 - Tunneling layer;

[0040] 4 - Channel layer;

[0041] 5 - Source electrode;

[0042] 6 - Drain electrode. Detailed implementation manners

[0043] To make the objectives, technical solutions, and advantages of the present invention more clearly understood, the following provides a further detailed description of the present invention in conjunction with specific embodiments and with reference to the accompanying drawings. However, the present invention can be implemented in different forms and should not be construed as limited to the embodiments presented herein. On the contrary, providing these embodiments will make the invention thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated, and the same reference numerals throughout the drawings denote the same elements.

[0044] The terms used herein are merely for the purpose of describing specific embodiments and are not intended to limit the present invention. The terms "including", "comprising", etc. used herein indicate the presence of the described features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0045] In the related art, with the rapid development of artificial intelligence technology, the accuracy requirements for image recognition are increasing day by day. However, the optical synaptic weight accuracy of existing devices is limited, which restricts their recognition accuracy in image classification tasks.

[0046] In view of this, the present invention provides an optoelectronic synaptic device, its modulation method, and applications to solve the problem of insufficient optical weight accuracy of existing synaptic devices and to realize their applications in the fields of optoelectronic logic, associative learning, and neuromorphic computing.

[0047] The optoelectronic floating-gate transistor based on two-dimensional material van der Waals heterojunction has become an important candidate for optoelectronic synaptic devices due to its high bandwidth, low crosstalk, and ultra-large storage capacity. By inducing excitatory and inhibitory current spikes with light pulses and electrical pulses respectively, such devices have successfully simulated a series of synaptic functions and are capable of efficiently performing pattern recognition tasks. By optimizing the light source parameters (such as wavelength, power, and pulse frequency), it is expected to achieve high-precision multi-bit optical synaptic weights, thereby significantly improving the accuracy of image classification and promoting the development of neuromorphic computing.

[0048] Figure 1 A three-dimensional schematic diagram of the optoelectronic synaptic device provided by an embodiment of the present invention.

[0049] Figure 2 A cross-sectional schematic diagram of the optoelectronic synaptic device provided by an embodiment of the present invention.

[0050] According to an exemplary embodiment of the present invention, the present invention provides an optoelectronic synaptic device. Referring to Figure 1 , Figure 2 as shown, it includes:

[0051] Substrate 1;

[0052] Floating gate layer 2, located on substrate 1;

[0053] A tunneling layer 3, located on the floating gate layer 2;

[0054] A channel layer 4, located on the tunneling layer 3. The channel layer 4 includes a two-dimensional rhenium disulfide material layer. The channel layer 4 generates photo-generated electron-hole pairs under the action of an optical pulse. At the same time, the floating gate layer 2 is adapted to receive photo-generated holes to regulate the conductance of the channel layer 4; and

[0055] A source electrode 5 and a drain electrode 6, respectively located on the channel layer 4;

[0056] Wherein, the initial state of the channel layer 4 presents a write state with a first conductance. By regulating the parameters of the optical pulse incident on the channel layer 4, the optoelectronic synaptic device presents multiple erase states corresponding to multiple erase conductances respectively; after the channel layer 4 presents an erase state with a second conductance, by applying a positive electrical pulse on the substrate 1, the optoelectronic synaptic device is restored to the write state with the first conductance; wherein the first conductance is less than the second conductance, and the second conductance is the largest erase conductance among the multiple erase conductances.

[0057] In some embodiments, the floating gate layer 2 includes a two-dimensional graphene material layer. The floating gate layer 2 is adapted to store charges. By using the two-dimensional graphene material layer to fabricate the floating gate layer 2, the floating gate layer 2 can achieve an ultra-large storage capacity, effectively expanding the charge storage density.

[0058] In some embodiments, the thickness of the floating gate layer 2 is less than or equal to 20 nm. For example, it can be 1 nm, 5 nm, 10 nm, 15 nm, 20 nm, but is not limited to the recited values. If the thickness of the floating gate layer 2 is too large, the ability of the gate voltage to regulate the conductance of the channel layer 4 will be weakened. By controlling the thickness of the floating gate layer 2 within the above requirements, the regulation effect of the gate voltage on the conductance of the channel layer 4 can be effectively achieved.

[0059] In some embodiments, the tunneling layer 3 includes a two-dimensional hexagonal boron nitride material layer. The two-dimensional hexagonal boron nitride material layer is a high-k (dielectric constant) material, which can achieve a more stable electrical isolation effect at the same physical thickness, ensuring the charge storage ability of the floating gate layer 2.

[0060] In some embodiments, the thickness of the tunneling layer 3 is less than or equal to 20 nm. For example, it can be 1 nm, 5 nm, 10 nm, 15 nm, 20 nm, but is not limited to the recited values. If the thickness of the tunneling layer 3 is too large, a high tunneling barrier will be caused; by controlling the thickness of the tunneling layer 3 within the above requirements, a lower tunneling barrier can be achieved, which can significantly reduce the gate voltage and dynamic power consumption.

[0061] In some embodiments, the thickness of the channel layer 4 is less than or equal to 20 nm. For example, it can be 1 nm, 5 nm, 10 nm, 15 nm, 20 nm, but is not limited to the listed values. If the thickness of the channel layer 4 is too large (greater than 20 nm), it is difficult to adjust the conductance of the channel layer through optical / electrical pulses. This is because for the same optical / electrical pulse input, the charge storage amount in the floating gate layer 2 and the channel modulation effect it causes are fixed; this means that the increment of the conductance of the channel material is certain. When the channel layer 4 is thicker, the total conductance is larger, the relative variable of conductance modulation is lower, and its switching current ratio is lower, resulting in difficulty in regulating the conductance of the channel layer 4 through optical / electrical pulses.

[0062] In an embodiment of the present invention, the source electrode 5 may include, for example, a 50 nm chromium layer (Cr) and a 250 nm gold layer (Au) located on the chromium layer. The materials of the source electrode 5 and the drain electrode 6 may be the same.

[0063] In an embodiment of the present invention, the optical pulse is between the ultraviolet and visible light bands, and the wavelength of the optical pulse can be, for example, 405 nm.

[0064] In an embodiment of the present invention, as a new two-dimensional material, rhenium disulfide has strong light absorption, high carrier mobility, and a direct bandgap characteristic independent of the number of layers. These unique physical properties make it an ideal channel material for optoelectronic synaptic devices, capable of effectively enhancing the sensitivity of optical perception and the resolution of weight update.

[0065] According to an exemplary embodiment of the present invention, the present invention provides a modulation method for an optoelectronic synaptic device, including:

[0066] Making the initial state of the channel layer 4 present a write state with a first conductance; regulating the parameters of the optical pulse incident on the channel layer 4 to make the optoelectronic synaptic device present multiple erase states corresponding to multiple erase conductances respectively; and after the channel layer 4 presents an erase state with a second conductance, by applying a positive electrical pulse on the substrate 1, making the optoelectronic synaptic device restore the write state with the first conductance; where the first conductance is less than the second conductance, and the second conductance is the largest erase conductance among the multiple erase conductances.

[0067] In an embodiment of the present invention, regulating the optical pulse includes: regulating at least one of the optical power density, optical pulse width, optical pulse frequency, and optical pulse number of the optical pulse to change the conductance of the channel layer 4.

[0068] According to an exemplary embodiment of the present invention, the present invention provides a device, including an optoelectronic synaptic device array, and the optoelectronic synaptic device array includes multiple optoelectronic synaptic devices as described above.

[0069] Figure 3 It is a schematic flow chart of the preparation method of the optoelectronic synaptic device provided by the embodiment of the present invention.

[0070] According to an exemplary embodiment of the present invention, the present invention provides a method for preparing a photoelectric synaptic device, as shown in reference to Figure 3 shown, including: operations S1 to S5.

[0071] Operation S1, transferring the floating gate layer 2 onto the substrate 1.

[0072] In some embodiments, the substrate 1 includes a dielectric layer 11 and an insulating layer 12 located on the dielectric layer 11. The dielectric layer 11 can be, for example, silicon, and the insulating layer 12 can be, for example, silicon dioxide or alumina.

[0073] In some embodiments, the dielectric layer 11 can be, for example, heavily doped p-type silicon, and the insulating layer 12 can be, for example, 285 nm thick silicon dioxide.

[0074] In an embodiment of the present invention, before transferring the floating gate layer 2 onto the substrate 1, the substrate 1 is pretreated to remove impurities on the surface of the substrate 1. Specifically, the oxygen plasma treatment technology is used to thoroughly clean the substrate 1. The specific parameters of the treatment process can be, for example: air pressure 999 Pa, power 200 W, cleaning time 5 min.

[0075] In some embodiments, the floating gate layer 2 is a graphene two-dimensional material layer. The mechanical peeling and dry transfer technologies are used to transfer the graphene two-dimensional material layer onto the substrate 1. Specifically, the tape is used to repeatedly paste the graphene bulk material to break the interlayer van der Waals force of the graphene bulk material, and the thin-layer graphene two-dimensional material layer is separated layer by layer. The peeled graphene two-dimensional material layer is transferred to the surface of polydimethylsiloxane (PDMS) on a glass slide. The thin-layer, uniform and appropriately shaped and sized graphene two-dimensional material layer is screened under an optical microscope. Through dry transfer, the graphene two-dimensional material layer on the PDMS is transferred onto the substrate 1.

[0076] Operation S2, transferring the tunneling layer 3 onto the floating gate layer 2.

[0077] In an embodiment of the present invention, the tunneling layer 3 is a hexagonal boron nitride two-dimensional material layer (h-BN). The mechanical peeling and dry transfer technologies are used to transfer the h-BN onto the floating gate layer 2. Specifically, the tape is used to repeatedly paste the hexagonal boron nitride bulk material to break the interlayer van der Waals force of the hexagonal boron nitride bulk material, and the thin-layer hexagonal boron nitride two-dimensional material layer is separated layer by layer. The peeled hexagonal boron nitride two-dimensional material layer is transferred to the surface of PDMS on a glass slide. The thin-layer, uniform and appropriately shaped and sized hexagonal boron nitride two-dimensional material layer is screened under an optical microscope. Through dry transfer, the hexagonal boron nitride two-dimensional material layer on the PDMS is transferred onto the floating gate layer 2.

[0078] Operation S3, transferring the channel layer 4 onto the tunneling layer 3.

[0079] In an embodiment of the present invention, the channel layer 4 is a two-dimensional rhenium disulfide material layer (ReS 2 ), and the ReS 2 is transferred onto the tunneling layer 3 by using mechanical exfoliation and dry transfer techniques. Specifically, the rhenium disulfide bulk material is repeatedly pasted with tape to break the interlayer van der Waals force of the rhenium disulfide bulk material, and thin-layer two-dimensional rhenium disulfide material layers are separated layer by layer. The exfoliated two-dimensional rhenium disulfide material layer is transferred to the PDMS surface on a glass slide. Under an optical microscope, thin-layer, uniform and appropriately shaped two-dimensional rhenium disulfide material layers are screened out. Through dry transfer, the two-dimensional rhenium disulfide material layer on the PDMS is transferred onto the tunneling layer 3.

[0080] Operation S4: Source electrode 5 and drain electrode 6 are respectively formed on the channel layer 4.

[0081] In an embodiment of the present invention, first, a photoresist layer is spin-coated on the channel layer 4. The photoresist layer is a positive photoresist. The photoresist layer is patterned by using electron beam lithography technology. Then, the photoresist in the exposed area of the photoresist layer is removed in a developer, and the photoresist in the unexposed area is retained; subsequently, a Cr layer and an Au layer are sequentially deposited on the channel layer 4 by using electron beam evaporation technology, and finally, it is successively immersed in acetone, isopropyl alcohol and deionized water for cleaning to remove the photoresist in the unexposed area. Among them, the vacuum degree in the electron beam lithography technology is less than 10 -5 Pa, and the vacuum degree in the electron beam evaporation technology is less than 10 -5 Pa. During the development process, the developer and isopropyl alcohol are required to clean successively.

[0082] In some embodiments, the process of spin-coating the photoresist layer on the channel layer 4 includes pre-spinning at 600 RPM for 30 seconds first, and then officially spinning at 2000 RPM for 60 seconds to obtain a uniform 500-nm photoresist, and then baking at 180°C for 90 s.

[0083] Operation S5: After the source electrode 5 and the drain electrode 6 are formed, an annealing treatment is performed so that the source electrode 5 and the drain electrode 6 respectively form ohmic contacts with the channel layer 4.

[0084] In an embodiment of the present invention, the process of performing the annealing treatment includes: in an environment of a mixed gas of 2% hydrogen and 98% nitrogen, the temperature is raised to 300°C within 16 s, held for 3 min, and then cooled to room temperature.

[0085] Figure 4A It is a schematic diagram of the principle of the pure electric synapse device provided by the embodiment of the present invention during the electron writing and electron erasing processes.

[0086] Figure 4B It is a schematic diagram of the principle of the optoelectronic synapse device provided by the embodiment of the present invention during the electron writing and optical erasing processes.

[0087] During the biological synapse simulation process, electrical stimulation (electrical pulse) is input through the substrate 1, and optical stimulation (optical pulse) is input by irradiating the channel layer 4. The channel conductance under a 2V source-drain voltage is mapped as the synaptic weight.

[0088] Reference Figure 4A As shown, a positive electrical pulse is applied to the substrate 1. The positive electrical pulse can be, for example, +40V, 1ms. Electrons in the two-dimensional rhenium disulfide material layer (ReS 2 ) tunnel through the two-dimensional hexagonal boron nitride material layer (h-BN) and are stored in the two-dimensional graphene material layer (Graphene). After removing the positive electrical pulse, the electrons stored in the two-dimensional graphene material layer (Graphene) cannot return to the two-dimensional rhenium disulfide material layer (ReS 2 ) due to the high tunneling barrier of the two-dimensional hexagonal boron nitride material layer (h-BN), resulting in a low-conductance write state of the pure electrical synaptic device. On the contrary, a negative electrical pulse is applied to the substrate 1. The negative electrical pulse can be, for example, -40V, 1ms. The electrons stored in the two-dimensional graphene material layer (Graphene) are released into the two-dimensional rhenium disulfide material layer (ReS 2 ), causing the pure electrical synaptic device to switch to a high-conductance erase state.

[0089] Reference Figure 4B As shown, when an optical pulse is applied to the two-dimensional rhenium disulfide material layer (ReS 2 ), a large number of photo-generated electron-hole pairs are generated in the two-dimensional rhenium disulfide material layer (ReS 2 ) under the action of the optical pulse. Under the influence of the electrons stored in the two-dimensional graphene material layer (Graphene), the photo-generated holes overcome the tunneling barrier and are stored in the two-dimensional graphene material layer (Graphene). Due to the capacitive coupling of graphene and the accumulation of photo-generated electrons, the conductivity of the ReS 2 channel shows a non-volatile enhancement effect. Specifically, since the photo-generated holes are stored in the two-dimensional graphene material layer, the photo-generated holes (positive charges) cause the accumulation of electrons at the h-BN / ReS 2 interface, increasing the mobility of the carriers in the channel layer; and the photo-generated holes tunnel into the two-dimensional graphene material layer, and the remaining electrons in the channel layer increase the carrier concentration in the channel layer. The increase in the mobility and carrier concentration of the carriers in the channel layer results in an increase in the channel layer conductance; and due to the strong charge storage ability of the floating gate layer, the conductivity of the ReS 2 channel shows a non-volatile enhancement effect. By reducing the power and width of the optical pulse, the amplitude of the unit conductance change of the device is reduced, and the resolution of the synaptic weight update is improved.

[0090] Figure 5The postsynaptic current (i.e., source-drain current) of the optoelectronic synaptic device provided by the embodiment of the present invention under the irradiation of optical pulses with different wavelengths.

[0091] Reference Figure 5 As shown, optical pulses with wavelengths of 255 nm, 365 nm, 405 nm, 520 nm, and 638 nm (optical power of 100 mW / cm 2 , and irradiation duration of 1 s) are used to irradiate the optoelectronic synaptic device. The optoelectronic synaptic device exhibits significant positive optoelectronic response characteristics in the wavelength range of 255 nm to 638 nm, and the response current increases with the decrease of wavelength. Based on the optical sensing characteristics, the 405 nm laser with the most significant response is selected as the light source for optical synaptic plasticity simulation.

[0092] Figure 6 The paired-pulse facilitation characteristic curve of the optoelectronic synaptic device provided by the embodiment of the present invention under the irradiation of 405 nm optical pulses, where Figure 6 the abscissa represents the first interval time, that is, the interval time between two optical stimulations, Figure 6 the ordinate represents the paired-pulse facilitation value (PPF index), Figure 6 the abscissa of the inset in Figure 6 represents time,

[0093] Reference Figure 6 As shown, two consecutive optical stimulations are applied to the optoelectronic synaptic device, that is, optical pulses with a wavelength of 405 nm and a power of 1 mW / cm 2 . According to the fitting curve, as the first interval time (the interval time between two optical stimulations) becomes smaller, the paired-pulse facilitation value of the optoelectronic synaptic device becomes larger, and the synaptic enhancement effect of the optoelectronic synaptic device is more significant.

[0094] Paired-Pulse Facilitation (PPF) means that when two consecutive optical pulse stimulations are applied, the response amplitude A2 of the second optical pulse is greater than the response amplitude A1 of the first optical pulse. The PPF effect is one of the short-term plasticity characteristics of biological synapses. Figure 6 The inset in

[0095] Figure 7A shows a typical curve similar to that of biological synapses, indicating that the optoelectronic synaptic device realizes the simulation of paired-pulse facilitation (PPF), and the device realizes a preliminary short-term memory effect.

[0096] Figure 7B The postsynaptic current of the optoelectronic synaptic device provided by the embodiment of the present invention under the irradiation of optical pulses with different pulse widths.

[0097] Reference Figure 7A As shown, the smaller the intensity (optical power density) of the optical pulse, the smaller the excitatory postsynaptic current induced by the charge tunneling effect of the optoelectronic synaptic device. Therefore, by reducing the power of the optical pulse, the amplitude of the unit conductance change of the device can be reduced, and the resolution of synaptic weight update can be improved.

[0098] Reference Figure 7B As shown, the smaller the pulse width of the optical pulse, the smaller the excitatory postsynaptic current induced by the charge tunneling effect of the optoelectronic synaptic device. Therefore, by reducing the width of the optical pulse, the amplitude of the unit conductance change of the device can be reduced, and the resolution of synaptic weight update can be improved.

[0099] Figure 8A The postsynaptic current of the optoelectronic synaptic device provided by the embodiment of the present invention under the irradiation of optical pulses with different pulse frequencies.

[0100] Figure 8B The decay curve of the normalized postsynaptic current of the optoelectronic synaptic device provided by the embodiment of the present invention under the irradiation of different numbers of optical pulses.

[0101] Apply optical pulse sequences with different frequencies to the optoelectronic synaptic device. Reference Figure 8A As shown, the lower the frequency of the optical pulse sequence, the lower the amplitude of the unit conductance change of the device. Therefore, by reducing the frequency of the optical pulse, the resolution of synaptic weight update can be improved.

[0102] Reference Figure 8B As shown, by repeatedly applying presynaptic optical pulses, the memory consolidation process of the human brain is simulated, and the transition from short-term spiking plasticity (STSP) based on optical pulses to long-term spiking plasticity (LTSP) based on optical pulses is realized. Specifically, as the number of pulses increases, the retention time of the synaptic weight (decreases to 20% of the initial value) increases from 50 s to 3 minutes (fitting result), which indicates the realization of the transition from short-term plasticity to long-term plasticity. Obviously, the postsynaptic current of the optoelectronic synaptic device is closely related to the optical power density, optical pulse width, optical pulse frequency, and number of optical pulses of the optical pulse.

[0103] Figure 9 The weight change of the optoelectronic synaptic device provided by the embodiment of the present invention after electrical and optical stimulations with different interval times; where Figure 9 the abscissa represents the second interval time, that is, the interval time between the electrical stimulation and the optical stimulation, Figure 9 the ordinate represents the weight change, that is, the relative change amount of the postsynaptic current.

[0104] Among them, for example, an interval time of -5 s means that the interval time between the electrical stimulus and the optical stimulus is -5 s, that is, the optical stimulus is applied first, and then the electrical stimulus is applied, and the time difference between the two is 5 s.

[0105] Figure 9 In the illustration of [], the abscissa represents time and the ordinate represents the postsynaptic current. See Figure 9 In the illustration of [], an electrical stimulus is applied to the optoelectronic synaptic device at the 2nd s, and the postsynaptic current of the optoelectronic synaptic device is W i ; an optical stimulus is applied to the optoelectronic synaptic device at the 3rd s, and the optical stimulus ends at the 4th s. The postsynaptic current of the optoelectronic synaptic device is W f ; the first interval time is +1 s, the postsynaptic current of the optoelectronic synaptic device increases, and the relative change amount of the postsynaptic current (i.e., the synaptic weight) is ΔW, ΔW = (W f -W i ) / W i .

[0106] Refer to Figure 9 As shown, the synaptic weight is updated by adjusting the interval time between the electrical stimulus (an electrical signal with a voltage of -10 V and a pulse width of 1 ms) applied to the synaptic front end (applied on the substrate) and the optical stimulus (an optical pulse with a light power of 1 mW / cm² and a pulse width of 1 s) applied to the synaptic back end (applied on the channel layer). This learning rule based on the order of neuron pulse signals to adjust the connection strength enables the neural network to adapt to environmental changes by dynamically adjusting the synaptic connection strength.

[0107] It should be noted that the optoelectronic tests are carried out in a room temperature and dark room environment, using a Metatest E2 fiber-coupled optoelectronic test probe station. The probe station is placed on an optical platform to avoid external vibration interference. The voltage input is provided by a Keithley 2450 single-channel system digital source meter, and the optical input is generated by an mLaser series light source. The source meter can apply a voltage to the probe arm and the sample holder and synchronously measure the voltage and current values of the ports.

[0108] The designed optoelectronic synaptic device is schematically described below. It should be noted that this illustrative example is only a specific embodiment of the present invention and does not limit the protection scope of the present invention.

[0109] Comparative Example 1

[0110] A pure electrical synaptic device is prepared. Specifically, the pure electrical synaptic device includes: a substrate 1; a floating gate layer 2 located on the substrate 1; a tunneling layer 3 located on the floating gate layer 2; a channel layer 4 located on the tunneling layer 3, and the channel layer 4 includes a two-dimensional molybdenum disulfide material layer; and a source electrode 5 and a drain electrode 6, which are respectively located on the channel layer 4.

[0111] A positive electrical pulse is applied to the substrate 1 of the purely electrical synaptic device to regulate the purely electrical synaptic device to present a writing state; or a negative electrical pulse is applied to the substrate 1 to regulate the purely electrical synaptic device to present an erasing state.

[0112] Example 1

[0113] Prepare an optoelectronic synaptic device. Specifically, the optoelectronic synaptic device includes a substrate 1; a floating gate layer 2 located on the substrate 1; a tunneling layer 3 located on the floating gate layer 2; a channel layer 4 located on the tunneling layer 3, and the channel layer 4 includes a two-dimensional molybdenum disulfide material layer; and a source electrode 5 and a drain electrode 6 respectively located on the channel layer 4.

[0114] The initial state of the channel layer 4 is made to present a writing state with a first conductance; the parameters of the light pulse incident on the channel layer 4 are regulated to make the optoelectronic synaptic device present a plurality of erasing states respectively corresponding to a plurality of erasing conductances; and after the channel layer 4 presents an erasing state with a second conductance, by applying a positive electrical pulse to the substrate 1, the optoelectronic synaptic device is restored to the writing state with the first conductance; wherein the first conductance is less than the second conductance, and the second conductance is the maximum erasing conductance among the plurality of erasing conductances.

[0115] Figure 10A For the synaptic weights of the purely electrical synaptic device of Comparative Example 1 during electrical enhancement and electrical inhibition processes.

[0116] Figure 10B For the synaptic weights of the optoelectronic synaptic device provided in Example 1 of the present invention during optical enhancement and electrical inhibition processes.

[0117] Reference Figure 10A As shown, the number of synaptic weights of the purely electrical synaptic device of Comparative Example 1 during the electrical enhancement process (Electrical Long-Term Potentiation, abbreviated as Electrical LTP) is 128 (7 bits), and the electrical pulse parameters are set to -10V, pulse width 1ms, and pulse frequency 1Hz; during the electrical inhibition process (Electrical Long-Term Depression, abbreviated as Electrical LTD), the number of synaptic weights is 128 (7 bits), and the electrical pulse parameters are set to +9V, pulse width 1ms, and pulse frequency 1Hz.

[0118] Reference Figure 10B As shown, for the optoelectronic synaptic device provided in Example 1 of the present invention, the number of synaptic weights during the optical enhancement process (Optiacl Long-Term Potentiation, abbreviated as Optiacl LTP) reaches 1024 (10 bits), where the light pulse parameters are set to a power of 1mW / cm 2, Pulse width 100 ms, pulse frequency 1 Hz. The number of synaptic weights during the Electrical Long-Term Depression (abbreviated as Electrical LTD) is 128 (7 bits), where the electrical pulse parameters are set to +9V, pulse width 1 ms, and pulse frequency 1 Hz. Specifically, an optical pulse is applied to the channel layer 4 of the optoelectronic synaptic device, and the conductance of the optoelectronic synaptic device is regulated by the optical pulse, enabling the conductance of the optoelectronic synaptic device to achieve 1024 states, and the optoelectronic synaptic device realizes multi-bit (10-bit) storage capacity. The multi-level conductance states of the optical synapse provide a computational paradigm closer to the biological brain, promoting the development of more efficient and intelligent bionic vision neural networks.

[0119] Applying the optoelectronic synaptic device provided in Embodiment 1 of the present invention to a reconfigurable logic gate, based on the dual-mode cooperative modulation of light and electricity, the optoelectronic synaptic device can perform various logic functions using optical and electrical stimuli, respectively realizing the logic functions of "AND", "OR", and "non-material implication".

[0120] Figure 11A This is the "AND" logic function realized by the optoelectronic synaptic device provided in Embodiment 1 of the present invention based on the dual-mode cooperative modulation of light and electricity.

[0121] Under the dual-mode cooperative modulation of light and electricity, the input signal includes optical and electrical stimuli. The optical stimulus is an optical pulse with a power of 1 mW / cm 2 and a pulse width of 1 s, where the state of no light is defined as logic "0" and the state of having light is defined as logic "1"; the electrical stimulus is an electrical pulse with a voltage of -5V and a pulse width of 10 ms, where the off state of the electrical pulse is defined as logic "0" and the on state of the electrical pulse is defined as logic "1".

[0122] Set the threshold current to 100 nA. The postsynaptic current less than or equal to 100 nA is defined as the output result of "0", and the postsynaptic current greater than 100 nA is defined as the output result of "1". The postsynaptic current of the optoelectronic synaptic device is jointly determined by the optical power density of the optical pulse and the amplitude of the electrical pulse.

[0123] Refer to Figure 11A As shown, electrical and optical stimuli are applied to the optoelectronic synaptic device. When the input signals are (0,0), (0,1), and (1,0) respectively, the output results are all "0". When the optical stimulus includes an optical pulse with a power of 1 mW / cm 2 and a pulse width of 1 s, and the electrical stimulus includes an electrical pulse with a voltage of -5 V and a pulse width of 10 ms, that is, when the input signal is (1,1), the output result is "1", realizing the "AND" logic function.

[0124] Figure 11B The "OR" logic function implemented by the optoelectronic synaptic device provided in Embodiment 1 of the present invention is based on the dual - mode collaborative modulation of light and electricity.

[0125] Under the dual - mode collaborative modulation of light and electricity, the input signals include optical stimuli and electrical stimuli. The optical stimulus is a light pulse with a power of 100 mW / cm 2 and a pulse width of 1 s. Here, the state without light is defined as logic "0", and the state with light is defined as logic "1". The electrical stimulus is an electrical pulse with a voltage of - 10 V and a pulse width of 10 ms. The off - state of the electrical pulse is defined as logic "0", and the on - state of the electrical pulse is defined as logic "1".

[0126] The threshold current is set to 100 nA. A postsynaptic current less than or equal to 100 nA is defined as an output result of "0", and a postsynaptic current greater than 100 nA is defined as an output result of "1". The postsynaptic current of the optoelectronic synaptic device is jointly determined by the optical power density of the light pulse and the amplitude of the electrical pulse.

[0127] Reference Figure 11B As shown, when electrical stimuli and optical stimuli are applied to the optoelectronic synaptic device, when the input signal is (0, 0), the output result is "0". When the input signals are (0, 1), (1, 0), and (1, 1) respectively, the output results are all "1", realizing the "OR" logic function.

[0128] Figure 11C The "non - material implication" logic function implemented by the optoelectronic synaptic device provided in Embodiment 1 of the present invention is based on the dual - mode collaborative modulation of light and electricity.

[0129] Under the dual - mode collaborative modulation of light and electricity, the input signals include optical stimuli and electrical stimuli. The optical stimulus is a light pulse with a power of 100 mW / cm 2 and a pulse width of 1 s. Here, the state without light is defined as logic "0", and the state with light is defined as logic "1". The electrical stimulus is an electrical pulse with a voltage of 10 V and a pulse width of 10 ms. The off - state of the electrical pulse is defined as logic "0", and the on - state of the electrical pulse is defined as logic "1".

[0130] The threshold current is set to 100 nA. A postsynaptic current less than or equal to 100 nA is defined as an output result of "0", and a postsynaptic current greater than 100 nA is defined as an output result of "1". The postsynaptic current of the optoelectronic synaptic device is jointly determined by the optical power density of the light pulse and the amplitude of the electrical pulse.

[0131] Reference Figure 11CAs shown, electrical and optical stimuli are applied to the optoelectronic synaptic device. When the input signal is (1, 0), the output result is "1". When the input signals are (0, 0), (0, 1), and (1, 1) respectively, the output result is "0". That is to say, only when the optical pulse is in the on state and the electrical pulse is in the off state, the output result is "1", realizing the "non-material implication" logic function. Specifically, non-material implication is a binary logic that outputs 1 only when the input is (1, 0), and outputs 0 in the remaining cases (0, 0), (0, 1), and (1, 1). Its logic can be expressed as "A holds and B does not hold"; this logic function can be used for strict discrimination of specific conditions in fields such as circuit design and fault detection.

[0132] Figures 12A to 12F This is the process of simulating associative learning of the optoelectronic synaptic device provided in Embodiment 1 of the present invention.

[0133] Refer to Figure 12A As shown, a neutral stimulus (such as a bell sound) can trigger a conditioned reflex by being paired with an unconditioned stimulus (such as food). A 100 nA output current is selected as the threshold for saliva secretion. Electrical pulses (-10 V, 10 ms) simulate the bell sound to trigger the conditioned reflex, while optical pulses (405 nm, 100 mW / cm 2 , 0.5 s) simulate food stimuli to induce saliva secretion.

[0134] Figure 12B , Figure 12C , Figure 12D Shows an extended version of the Pavlov experiment, including the establishment, extinction, reconstruction, and forgetting of conditioned reflexes.

[0135] Refer to Figure 12B As shown, before training, the postsynaptic current generated by 10 electrical pulses is 80 nA, which is not sufficient to trigger saliva secretion; while 10 optical pulses increase the postsynaptic current to 240 nA, far exceeding the threshold. During training, 10 synchronous electrical and optical pulses establish the association between the bell sound and food. After training, electrical stimulation alone can increase the postsynaptic current to 130 nA, indicating that the conditioned reflex has been established.

[0136] Refer to Figure 12C As shown, after completing training and taking a 100-second break, the same electrical stimulation (10 electrical pulses) no longer triggers saliva secretion, indicating that the conditioned reflex has disappeared. Due to the remaining photo-generated electrons in the channel, the conditioned reflex can be reconstructed through fewer retraining cycles. After 5 synchronous electrical and optical pulse retrainings, electrical stimulation increases the postsynaptic current to 120 nA, re-establishing the conditioned reflex.

[0137] Refer to Figure 12DAs shown, after a 500 - second rest, the association between the bell sound and food completely disappeared, and the device conductivity returned to its initial state. After 5 times of retraining with synchronous electrical and optical pulses, the bell sound stimulation (10 electrical pulses) failed to trigger salivation.

[0138] Figure 12A 、 12E Figures 12E and 12F show the demonstration process of the above - mentioned optoelectronic synaptic device simulating paired - associative learning.

[0139] Reference Figure 12A As shown, in the paired - associative task of the monkey brain, by repeatedly pairing the target item (such as color) with a specific stimulus (such as fruit), an association between two unrelated objects is formed. Under the dual - modal co - modulation of light and electricity, a paired relationship between two colors and two fruits is successfully established.

[0140] Output currents lower than 200 nA and higher than 300 nA represent invalid responses and pain perception respectively, while when the output current is between 200 and 300 nA, the paired relationship is successfully established.

[0141] Electrical pulse sequences (10 ms width, 1 s period, 10 pulses) and optical pulse sequences (405 nm, 0.5 s width, 1 s period, 10 pulses) are used to simulate fruits and colors. Electrical pulses with amplitudes of - 10 V and - 5 V represent banana and grape (signal 1 and signal 2) respectively, while optical pulses with light intensities of 0.2 mW / cm 2 and 1 mW / cm 2 are used to represent yellow and purple cards (signal 1' and signal 2') respectively.

[0142] Reference Figure 12E As shown, before training, when signals 1 and 1' are synchronously input, the postsynaptic current output is 100 nA, indicating an invalid pairing. During training, 5 times of synchronous signals 1 and 1' establish a paired relationship between banana and yellow card. After training, when signals 1 and 1' are synchronously input, the postsynaptic current output is 270 nA, indicating a successful pairing. Similarly, signals 1 and 2' are paired for training. After training, when signals 1 and 2' are synchronously input, the postsynaptic current output is 440 nA, and pain perception leads to a failed pairing.

[0143] Reference Figure 12FAs shown, before training, when the synchronous input signals 2 and 2' were input, the output postsynaptic current was 100 nA, indicating that the pairing was invalid. During training, the synchronous signals 2 and 2' were presented 5 times to establish the pairing relationship between the grape and the purple card. After training, when the synchronous input signals 2 and 2' were input, the output postsynaptic current was 280 nA, indicating that the pairing was successful. Similarly, the pairing training was performed on signals 2 and 1'. After training, when the synchronous input signals 2 and 1' were input, the output postsynaptic current was 90 nA, indicating that the pairing was invalid. The establishment of this paired memory depends on the excitation of photo-generated electrons, while forgetting is controlled by the spontaneous relaxation of electrons.

[0144] Figures 13A to 13D This is the learning effect of the simulated neural network constructed by the optoelectronic synaptic device array provided in the embodiment of the present invention when performing an image classification task.

[0145] Figure 13A This is a schematic diagram of the simulated neural network constructed for the synaptic device, which includes an input layer (784 neurons), a hidden layer (100 neurons), and an output layer (5 neurons).

[0146] The optoelectronic synaptic device provided by the present invention is suitable for constructing a simulated neural network to realize the image classification function of color blindness and color weakness maps. The color blindness and color weakness maps are preprocessed and adjusted to 28×28 pixels to match the input neurons, and finally classified into one of five categories: "animal" (0), "graph" (1), "number" (2), "English word" (3), and "Chinese word" (4).

[0147] The backpropagation algorithm is used in the training process. The input layer and the hidden layer receive 10,000 initial samples and their weighted sums, and after activation, they are passed to the output layer. During the test, 1000 test images are used to evaluate the pattern recognition capabilities of the electrical synaptic device and the optoelectronic synaptic device.

[0148] The test results of the pure electrical synaptic device in Comparative Example 1 (refer to Figure 10A shown) are used as the synaptic weights for the training of the simulated neural network and input into the Figure 13A simulated neural network for training. The dataset is trained during the training process and verified after the training is completed.

[0149] The test results of the optoelectronic synaptic device in Embodiment 1 of the present invention (refer to Figure 10B shown) are used as the synaptic weights for the training of the simulated neural network and input into the Figure 13A simulated neural network for training. The dataset is trained during the training process and verified after the training is completed.

[0150] Figure 13B This is a schematic diagram of the equivalent circuit of the optoelectronic synaptic device array.

[0151] Reference Figure 13B As shown, multiple optoelectronic synaptic devices form an optoelectronic synaptic device array through array arrangement, and the optoelectronic synaptic device array operates a simulated neural network.

[0152] Optical pulses are input through bit line 1 to simulate Figure 10B the process of optical enhancement of synaptic weights in Figure 10A ; electrical pulses (negative electrical pulses) are input through word lines to simulate

[0153] Figure 13C the process of electronic enhancement of synaptic weights in

[0154] Reference Figure 13C As shown, when the pure electrical synaptic device array is applied to an artificial neural network, in the artificial neural network, after 200 training cycles, the pure electrical synaptic device provided in Comparative Example 1 achieved an accuracy rate of 95.8% in the image classification task. The optoelectronic synaptic device provided in Embodiment 1 of the present invention achieved an accuracy rate of 98.8% in the image classification task, and the recognition accuracy rate increased by 3%.

[0155] Figure 13D It is a comparison chart of the confusion matrices of the image classification effects of the pure electrical synaptic device provided in Comparative Example 1 and the optoelectronic synaptic device array provided in Embodiment 1 of the present invention.

[0156] Reference Figure 13D As shown, compared with the pure electrical synaptic device array of Comparative Example 1, the recognition accuracy rate of the image classification effect of the optoelectronic synaptic device array of Embodiment 1 of the present invention is significantly improved. The optoelectronic synaptic array of Embodiment 1 of the present invention realizes more accurate image classification under the dual-modal cooperative modulation of light and electricity. That is to say, the optoelectronic synaptic device with multi-bit storage capacity provided in the embodiments of the present invention provides a promising solution for the development of efficient neuromorphic computing systems.

[0157] The specific embodiments described above further elaborate on the object, technical solution, and beneficial effects of the present invention. It should be understood that the above description is only for the specific embodiments of the present invention and is not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A photoelectric synapse device, characterized in that: include: Substrate (1); A floating gate layer (2) located on the substrate (1); A tunneling layer (3), located on the floating gate layer (2); A channel layer (4) is located on the tunneling layer (3), the channel layer (4) comprises a two-dimensional material layer of rhenium disulfide, the channel layer (4) generates photogenerated electron-hole pairs under the action of light pulses, and the floating gate layer (2) is suitable for receiving photogenerated holes to regulate the conductivity of the channel layer (4); as well as A source electrode (5) and a drain electrode (6), respectively located on the channel layer (4); The initial state of the channel layer (4) presents a write state of a first conductance, and by adjusting the parameters of a light pulse incident on the channel layer (4), the photoelectric synapse device presents a plurality of erased states corresponding to the plurality of erased conductances respectively; After the channel layer (4) presents an erased state of a second conductance, a positive electrical pulse is applied to the substrate (1) to restore the photoelectric synapse device to a written state of a first conductance; wherein the first conductance is smaller than the second conductance, and the second conductance is the largest erased conductance among the multiple erased conductances.

2. The optoelectronic synapse device according to claim 1, characterized in that: The floating gate layer (2) comprises a graphene two-dimensional material layer; The thickness of the floating gate layer (2) is less than or equal to 20 nm.

3. The optoelectronic synapse device according to claim 1, characterized in that: The tunneling layer (3) comprises a hexagonal boron nitride two-dimensional material layer; The thickness of the tunneling layer (3) is less than or equal to 20 nm.

4. The optoelectronic synapse device according to claim 1, characterized in that: The thickness of the channel layer (4) is less than or equal to 20 nm.

5. The optoelectronic synapse device according to claim 1, characterized in that: The light pulses are in the range from ultraviolet to visible light.

6. A modulation method for an optoelectronic synapse device according to any one of claims 1 to 5, characterized in that: include: Making the initial state of the channel layer (4) present a writing state of the first conductivity; Regulating the parameters of the light pulse incident on the channel layer (4) so ​​that the photoelectric synapse device presents a plurality of erased states corresponding to the plurality of erased conductances; as well as After the channel layer (4) presents an erased state of a second conductivity, a positive electrical pulse is applied to the substrate (1) to restore the photoelectric synapse device to a written state of the first conductivity; wherein the first conductivity is smaller than the second conductivity, and the second conductivity is the largest erased conductivity among the multiple erased conductivities.

7. The modulation method according to claim 6, characterized in that: The parameters for controlling the light pulse incident on the channel layer (4) include: At least one of the optical power density, optical pulse width, optical pulse frequency and optical pulse quantity of the optical pulse is regulated to change the conductivity of the channel layer (4).

8. An application of the optoelectronic synapse device according to any one of claims 1 to 5 in a reconfigurable logic gate, characterized in that: Under the dual-mode cooperative modulation of light and electricity, the optoelectronic synapse device is suitable for performing the logical functions of "AND", "OR" and "non-essential implication" respectively.

9. An application of the optoelectronic synaptic device according to any one of claims 1 to 5 in associative learning bionics, characterized in that: Under the dual-modal coordinated modulation of light and electricity, the optoelectronic synaptic device is suitable for simulating an extended version of Pavlov's experiment and paired associations in the monkey brain.

10. An application of an optoelectronic synaptic device array constructed by using a plurality of optoelectronic synaptic devices according to any one of claims 1 to 5 in neuromorphic computing, characterized in that: Under the dual-modal coordinated modulation of light and electricity, the optoelectronic synaptic device array is suitable for constructing a simulated neural network to realize the image classification function of color blindness and color weakness maps.

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