TOPCon battery and preparation method thereof

Abstract

The invention relates to a TOPCon battery and a preparation method thereof.Ohmic contact is formed between metal grid lines on the front face of the TOPCon battery and a P + + area of a silicon substrate in a contact point mode, the contact area of the metal grid lines and the silicon substrate is small, a low-damage metal contact structure can be achieved, and therefore low compounding is achieved while low contact resistance is guaranteed, and the performance of the TOPCon battery is improved. The damage to the silicon substrate is smaller, the performance of the polycrystalline silicon can be fully exerted, the damage to the passivation layer is reduced, the open-circuit voltage is improved, and the battery efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the field of solar cells, and particularly to a TOPCon cell and a preparation method thereof. Background Art

[0002] TOPCon, i.e., tunnel oxide passivated contact cell. The mainstream TOPCon cells use N-type silicon wafers. First, a 1-2 nm ultra-thin oxide layer is prepared on the back of the cell, and then a polysilicon layer is deposited on the oxide layer. Then, antireflection films are deposited on the front and back sides. After that, annealing crystallization is carried out to enhance the passivation effect. In the TOPCon process, lasers are mainly applied to the boron diffusion + SE process. Compared with the simple boron diffusion process of traditional TOPCon, the application of laser technology can be combined with it to form an SE structure, thereby boosting the conversion efficiency by more than 0.3%.

[0003] Currently, in the prior art, high-temperature sintering is used for screen-printed metal grid lines. The metal paste will ablate the film layer structure, causing great damage, resulting in a decline in the passivation performance and electrical performance of the cell.

[0004] Currently, cases of laser application for assisted sintering have been studied at home and abroad. Through laser-assisted sintering, the efficiency can be increased by more than 0.5%, and it is currently gradually moving towards mass production.

[0005] The invention patent CN116705903A discloses a method for laser sintering of crystalline silicon solar cells, including: preparing in advance a crystalline silicon solar cell with patterned metal grid lines on both the front and back surfaces; drying the metal grid lines on the front and back surfaces of the crystalline silicon solar cell to volatilize the organic materials in the metal grid lines to solidify the metal grid lines; then irradiating the metal grid lines on the front and back surfaces of the crystalline silicon solar cell with a laser and applying a positive bias voltage to the metal grid lines to sinter the metal grid lines; the crystalline silicon solar cell is an N-type cell; the positive bias voltage is 1.0 - 15.0 V, and the loading time is 0.1 - 2.5 s. This method can significantly reduce the peak power of laser sintering, shorten the sintering time, expand the process window, reduce the requirements for the stability of the laser system, and improve the metallization performance of the cell; and it takes into account the contact performance, processing efficiency, and production capacity. However, there is no pre-sintering, and both grid line curing and sintering are processed by lasers. Laser processing will cause certain damage to the silicon substrate, and in this method, ohmic contact is formed by directly contacting all parts of the grid line with the silicon substrate, and the contact area with the silicon substrate is relatively large, which may increase the recombination area. Summary of the Invention

[0006] To overcome the defects of the prior art, the present invention provides a TOPCon cell and a preparation method thereof.

[0007] The first aspect of the present invention provides a TOPCon cell, which includes, from bottom to top, a back antireflection layer, a phosphorus-doped polysilicon layer, a tunneling layer, a silicon substrate, a passivation layer, and a front antireflection layer. Among them, except for the lightly doped P + region on the front surface of the silicon substrate, there is also a heavily doped P ++ region. The front metal grid lines are in contact with the front antireflection film, the passivation layer, and the P ++ region of the silicon substrate from top to bottom. The P ++ region of the silicon substrate coincides with the projection of the front metal grid line on the horizontal plane, and the horizontal width of the contact region formed by the front metal grid line and the P ++ region of the silicon substrate is less than the line width of the metal grid line. The contact between the metal grid line and the P ++ region of the silicon substrate is an ohmic contact in the form of a point contact, and the contact resistivity of the contact point is 1.2 - 1.4 mΩ·cm 2 .

[0008] For the TOPCon cell according to the first aspect, the boron doping concentration in the P ++ region is 1.0E18 - 1.0E21 cm -3 , the boron doping concentration in the P + region is 5.0E17 - 1.0E19 cm -3 , and the boron doping concentration in the P ++ region is higher than the boron doping concentration in the P + region.

[0009] For the TOPCon cell according to the first aspect, the thickness of the front antireflection layer is 55 - 95 nm, preferably 75 - 85 nm;

[0010] the thickness of the passivation layer is 5 - 20 nm, preferably 7 - 12 nm;

[0011] the thickness of the P ++ region is 1.5 - 2.5 μm, preferably 1.8 - 2.0 μm.

[0012] For the TOPCon cell according to the first aspect, the material of the front antireflection layer and / or the back antireflection layer is selected from one or more of the following: silicon nitride, silicon oxynitride, silicon oxide.

[0013] For the TOPCon cell according to the first aspect, the material of the passivation layer is aluminum oxide.

[0014] The second aspect of the present invention provides a method for preparing the TOPCon cell of the first aspect, and this method includes:

[0015] (1) Perform boron doping on the front surface of the silicon substrate to form a heavily doped P ++Region and lightly doped P + region, wherein the P ++ region corresponds to the pattern of the front metal gate line;

[0016] (2) A passivation layer and a front antireflection layer are sequentially prepared on the front of the silicon substrate obtained in step (1), and a tunneling layer, a phosphorus-doped polysilicon layer, and a back antireflection layer are sequentially prepared on the back;

[0017] (3) Printing and pre-sintering the front metal gate line on the front of the battery device obtained in step (2), and performing laser-assisted induced sintering on the pre-sintered front metal gate line;

[0018] (4) A back metal electrode is prepared on the back of the battery device obtained in step (3) to obtain the TOPCon battery.

[0019] According to the method of the second aspect, in step (3), the power of the pre-sintering is 1000W to 3000W, preferably 1800 to 2200W;

[0020] The temperature of the pre-sintering is 400°C to 800°C, preferably 650 to 750°C;

[0021] The time of the pre-sintering is 10s to 200s, preferably 30 to 80s.

[0022] According to the method of the second aspect, in step (3), the laser-assisted induced sintering includes applying a forward deflection voltage of 5V to 30V, preferably 11 to 18V, to the metal gate line; and / or

[0023] The processing time of the laser-induced assisted sintering is 0.5 to 3s, preferably 1 to 2s.

[0024] According to the method of the second aspect, in step (3), the sintering temperature of the laser-induced assisted sintering is 100 to 900°C, preferably 100 to 600°C, more preferably 100 to 500°C; and / or

[0025] The laser power of the laser-induced assisted sintering is 25 to 65W, preferably 40 to 50W.

[0026] According to the method of the second aspect, in step (2), the front antireflection layer and / or the back antireflection layer are prepared by a plasma deposition method; and / or

[0027] The passivation layer is prepared by an atomic layer deposition method.

[0028] The TOPCon battery of the present invention has the following beneficial effects but is not limited to:

[0029] The TOPCon cell of the present invention forms a specific metal contact structure on the front side of the cell through laser-assisted sintering, and only ablates the metal paste of the P ++ layer to form an ohmic contact with the silicon substrate, and forms a metal-silicon matrix contact in the form of contact points. The metal grid lines of the TOPCon cell with this contact structure have a small contact area with the silicon matrix, and a low-damage metal contact structure can be achieved. While ensuring a low contact resistance, low recombination is also achieved, and the damage to the silicon matrix is smaller, the performance of polysilicon can be fully exerted, the damage to the passivation layer is reduced, the open-circuit voltage is increased, and the cell efficiency is improved. Description of the Drawings

[0030] Figure 1 Shows a schematic structural diagram of the TOPCon cell of the present invention.

[0031] Figure 2 Shows a partial schematic diagram of the front grid line contact area of the TOPCon cell of the present invention.

[0032] Figure 3 Shows a partial schematic diagram of the front grid line contact area of the TOPCon cell of the present invention.

[0033] Figure 4 Shows a partial schematic diagram of the front grid line contact area of the TOPCon cell of the present invention.

[0034] Figure 5 Shows a partial schematic diagram of the front grid line contact area of the TOPCon cell of the present invention.

[0035] Description of the Reference Numerals:

[0036] 1. Front antireflection layer; 2. Passivation layer; 3. P + region; 4. Silicon substrate; 5. Tunneling layer; 6. Polysilicon layer; 7. Back antireflection layer; 8. P ++ region; 9. Back metal electrode; 10. Front metal grid line. Detailed Description of the Embodiments

[0037] The present application will be further described in detail below with reference to the drawings and embodiments. Through these descriptions, the features and advantages of the present application will become more clearly defined.

[0038] The special term "exemplary" here means "serving as an example, embodiment or illustration". Any embodiment described as "exemplary" here does not have to be construed as superior to or better than other embodiments. Although various aspects of the embodiments are shown in the drawings, the drawings do not have to be drawn to scale unless otherwise specified.

[0039] In addition, the technical features involved in different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0040] Before elaborating on the technical solution of the present invention, the terms used herein are defined as follows:

[0041] The term "TOPCon" refers to: Tunnel Oxide Passivating Contacts, that is, tunneling oxide passivation contacts.

[0042] The term "P ++ region" refers to: the region on the surface of the silicon substrate where boron is heavily doped.

[0043] The term "P + region" refers to: the region on the surface of the silicon substrate where boron is lightly doped.

[0044] The present invention provides a TOPCon cell, which includes, from bottom to top, a back antireflection layer, a phosphorus-doped polysilicon layer, a tunneling layer, a silicon substrate, a passivation layer, and a front antireflection layer arranged in sequence. Among them, except for the lightly doped P + region, the front of the silicon substrate also includes a heavily doped P ++ region. The front metal grid lines are in contact with the front antireflection film, the passivation layer, and the P ++ region of the silicon substrate from top to bottom. The P ++ region of the silicon substrate coincides with the projection of the front metal grid line on the horizontal plane, and the horizontal width of the contact region formed by the front metal grid line and the P ++ region of the silicon substrate is less than the line width of the metal grid line. The contact between the metal grid line and the P ++ region of the silicon substrate is an ohmic contact in the form of a point contact, and the contact resistivity of the contact point is 1.2 - 1.4 mΩ·cm 2 .

[0045] The structure of the TOPCon cell of the present invention is as Figure 1 shown. The contact structure of the TOPCon cell includes a back antireflection layer 7, a phosphorus-doped polysilicon layer 6, a tunneling layer 5, a silicon substrate 4, a passivation layer 2, and a front antireflection layer 1 arranged in sequence from bottom to top. Among them, the P ++ region 8 is the boron heavily doped region of the silicon substrate, and the P+ region 3. The passivation layer is an AlO x layer. The antireflection layer is one or more of silicon nitride, silicon oxynitride, or silicon oxide.

[0046] The front grid line contact region of the TOPCon cell of the present invention can have various structures. Figures 2 - 5 shows a schematic diagram of a partial front grid line contact region. For example, its cross-section can be trapezoidal ( Figure 2 ), triangular (Figure 3 ) Symmetric stepped shape ( Figure 4 ) or asymmetric stepped shape ( Figure 5 ). Through laser-assisted sintering, part of the slurry is ablated onto the front antireflection layer 1, part of the slurry is ablated onto the passivation layer 2, and part of the slurry is ablated onto the P ++ region 8. The P ++ region 8 coincides with the projection of the front metal grid line 10 on the horizontal plane, and the horizontal width of the contact region formed by the front metal grid line 10 and the P ++ region 8 is less than the line width of the metal grid line. The "horizontal width of the contact region formed by the front metal grid line and the P ++ region" refers to the projection width of the contact region formed by the front metal grid line and the P ++ region on the horizontal plane. Only the part of the slurry ablated onto the P ++ region 8 will form an ohmic contact with the silicon substrate, forming a metal-silicon matrix contact in the form of contact points, and the contact resistivity of the contact points is 1.2 - 1.4 mΩ·cm 2 . The number of such contact points is 1 - 10 4 per mm 2 . Such a contact structure has a small contact area, can achieve a low-damage metal contact structure, ensure a low contact resistance while also achieving low recombination, cause less damage to the silicon matrix, can give full play to the performance of polysilicon, improve the collection of photoelectrons, and thus improve the efficiency of the battery.

[0047] In one embodiment, the boron doping concentration of the P ++ region is 1.0E18 - 1.0E21 cm -3 , the boron doping concentration of the P + region is 5.0E17 - 1.0E19 cm -3 , and the boron doping concentration of the P ++ region is higher than that of the P + region.

[0048] In one embodiment, the thickness of the front antireflection layer is 55 - 95 nm, preferably 75 - 85 nm;

[0049] The thickness of the passivation layer is 5 - 20 nm, preferably 7 - 12 nm;

[0050] The thickness of the P ++ region is 1.5 - 2.5 nm, preferably 1.8 - 2.0 nm.

[0051] In one embodiment, the material of the front antireflection layer and / or the back antireflection layer is selected from one or more of the following: silicon nitride, silicon oxynitride, silicon oxide.

[0052] In one embodiment, the material of the passivation layer is aluminum oxide.

[0053] The present invention provides a method for preparing the above TOPCon cell, and the method includes:

[0054] (1) Boron doping is carried out on the front surface of the silicon substrate to form a heavily doped P ++ region and a lightly doped P + region, wherein the P ++ region corresponds to the pattern of the front metal grid line, and the P ++ region coincides with the projection of the front metal grid line on the horizontal plane;

[0055] (2) A passivation layer and a front antireflection layer are sequentially prepared on the front surface of the silicon substrate obtained in step (1), and a tunneling layer, a phosphorus-doped polysilicon layer, and a back antireflection layer are sequentially prepared on the back surface;

[0056] (3) Printing and pre-sintering of the front metal grid line are carried out on the front surface of the cell device obtained in step (2), and laser-assisted induced sintering is carried out on the pre-sintered front metal grid line;

[0057] (4) A back metal electrode is prepared on the back surface of the cell device obtained in step (3) to obtain the TOPCon cell.

[0058] Through the method of laser-induced assisted sintering, the present invention can obtain a contact structure as shown Figure 2 at a relatively low sintering temperature, reduce the damage to the surface of the silicon substrate while ensuring a low contact resistance, realize improved recombination, and improve the cell efficiency.

[0059] In one embodiment, in step (3), the power of the pre-sintering is 1000W - 3000W;

[0060] the temperature of the pre-sintering is 400°C - 800°C, preferably 650 - 750°C; and / or

[0061] the time of the pre-sintering is 10s - 200s, preferably 30 - 80s.

[0062] In one embodiment, in step (3), the laser-assisted induced sintering includes applying a forward deflection voltage of 5V - 30V, preferably 11 - 18V, to the metal grid line; and / or

[0063] the processing time of the laser-induced assisted sintering is 0.5 - 3s, preferably 1 - 2s.

[0064] In one embodiment, in step (3), the sintering temperature of the laser-induced assisted sintering is 100 - 900°C, preferably 100 - 600°C, more preferably 100 - 500°C; and / or

[0065] The laser power of the laser-induced assisted sintering is 25-65 W, preferably 40-50 W.

[0066] In one embodiment, in step (2), the front antireflection layer and / or the back antireflection layer are prepared by a plasma deposition method; and / or

[0067] The passivation layer is prepared by an atomic layer deposition method.

[0068] Example 1

[0069] This example is used to illustrate the contact structure of the TOPCon battery and the preparation method of the TOPCon battery of the present invention.

[0070] S1. At a certain concentration, temperature, and time, using the anisotropic etching characteristics of silicon in a low-concentration alkaline solution, a pyramid texture (the texture structure is not shown in the figure) is formed on the surface of the silicon substrate 4;

[0071] In step S1 of this example, the alkaline solution used is a KOH or NaOH alkaline solution with a concentration of 0.6-1.2%, the texturing temperature is 78-85 °C, and the texturing time is 380-480 s.

[0072] S2. At a certain concentration, temperature, pressure, and time, the boron source is vaporized in a tube furnace, and after a series of chemical reactions, BSG is deposited on the surface of the silicon substrate 4 to obtain a suitable doping concentration, and a lightly doped P + region 3 is formed on the silicon substrate 4.

[0073] In step S2 of this example, BBr 3 or BCl 3 is used as the boron source, and the silicon wafer is doped with boron at a flow rate of 100-600 sccm, a temperature of 850-1100 °C, a pressure of 100-300 mbar, and a time of 200-550 s to obtain a silicon wafer with a boron doping concentration in the P + region of 5.0E17-1.0E19 cm -3 In the embodiment of the present invention, the boron doping concentration in the P + region is 6.0E18-8.0E18 cm -3 .

[0074] S3. Use a laser for selective heavy doping treatment, and the heavy doping region should coincide with the metallization region, and a heavily doped P ++ region 8 with a thickness of 1.5-2.5 μm, preferably 1.8-2.0 μm, is formed on the silicon substrate 4. The P ++ region 8 coincides with the projection of the front metal grid line 10 on the horizontal plane. In the embodiment of the present invention, the thickness of the P ++ region is 1.8-2.0 μm.

[0075] In step S3 of this embodiment, the boron doping concentration in the heavily doped P ++ region is 1.0E18 - 1.0E21 cm -3 , and the boron doping concentration in the P ++ region is higher than that in the P + region. In the embodiment of the present invention, the boron doping concentration in the P ++ region is 1.0E19 - 1.5E19 cm -3 .

[0076] S4 performs thermal oxidation on the front surface of the silicon wafer to generate a dense silicon oxide film. Utilizing the characteristic that the alkali solution does not easily react with silicon oxide, the front surface is protected during the polishing process.

[0077] In step S4 of this embodiment, the thermal oxidation conditions are as follows: an oxygen flow rate of 10000 - 20000 sccm, a temperature of 850 - 1100 °C, an atmospheric pressure of about 1060 mbar, and a time of 40 - 80 min, to form a silicon oxide film passivation layer with a thickness of 80 - 140 nm.

[0078] S5 removes BSG and polishes the back surface: removes borosilicate glass. The alkali solution used for back surface polishing is a KOH or NaOH alkali solution with a concentration of 0.8 - 1.5%, the back polishing temperature is 78 - 85 °C, and the time is 180 - 280 s.

[0079] S6 prepares a tunneling layer. At a high temperature, using nitrous oxide as the reaction gas, a SiO x tunneling oxide film is formed on the surface of the silicon wafer by plasma deposition to form the tunneling layer 5, then a doped amorphous silicon layer is prepared, and after high-temperature annealing treatment, the amorphous silicon layer on the back surface of the silicon wafer is transformed into a polycrystalline silicon layer 6.

[0080] In step S6 of this embodiment, at 400 - 500 °C, using N 2 O as the reaction gas, a tunneling oxide film with a thickness of 1.0 - 1.8 nm is deposited on the surface of the silicon wafer, and then a doped amorphous silicon antireflection film with a thickness of 90 - 130 nm is prepared by the PECVD method.

[0081] S7 completes the transformation from amorphous silicon to polycrystalline silicon through high-temperature annealing.

[0082] In step S7 of this embodiment, annealing is carried out at 700 - 1000 °C for 30 - 60 min.

[0083] S8 uses a chain PSG removal machine to remove the diffused phosphosilicate glass, then completes the back surface etching and polishing, and then performs RCA cleaning to remove the silicon oxide film protecting the front surface.

[0084] S9 performs spatial atomic layer deposition (ALD) on the front surface of the silicon wafer to prepare AlO xA thin film, namely the passivation layer 2. That is, a dielectric film with a high stable charge is added near the surface to create a gradient electric field near the surface, reduce the surface electron concentration, and thus reduce the recombination rate of electron-hole pairs to achieve a higher level of photovoltaic conversion.

[0085] In step S9 of this embodiment, a layer of AlO with a thickness of 5 - 20 nm, preferably 7 - 12 nm, is deposited on the front side of the silicon wafer by ALD. x A thin film. In the embodiment of the present invention, an AlO thin film with a thickness of 10 - 12 nm is formed. x Thin film.

[0086] S10 uses low-temperature plasma as an energy source. The silicon wafer is placed on the cathode of a glow discharge under low pressure. The silicon wafer is heated to a predetermined temperature by glow discharge (or an additional heating element), and then a certain amount of SiH 4 and NH 3 are introduced. Through a series of chemical reactions and plasma reactions, solid thin films, namely the front antireflection layer 1 and the back antireflection layer 7, are formed on the front and back sides of the cell. The composition of the solid thin film can be one or more of silicon nitride, silicon oxynitride, or silicon oxide.

[0087] In step S10 of this embodiment, the silicon wafer is heated to 400 - 550 °C by glow discharge, and SiH with a flow rate of 1400 - 3000 sccm 4 and NH with a flow rate of 10000 - 18000 sccm 3 are introduced. The gas injection time is 13 - 17 min, and a front antireflection layer 1 and a back antireflection layer 7 with a thickness of 55 - 95 nm, preferably 75 - 85 nm, are formed on the surface of the silicon wafer. In the embodiment of the present invention, an antireflection layer with a thickness of 78 - 80 nm is formed.

[0088] S11 performs a light injection once, injecting light into the whole cell to activate H + activity, recombining the defects (such as lattice defects, etc.) inside the cell, and reducing the carrier recombination. The light injection power is 1000 W - 2000 W, the temperature is 200 °C - 600 °C, and the light injection time is 5 - 60 s.

[0089] In step S11 of this embodiment, the light injection power is 1600 W, the temperature is 600 °C, and the light injection time is 25 s.

[0090] S12 uses a screen pattern to print the front electrode and the back electrode.

[0091] S13 performs pre-sintering. The pre-sintering power is 1000 W - 3000 W, the pre-sintering temperature is 400 °C - 800 °C, and the pre-sintering time is 10 s - 200 s.

[0092] In step S13 of this embodiment, the pre-sintering power is 1800 W, the pre-sintering temperature is 730 °C, and the pre-sintering time is 35 s.

[0093] S14 Laser-assisted induced sintering: High-intensity laser is irradiated on the front fine grid of the cell, and at the same time, a forward deflection voltage of 5 V to 30 V is applied. The resulting local current will significantly reduce the contact resistance between the metal and the semiconductor. The processing time for each cell is 0.5 to 3 s, the laser power is 40 to 50 W, and the laser sintering temperature is 100 to 900 °C. In the embodiment of the present invention, the sintering temperature is 860 °C.

[0094] As Figures 2 - 5 shown, through laser-induced sintering, part of the paste is ablated onto the front antireflection layer 1, part of the paste is ablated onto the passivation layer 2, and part of the paste is ablated onto the heavily doped P ++ region 8 on the silicon substrate 4, and the horizontal width of the contact area formed by the front metal grid line 10 and the P ++ region 8 is smaller than the line width of the metal grid line. Only the part of the paste that is ablated onto the P ++ layer will form an ohmic contact with the silicon substrate, and a metal-silicon substrate contact is formed in the form of contact points. The contact resistivity of the P ++ emitter contact points is 1.2 - 1.4 mΩcm 2 . By first pre-sintering and then performing laser-assisted induced sintering, the present invention first forms partial ohmic contact through pre-sintering to reduce the erosion of the passivation layer, and then only forms better ohmic contact in the contact area between the metal grid line and the silicon substrate through laser-assisted induced sintering. The formed contact structure has a small contact area, can achieve a low-damage metal contact structure, ensure a low contact resistance, and at the same time can achieve low recombination. It has less damage to the silicon substrate, can give full play to the performance of polysilicon, and improve the efficiency of the battery.

[0095] In step S14 of this embodiment, a forward deflection voltage of 15 V is applied to the front of the cell, the processing time is 1 s, and the laser power is 45 W.

[0096] S15 Prepare the back metal electrode 9 by screen printing method to obtain the TOPCon cell structure as Figure 1 shown.

[0097] S16 Light injection: Perform light injection on the finished cell to repair the defects in the metallization area. The light injection temperature is 400 °C to 800 °C, and the light injection time is 10 s to 35 s.

[0098] In step S16 of this embodiment, the light injection temperature is 700 °C, and the light injection time is 25 s.

[0099] Embodiment 2

[0100] The TOPCon cell was prepared in the same manner as in Example 1, except that in step S14, the deflection voltage was 13V, the processing time was 1s, and the laser power was 45W.

[0101] Example 3

[0102] The TOPCon cell was prepared in the same manner as in Example 1, except that in step S14, the deflection voltage was 15V, the processing time was 1s, and the laser power was 40W.

[0103] Comparative Example 1

[0104] The TOPCon cell was prepared in the same manner as in Example 1, except that in Comparative Example 1, the laser-induced sintering in steps S13 and S14 was not carried out, and an ordinary metal grid sintering method was adopted, with a sintering power of 2200 - 2500W, a sintering temperature of 790°C, and a sintering time of 30 - 35s.

[0105] Comparative Example 2

[0106] The TOPCon cell was prepared in the same manner as in Example 1, except that in Comparative Example 2, after step S12, step S13 was not a pre-sintering treatment, but a front and back grid drying and curing treatment, and a laser drying treatment was carried out. The frequency of the laser was 100kHz, the pulse width was 500ns, the peak energy was 0.5J / cm2, the drying temperature was 350°C, and the drying time was 0.8s; in step S14, the front and back surface metal grids were irradiated with laser on both sides, and a forward bias voltage of 1.0 - 15V, 0.1 - 2.5s was applied to the metal grids on the crystalline silicon solar cell to sinter the metal grids.

[0107] Test Example

[0108] The electrical performance of the cells was tested, and the test results of Examples 1 - 3 and Comparative Examples 1 - 2 are shown in Table 1:

[0109] Table 1

[0110]

[0111]

[0112] It can be seen from the above results that:

[0113] Compared with the cells with ordinary sintering in Comparative Example 1 and the cells without pre-sintering treatment in Comparative Example 2, the P of the TOPCon cells prepared in Examples 1 - 3 of the present invention +The emitter contact resistivity is significantly lower than that of Comparative Examples 1 and 2, obtaining an ohmic contact structure with low contact resistivity, and having a higher open circuit voltage, fill factor, and photoelectric conversion efficiency, indicating that the TOPCon cell prepared by the present invention has better passivation performance and higher cell efficiency.

[0114] The above description of the present application is combined with preferred embodiments, but these embodiments are only exemplary and only serve an illustrative purpose. On this basis, various substitutions and improvements can be made to the present application, and these all fall within the protection scope of the present application.

Claims

1. A TOPCon battery, characterized in that: The TOPCon cell includes a back anti-reflection layer, a phosphorus-doped polysilicon layer, a tunneling layer, a silicon substrate, a passivation layer, and a front anti-reflection layer arranged in sequence from bottom to top, wherein the front side of the silicon substrate is lightly doped with P + The area outside also includes heavily doped P ++ The front metal grid line is connected to the front anti-reflection film, the passivation layer and the silicon substrate from top to bottom. ++ The silicon substrate P ++ The projection of the front metal gate line on the horizontal plane coincides with the projection of the front metal gate line on the silicon substrate. ++ The horizontal width of the contact area formed by the region is smaller than the line width of the metal gate line, and the metal gate line is adjacent to the silicon substrate P ++ The contact area is an ohmic contact in the form of a point contact, and the contact resistivity of the contact point is 1.2 to 1.4 mΩ cm 2 .

2. The TOPCon battery according to claim 1, characterized in that The P ++ The boron doping concentration in the region is 1.0E18 to 1.0E21 cm -3 , the P + The boron doping concentration in the region is 5.0E17~1.0E19 cm -3 , and the P ++ The boron doping concentration of the P + The boron doping concentration in the region.

3. The TOPCon battery according to claim 1, characterized in that The thickness of the front anti-reflection layer is 55 to 95 nm, preferably 75 to 85 nm; The thickness of the passivation layer is 5 to 20 nm, preferably 7 to 12 nm; The P ++ The thickness of the region is 1.5 to 2.5 μm, preferably 1.8 to 2.0 μm.

4. The TOPCon battery according to claim 1, characterized in that The material of the front anti-reflection layer and / or the back anti-reflection layer is selected from one or more of the following: silicon nitride, silicon oxynitride, and silicon oxide.

5. The TOPCon battery according to claim 1, characterized in that The material of the passivation layer is aluminum oxide.

6. A method for preparing a TOPCon cell according to any one of claims 1 to 5, characterized in that: The method includes: (1) Boron doping is performed on the front side of the silicon substrate to form heavily doped P ++ region and lightly doped P + Area, where P ++ The area corresponds to the pattern of the front metal grid line; (2) sequentially preparing a passivation layer and a front anti-reflection layer on the front side of the silicon substrate obtained in step (1), and sequentially preparing a tunneling layer, a phosphorus-doped polysilicon layer and a back anti-reflection layer on the back side; (3) printing and pre-sintering the front metal grid lines on the front side of the battery device obtained in step (2), and performing laser-assisted induced sintering on the pre-sintered front metal grid lines; (4) preparing a back metal electrode on the back side of the battery device obtained in step (3) to obtain the TOPCon battery.

7. The method according to claim 6, characterized in that In step (3), the power of the pre-sintering is 1000W to 3000W, preferably 1800 to 2200W; The pre-sintering temperature is 400°C to 800°C, preferably 650°C to 750°C; The pre-sintering time is 10s to 200s, preferably 30 to 80s.

8. The method according to claim 6, characterized in that In step (3), the laser-assisted induced sintering comprises applying a forward deflection voltage of 5V to 30V, preferably 11 to 18V to the metal grid line; and / or The processing time of the laser induced assisted sintering is 0.5 to 3 seconds, preferably 1 to 2 seconds.

9. The method according to any one of claims 6 to 8, characterized in that In step (3), the sintering temperature of the laser induced assisted sintering is 100 to 900° C., preferably 100 to 600° C., more preferably 100 to 500° C.; and / or The laser power of the laser induced assisted sintering is 25 to 65 W, preferably 40 to 50 W.

10. The method according to claim 6, characterized in that In step (2), the front anti-reflection layer and / or the back anti-reflection layer are prepared by a plasma deposition method; and / or The passivation layer is prepared by an atomic layer deposition method.

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