PN different-surface back incident light type detector chip testing device and testing method

Abstract

The invention relates to a PN different-surface back incident light type detector chip testing device and a testing method, the PN different-surface back incident light type detector chip testing device comprises a light-transmitting carrying disc and a conductive disc, the conductive disc comprises a metal conductive ring and a light-transmitting area, the metal conductive ring is fixed on the light-transmitting carrying disc, the metal conductive ring is provided with a wafer N-level contact area and a probe contact area, and the light-transmitting area is fixed on the metal conductive ring; the probe contact area is located on the periphery of the wafer N-level contact area; the first probe is used for being in contact with the probe contact area, and the second probe is used for being in contact with the P level of the wafer to be tested. The wafer N-level contact area on the metal conducting ring can be in contact with the N level of the wafer to be tested, and the probe contact area on the metal conducting ring can be in contact with the first probe, so that the first probe is conducted with the N level of the wafer to be tested, and meanwhile, the second probe is conducted with the P level of the wafer to be tested; and the light-transmitting carrying disc and the light-transmitting area ensure that the incident light irradiates to the back incident surface of the wafer to be tested, so that the light current test is completed.

Description

Technical Field

[0001] This application relates to the technical field of semiconductor photodetectors, and particularly to a test device and test method for a PN heterojunction back-illuminated photodetector chip. Background Art

[0002] Currently, photodetection technology is widely used in fields such as optical communication, intelligent sensing, infrared detection, medical treatment, and artificial intelligence. And semiconductor photodetector technology is the mainstream technology in photodetector technology. In the whole system, the function of the detector chip is to convert the externally input optical signal into an electrical signal for output. Therefore, the quality of the chip performance directly determines the performance of the entire detector system. In order to evaluate and screen out chips with good performance, we need to test their characteristics such as IV (current-voltage) and (current-voltage) under light input conditions. Currently, the DC IV characteristic test of photodetector chips is mainly completed on a probe test bench, that is, by applying a bias voltage or bias current on the two electrodes of the detector PN through probes, and at the same time collecting and detecting the corresponding current and voltage through an external circuit. For the optical test part, generally, light is coupled into the detector chip to be tested through an optical fiber to generate a corresponding photocurrent, and similarly, the corresponding current and voltage are collected and detected through an external circuit.

[0003] In the related art, according to the difference in the relative positions of the electrodes and the photosensitive region of the detector, detectors can be classified into front-illuminated PN heterojunction detectors, front-illuminated PN homojunction detectors, back-illuminated PN homojunction detectors, and back-illuminated PN heterojunction detectors.

[0004] Among them, for the front-illuminated PN heterojunction detector, the test can be achieved by a front-incident light source, a single probe, and a metal base electrode; similarly, it is relatively easy to achieve the test for the front-illuminated PN homojunction detector with a front-incident light source and front double probes; for the back-illuminated PN homojunction detector, the test can be achieved by a back-incident light source and double probes; however, for the back-illuminated PN heterojunction, the above methods are not practical. For the PN heterojunction electrodes, a single probe plus a metal base electrode method is required for power supply, but once a conventional metal base is used, it will inevitably block the incident light, making the photocurrent test of the detector impossible to carry out.

[0005] Therefore, it is necessary to design a new test device and test method for a PN heterojunction back-illuminated photodetector chip to overcome the above problems. Summary of the Invention

[0006] This application provides a test device and test method for a PN heterojunction back-illuminated photodetector chip, which can solve the technical problem that using a conventional metal base in the related art will block the incident light and make the photocurrent test of the detector impossible to carry out.

[0007] In a first aspect, an embodiment of the present application provides a test device for a PN heteroplanar back-illuminated photodetector chip, which includes: a light-transmitting carrier plate; a conductive plate, the conductive plate includes a metal conductive ring and a light-transmitting area located within the metal conductive ring, and the metal conductive ring is fixed to the light-transmitting carrier plate; the metal conductive ring has a wafer N-level contact area and a probe contact area, and the probe contact area is located outside the wafer N-level contact area; a first probe and a second probe, the first probe is used to contact the probe contact area, and the second probe is used to contact the P-level of the wafer to be tested.

[0008] In combination with the first aspect, in an embodiment, the light-transmitting carrier plate is made of a glass material, and the light-transmitting area is hollowed out.

[0009] In combination with the first aspect, in an embodiment, the light-transmitting carrier plate, the conductive plate, and the light-transmitting area are all set to be circular, and the metal conductive ring is a circular ring, and both the wafer N-level contact area and the probe contact area are also circular rings.

[0010] In combination with the first aspect, in an embodiment, the test device for the PN heteroplanar back-illuminated photodetector chip further includes a light source, the light source is arranged on the side of the light-transmitting carrier plate away from the conductive plate along the axis direction of the conductive plate, and the light source is used to emit light to the light-transmitting area.

[0011] In combination with the first aspect, in an embodiment, the refractive index of the light-transmitting carrier plate is 1.9 to 2.1; the thickness of the light-transmitting carrier plate along the axis direction of the conductive plate is 2 to 3 mm.

[0012] In combination with the first aspect, in an embodiment, the thickness of the light-transmitting area along the axis direction of the conductive plate is less than 100 μm.

[0013] In a second aspect, an embodiment of the present application provides a test method for a PN heteroplanar back-illuminated photodetector chip, which includes the following steps:

[0014] Place the wafer to be tested on the conductive plate; wherein, the conductive plate includes a metal conductive ring and a light-transmitting area located within the metal conductive ring, the metal conductive ring is fixed to the light-transmitting carrier plate, the metal conductive ring has a wafer N-level contact area and a probe contact area, the N-level of the wafer to be tested contacts the wafer N-level contact area, and the light-transmitting area is located below the back-illuminated surface of the wafer to be tested.

[0015] Insert the first probe into the probe contact area, and place the second probe on the P-level of the wafer to be tested.

[0016] In combination with the second aspect, in an embodiment, the test method for the PN heteroplanar back-illuminated photodetector chip further includes:

[0017] The light source is placed below the light-transmitting carrier, so that the light emitted by the light source passes through the light-transmitting carrier and the light-transmitting area and enters the back light-incident surface of the wafer to be tested.

[0018] In combination with the second aspect, in one embodiment, the outer diameter D of the metal conductive ring is 3 Greater than the diameter D of the wafer to be tested 1 , and the diameter D of the wafer to be tested 1 Greater than the diameter D of the light-transmitting area 2 .

[0019] In combination with the second aspect, in one embodiment, the metal conductive ring is provided with a plurality of microholes; placing the wafer to be tested on the conductive disk includes: evacuating the microholes so that the microholes adsorb and fix the wafer to be tested to the conductive disk.

[0020] The beneficial effects brought by the technical solution provided in the embodiments of the present application include:

[0021] By arranging a metal conductive ring and a light-transmitting area on the conductive disk and fixing the conductive disk to the light-transmitting carrier, during testing, the wafer N-level contact area on the metal conductive ring can contact the N-level of the wafer to be tested, and the probe contact area on the metal conductive ring can contact the first probe, so that the first probe is connected to the N-level of the wafer to be tested, and the second probe is connected to the P-level of the wafer to be tested. The light-transmitting carrier and the light-transmitting area on the conductive disk can ensure that the incident light is irradiated to the back light-incident surface of the wafer to be tested, so that the detector chip can perform photocurrent testing, which solves the technical problem in the related art that the conventional metal base will block the incident light, making the photocurrent testing of the detector impossible. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0023] Figure 1 A schematic diagram of the structure of a PN back-illuminated detector chip testing device provided in an embodiment of the present application;

[0024] Figure 2 A schematic diagram of the structure of a conductive disk provided in an embodiment of the present application;

[0025] Figure 3 A schematic diagram of the structure of a wafer to be tested provided in an embodiment of the present application;

[0026] Figure 4Schematic diagram of the structure for placing the wafer to be tested provided by the embodiment of the present application on the conductive disk.

[0027] In the figure:

[0028] 1. Conductive disk; 11. Metal conductive ring; 111. Wafer N-level contact area; 112. Probe contact area; 12. Light-transmitting area;

[0029] 2. First probe; 3. Second probe; 4. Wafer to be tested; 5. Light source; 6. Light-transmitting carrier. Specific implementation manner

[0030] In order to enable those skilled in the art to better understand the solution of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0031] For a PN heteroplanar back-illuminated photodetector chip, since the PN junctions of the chip are respectively at the front and back ends of the chip; and the light-incident surface is on the back of the chip. Different from the PN heteroplanar front-illuminated photodetector, it is easy to achieve electrical conduction with a metal chuck disk for the P-level on the front of the probe chip and the N-level on the back of the bottom substrate. The technical bottleneck encountered by the PN heteroplanar back-illuminated photodetector is that the conductive chuck disk, generally made of metal, is not light-transmitting. It is impossible to achieve the compatibility of the light-incident surface and the conductive surface. On the other hand, obviously, the heteroplanar electrodes cannot adopt the wire bonding method with PN coplanarity.

[0032] In the related art, in order to realize the test of the back-illuminated PN heteroplanar detector, the method of directly testing on the wafer is abandoned. After cutting and cleaving the wafer of the back-illuminated product to be tested into independent small chips, the small chips are then flip-chip mounted on the corresponding carrier. The electrodes on the carrier can connect the electrodes of the small chips and extend the electrodes of the small chips to the front of the carrier, and the photocurrent is tested by probing or wire bonding on the front of the carrier. This test scheme has great limitations, the test time is relatively lagging, the number of small chips is huge, often more than tens of thousands, and it takes a huge amount of time to mount each chip. More importantly, the mounting of defective small chips mixed in will cause a large waste of human and material resources costs.

[0033] The embodiment of the present application provides a PN heteroplanar back-illuminated photodetector chip test device and test method, which can solve the technical problem that the use of a conventional metal base in the related art will block the incident light and make it impossible to perform the photocurrent test of the detector.

[0034] See Figure 1 and Figure 2 As shown, a PN heteroplanar back-illuminated detector chip testing device provided by an embodiment of the present application may include: a light-transmitting carrier plate 6 and a conductive plate 1. The conductive plate 1 includes a metal conductive ring 11 and a light-transmitting area 12 located inside the metal conductive ring 11. The metal conductive ring 11 is fixed to the light-transmitting carrier plate 6. The metal conductive ring 11 has a wafer N-level contact area 111 and a probe contact area 112. The probe contact area 112 is located on the periphery of the wafer N-level contact area 111. A first probe 2 and a second probe 3. The first probe 2 is used to contact the probe contact area 112, and the second probe 3 is used to contact the P-level of the wafer to be tested 4. The structure of the wafer to be tested 4 is as Figure 3 shown

[0035] In this embodiment, see Figure 2 As shown, the metal conductive ring 11 is arranged in a ring shape, and the light-transmitting area 12 is located in the inner ring of the metal conductive ring 11. Both the light-transmitting carrier plate 6 and the light-transmitting area 12 are in a transparent state, capable of allowing light to pass through and irradiate the back light-incident surface of the wafer to be tested 4. See Figure 4 As shown, the outer diameter D of the above-mentioned metal conductive ring 11 3 is greater than the diameter D of the wafer to be tested 4 1 , and the diameter D of the wafer to be tested 4 1 is greater than the diameter D of the light-transmitting area 12 2 , and the inner diameter of the probe contact area 112 is greater than or equal to the outer diameter of the wafer N-level contact area 111, so that after the wafer to be tested 4 is placed on the conductive plate 1, the wafer to be tested 4 can be supported on the metal conductive ring 11, and the N-level on the back of the wafer to be tested 4 will contact the metal conductive ring 11, that is, contact the wafer N-level contact area 111 of the metal conductive ring 11, and the wafer N-level contact area 111 is electrically connected to the probe contact area 112. When the first probe 2 pierces the probe contact area 112, the first probe 2 can conduct with the N-level on the back of the wafer to be tested 4. And after the wafer to be tested 4 is placed on the conductive plate 1, the wafer to be tested 4 will not completely block the metal conductive ring 11, and at least a part of the probe contact area 112 will be exposed for easy contact and conduction with the first probe 2. When the second probe 3 is used, it can be directly hit on the P-level of the small chip to be tested on the front of the wafer to be tested 4

[0036] In this embodiment, a metal conductive ring 11 and a light-transmitting area 12 are arranged on the conductive disk 1, and the conductive disk 1 is fixed to the light-transmitting carrier disk 6. During testing, the N-level contact area 111 on the metal conductive ring 11 can be in contact with the N-level of the wafer to be tested 4, and the probe contact area 112 on the metal conductive ring 11 can be in contact with the first probe 2, so that the first probe 2 is conducted with the N-level of the wafer to be tested 4. At the same time, the second probe 3 can be conducted with the P-level of the wafer to be tested 4. Since the back surface of the entire wafer to be tested 4 is a highly doped N-type semiconductor, the flow of charged carriers can be realized. Therefore, under the action of the first probe 2 and the second probe 3, the IV (current-voltage) characteristics of the chips on the wafer to be tested 4 can be captured by the external circuit; and the light-transmitting carrier disk 6 and the light-transmitting area 12 arranged on the conductive disk 1 can ensure that the incident light on the back surface passes through the light-transmitting carrier disk 6 and the light-transmitting area 12 and irradiates the back light-incident surface of the wafer to be tested 4, so that the detector chip can perform photocurrent testing, solving the technical problem that in the related art, the conventional metal base will block the incident light and the photocurrent testing of the detector cannot be carried out. This embodiment can completely solve the problem that the light characteristic IV curve cannot be directly tested on the wafer compared with the solution in the related art, and can avoid the problems of increased cost and time caused by cutting the wafer.

[0037] Further, in a preferred embodiment, the light-transmitting carrier disk 6 is made of glass material, and the light-transmitting area 12 is hollowed out. In this embodiment, in the middle area of the conductive disk 1, that is, the light-transmitting area 12 adopts a hollow structure, and the light can directly pass through. Moreover, the light-transmitting carrier disk 6 is made of glass material, and the glass has a light-gathering effect. By adjusting the thickness and refractive index of the glass, the size of the light spot irradiated from the light source 5 to the back light-incident surface of the wafer to be tested 4 can be adjusted to adapt to the chips of different sizes on the wafer to be tested 4. Of course, in other embodiments, if there is no need for a light-gathering effect, other methods or materials can also be used to form the light-transmitting carrier disk 6 as long as the light can pass through.

[0038] Further, in an embodiment, the light-transmitting carrier disk 6, the conductive disk 1, and the light-transmitting area 12 are all set to be circular, and the metal conductive ring 11 is a circular ring, and the wafer N-level contact area 111 and the probe contact area 112 are also both circular rings. Refer to Figure 2 As shown, the light-transmitting carrier disk 6 and the conductive disk 1 in this embodiment are disks and have the same outer diameter size. The conductive disk 1 is fixed above the light-transmitting carrier disk 6, and the light-transmitting area 12 is also circular. Since the wafer to be tested 4 is generally circular, setting the light-transmitting carrier disk 6, the conductive disk 1, and the light-transmitting area 12 to be circular, and the metal conductive ring 11, the wafer N-level contact area 111, and the probe contact area 112 to be circular rings can better match the size of the wafer to be tested 4, and at the same time improve the area utilization rate of the conductive disk 1.

[0039] Further, in some embodiments, refer to Figure 1 As shown, the PN heteroplanar back-illuminated detector chip testing device further includes a light source 5. The light source 5 is disposed on a side of the light-transmitting carrier 6 away from the conductive disk 1 along the axis direction of the conductive disk 1, and the light source 5 is used to emit light to the light-transmitting area 12. In this embodiment, in order to test the photocurrent of the PN heteroplanar back-illuminated detector chip, the light source 5 can be placed below the light-transmitting carrier 6, and the light emitted by the light source 5 can enter the back light-incident surface of the wafer 4 to be tested through the light-transmitting carrier 6 and the light-transmitting area 12 of the conductive disk 1, thereby realizing the photocurrent test.

[0040] Further, in one embodiment, the refractive index of the light-transmitting carrier 6 is between 1.9 and 2.1; the thickness of the light-transmitting carrier 6 along the axis direction of the conductive disk 1 is 2 to 3 mm. In this embodiment, the light-transmitting carrier 6 is made of glass. By adjusting the thickness of the glass along the axis direction of the conductive disk 1, the optical path of the light emitted by the light source 5 can be adjusted. Different thicknesses result in different optical paths. The thickness of the light-transmitting carrier 6 is between 2 and 3 mm. This thickness range ensures a certain mechanical stability of the glass carrier, and the refractive index of the glass is set in the range of 1.9 to 2.1. At this time, the light has the maximum transmittance, and the most light enters the chip to be tested; preferably, the refractive index is set to 2. By adjusting the refractive index of the glass, the size of the light spot formed after the light emitted by the light source 5 passes through the light-transmitting carrier 6 can be adjusted, so as to more accurately realize the photocurrent test. For example, when the chip size on the wafer 4 to be tested is small, by adjusting the refractive index of the glass, a light spot with a smaller diameter can be formed after the light passes through the light-transmitting carrier 6 and irradiates the back light-incident surface of the wafer 4 to be tested. When the chip size is small, if the incident light spot size is large, some light cannot enter the active area of the chip and is thus lost, which will lead to inaccurate measurement of the optical parameters of the chip.

[0041] Further, in some alternative embodiments, the thickness of the light-transmitting area 12 along the axis direction of the conductive disk 1 is less than 100 μm. In this embodiment, the light-transmitting area 12 is a hollow structure, and this thickness range can minimize the light loss of the glass layer and the chip to be tested.

[0042] The embodiment of the present application also provides a method for testing a PN heteroplanar back-illuminated detector chip, which may include the following steps:

[0043] S1: Place the wafer 4 to be tested on the conductive disk 1; wherein the conductive disk 1 includes a metal conductive ring 11 and a light-transmitting area 12 located in the metal conductive ring 11, the metal conductive ring 11 is fixed to the light-transmitting carrier 6, the metal conductive ring 11 has a wafer N-level contact area 111 and a probe contact area 112, the N-level of the wafer 4 to be tested contacts the wafer N-level contact area 111, and the light-transmitting area 12 is located below the back light-incident surface of the wafer 4 to be tested.

[0044] S2: Insert the first probe 2 into the probe contact area 112, and insert the second probe 3 into the P level of the wafer 4 to be tested. Since the back side of the entire wafer 4 to be tested is a highly doped N-type semiconductor, the flow of charged carriers can be realized. Therefore, under the action of the first probe 2 and the second probe 3, the IV (current-voltage) characteristics of the small chip on the wafer 4 to be tested can be captured by the external circuit.

[0045] In this embodiment, when performing a PN out-of-plane back-lighting detector chip test, the PN out-of-plane back-lighting detector chip test device provided in any of the above embodiments can be used. The PN out-of-plane back-lighting detector chip test device may include: a light-transmitting carrier plate 6 and a conductive plate 1, wherein the conductive plate 1 includes a metal conductive ring 11 and a light-transmitting area 12 located in the metal conductive ring 11, wherein the metal conductive ring 11 has a wafer N-level contact area 111 and a probe contact area 112, wherein the probe contact area 112 is located at the periphery of the wafer N-level contact area 111; a first probe 2 and a second probe 3, wherein the first probe 2 is used to contact the probe contact area 112, and the second probe 3 is used to contact the P level of the wafer 4 to be tested.

[0046] Furthermore, in a preferred embodiment, the light-transmitting carrier 6 is made of glass material, and the light-transmitting area 12 is hollowed out. In this embodiment, the middle area of ​​the conductive disk 1, that is, the light-transmitting area 12, adopts a hollow structure, and light can pass through directly, and the light-transmitting carrier 6 is made of glass material, and the glass has a light-collecting effect, and the size of the light spot from the light source 5 to the back light-incident surface of the wafer 4 to be tested can be adjusted by adjusting the thickness and refractive index of the glass to adapt to small chips of different sizes on the wafer 4 to be tested. Of course, in other embodiments, if the light-collecting effect is not required, other methods or materials can be used to form the light-transmitting carrier 6, as long as it can allow light to pass through.

[0047] Furthermore, in one embodiment, the light-transmitting carrier plate 6, the conductive plate 1 and the light-transmitting area 12 are all arranged in a circular shape, and the metal conductive ring 11 is a circular ring, and the wafer N-level contact area 111 and the probe contact area 112 are also circular rings. Figure 2As shown, the light-transmitting carrier plate 6 and the conductive plate 1 in this embodiment are disks with the same outer diameter. The conductive plate 1 is fixed above the light-transmitting carrier plate 6, and the light-transmitting area 12 is also circular. Since the wafer 4 to be tested is generally circular, the light-transmitting carrier plate 6, the conductive plate 1, and the light-transmitting area 12 are all set to be circular. Moreover, the metal conductive ring 11, the wafer N-level contact area 111, and the probe contact area 112 are all rings, which can better match the size of the wafer 4 to be tested and improve the area utilization rate of the conductive plate 1 at the same time.

[0048] Further, in some embodiments, as shown in Figure 1 the PN hetero-plane back-illuminated detector chip testing device further includes a light source 5. The light source 5 is arranged on the side of the light-transmitting carrier plate 6 away from the conductive plate 1 along the axis direction of the conductive plate 1, and the light source 5 is used to emit light to the light-transmitting area 12. In this embodiment, in order to test the photocurrent of the PN hetero-plane back-illuminated detector chip, the light source 5 can be placed below the light-transmitting carrier plate 6. The light emitted by the light source 5 can enter the back light-incident surface of the wafer 4 to be tested through the light-transmitting area 12 of the light-transmitting carrier plate 6 and the conductive plate 1, thereby realizing the photocurrent test.

[0049] Further, in one embodiment, the refractive index of the light-transmitting carrier plate 6 is between 1.9 and 2.1; the thickness of the light-transmitting carrier plate 6 along the axis direction of the conductive plate 1 is 2 to 3 mm. In this embodiment, the light-transmitting carrier plate 6 is made of glass. By adjusting the thickness of the glass along the axis direction of the conductive plate 1, the optical path of the light emitted by the light source 5 can be adjusted. Different thicknesses result in different optical paths. The thickness of the light-transmitting carrier plate 6 is between 2 and 3 mm. This thickness range ensures that the glass carrier plate has a certain mechanical stability, and the refractive index of the glass is set in the range of 1.9 to 2.1. At this time, the light has the maximum transmittance, and the most light enters the chip to be tested. Preferably, the refractive index is set to 2. By adjusting the refractive index of the glass, the size of the light spot formed after the light emitted by the light source 5 passes through the light-transmitting carrier plate 6 can be adjusted, so as to more accurately realize the photocurrent test. For example, when the chip size on the wafer 4 to be tested is small, by adjusting the refractive index of the glass, the light can form a light spot with a smaller diameter after passing through the light-transmitting carrier plate 6 and irradiate the back light-incident surface of the wafer 4 to be tested. When the chip size is small, if the incident light spot size is large, some light cannot enter the active area of the chip and is lost, which will lead to inaccurate measurement of the optical parameters of the chip.

[0050] Further, in some alternative embodiments, the thickness of the light-transmitting area 12 along the axis direction of the conductive plate 1 is less than 100 μm. In this embodiment, the light-transmitting area 12 is a hollow structure, and this thickness range can minimize the light loss of the glass layer and the chip to be tested.

[0051] Furthermore, in some embodiments, the PN out-of-plane back-lighting detector chip test method may also include: placing the light source 5 below the light-transmitting carrier 6, so that the light emitted by the light source 5 enters the back light-incident surface of the wafer 4 to be tested through the light-transmitting carrier 6 and the light-transmitting area 12. In this embodiment, in order to test the photocurrent of the PN out-of-plane back-lighting detector chip, the light source 5 may be placed below the light-transmitting carrier 6, and the light emitted by the light source 5 may enter the back light-incident surface of the wafer 4 to be tested through the light-transmitting carrier 6 and the light-transmitting area 12 of the conductive disk 1, thereby realizing the photocurrent test.

[0052] Preferably, see Figure 4 As shown, the outer diameter D of the metal conductive ring 11 is 3 Greater than the diameter D of the wafer 4 to be tested 1 , and the diameter D of the wafer 4 to be tested 1 Greater than the diameter D of the light-transmitting area 12 2 In this embodiment, the outer diameter D of the metal conductive ring 11 is 3 Greater than the diameter D of the wafer 4 to be tested 1 , the diameter D of the wafer 4 to be tested 1 Greater than the diameter D of the light-transmitting area 12 2 , and the inner diameter of the probe contact area 112 is greater than or equal to the outer diameter of the wafer N-level contact area 111, so that after the wafer 4 to be tested is placed on the conductive disk 1, the wafer 4 to be tested can be supported on the metal conductive ring 11, and the N-level on the back of the wafer 4 to be tested will contact the metal conductive ring 11, that is, the wafer N-level contact area 111 that contacts the metal conductive ring 11, and the wafer N-level contact area 111 and the probe contact area 112 are electrically connected together, when the first probe 2 is inserted into the probe contact area 112, the first probe 2 can be connected to the N-level on the back of the wafer 4 to be tested. And after the wafer 4 to be tested is placed on the conductive disk 1, the wafer 4 to be tested will not completely block the metal conductive ring 11, and at least a part of the probe contact area 112 will be exposed to facilitate contact and conduction with the first probe 2.

[0053] Furthermore, in one embodiment, the metal conductive ring 11 is provided with a plurality of micropores; the placing of the wafer piece 4 to be tested on the conductive plate 1 may include: evacuating the micropores so that the micropores adsorb and fix the wafer piece 4 to be tested to the conductive plate 1. In this embodiment, the micropores may be vacuum holes, and when the wafer piece 4 to be tested is placed on the conductive plate 1, the bottom surface of the wafer piece 4 to be tested will contact some of the micropores, and by evacuating the micropores, the wafer piece 4 to be tested can be adsorbed and fixed on the conductive plate 1, and the wafer piece 4 to be tested is not easily damaged.

[0054] In the description of the present application, it should be noted that the orientation or positional relationship indicated by terms such as "upper" and "lower" is based on the orientation or positional relationship shown in the drawings. This is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation to the present application. Unless otherwise clearly specified and defined, the terms "installed", "connected", and "coupled" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific circumstances.

[0055] It should be noted that in the present application, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprising", "including" or any other variation thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the existence of additional identical elements in the process, method, article or device comprising the said element.

[0056] The above are only specific embodiments of the present application, enabling those skilled in the art to understand or implement the present application. Various modifications to these embodiments will be obvious to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to these embodiments shown herein, but rather to the broadest scope consistent with the principles and novel features claimed herein.

Claims

1. A PN back-light detector chip testing device, characterized in that: It includes: A light-transmitting carrier plate (6); A conductive disk (1), the conductive disk (1) comprising a metal conductive ring (11) and a light-transmitting area (12) located in the metal conductive ring (11), the metal conductive ring (11) being fixed to the light-transmitting carrier disk (6), the metal conductive ring (11) having a wafer N-level contact area (111) and a probe contact area (112), the probe contact area (112) being located at the periphery of the wafer N-level contact area (111); A first probe (2) and a second probe (3), wherein the first probe (2) is used to contact the probe contact area (112), and the second probe (3) is used to contact the P level of a wafer (4) to be tested.

2. The PN back-light detector chip testing device according to claim 1, characterized in that: The light-transmitting carrier plate (6) is made of glass material, and the light-transmitting area (12) is hollow.

3. The PN back-light detector chip testing device according to claim 1, characterized in that: The light-transmitting carrier plate (6), the conductive plate (1) and the light-transmitting area (12) are all arranged in a circular shape, the metal conductive ring (11) is a circular ring, and the wafer N-level contact area (111) and the probe contact area (112) are also circular rings.

4. The PN back-light detector chip testing device according to claim 1, characterized in that: The PN back-input type detector chip testing device further comprises a light source (5), wherein the light source (5) is arranged on a side of the light-transmitting carrier plate (6) away from the light-transmitting plate (1) along the axial direction of the light-transmitting plate (1), and the light source (5) is used to emit light to the light-transmitting area (12).

5. The PN back-light detector chip testing device according to claim 1, characterized in that: The refractive index of the light-transmitting carrier disk (6) is 1.9 to 2.1; the thickness of the light-transmitting carrier disk (6) along the axial direction of the conductive disk (1) is 2 to 3 mm.

6. The PN back-light detector chip testing device according to claim 5, characterized in that: The thickness of the light-transmitting area (12) along the axial direction of the conductive disk (1) is less than 100 μm.

7. A PN back-light detector chip testing method, characterized in that: It includes the following steps: The wafer (4) to be tested is placed on a conductive disk (1); wherein the conductive disk (1) comprises a metal conductive ring (11) and a light-transmitting area (12) located in the metal conductive ring (11); the metal conductive ring (11) is fixed to a light-transmitting carrier disk (6); the metal conductive ring (11) has a wafer N-level contact area (111) and a probe contact area (112); the N-level of the wafer (4) to be tested contacts the wafer N-level contact area (111); and the light-transmitting area (12) is located below the back light-incident surface of the wafer (4) to be tested; The first probe (2) is inserted into the probe contact area (112), and the second probe (3) is inserted into the P level of the wafer (4) to be tested.

8. The PN back-light detector chip testing method according to claim 7, characterized in that: The PN back-light detector chip testing method further includes: The light source (5) is placed below the light-transmitting carrier (6), so that the light emitted by the light source (5) passes through the light-transmitting carrier (6) and the light-transmitting area (12) and enters the back light-incident surface of the wafer (4) to be tested.

9. The PN back-light detector chip testing method according to claim 7, characterized in that: The outer diameter D3 of the metal conductive ring (11) is greater than the diameter D1 of the wafer to be tested (4), and the diameter D1 of the wafer to be tested (4) is greater than the diameter D2 of the light-transmitting area (12).

10. The PN back-light detector chip testing method according to claim 7, characterized in that: The metal conductive ring (11) is provided with a plurality of micro-holes; the step of placing the wafer (4) to be tested on the conductive plate (1) comprises: The micropores are evacuated so that the micropores adsorb and fix the wafer piece (4) to be tested to the conductive plate (1).

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