Efficient test optimization method, system and device for chip test equipment

Abstract

The invention relates to an efficient test optimization method, system and device for chip test equipment, and the method comprises the steps: obtaining the equipment state data and test management information of the chip test equipment, carrying out the test unit division of the equipment state data based on the test management information, and obtaining the regional test information; acquiring real-time operation data of the chip test equipment, and performing matching analysis on the real-time operation data and the regional test information to obtain a real-time test task group; acquiring chip performance data acquired by the chip test equipment, performing load prediction on the regional test information to obtain a test load trend, and performing resource planning analysis with a real-time test task group to obtain an initial test scheme; performing exception identification on the chip performance data to obtain chip exception information; and performing global optimization on the initial test scheme according to the priority test sequence to obtain a global test strategy. According to the invention, fine management of different test tasks can be realized.

Description

Technical Field

[0001] The present invention relates to the technical field of chip testing, and particularly to an efficient testing optimization method, system and device for a chip testing device. Background Art

[0002] In the application of modern chip testing devices, how to improve testing efficiency and accuracy has become a hot research issue. With the continuous development of chip technology, the functions and complexities of chips have been increasing, which requires testing devices to have higher testing capabilities and optimization strategies to ensure the performance stability and reliability of chips under different working conditions. Most of the existing chip testing methods focus on single testing parameters or specific testing processes, and fail to fully consider the state changes of chip devices and the load differences in different regions. In addition, traditional testing methods usually ignore the dynamic matching analysis between real-time data and test management information, resulting in inaccurate test task arrangements, thus affecting the overall testing efficiency and resource utilization rate. Therefore, how to optimize test tasks based on device state data and real-time operation data, reasonably allocate test resources, and globally optimize the test plan by combining chip performance data and load trends has become an urgent problem to be solved in the current chip testing field. Summary of the Invention

[0003] The main object of the present invention is to provide an efficient testing optimization method, system and device for a chip testing device, which can perform matching analysis on real-time operation data and regional test information to achieve refined management of different test tasks.

[0004] To achieve the above object, the present invention provides an efficient testing optimization method for a chip testing device, including: Obtaining device state data and test management information of the chip testing device, and performing test unit division on the device state data based on the test management information to obtain regional test information; Obtaining real-time operation data of the chip testing device, and performing matching analysis on the real-time operation data and the regional test information to obtain a real-time test task group; Obtaining chip performance data collected by the chip testing device, performing load prediction on the regional test information to obtain a test load trend, and performing resource planning analysis on the real-time test task group to obtain an initial test plan; Performing anomaly identification on the chip performance data to obtain chip anomaly information, and performing priority prediction on the chip anomaly information based on the test load trend to obtain a priority test sequence; Globally optimizing the initial test plan according to the priority test sequence to obtain a global test strategy.

[0005] Further, obtaining the device status data and test management information of the chip testing device, and based on the test management information, dividing the device status data into test units to obtain regional test information, including: Collecting the operating parameters of the chip testing device to obtain the device status data including test temperature, test voltage, and test frequency; Extracting the test management data of the chip testing device to obtain the test management information including test case configuration information, test resource allocation information, and test scheduling strategy; Clustering the device status data according to the test management information to obtain an initial test unit set; Calculating the similarity of the initial test unit set to obtain a test unit similarity matrix; Performing hierarchical clustering on the initial test unit set according to the similarity matrix to obtain a test unit hierarchical tree; Performing threshold segmentation on the test unit hierarchical tree to obtain independent test regions; Mapping the independent test regions according to the resource allocation information to obtain a regional resource distribution map; Performing regional correlation analysis on the regional resource distribution map and the test management information to obtain regional test information.

[0006] Further, obtaining the real-time operation data of the chip testing device, and performing matching analysis on the real-time operation data and the regional test information to obtain a real-time test task group, including: Performing device status analysis according to the real-time operation data to obtain operation status indicators; Parsing the test items of the regional test information to obtain a test item attribute table; Performing association matching on the test item attribute table according to the operation status indicators to obtain a test matching result; Grouping the test matching results to obtain an initial task set; Performing resource allocation evaluation according to the initial task set to obtain resource allocation information; Performing test constraint condition analysis on the resource allocation information to obtain task execution boundaries; Performing test configuration optimization on the initial task set according to the task execution boundaries to obtain a real-time test task group.

[0007] Further, obtaining the chip performance data collected by the chip testing device, performing load prediction on the regional test information to obtain a test load trend, and performing resource planning analysis on the test load trend and the real-time test task group to obtain an initial test plan, including: Extract performance features from the chip performance data to obtain a chip performance feature sequence; Perform hierarchical clustering on the area test information according to the chip performance feature sequence to obtain a test area load distribution map; Perform test prediction on the test area load distribution map to obtain the test load trend; Analyze the task dependency relationship of the real-time test task group to obtain a task dependency network; Perform resource allocation calculation on the task dependency network according to the test load trend to obtain a resource allocation matrix; Optimize the test constraint conditions and schedule the real-time test task group according to the resource allocation matrix to obtain the initial test plan.

[0008] Further, perform anomaly identification on the chip performance data to obtain chip anomaly information, and predict the priority of the chip anomaly information based on the test load trend, including: Perform anomaly residual analysis and anomaly outlier detection on the chip performance data to obtain an initial anomaly data cluster; Perform anomaly topology construction on the initial anomaly data cluster to obtain an anomaly topology graph; Classify the initial anomaly data cluster according to the anomaly topology graph to obtain the chip anomaly information; Perform load distribution segmentation on the test load trend to obtain a load intensity distribution matrix; Perform anomaly matching calculation on the chip anomaly information according to the load intensity distribution matrix to obtain an anomaly matching coefficient matrix; Construct a multi-objective priority function based on the anomaly matching coefficient matrix to obtain a priority evaluation function; Based on the priority evaluation function, perform iterative sorting of test nodes on the anomaly topology graph to obtain the priority test sequence.

[0009] Further, the classifying the initial anomaly data cluster according to the anomaly topology graph to obtain the chip anomaly information includes: Perform structural feature clustering on the anomaly topology graph to obtain an anomaly clustering cluster; Analyze the fault nodes of the anomaly clustering cluster according to a preset fault node data table to obtain a fault feature set; Perform rule matching classification on the anomaly clustering cluster according to the fault feature set to obtain a fault type set; Perform frequency statistics and fault sorting on the fault type set to obtain a fault mode priority; Sort the associated test nodes of the abnormal topology diagram according to the priority of the fault mode to obtain the priority test sequence.

[0010] Further, globally optimizing the initial test plan according to the priority test sequence to obtain a global test strategy, including: Perform task order dependency analysis on the real-time test task group to obtain execution order constraint information; Conduct scheduling plan analysis according to the execution order constraint information and the priority test sequence to obtain a task scheduling table; Perform parallelism analysis on the task scheduling table to obtain a list of parallel test tasks; Perform resource allocation according to the list of parallel test tasks and the device status data to obtain a resource allocation plan; Optimize and adjust the resource allocation plan according to the test load trend to obtain a target resource scheduling plan; Perform global test optimization and adjustment on the task scheduling table according to the target resource scheduling plan to obtain the global test strategy.

[0011] Further, the conducting scheduling plan analysis according to the execution order constraint information and the priority test sequence to obtain a task scheduling table includes Sort the dependency relationships of the test tasks according to the execution order constraint information to obtain the task priority execution order; Match the test tasks according to the priority execution order and the priority test sequence to obtain a preliminary task scheduling list; Perform time allocation on the preliminary task scheduling list to obtain a time scheduling list; Identify parallel execution of the test tasks according to the time scheduling list to obtain a parallel task group; Perform optimized allocation of scheduling resources on the preliminary task scheduling list according to the parallel task group to obtain the task scheduling table.

[0012] The present invention also provides an efficient test optimization system for a chip testing device, which is applied to the efficient test optimization method of the chip testing device described in any one of the above, including: An acquisition module, which is used to obtain the device status data and test management information of the chip testing device, and divide the device status data into test units based on the test management information to obtain regional test information; An analysis module, which is used to obtain the real-time operation data of the chip testing device, and perform matching analysis on the real-time operation data and the regional test information to obtain a real-time test task group; An association module, which is used to obtain the chip performance data collected by the chip test device, perform load prediction on the area test information to obtain a test load trend, and perform resource planning analysis with the real-time test task group to obtain an initial test plan; A processing module, which is used to identify anomalies in the chip performance data to obtain chip anomaly information, and predict the priority of the chip anomaly information based on the test load trend to obtain a priority test sequence; A control module, which is used to globally optimize the initial test plan according to the priority test sequence to obtain a global test strategy.

[0013] The present invention also provides an efficient test optimization device for a chip test device, including: A memory, which is used to store programs; A processor, which is used to execute the program to implement each step of the efficient test optimization method for a chip test device described in any one of the above.

[0014] The efficient test optimization method, system and device for a chip test device provided by the present invention have the following beneficial effects: By obtaining device status data and test management information and performing test unit division, it is possible to more accurately evaluate the test requirements of different regions, thereby improving the accuracy of test task allocation and providing a more reliable basis for formulating test plans. Matching and analyzing real-time operation data with area test information realizes the refined management of different test tasks, helps to achieve on-demand testing, avoids waste of test resources, and solves the problem of inaccurate test task arrangement in traditional test methods. Performing load prediction on area test information based on chip performance data can ensure that the test device can operate efficiently under different working conditions, reduce unnecessary resource consumption, improve the overall operation efficiency of the test system, and effectively solve the problem of unreasonable resource planning during the test process. By identifying anomalies in chip performance data and combining the test load trend for priority prediction, a more reasonable priority test sequence is formulated, and the optimal operation of the entire test system is achieved through global optimization, thereby effectively utilizing test resources, reducing test time and costs, and solving the problem that the test plan cannot adapt to the actual working state of the chip. By considering the impact of chip anomaly information on test priorities, it is possible to flexibly adjust test strategies according to the characteristics and performance changes of different chips, making the system more adaptable to diverse test scenarios and improving the pertinence and effectiveness of chip testing. Description of the Drawings

[0015] Figure 1 It is a flowchart of an efficient test optimization method for a chip test device provided by the present invention; Figure 2 It is a structural diagram of an efficient test optimization system for a chip test device provided by the present invention; Figure 3 It is a structural diagram of an efficient test optimization device for a chip test device provided by the present invention.

[0016] The realization of the purpose, functional characteristics and advantages of the present invention will be further described in conjunction with the embodiments with reference to the accompanying drawings. Specific embodiments

[0017] In order to make the purpose, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention and are not used to limit the present invention.

[0018] Next, in conjunction with the accompanying drawings and specific embodiments, the present invention will be further described.

[0019] Referring to Figure 1 as shown, the present invention provides an efficient test optimization method for a chip test device, including: Step S1: Obtain the device status data and test management information of the chip test device, and divide the device status data based on the test management information to obtain regional test information; Step S2: Obtain the real-time operation data of the chip test device, and perform matching analysis on the real-time operation data and the regional test information to obtain a real-time test task group; Step S3: Obtain the chip performance data collected by the chip test device, perform load prediction on the regional test information to obtain a test load trend, and perform resource planning analysis on the real-time test task group to obtain an initial test plan; Step S4: Perform anomaly identification on the chip performance data to obtain chip anomaly information, and perform priority prediction on the chip anomaly information based on the test load trend to obtain a priority test sequence; Step S5: Globally optimize the initial test plan according to the priority test sequence to obtain a global test strategy.

[0020] Based on the above steps, the detailed step process is as follows: Step S1: Obtain two types of key data: device status data and test management information. The device status data includes information such as the operating parameters, environmental conditions, and hardware configuration of the test device, reflecting the current working status of the test device; the test management information covers management-level data such as test plans, test project configurations, and test specifications. Based on the test management information, divide the device status data into test units, and this process involves data mapping and clustering analysis. Specifically, when implementing, establish a test unit model, and partition and map the device status data according to dimensions such as test items, test board distribution, and test function modules defined in the test management information. Through data correlation analysis, identify sets of device status data with similar characteristics or functional associations to form test units. The division of test units uses algorithms such as hierarchical clustering or density clustering to achieve effective grouping of data. After the division is completed, each test unit contains the status information of a specific area or functional module, constituting regional test information. The regional test information reflects the resource status and test capabilities of each functional area of the test device, laying a foundation for subsequent real-time test task allocation. The regional test information usually includes elements such as test area identifiers, available resource quantities, supported test types, and current load levels, and this information is stored in the form of structured data for matching analysis and resource planning in subsequent steps.

[0021] Step S2: First, collect real-time operation data from the chip test device. These data include, but are not limited to, dynamic parameters such as the current execution status of the test process, resource occupancy, test instruction queue, and response time. The real-time operation data reflects the immediate working conditions of the test and the execution of test tasks. Perform a matching analysis on the collected real-time operation data and the regional test information obtained in Step S1. The matching analysis process uses data association technology to establish a mapping relationship between the real-time operation data and the regional test information based on key attributes such as test project ID, test area identifier, and resource type. The matching analysis algorithm considers data timeliness, resource dependence, and functional association, and achieves accurate matching through multi-dimensional data fusion. The matching analysis results are used to generate real-time test task groups, and each real-time test task group contains a set of test tasks with similar resource requirements or functional associations. The real-time test task groups are usually classified according to priority, resource type, test function, or test area to form structured task management units. The generation of real-time test task groups uses task aggregation and resource balancing algorithms to ensure that the task grouping meets both test requirements and resource utilization. The real-time test task groups contain attributes such as task identifiers, resource requirements, expected execution times, and dependencies, providing basic data for subsequent load prediction and resource planning. The real-time test task groups output in this step dynamically reflect the current task composition and resource requirement status of the test.

[0022] Step S3: First, obtain the chip performance data collected by the chip testing equipment. These data are from the monitoring of various performance indicators of the chip under test, including key indicators such as power consumption, timing parameters, temperature distribution, and signal integrity. The chip performance data reflects the actual performance and characteristics of the chip under test under the test conditions. Based on the obtained regional test information, perform load prediction. The load prediction uses time series analysis and machine learning algorithms. The prediction process considers factors such as historical test data patterns, periodic change characteristics, and test task distribution rules, and combines the current test queue situation to generate the resource demand curve and test load trend for each test area within a certain period in the future. The test load trend usually uses time as the horizontal axis and resource occupancy rate as the vertical axis to reflect the change trend of the test load over time. After obtaining the test load trend, perform resource planning analysis on it together with the generated real-time test task group. The resource planning analysis is based on a constraint optimization algorithm, considering constraint conditions such as resource availability, task priority, and test time window, and reasonably schedules and allocates resources for the test tasks. The planning analysis process includes links such as resource conflict detection, task dependency analysis, and execution time evaluation, and finally generates an initial test plan. The initial test plan includes elements such as the execution order of test tasks, resource allocation strategy, and test time arrangement, providing a basic framework for subsequent exception handling and global optimization. This initial plan takes into account the current resource status and expected load changes, and has a certain resource utilization efficiency and test execution rationality.

[0023] Step S4: Conduct in-depth analysis on the chip performance data, and use anomaly detection algorithms to identify abnormal states during the chip operation. The anomaly identification process combines statistical analysis methods and machine learning models, and identifies potential chip anomalies through multi-dimensional analysis of the fluctuation characteristics, trend changes, and threshold exceedance of chip performance indicators. The anomaly identification algorithm uses methods such as density-based clustering analysis, support vector machines, or deep learning to establish a normal behavior model of the chip performance data, and discovers anomaly points through deviation analysis with the actual data. The identified chip anomaly information includes attributes such as anomaly type, anomaly degree, occurrence time, and influence range. Based on the obtained test load trend, perform priority prediction on the chip anomaly information. The priority prediction process considers factors such as the severity of the anomaly, propagation risk, and resource consumption, and combines the resource availability and time window constraints in the test load trend to calculate the priority score for each abnormal test item. The priority prediction uses a multi-objective optimization algorithm to balance the test efficiency and the urgency of anomaly handling, and generates a priority test sequence. The priority test sequence is sorted according to the priority level, and includes the execution order, expected resource requirements, and time requirements of each test item, providing a decision basis for the optimization of the global test strategy.

[0024] Step S5: Based on the generated initial test plan, perform global optimization and adjustment according to the obtained prioritized test sequence. The global optimization process adopts a heuristic algorithm or a reinforcement learning method, and continuously improves the execution efficiency and resource utilization rate of the test plan through iterative optimization. The optimization algorithm considers multiple key factors: the priority ranking of test tasks, the balance of resource allocation, the constraint conditions of test time, the timeliness of exception handling, etc. The global optimization process dynamically adjusts the execution order of test tasks and the resource allocation plan, while ensuring that high-priority test tasks are processed in a timely manner, the overall test efficiency. The optimization result forms a global test strategy, which includes detailed test execution plans, resource scheduling plans, exception handling preplans, and other contents. The global test strategy has dynamic adaptability and can adjust the strategy according to the real-time situation during the test process to ensure the efficiency and reliability of the test process. Through reasonable task scheduling and resource allocation, this strategy achieves the optimal operating state of the test equipment and improves the overall efficiency of chip testing. As the final output, the global test strategy guides the test equipment to execute specific test tasks, realizing the intelligentization and optimized control of the chip testing process.

[0025] An efficient test optimization method for a chip testing device provided by the present invention can more accurately evaluate the test requirements of different regions by obtaining device status data and test management information and performing test unit division, thereby improving the accuracy of test task allocation and providing a more reliable basis for formulating test plans. Matching and analyzing real-time operation data with regional test information realizes the refined management of different test tasks, helps to achieve on-demand testing, avoids waste of test resources, and solves the problem of inaccurate test task arrangement in traditional test methods. Load prediction of regional test information based on chip performance data can ensure the efficient operation of the test equipment under different working conditions, reduce unnecessary resource consumption, improve the overall operation efficiency of the test system, and effectively solve the problem of unreasonable resource planning during the test process. By identifying anomalies in chip performance data and combining test load trends for priority prediction, a more reasonable prioritized test sequence is formulated, and the optimized operation of the entire test system is achieved through global optimization, thereby effectively utilizing test resources, reducing test time and costs, and solving the problem that the test plan cannot adapt to the actual working state of the chip. By considering the impact of chip anomaly information on test priorities, the test strategy can be flexibly adjusted according to the characteristics and performance changes of different chips, making the system more adaptable to diverse test scenarios and improving the pertinence and effectiveness of chip testing.

[0026] In one embodiment, device status data and test management information of a chip testing device are obtained, and the device status data is divided into test units based on the test management information to obtain regional test information, including: In the device status data acquisition stage, the test device monitors and records the operating parameters in real time. The test temperature collects the temperature values of each test point of the chip through a temperature sensor, with a measurement range of -55°C to 125°C and a sampling frequency of 10Hz; the test voltage obtains the operating voltage of each functional module of the chip through a voltage sampling circuit, with a voltage range of 0.8V to 3.3V and a sampling accuracy of 1mV; the test frequency uses a frequency counter to record the chip clock signal, with a frequency range of 1MHz to 1GHz and a counting period of 1ms. These parameters constitute a complete device status data set.

[0027] In the test management data extraction process, the test case configuration information is obtained from the test platform database, including the test item type, test vector sequence, expected output result, etc.; the test resource allocation information records the hardware resource status of the test device, such as the number of test channels, storage space capacity, processor load, etc.; the test scheduling strategy defines the priority rules, parallelism limit, resource competition handling mechanism, etc. of the test tasks.

[0028] In the test unit clustering stage, the K-means algorithm is used to group the device status data based on the configuration features in the test management information. The clustering feature vector includes three dimensions: test temperature, voltage, and frequency, and the Euclidean distance is used as the similarity measurement standard. The initial clustering center is selected by the maximum-minimum distance method and iteratively optimized until the within-class variance is minimized, obtaining the initial test unit set.

[0029] The similarity calculation uses the cosine similarity method to calculate the similarity relationship between the initial test units. For any two test units, their feature vectors are extracted to calculate the cosine value of the included angle, and an n×n similarity matrix is constructed, where n is the number of initial test units. The similarity value ranges between [0, 1], and the larger the value, the more similar the test units are.

[0030] Hierarchical clustering uses the AGNES (Agglomerative Nesting) algorithm to construct a test unit hierarchical tree from bottom to top based on the test unit similarity matrix. The minimum distance method is used as the inter-class distance measurement criterion, and the most similar categories are gradually merged until all test units are grouped into one category. The hierarchical tree records the merging order and hierarchical relationship during the clustering process.

[0031] Threshold segmentation is based on the structural characteristics of the hierarchical tree, and the similarity threshold is set to 0.8. Starting from the root of the tree and traversing downwards, when the similarity between nodes is lower than the threshold, a split is performed to obtain multiple independent test regions. The test units within each region have high similarity and are suitable for centralized scheduling and execution.

[0032] During the regional resource mapping process, the test resource allocation information is corresponded to the independent test regions. A bipartite graph model is established, with test regions and hardware resources as two types of vertices, and the edge weights are set according to the resource requirements. The Hungarian algorithm is used to solve the optimal matching and generate the regional resource distribution map.

[0033] In the regional association analysis stage, the regional resource distribution map is combined with the scheduling strategy in the test management information. The dependency relationships between regions are analyzed through the association rule mining algorithm, and the support and confidence metrics are calculated. The support threshold is set to 0.3, and the confidence threshold is set to 0.7 to extract the significant association rules. The finally generated regional test information includes test unit grouping, resource allocation scheme, inter-regional scheduling constraints, etc.

[0034] Among them, the test case configuration information refers to the detailed configuration of the test plans designed for each functional module of the chip, including the following: test item types (such as functional test, performance test, stability test, boundary test, etc.); test vector sequences (i.e., the excitation signal sequences input to the chip, with the level changes applied according to a specific timing); expected output results (the standard output signals that the chip should generate under the action of specific test vectors); test parameter limits (the qualified upper and lower limits of the chip's various performance indicators); test condition settings (such as environmental factors like temperature conditions, power supply conditions, etc.); test coverage requirements (the test coverage of each functional module of the chip). The test case configuration information provides a functional attribute basis for test unit division.

[0035] The test resource allocation information describes the status of the hardware resources of the test equipment, mainly including: the number of test channels (the number of parallel channels that can perform tests simultaneously); the storage space capacity (the memory size for storing test vectors and result data); the processor load (the usage rate of the test CPU); the test board configuration (the models and quantities of various test boards); the test pin resources (the number of test pins available for connecting to the chip pins); the status of measurement instruments (such as the occupancy of auxiliary test equipment like oscilloscopes, spectrum analyzers, etc.); the power module capacity (the capabilities of the power supply units providing test voltages and currents). The test resource allocation information reflects the resource limitations and provides basic data for regional resource mapping.

[0036] The test scheduling strategy defines the execution rules and priority mechanisms for test tasks, including the following aspects: test task priority rules (the priority division criteria for different test items); parallelism limit (the upper limit of the number of test tasks that can be executed simultaneously); resource contention handling mechanism (the scheduling rules when multiple test tasks compete for the same resources); failure handling strategy (the retry mechanism and exception handling process after a test failure); test process dependency relationship (the pre- and post-constraint conditions between test items); load balancing strategy (the allocation method of test tasks among multiple processors or multiple test channels); time window limit (the execution time constraint for specific test items). The test scheduling strategy provides execution constraint conditions for test unit clustering and regional association analysis.

[0037] In this embodiment, through the systematic analysis and optimization of the device status data and test management information of the chip testing equipment, the resource utilization efficiency and test accuracy in the test process can be effectively improved. Through the combined analysis of the real-time acquisition of operating parameters and test management information, the test units can be accurately divided to ensure that the configuration of each test unit matches the requirements, thus avoiding the problems of resource waste and low test efficiency. The application of the hierarchical clustering method makes the grouping of test units more scientific, improves the parallelism and flexibility of the test, reduces the redundant work in the test process, and ensures the optimal allocation of test resources. The combination of threshold segmentation and regional resource mapping provides clear guidance for the resource allocation in each region during the chip testing process, enabling a closer connection between the resource requirements of the test region and the actual test tasks, and improving the overall test scheduling efficiency. The application of regional association analysis further enhances the scheduling optimization between test tasks, effectively avoids resource conflicts, and improves the execution efficiency of test tasks. Through this series of optimization measures, the chip testing equipment can execute test tasks more efficiently, reduce the redundant operations and time waste in the test process, and finally achieve the high efficiency, accuracy and intelligence of the test process.

[0038] In one embodiment, the real-time operating data of the chip testing equipment is obtained, and the real-time operating data is matched and analyzed with the regional test information to obtain a real-time test task group, including: During the operation of the chip testing equipment, the real-time operating data is collected through the built-in sensor network of the equipment. These data include but are not limited to key parameters such as device temperature, voltage fluctuation, test needle position accuracy, response time, etc. The system uses the data acquisition module to sample these parameters at a frequency of 100 times per second to form a device real-time status data stream. After the acquisition is completed, all the data is transmitted to the central processing unit for subsequent analysis.

[0039] The equipment status is analyzed based on the real-time operation data to obtain the operation status index. In this step, the system applies the equipment status evaluation algorithm to process the collected real-time data. The algorithm first pre-processes the data, including denoising, outlier screening and data smoothing. Subsequently, the system calculates key performance indicators, including test stability index (TSI), device response efficiency (DRE), temperature fluctuation range (TVR), etc. These indicators are converted into standard scores of 0-100 through mathematical models to form an equipment operation status score table. The calculation results of the operation status indicators serve as an important basis for matching subsequent test items.

[0040] The regional test information is parsed for test items to obtain a test item attribute table. Regional test information refers to the test requirements and characteristic data of a specific chip area. The system extracts the regional test information of the current chip to be tested from the test database, including the test area identification, test type code, test parameter range, etc. The test item parsing engine structures this information and converts unstructured test requirements into standardized test item attributes. The generated test item attribute table contains fields such as test item ID, test area coordinates, test type, parameter requirements, expected result range, test priority, and resource consumption assessment.

[0041] According to the operating status indicators, the test item attribute table is correlated and matched to obtain the test matching results. This step uses an intelligent matching algorithm to perform multi-dimensional correlation analysis on the operating status indicators obtained in the first two steps and the test item attributes. The matching process is based on the following rules: If the test item's requirement for equipment stability is higher than the current TSI value, its matching priority is reduced; if the equipment response efficiency DRE meets the time sensitivity requirements of the test item, its matching weight is increased; if the temperature fluctuation range TVR exceeds the temperature tolerance allowed by the test item, the test item is marked as a risk item. The matching algorithm calculates the comprehensive matching score, generates a matching fitness score for each test item, and forms a test matching result table.

[0042] The test matching results are grouped into tasks to obtain an initial task set. The system uses a multi-objective optimization clustering method to group the matching results. This method first performs preliminary grouping according to the physical location of the test area to reduce the moving distance of the test probe. Subsequently, the system performs secondary grouping based on the similarity of the test types, so that projects of the same or similar test types are arranged together for execution, reducing the test mode switching overhead. Finally, the system considers the resource dependencies of the test items and assigns mutually exclusive test items to different groups to form an initial task set. This set contains multiple test task groups, each of which contains multiple test items, and is marked with the execution order within the group, the estimated execution time, and the resource requirement list.

[0043] Resource allocation assessment is carried out according to the initial task set to obtain resource allocation information. The system conducts a resource feasibility analysis on the initial task set through a resource allocation model. This model is based on the resource constraint conditions of the chip testing equipment, including hardware limitations such as the number of test channels, parallel processing capabilities, and power supply capabilities, as well as environmental factors such as the temperature control accuracy of the test environment and the vibration control level. The resource allocation model uses the integer linear programming method, with maximizing resource utilization and test throughput as the objective function, to calculate the optimal resource allocation plan. The resource allocation information includes data such as the execution time window of each task group, the hardware resource allocation table, and the power distribution curve.

[0044] Analysis of the test constraint conditions is carried out on the resource allocation information to obtain the task execution boundary. The analysis of test constraint conditions aims to ensure that the test plan meets all technical and business constraints. The constraint conditions analyzed by the system include test timing constraints (certain test items must be executed in a specific order), test coverage constraints (ensuring 100% coverage of key functional areas), test accuracy constraints (higher-precision tests have higher environmental requirements), etc. The constraint condition analysis engine applies the constraint propagation algorithm to determine the influence boundary of each constraint condition on task execution. The task execution boundary clarifies the execution condition limitations of each test task group, including the allowable execution time window range, the upper and lower limits of resource usage, and the test parameter adjustment range.

[0045] Based on the task execution boundary, the initial task set is optimized for test configuration to obtain the real-time test task group. The system makes refined adjustments to the initial task set based on the dynamic programming algorithm. The test configuration optimization process takes into account the constraint conditions of the task execution boundary and adaptively adjusts the test parameter configuration, including parameters such as the test voltage level, signal frequency, and sampling rate. For tasks with harsh test boundary conditions, the system adds its robustness processing logic; for areas with intense resource competition, the system implements a peak-shifting strategy for the test time window. The optimized real-time test task group includes a complete test execution plan, a parameter configuration table, and an exception handling plan, providing an efficient and accurate test execution plan for the chip testing equipment.

[0046] In this embodiment, through the intelligent acquisition and analysis of the real-time operation data of the chip testing equipment, combined with the accurate matching of regional testing information, the dynamic optimal allocation of testing tasks is achieved. This method ensures the efficient utilization of testing resources through multi-dimensional correlation analysis of operation status indicators and testing items, effectively avoiding the waste and conflict of testing resources. Based on the task grouping strategy of multi-objective optimization clustering, the moving distance of testing probes and the switching times of testing modes are significantly reduced, improving the testing efficiency. By analyzing resource allocation evaluation and constraint conditions, a complete task execution boundary is established, ensuring the stability and reliability of the testing process. This method uses the dynamic programming algorithm to optimize the testing configuration, realizes the adaptive adjustment of testing parameters, and enhances the system's ability to handle abnormal situations. Overall, this method significantly improves the accuracy and efficiency of chip testing, reduces the testing cost, and has important value for improving the chip production quality.

[0047] In one embodiment, the chip performance data collected by the chip testing equipment is obtained, the load prediction of the regional testing information is carried out, the testing load trend is obtained, and resource planning analysis is carried out with the real-time testing task group to obtain an initial testing plan, including: The original data obtained in the chip performance data collection stage includes static parameters (such as chip size, number of pins, process technology, etc.) and dynamic parameters (such as working voltage, working current, power consumption index, timing parameters, etc.). The original data is standardized to eliminate the influence of dimension. The principal component analysis method (PCA) is used for feature dimensionality reduction to extract the main feature vectors. The feature importance is screened by the maximum information coefficient method, and the feature combinations with strong correlation are retained. The finally obtained chip performance feature sequence is an n-dimensional vector, and each dimension represents a key performance indicator.

[0048] Based on the chip performance feature sequence, a similarity matrix is constructed, and the Ward minimum variance method is used for hierarchical clustering. The Euclidean distance between different testing regions is calculated, and a clustering threshold is set. Through bottom-up iterative merging, the regions with a distance less than the threshold are combined into clusters. The center point of each cluster represents the average load level of the region. The finally generated testing region load distribution map uses the color depth to represent the load intensity, with red representing high-load regions and blue representing low-load regions.

[0049] The stationarity test is carried out on the time series data in the testing region load distribution map, including the unit root test and the white noise test. According to the test results, a suitable prediction model is selected. The SARIMA model is used for seasonal data, and the ARIMA model is used for non-seasonal data. The model parameters are determined by the maximum likelihood estimation method, and the AIC criterion is used for model selection. The prediction results include point prediction values and confidence intervals, forming a testing load trend curve.

[0050] Represent the real-time test task group as a directed acyclic graph G(V, E), where the vertices V represent test tasks and the edges E represent the dependencies between tasks. Identify the strongly connected components in the graph through the depth-first search algorithm to determine the critical path of task execution. Calculate the earliest start time and the latest completion time of each task to construct the task time window. The edge weights in the task dependency network represent the tightness between tasks, and the larger the weight value, the stronger the dependency relationship.

[0051] Establish an integer programming model with the objective function of minimizing the total test time. The constraint conditions include: total resource constraint, task time window constraint, task priority constraint, resource mutual exclusion constraint, etc. Use the branch and bound algorithm to solve the integer programming problem to obtain the resource allocation matrix. The matrix element aij represents the number of the jth type of resources allocated to the ith test task. Handle complex constraints through the Lagrangian relaxation method to improve the solution efficiency.

[0052] Based on the resource allocation matrix, establish a linear programming model for test constraint conditions. The constraint conditions include: test equipment quantity constraint (the parallel test number of each type of equipment does not exceed the total number of equipment), test time constraint (the task completion time does not exceed the maximum limit), test sequence constraint (follow the task dependency relationship). Use the simplex method to solve the linear programming problem to obtain the optimal test time arrangement. According to the optimization results, formulate a detailed test task scheduling plan, including the specific execution time period of each task, the equipment number used, the test parameter configuration and other information.

[0053] The test plan presents the task execution plan in the form of a Gantt chart, with the horizontal axis representing time and the vertical axis representing test resources. The execution parameters of each test task are detailed in the plan, including the test voltage range, the test temperature requirement, the test frequency setting, etc. For tasks executed in parallel, the task priority and the resource competition mechanism are clearly specified. The plan also includes an emergency handling preplan, an alternative execution path when a test anomaly occurs.

[0054] In this embodiment, by adopting an efficient test optimization method based on chip performance data analysis, accurate allocation and optimization of chip test resources can be achieved. Through the performance feature extraction step, in-depth analysis is carried out on various dynamic and static performance parameters of the chip, and the most representative performance indicators are extracted, thereby improving the accuracy and reliability of performance evaluation. The hierarchical clustering of regional test information not only helps to reveal the load distribution of the test area, but also provides a scientific basis for subsequent load prediction, and then realizes the accurate prediction of the test load trend, ensuring the timely and efficient execution of test tasks. In the task dependency analysis, based on the modeling method of directed acyclic graph, the execution order and critical path between tasks are accurately determined, providing theoretical support for resource optimization. Through resource allocation calculation, resources between test tasks and devices can be reasonably configured, thereby minimizing the test time and improving the test efficiency. The optimization of test constraint conditions and scheduling planning ensures the timely completion of test tasks and full utilization of resources through the operation of the linear programming model, avoiding resource waste and over-scheduling.

[0055] In one embodiment, abnormal identification is performed on chip performance data to obtain chip abnormal information, and priority prediction is performed on the chip abnormal information based on the test load trend to obtain a priority test sequence, including: When performing abnormal identification on chip performance data, the deviation between the performance data and the expected standard value is calculated through the abnormal residual analysis method, and the residual threshold is set to μ±3σ (μ is the sample mean, σ is the standard deviation). When the residual of a data point exceeds this threshold range, it is marked as an abnormal point. At the same time, the local outlier factor (LOF) algorithm is used for abnormal outlier detection, and the local density ratio of the data point to its k nearest neighbors is calculated. When the LOF value is greater than the preset threshold of 1.5, it is determined as an abnormal point. The union of the abnormal point sets detected by the above two methods is taken to form an initial abnormal data cluster.

[0056] In the abnormal topology construction link, a minimum spanning tree is constructed based on the initial abnormal data cluster. The abnormal points are used as nodes, and the Euclidean distance between nodes is used as the edge weight. The Prim algorithm is used to generate a tree structure with the minimum weight connection to obtain an abnormal topology graph. This topology graph reflects the association relationship between abnormal points.

[0057] Fault mode classification is to classify abnormal points with similar characteristics by using the spectral clustering algorithm based on the abnormal topology graph. By calculating the eigenvalues of the Laplacian matrix of the topology graph, the eigenvectors corresponding to the smallest k eigenvalues are selected for K-means clustering to obtain different categories of chip abnormal information.

[0058] During the load distribution segmentation process, time series analysis is performed on the test load trend data. The sliding time window method is used to divide the load data by time period, and the load intensity indicators (including CPU usage rate, memory occupancy rate, etc.) within each time window are calculated to generate a load intensity distribution matrix M of m×n dimensions. Here, m is the number of time windows, and n is the load indicator dimension.

[0059] In the abnormal matching calculation stage, the chip abnormal information is correlated and analyzed with the load intensity distribution matrix. The Pearson correlation coefficient between each type of abnormality and each load indicator is calculated to construct an abnormal matching coefficient matrix R of p×n dimensions. Here, p is the number of abnormal categories, and the matrix element rij represents the degree of correlation between the i-th type of abnormality and the j-th load indicator.

[0060] During the construction of the multi-objective priority function, the priority evaluation function includes three evaluation dimensions: abnormality severity, test cost, and resource consumption. The abnormality severity reflects the degree of impact of the abnormality on the chip performance, which is determined by the coefficient values in the abnormal matching coefficient matrix. The test cost includes two parts: time cost and equipment cost. The time cost refers to the duration required to complete the test, and the equipment cost refers to the usage cost of the test equipment. The resource consumption includes CPU usage rate and memory occupancy rate, which respectively represent the occupancy of processor and memory resources during the test process.

[0061] When constructing the priority evaluation function, the relevant coefficient values in the abnormal matching coefficient matrix are used to calculate the abnormality severity. The test cost and resource consumption indicators are normalized to unify the dimensions of each indicator. The weight coefficients of the three evaluation dimensions are determined by the analytic hierarchy process, a judgment matrix is established, and the eigenvector is calculated to obtain the weight values of each dimension. The normalized indicator values are multiplied by the corresponding weight coefficients and summed to obtain the final priority evaluation function.

[0062] The test node sorting iteration is implemented using an improved genetic algorithm. The population size is set to 100 individuals, and each individual is a candidate test sequence. The chromosome uses a real number coding method, and the coding length is equal to the number of nodes in the abnormal topology graph. The initial population is generated randomly to ensure population diversity.

[0063] The selection operation adopts the tournament selection mechanism. Each time, 3 individuals are randomly selected from the population, and the fitness values of each individual are calculated. The fitness values are calculated by the priority evaluation function. The individual with the highest fitness value is selected to enter the next generation population.

[0064] The crossover operation adopts the partially matched crossover method, and the crossover probability is set to 0.8. Two parent individuals are selected from the population, two crossover positions are randomly determined, and the segments between the positions are exchanged. After the exchange, the duplicate genes are repaired to ensure the integrity of the test sequence.

[0065] The mutation operation adopts the swap mutation method, and the mutation probability is set to 0.1. Two positions of genes on the chromosome are randomly selected for swapping. At the same time, an elite retention strategy is introduced to directly retain the optimal individual in the current population to the next generation to avoid the loss of excellent genes.

[0066] During the algorithm iteration process, two termination conditions are set: the iteration times reach 200 times or the optimal solution has no change for 20 consecutive generations. When either condition is met, the iteration stops, and the current optimal individual is output as the priority test sequence. This sequence represents the execution order of test nodes in the abnormal topology graph.

[0067] When actually performing tests, the system executes test items in the order of the priority test sequence. During the execution process, the system load status is monitored in real time. When the CPU usage rate or memory occupancy rate exceeds the preset threshold, the system automatically pauses the current test and adjusts the execution order. After the test is completed, the data of the abnormal matching coefficient matrix is updated to provide a basis for subsequent test optimization.

[0068] The sorting iteration of test nodes is to sort nodes on the abnormal topology graph based on the value of the priority evaluation function f(x). The genetic algorithm is used to iteratively optimize the node sequence, and the fitness function is the maximum value of f(x). The optimal individual obtained after the population evolution is the priority test sequence, which determines the execution order of chip test items.

[0069] Among them, the specific algorithm of the priority evaluation function includes: Abnormality severity : The correlation coefficient between the i-th type of abnormality and the j-th load index in the abnormal matching coefficient matrix R.

[0070] : The weight coefficient of the j-th load index, .

[0071] i ∈ [1, p], p is the total number of abnormality categories, j ∈ [1, n], n is the dimension of load indexes.

[0072] Test cost : Time cost, : Equipment cost, The maximum time cost in historical test data max( ): The maximum equipment cost in historical test data, w1, w2: The weight coefficients of time cost and equipment cost, Resource consumption: ; : CPU usage rate, : Memory occupancy rate, : The maximum CPU usage rate allowed by the system, max( ): The maximum memory occupancy rate allowed by the system. , : The weight coefficient of CPU usage rate and memory occupancy rate, Comprehensive weight coefficient , , Calculated by the Analytic Hierarchy Process (AHP): The element aij in the judgment matrix A represents the importance degree of index i to j. The eigenvector W corresponds to the maximum eigenvalue λmax, and normalization processing ensures that the sum of weights is 1.

[0073] Calculate the eigenvalue and eigenvector: Normalization processing to obtain the weight vector: Positive term ×S represents the priority improvement brought by the severity of the anomaly. Negative terms - ×C and - ×R represent the priority reduction brought by cost and resource consumption. The larger the function value, the higher the test priority.

[0074] In this embodiment, through anomaly recognition and priority prediction of chip performance data, the intelligent optimization of the chip testing process is realized. Based on the dual mechanisms of anomaly residual analysis and anomaly outlier detection, the accuracy and reliability of anomaly recognition are improved. The method of constructing an anomaly topology map is adopted to effectively show the correlation between anomaly points, providing a reliable basis for fault mode classification. Through load distribution segmentation and anomaly matching calculation, the correlation degree between test load and chip anomaly is accurately evaluated. The test node sorting method based on the multi-objective priority function and genetic algorithm significantly improves the test efficiency while ensuring the test quality. This method comprehensively considers three dimensions of anomaly severity, test cost, and resource consumption, realizes the quantitative evaluation of test priority, and makes the test process more scientific and reasonable. By real-time monitoring the system load status and dynamically adjusting the test order, the stability and reliability of the test process are ensured.

[0075] In one embodiment, the initial abnormal data clusters are classified according to the abnormal topology map to obtain chip abnormal information, including: Each abnormal point generated during the chip testing process reflects the electrical abnormality of the chip at a specific location. These abnormal points form a distribution on the chip plane according to their spatial positions, and are usually displayed through an abnormal topology map. The abnormal topology map provides us with the positions of each abnormal point and their electrical performances.

[0076] To accurately identify and classify different types of chip faults, first, a structural feature clustering method is used to analyze the abnormal data in the abnormal topology map. The core objective of clustering is to divide the abnormal points into different clusters through a density clustering algorithm, and identify abnormal points with similar properties in space. For example, if the distance between certain abnormal points is less than the set threshold, these points will be grouped into the same abnormal clustering cluster. When setting the threshold, it will be adjusted according to the chip manufacturing process and testing accuracy. For example, for a 90nm process, the clustering algorithm may use 100 microns as the threshold.

[0077] Through the processing of this stage, the abnormal points in the abnormal topology map can be divided into multiple abnormal clustering clusters. The regions corresponding to these clustering clusters usually reveal potential fault modes. For example, the abnormal points appearing in certain regions may imply specific defect types. The processing result of this stage is multiple abnormal clustering clusters, and each cluster represents a fault area on the chip, and there are commonalities in its spatial characteristics and electrical characteristics.

[0078] After obtaining multiple abnormal clustering clusters, the next step is to perform fault node analysis. Fault node analysis is a process of analyzing each abnormal clustering cluster based on a preset fault node data table. The fault node data table contains known fault types and their characteristic parameters, and these parameters include: Spatial distribution pattern: For example, whether the abnormal points show a linear, circular or random distribution.

[0079] Density feature: That is, the number of abnormal points in each region.

[0080] Shape feature: Whether the geometric shape of the abnormal region is regular or there is an irregular distribution.

[0081] By comparing and analyzing the spatial distribution of each abnormal clustering cluster with the characteristics in the fault node data table, the fault type corresponding to the clustering cluster can be identified. For example, if a clustering cluster shows a linear distribution and the number of its abnormal points reaches a certain density, this clustering cluster may be determined to be a fault caused by chip scratching. On the contrary, if the clustering cluster is circular and has a high density, it may be caused by particle contamination or other similar fault types.

[0082] The result of this stage is the generation of a fault feature set, which contains the fault feature information of each abnormal clustering cluster. The fault feature set reflects information such as the spatial distribution pattern, density distribution, and shape of each clustering cluster, providing basic data for subsequent fault classification.

[0083] After the fault feature set is generated, the next step is to perform rule matching classification. The goal of fault mode classification is to determine the specific fault type of each abnormal clustering cluster based on the information in the fault feature set. At this time, the fault feature set is matched with a preset fault classification rule library. The fault classification rule library contains the determination rules for various fault types, which are defined based on the common fault modes and their characteristic parameters in the chip production process.

[0084] For example, a rule in the rule library might be: when the abnormal points show a linear distribution and a high density (e.g., more than 10 abnormal points per square millimeter), it may be caused by chip scratching faults; another rule might be: when the abnormal points show an obvious circular distribution and a density higher than 15 per square millimeter, it may be caused by particle contamination or other similar faults.

[0085] According to these rules, each abnormal clustering cluster will be classified and assigned to a specific fault type. The fault types of each abnormal clustering cluster will ultimately be output as a set of fault types. The processing result at this time is a set containing multiple fault types, and each fault type is associated with one or more abnormal clustering clusters.

[0086] Frequency statistics are performed on each fault type in the set of fault types. The purpose of frequency statistics is to calculate the number of times each fault type appears in all abnormal clustering clusters, so as to determine which fault types are the most common and which have the greatest impact on chip performance or yield.

[0087] For example, in a large-scale test, particle contamination faults may occur more frequently, while scratching faults may occur less frequently. The fault types after frequency statistics will be sorted from high to low according to the occurrence frequency. The higher the frequency of a fault type, the higher the priority it needs to be focused on during the test.

[0088] The output result of this stage is a list of fault mode priorities, which lists the priorities of the fault types. Fault types with higher priorities usually indicate that they occur more frequently in the chip or have a greater impact on the chip's performance or quality. Therefore, fault types with higher priorities need to be processed and detected earlier.

[0089] Generate a prioritized test sequence according to the fault mode priority list. The prioritized test sequence refers to which test nodes should be preferentially tested during the test. Test nodes are specific locations on the chip used for electrical parameter testing or function verification. According to the priority of the fault type, the test nodes involved in the high-priority fault types will be ranked at the front of the test sequence.

[0090] Based on the physical locations between the test nodes, optimize the movement path of the probe to reduce the ineffective waiting time during the test. Through reasonable sorting, it can ensure that the most critical fault types are detected first, thereby reducing the test time and resource consumption and improving the test efficiency.

[0091] The generated prioritized test sequence will be tested in the order of priority, and ensure that the most important fault modes can be identified and repaired as early as possible during the test.

[0092] In this embodiment, by performing structural feature clustering analysis on the abnormal topology graph, it can quickly identify and locate the abnormal areas on the chip, improving the accuracy and efficiency of fault detection. By establishing a fault node data table for feature matching, the system can automatically identify different types of fault modes, avoiding the errors that may be brought by manual judgment and significantly improving the reliability of the test. Based on the frequency statistics and priority sorting of the fault types, the test process can focus on the high-occurrence faults and critical faults first, effectively shortening the test time. By generating an optimized test sequence, it reduces the ineffective movement of the test probe, reduces the loss of the test equipment, and improves the test efficiency at the same time. The implementation of the overall solution not only improves the accuracy of chip testing, but also significantly reduces the test cost, providing reliable technical support for chip manufacturing quality control.

[0093] In one embodiment, globally optimize the initial test plan according to the prioritized test sequence to obtain a global test strategy, including: Perform task sequence dependency analysis on the real-time test task group to obtain execution sequence constraint information. The real-time test task group refers to a group of test tasks that need to be completed within a specific time period, and the task sequence dependency analysis refers to determining the execution sequence by analyzing the dependency relationships between these test tasks. The execution sequence constraint information will be used as the basis for subsequent scheduling to ensure that the test tasks are correctly executed according to the dependency relationships.

[0094] Schedule plan analysis is carried out according to the execution order constraint information and the priority test sequence to obtain a task schedule table. The priority test sequence refers to the sequence arranged according to the importance and urgency of the test tasks. Schedule plan analysis is to formulate a reasonable test task execution plan by combining the execution order constraint information and the priority test sequence. The task schedule table is the result of the schedule plan analysis, which contains the execution time and order of each test task. The task schedule table ensures that the test tasks can be tested in the optimal order and time under the premise of meeting the order constraints.

[0095] Parallelism analysis is carried out on the task schedule table to obtain a list of parallel test tasks. Parallelism analysis refers to analyzing the test tasks in the task schedule table to find out the tasks that can be executed simultaneously without interfering with each other. The list of parallel test tasks is the result of the parallelism analysis, which contains the set of tasks that can be tested simultaneously. The generation of the list of parallel test tasks helps to improve the test efficiency. By executing multiple test tasks in parallel, the overall test time can be shortened and the utilization rate of test equipment can be improved.

[0096] Resource allocation is carried out according to the list of parallel test tasks and the device status data to obtain a resource allocation plan. The device status data refers to the current working status and resource usage of the test equipment. Resource allocation is to allocate test resources according to the task requirements in the list of parallel test tasks and the device status data to ensure the availability of the resources required by each test task during the execution process. The resource allocation plan is the result of the resource allocation, which contains the specific resources allocated to each test task. The resource allocation plan ensures that the test tasks can proceed smoothly with the support of the required resources.

[0097] Based on the test load trend, the resource allocation plan is optimized and adjusted to obtain a target resource scheduling plan. The test load trend refers to the change in the resource requirements of test tasks in different time periods. The optimization and adjustment of resource allocation is to analyze the test load trend and adjust the resource allocation plan to improve the resource utilization rate and test efficiency. The target resource scheduling plan is the result of the optimization and adjustment of resource allocation, which contains the optimized resource allocation plan. In the target resource scheduling plan, the resource allocation is more reasonable, which can better cope with the change of test load and ensure that the test tasks are completed with high resource utilization.

[0098] The task scheduling table is globally tested, optimized, and adjusted according to the target resource scheduling plan to obtain a global test strategy. Global test optimization and adjustment refer to the global adjustment of the task scheduling table according to the target resource scheduling plan to ensure that test tasks are carried out in the optimal order and resource allocation within the global scope. The global test strategy is the result of global test optimization and adjustment, including the test task execution plan and resource allocation plan after comprehensive optimization. The global test strategy ensures that test tasks are carried out under optimal conditions, maximizing test efficiency and equipment utilization.

[0099] In this embodiment, through the implementation of an efficient test optimization method for chip test equipment, global optimization of test tasks is achieved. Through task sequence dependency analysis and scheduling plan analysis, it is ensured that test tasks are executed in a reasonable order, avoiding resource conflicts and task blockages during the test process and improving the coherence of the test process. Based on the parallel test task list obtained from parallelism analysis, multiple non-interfering test tasks can be carried out simultaneously, significantly improving the utilization efficiency of test equipment. Resource allocation and optimization adjustment based on device status data enable reasonable allocation of test resources, reducing resource idleness and waste. Resource allocation optimization based on test load trends enables the system to dynamically adapt to changes in test tasks and maintain the stability of test efficiency. Finally, the global test strategy formed through global test optimization and adjustment realizes the optimal execution of test tasks, significantly improving the overall efficiency of chip testing while ensuring test quality.

[0100] In one embodiment, scheduling plan analysis is performed according to execution order constraint information and a priority test sequence to obtain a task scheduling table, including Execution order constraint information refers to the sequential dependency relationships between test tasks. For example, certain test items must be carried out after other tests are completed. The priority test sequence is a list of test priorities determined based on chip characteristics and test importance. Based on these two types of information, the dependency relationships of test tasks are sorted. During the sorting process, a directed acyclic graph is used to represent the dependency relationships between tasks, and the topological sorting algorithm is used to determine the priority execution order of tasks. The sorting result is an ordered sequence containing all test tasks, and this sequence satisfies all dependency relationship constraints.

[0101] Based on the obtained priority execution order and combined with the pre-set priority test sequence, matching analysis of test tasks is carried out. The matching process uses a task similarity calculation method to correspond the tasks in the priority execution order with the tasks in the priority test sequence. The similarity calculation considers multiple dimensions such as test type, test parameters, and test duration. Through matching analysis, a preliminary task scheduling list is formed, which contains the task execution order and its corresponding priority information.

[0102] Allocate specific execution times to each test task in the preliminary task scheduling list. The time allocation is based on the standard execution duration of the test tasks, the processing capabilities of the test equipment, and the switching overhead between tasks. By using the critical path analysis method, calculate the earliest start time and the latest completion time of each task to generate a time scheduling list. This list details the expected start time, end time, and total execution duration of each test task.

[0103] Based on the time scheduling list, identify test tasks that can be executed in parallel. The parallel execution identification uses a task conflict detection algorithm to analyze the mutual exclusion relationships of test tasks in terms of resource usage, time windows, etc. Combine tasks that do not conflict and meet the parallel execution conditions to form parallel task groups. The formation of parallel task groups significantly improves the resource utilization rate of the test equipment.

[0104] Optimize the allocation of scheduling resources for the preliminary task scheduling list according to the parallel task groups. The resource allocation uses a multi-objective optimization algorithm, considering objectives such as minimizing test time, maximizing resource utilization rate, and minimizing task switching overhead. During the optimization process, reasonably allocate hardware resources such as the processor, memory, and test channels of the test equipment to ensure that the parallel task groups can execute efficiently. The optimization result forms the final task scheduling table, which contains a detailed task execution plan, clearly specifying the execution time, used resources, and its coordination relationship with other tasks for each test task.

[0105] In this embodiment, by adopting a task scheduling method based on execution order constraint information and a priority test sequence, scientific scheduling and optimized allocation of chip test tasks are achieved. This method uses a directed acyclic graph and a topological sorting algorithm to perform dependency analysis on test tasks, ensuring that the execution order of test tasks strictly conforms to the dependency relationship requirements, effectively avoiding conflicts and deadlocks during the test process. Through task similarity calculation and multi-dimensional matching analysis, accurate scheduling of test tasks is realized, improving the utilization efficiency of test resources. By using parallel task group identification and a multi-objective optimization algorithm for resource allocation, the parallel processing ability of the test equipment is significantly improved, shortening the overall test time. Through systematic time allocation and resource optimization, this method not only ensures the reliability and stability of the test process but also realizes the optimal configuration of test equipment resources, providing effective technical support for improving chip test efficiency.

[0106] Refer to Figure 2 As shown, the present invention also provides an efficient test optimization system for a chip test device, which is applied to the efficient test optimization method of the chip test device in any one of the above, including: An acquisition module, which is used to acquire the device status data and test management information of the chip test device, and based on the test management information, divide the device status data into test units to obtain regional test information; An analysis module, which is used to obtain the real-time operation data of the chip testing device, match and analyze the real-time operation data with the regional test information to obtain a real-time test task group; An association module, which is used to obtain the chip performance data collected by the chip testing device, perform load prediction on the regional test information to obtain a test load trend, and perform resource planning analysis with the real-time test task group to obtain an initial test plan; A processing module, which is used to identify anomalies in the chip performance data to obtain chip anomaly information, and predict the priority of the chip anomaly information based on the test load trend to obtain a priority test sequence; A control module, which is used to globally optimize the initial test plan according to the priority test sequence to obtain a global test strategy.

[0107] Refer to Figure 3 As shown, the present invention also provides an efficient test optimization device for a chip testing device, including: A memory, which is used to store programs; A processor, which is used to execute programs to implement the steps of the efficient test optimization method for a chip testing device as described in any one of the above.

[0108] In this embodiment, the processor and the memory can be connected by a bus or other means. The memory may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as read-only memory, flash memory, hard disk, or solid-state drive. The processor may be a general-purpose processor, such as a central processing unit, a digital signal processor, an application-specific integrated circuit, or one or more integrated circuits configured to implement the embodiments of the present invention.

[0109] It should be noted that those skilled in the art can clearly understand that for the convenience and brevity of description, the specific working processes of the above-described system and each module can refer to the corresponding processes in the foregoing method embodiments, and will not be elaborated herein.

[0110] The above are only the preferred embodiments of the present invention, and do not limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made by using the description of the present invention and the content of the drawings, or directly or indirectly applied to other related technical fields, shall be equally included in the patent protection scope of the present invention.

Claims

1. An efficient test optimization method for chip testing equipment, characterized in that: include: Acquire device status data and test management information of a chip test device, divide the device status data into test units based on the test management information, and obtain regional test information; Acquire real-time operation data of the chip test equipment, match and analyze the real-time operation data with the regional test information, and obtain a real-time test task group; Obtain chip performance data collected by the chip testing equipment, perform load prediction on the regional test information, obtain test load trends, and perform resource planning analysis with the real-time test task group to obtain an initial test plan; Performing abnormality identification on the chip performance data to obtain chip abnormality information, and performing priority prediction on the chip abnormality information based on the test load trend to obtain a priority test sequence; The initial test plan is globally optimized according to the priority test sequence to obtain a global test strategy.

2. The efficient test optimization method for chip testing equipment according to claim 1, characterized in that: The step of acquiring device status data and test management information of a chip test device, dividing the device status data into test units based on the test management information, and obtaining regional test information includes: Collecting operating parameters of the chip testing equipment to obtain the equipment status data including test temperature, test voltage, and test frequency; Extracting test management data from the chip test equipment to obtain the test management information including test case configuration information, test resource allocation information, and test scheduling strategy; Performing test unit clustering on the device status data according to the test management information to obtain an initial test unit set; Performing similarity calculation on the initial test unit set to obtain a test unit similarity matrix; Performing hierarchical clustering on the initial test unit set according to the similarity matrix to obtain a test unit hierarchical tree; Performing threshold segmentation on the test unit hierarchy tree to obtain independent test areas; Mapping the independent test area according to the resource allocation information to obtain a regional resource distribution map; The regional resource distribution map and the test management information are subjected to regional association analysis to obtain regional test information.

3. The efficient test optimization method for chip testing equipment according to claim 1, characterized in that: The step of acquiring the real-time operation data of the chip test device, matching and analyzing the real-time operation data with the regional test information, and obtaining a real-time test task group includes: Performing equipment status analysis based on the real-time operation data to obtain an operation status indicator; Performing test item analysis on the regional test information to obtain a test item attribute table; According to the running status indicator, the test item attribute table is associated and matched to obtain a test matching result; Grouping the test matching results into tasks to obtain an initial task set; Perform resource allocation evaluation according to the initial task set to obtain resource allocation information; Performing test constraint analysis on the resource allocation information to obtain a task execution boundary; The test configuration of the initial task set is optimized according to the task execution boundary to obtain a real-time test task group.

4. The efficient test optimization method for chip testing equipment according to claim 1, characterized in that: The obtaining of chip performance data collected by the chip testing device, performing load prediction on the regional test information, obtaining a test load trend, and performing resource planning analysis with the real-time test task group to obtain an initial test plan includes: Extracting performance characteristics of the chip performance data to obtain a chip performance characteristic sequence; Performing hierarchical clustering on the regional test information according to the chip performance feature sequence to obtain a test region load distribution diagram; Performing test prediction on the load distribution diagram of the test area to obtain the test load trend; Performing task dependency analysis on the real-time test task group to obtain a task dependency network; Perform resource allocation calculation on the task-dependent network according to the test load trend to obtain a resource allocation matrix; The test constraint conditions of the real-time test task group are optimized and scheduled according to the resource allocation matrix to obtain the initial test plan.

5. The efficient test optimization method for chip testing equipment according to claim 1, characterized in that: The performing abnormality identification on the chip performance data to obtain chip abnormality information, and performing priority prediction on the chip abnormality information based on the test load trend to obtain a priority test sequence, includes: Performing abnormal residual analysis and abnormal outlier detection on the chip performance data to obtain an initial abnormal data cluster; Performing abnormal topology construction on the initial abnormal data cluster to obtain an abnormal topology map; Classifying the failure mode of the initial abnormal data cluster according to the abnormal topology map to obtain the chip abnormality information; Performing load distribution segmentation on the test load trend to obtain a load intensity distribution matrix; Performing anomaly matching calculation on the chip anomaly information according to the load intensity distribution matrix to obtain an anomaly matching coefficient matrix; A multi-objective priority function is constructed according to the abnormal matching coefficient matrix to obtain a priority evaluation function; The test nodes of the abnormal topology graph are iteratively sorted based on the priority evaluation function to obtain the priority test sequence.

6. The efficient test optimization method for chip testing equipment according to claim 5, characterized in that: The performing fault mode classification on the initial abnormal data cluster according to the abnormal topology diagram to obtain the chip abnormality information includes: Performing structural feature clustering on the abnormal topology graph to obtain abnormal clustering clusters; Performing fault node analysis on the abnormal cluster according to a preset fault node data table to obtain a fault feature set; Performing rule matching and classification on the abnormal clusters according to the fault feature set to obtain a fault type set; Performing frequency statistics and fault sorting on the fault type set to obtain a fault mode priority; The associated test nodes of the abnormal topology graph are sorted according to the fault mode priority to obtain the priority test sequence.

7. The efficient test optimization method for chip testing equipment according to claim 1, characterized in that: The globally optimizing the initial test scheme according to the priority test sequence to obtain a global test strategy includes: Performing task sequence dependency analysis on the real-time test task group to obtain execution sequence constraint information; Perform scheduling analysis based on the execution order constraint information and the priority test sequence to obtain a task scheduling table; Performing parallel analysis on the task scheduling table to obtain a parallel test task list; Allocate resources according to the parallel test task list and the device status data to obtain a resource allocation plan; Optimizing and adjusting the resource allocation scheme according to the test load trend to obtain a target resource scheduling scheme; The task scheduling table is globally optimized and adjusted for testing according to the target resource scheduling scheme to obtain the global testing strategy.

8. The efficient test optimization method for chip testing equipment according to claim 7, characterized in that: The scheduling plan analysis is performed according to the execution order constraint information and the priority test sequence to obtain a task scheduling table, including Sorting the test tasks according to the dependency relationships according to the execution order constraint information to obtain a task priority execution order; Match the test tasks according to the priority execution order and the priority test sequence to obtain a preliminary task scheduling list; Allocating time for the preliminary task scheduling list to obtain a time scheduling list; According to the time scheduling list, the test tasks are identified for parallel execution to obtain a parallel task group; The scheduling resources are optimally allocated to the preliminary task scheduling list according to the parallel task group to obtain the task scheduling table.

9. An efficient test optimization system for chip testing equipment, characterized in that: The efficient test optimization method for the chip test equipment according to any one of claims 1 to 8 comprises: An acquisition module, the acquisition module is used to obtain device status data and test management information of a chip test device, and divide the device status data into test units based on the test management information to obtain regional test information; An analysis module, the analysis module is used to obtain real-time operation data of the chip test equipment, match and analyze the real-time operation data with the regional test information, and obtain a real-time test task group; An association module, the association module is used to obtain chip performance data collected by the chip testing equipment, perform load prediction on the regional test information, obtain a test load trend, and perform resource planning analysis with the real-time test task group to obtain an initial test plan; A processing module, the processing module is used to identify abnormalities of the chip performance data, obtain chip abnormality information, and perform priority prediction on the chip abnormality information based on the test load trend to obtain a priority test sequence; A control module is used to globally optimize the initial test plan according to the priority test sequence to obtain a global test strategy.

10. An efficient test optimization device for chip testing equipment, characterized in that: include: Memory, used to store programs; The processor is used to execute the program to implement the various steps of the efficient test optimization method for a chip testing device as described in any one of claims 1-8.

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