Display panel and display device

Abstract

The embodiment of the invention provides a display panel and a display device. A first substrate comprises a first substrate, a transistor array layer, a pixel electrode layer, a common electrode layer, a first inorganic insulating layer and a second inorganic insulating layer; the transistor array layer is arranged on one side of the first substrate, and the pixel electrode layer and the common electrode layer are arranged on the side, away from the first substrate, of the transistor array layer; the transistor array layer comprises a transistor, the pixel electrode layer comprises a pixel electrode, and the common electrode layer comprises a common electrode; the insulating layer between one of the pixel electrode layer and the common electrode layer close to the transistor array layer and the transistor array layer is a first inorganic insulating layer; the second inorganic insulating layer is disposed between the pixel electrode layer and the common electrode layer. The insulating layer between one of the pixel electrode layer and the common electrode layer close to the transistor array layer and the transistor array layer is set as the inorganic insulating layer, so that the thickness of the display panel can be reduced, the preparation cost of the display panel is reduced, and the process steps are reduced.

Description

[0001] This application is a divisional application of the application with the application number 202310423575.3, the application date of April 19, 2023, and the invention title "A display panel and a display device".

Technical Field

[0002] This application relates to the field of display technologies, and particularly relates to a display panel and a display device.

Background Art

[0003] The active matrix flat panel display technology provides strong support for the development of display devices towards being thinner, clearer, and having a larger screen-to-body ratio. An important component of the active matrix flat panel display technology is the array substrate, that is, a substrate including transistors arranged in an array (hereinafter referred to as the array substrate), and the array substrate can drive pixels orderly and accurately.

[0004] The array substrate is widely used in the fields of liquid crystal display, organic light emitting display, micro light emitting diode (Micro-LED) display, and mini light emitting diode (Mini-LED) display, etc. How to optimize the performance and manufacturing process of existing display panels using the array substrate is an important research topic.

[0005]

Content of the Application

[0006] In view of this, embodiments of this application provide a display panel and a display device to optimize the performance and manufacturing process of existing display panels using the array substrate.

[0007] In a first aspect, an embodiment of this application provides a display panel, including a first substrate; the first substrate includes a first substrate, a transistor array layer, a pixel electrode layer, a common electrode layer, a first inorganic insulating layer, and a second inorganic insulating layer; the transistor array layer is disposed on one side of the first substrate, and the pixel electrode layer and the common electrode layer are both disposed on the side of the transistor array layer away from the first substrate; the transistor array layer includes transistors, the pixel electrode layer includes pixel electrodes, and the common electrode layer includes common electrodes; the insulating layer between the pixel electrode layer and the common electrode layer that is closer to the transistor array layer and the transistor array layer is the first inorganic insulating layer; the second inorganic insulating layer is disposed between the pixel electrode layer and the common electrode layer.

[0008] In a second aspect, an embodiment of this application provides a display device, including the display panel provided in the first aspect.

[0009] In the embodiments of the present application, by setting the insulating layer between one of the pixel electrode layer and the common electrode layer close to the transistor array layer and the transistor array layer as an inorganic insulating layer, the thickness of the display panel can be reduced. At the same time, the inorganic insulating layer has a lower cost and a simpler manufacturing process compared to the organic insulating layer, so the manufacturing cost of the display panel can be reduced. In addition, since the insulating layer between the pixel electrode layer and the common electrode layer also includes an inorganic insulating layer, the process steps for fabricating vias penetrating the first inorganic insulating layer and the second inorganic insulating layer can be reduced, that is, the portions of these vias located in the first inorganic insulating layer and the second inorganic insulating layer can be fabricated in a single etching process.

Description of the Drawings

[0010] To more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0011] Figure 1 Schematic diagram of a first substrate of a display panel provided by an embodiment of the present application;

[0012] Figure 2 Along Figure 1 A cross-sectional schematic diagram in the M1-M2 direction;

[0013] Figure 3 Along Figure 1 Another cross-sectional schematic diagram in the M1-M2 direction;

[0014] Figure 4 Schematic diagram of another first substrate of a display panel provided by an embodiment of the present application;

[0015] Figure 5 Along Figure 4 A cross-sectional schematic diagram in the N1-N2 direction;

[0016] Figure 6 Partial schematic diagram of a first substrate in a display panel provided by an embodiment of the present application;

[0017] Figure 7 Along Figure 6 A cross-sectional schematic diagram in the S1-S2 direction;

[0018] Figure 8 Another partial schematic diagram of a first substrate in a display panel provided by an embodiment of the present application;

[0019] Figure 9 Along Figure 8 A cross-sectional schematic diagram in the L1-L2 direction;

[0020] Figure 10 It is a partial schematic diagram of the first substrate in another display panel provided by an embodiment of the present application;

[0021] Figure 11 It is a schematic cross-sectional view along the Figure 10 K1-K2 direction in;

[0022] Figure 12 It is a partial schematic diagram of the first substrate in another display panel provided by an embodiment of the present application;

[0023] Figure 13 Along Figure 12 It is a schematic cross-sectional view along the V1-V2 direction in;

[0024] Figure 14 It is a partial schematic diagram of the first substrate in another display panel provided by an embodiment of the present application;

[0025] Figure 15 Along Figure 14 It is a schematic cross-sectional view along the F1-F2 direction in;

[0026] Figure 16 It is a partial schematic diagram of the first substrate in another display panel provided by an embodiment of the present application;

[0027] Figure 17 It is a schematic cross-sectional view along the Figure 16 T1-T2 direction in;

[0028] Figure 18 It is a partial schematic diagram of the first substrate in another display panel provided by an embodiment of the present application;

[0029] Figure 19 It is a schematic cross-sectional view along the Figure 18 I1-I2 direction in;

[0030] Figure 20 It is a partial schematic diagram of the first substrate in another display panel provided by an embodiment of the present application;

[0031] Figure 21 It is a partial schematic diagram of the first substrate in another display panel provided by an embodiment of the present application;

[0032] Figure 22 It is a schematic cross-sectional view along the Figure 21 D1-D2 direction in;

[0033] Figure 23 It is a schematic cross-sectional view along the Figure 21 Another schematic cross-sectional view along the D1-D2 direction in;

[0034] Figure 24Is a schematic cross-sectional view along the Figure 21 J1-J2 direction in Figure 21 ;

[0035] Figure 25 Is a schematic cross-sectional view along the Figure 21 Another schematic cross-sectional view along the J1-J2 direction in Figure 21 ;

[0036] Figure 26 Is a partial schematic view of the first substrate in another display panel provided by an embodiment of the present application;

[0037] Figure 27 Is a partial schematic view of the first substrate in another display panel provided by an embodiment of the present application;

[0038] Figure 28 Is a partial schematic view of the first substrate in another display panel provided by an embodiment of the present application;

[0039] Figure 29 Is a partial schematic view of a display panel provided by an embodiment of the present application;

[0040] Figure 30 Is Figure 29 A schematic view of some structures in the X1 region in Figure 29 ;

[0041] Figure 31 Is Figure 30 A schematic cross-sectional view along the A1-A2 direction in Figure 30 ;

[0042] Figure 32 Is Figure 29 Another schematic view of some structures in the X1 region in Figure 29 ;

[0043] Figure 33 Is a partial schematic view of another display panel provided by an embodiment of the present application;

[0044] Figure 34 Is Figure 33 A schematic view of some structures in the X2 region in Figure 33 ;

[0045] Figure 35 Is a partial schematic view of another display panel provided by an embodiment of the present application;

[0046] Figure 36 Is a partial schematic view of another display panel provided by an embodiment of the present application;

[0047] Figure 37 Is a schematic view of a display device provided by an embodiment of the present application.

Detailed implementation manners

[0048] In order to better understand the technical solution of the present application, the embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0049] It should be clear that the described embodiments are only a part of the embodiments of the present application, rather than all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present application.

[0050] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the present application. The singular forms of "a", "the" and "said" used in the embodiments of the present application and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0051] It should be understood that the term "and / or" used herein is only a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B may represent: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " herein generally represents an "or" relationship between the associated objects before and after.

[0052] In the description of this specification, it should be understood that the words such as "substantially", "approximately", "about", "around", "roughly", "generally" used in the claims and embodiments of the present application refer to values that can be generally recognized within a reasonable process operation range or tolerance range, rather than an exact value.

[0053] It should be understood that although terms such as first, second, and third may be used in the embodiments of the present application to describe regions, etc., these regions should not be limited to these terms. These terms are only used to distinguish regions from each other. For example, without departing from the scope of the embodiments of the present application, the first region may also be referred to as the second region, and similarly, the second region may also be referred to as the first region.

[0054] Through careful and in-depth research, the applicant of this case provides a solution to the problems existing in the prior art.

[0055] Figure 1 It is a schematic diagram of a first substrate of a display panel provided for the embodiments of the present application. Figure 2 is along Figure 1 a cross-sectional schematic diagram in the M1-M2 direction in Figure 3 is along Figure 1 another cross-sectional schematic diagram in the M1-M2 direction in

[0056] As Figures 1 to 3 shown, the display panel provided by the embodiments of the present application includes a first substrate 01, and the first substrate 01 includes a first substrate 11, a transistor array layer 12, a pixel electrode layer 13, a common electrode layer 14, a first inorganic insulating layer 15, and a second inorganic insulating layer 16.

[0057] The transistor array layer 12, the pixel electrode layer 13, and the common electrode layer 14 can be disposed on the same side of the first substrate 11. The transistor array layer 12 includes a plurality of transistors 120, the pixel electrode layer 13 includes a plurality of pixel electrodes 130, and the common electrode layer 14 includes a common electrode 140.

[0058] Both the pixel electrode layer 13 and the common electrode layer 14 are disposed on the side of the transistor array layer 12 away from the first substrate 11. Then, the manufacturing processes of the pixel electrode layer 13 and the common electrode layer 14 are carried out after the manufacturing process of the transistor array layer 12. Along the direction Z perpendicular to the plane where the first substrate 11 is located, the common electrode 140 covers at least two pixel electrodes 130, that is, the pixels to which the plurality of pixel electrodes 130 belong share the common electrode 140.

[0059] The transistor 120 can act as a switch, in combination with Figure 1 and Figure 2 and in combination with Figure 1 and Figure 3 , the first pole 121 and the second pole 122 of at least some of the transistors 120 are electrically connected to the data line DL and the pixel electrode 130 respectively, and these transistors 120 are used as switches between the data line DL and the pixel electrode 130.

[0060] In the pixel electrode layer 13 and the common electrode layer 14, the insulating layer between the one closer to the transistor array layer 12 and the transistor array layer 12 is the first inorganic insulating layer 15. That is, the insulating layer provided between the one closer to the transistor array layer 12 in the pixel electrode layer 13 and the common electrode layer 14 and the transistor array layer 12 only includes an inorganic insulating layer.

[0061] Wherein, the surface of the first inorganic insulating layer 15 closer to the first substrate 11 can be in contact with the transistor array layer 12, and the surface of the first inorganic insulating layer 15 away from the first substrate 11 can be in contact with the one closer to the transistor array layer 12 in the pixel electrode layer 13 and the common electrode layer 14.

[0062] For example, as Figure 3 shown, if the pixel electrode layer 13 is located on the side of the common electrode layer 14 closer to the transistor array layer 12, then the insulating layer between the pixel electrode layer 13 and the transistor array layer 12 is the first inorganic insulating layer 15. Optionally, the surface of the first inorganic insulating layer 15 closer to the first substrate 11 can be in contact with the transistor array layer 12, and the surface of the first inorganic insulating layer 15 away from the first substrate 11 can be in contact with the pixel electrode layer 13.

[0063] For example, as Figure 2As shown in the figure, the common electrode layer 14 is located on the side of the pixel electrode layer 13 close to the transistor array layer 12, and the insulating layer between the common electrode layer 14 and the transistor array layer 12 is the first inorganic insulating layer 15. Optionally, the surface of the first inorganic insulating layer 15 close to the first substrate 11 may be in contact with the transistor array layer 12, and the surface of the first inorganic insulating layer 15 away from the first substrate 11 may be in contact with the common electrode layer 14.

[0064] In the embodiment of the present application, the second inorganic insulating layer 16 is disposed between the pixel electrode layer 13 and the common electrode layer 14. Further, the insulating layer between the pixel electrode layer 13 and the common electrode layer 14 is the second inorganic insulating layer 16, that is, the insulating layer disposed between the pixel electrode layer 13 and the common electrode layer 14 only includes an inorganic insulating layer.

[0065] Among them, in the surface of the second inorganic insulating layer 16 close to the first substrate 11 and the surface away from the first substrate 11, one can be in contact with the pixel electrode layer 13, and the other can be in contact with the common electrode layer 14.

[0066] In the embodiment of the present application, by setting the insulating layer between the pixel electrode layer 13 and the common electrode layer 14, which is close to the transistor array layer 12, as an inorganic insulating layer, since the inorganic insulating layer has a thinner thickness than the organic insulating layer, therefore, the thickness of the display surface provided by the embodiment of the present application can be thinner. The inorganic insulating layer is usually prepared by methods such as chemical deposition. The inorganic insulating layer has a lower cost and a simpler preparation process than the organic insulating layer, so the preparation cost of the display panel can be reduced; and the preparation method of the inorganic insulating layer does not generate substances that damage the devices in the first substrate, so the preparation yield of the display panel can be improved.

[0067] In addition, the insulating layer between the pixel electrode layer 13 and the common electrode layer 14 also includes an inorganic insulating layer. Then, when fabricating vias that need to penetrate the first inorganic insulating layer 15 and the second inorganic insulating layer 16, a single etching process can be used to simultaneously etch the first inorganic insulating layer 15 and the second inorganic insulating layer 16 to simultaneously form vias on the first inorganic insulating layer 15 and vias on the second inorganic insulating layer 16. And when there are also vias in the second inorganic insulating layer 16 that do not penetrate the vias in the first inorganic insulating layer 15, these vias can also be formed together in the above etching process, greatly reducing the etching process.

[0068] In an embodiment of the present application, the first inorganic insulating layer 15 includes at least one of silicon oxide and silicon nitride. Then the first inorganic insulating layer 15 can be a silicon oxide layer, a silicon nitride layer, or a composite film layer of silicon oxide and silicon nitride arranged in layers. In addition, the first inorganic insulating layer 15 can also be a mixture film layer containing silicon oxide and silicon nitride.

[0069] In one embodiment of the present application, the second inorganic insulating layer 16 includes at least one of silicon oxide and silicon nitride. Then, the second inorganic insulating layer 16 can be a silicon oxide layer, a silicon nitride layer, or a composite film layer of silicon oxide and silicon nitride arranged in a stack. In addition, the second inorganic insulating layer 16 can also be a mixture film layer containing silicon oxide and silicon nitride.

[0070] In one embodiment of the present application, both the first inorganic insulating layer 15 and the second inorganic insulating layer 16 include silicon oxide, or both include silicon nitride. For example, the first inorganic insulating layer 15 is a composite film layer of silicon oxide and silicon nitride arranged in a stack, and the second inorganic insulating layer 16 is a silicon oxide layer or a silicon nitride layer.

[0071] Since the preparation processes of silicon oxide and silicon nitride are already very mature and the patterning processes of silicon oxide and silicon nitride are also very mature, when the first inorganic insulating layer 15 and the second inorganic insulating layer 16 include silicon oxide and / or silicon nitride, the preparation difficulty of the display panel can be reduced. In addition, silicon nitride and silicon oxide have good compactness, which can isolate the influence of water and oxygen on the device and can prevent the mutual interference of conductive particles between the transistor array layer, the pixel electrode layer, and the common electrode layer.

[0072] In one embodiment of the present application, the film thickness of the first inorganic insulating layer 15 is less than or equal to 6000 angstroms. For example, the thickness of the first inorganic insulating layer 15 can be about 3000 angstroms, about 2000 angstroms, or about 1000 angstroms.

[0073] In one embodiment of the present application, the film thickness of the second inorganic insulating layer 16 is less than or equal to 6000 angstroms. For example, the thickness of the second inorganic insulating layer 16 can be about 3000 angstroms, about 2000 angstroms, or about 1000 angstroms.

[0074] Setting the thicknesses of both the first inorganic insulating layer 15 and the second inorganic insulating layer 16 to be less than 6000 angstroms can effectively shorten the preparation cycle of the display panel. And at least some of the vias included in the first inorganic insulating layer 15 and the second inorganic insulating layer 16 penetrate through. When these penetrating vias are prepared by a single etching process, the process difficulty is low and the process yield is high.

[0075] In one embodiment of the present application, as Figure 2 and Figure 3 shown, the film thickness of the first inorganic insulating layer 15 can be greater than the film thickness of the second inorganic insulating layer 16. For example, the film thickness of the first inorganic insulating layer 15 is about 3000 angstroms, and the film thickness of the second inorganic insulating layer 16 is about 1000 angstroms.

[0076] Since the first inorganic insulating layer 15 is disposed on the transistor array layer 12, setting the thickness of the first inorganic insulating layer 15 to be relatively large can make the surface of the first inorganic insulating layer 15 away from the transistor array layer 12 relatively flat, and thus can provide a relatively flat bearing surface for the structure disposed thereon.

[0077] Setting the thickness of the second inorganic insulating layer 15 to be relatively small is conducive to realizing the thinning of the display panel and reducing the preparation period of the first substrate. In addition, since the thicknesses of the pixel electrode layer 13 and the common electrode layer 14 are usually relatively thin, whether the second inorganic insulating layer 15 is prepared after the pixel electrode layer 13 or after the common electrode layer 14, the surface thereof away from the first inorganic insulating layer 15 is relatively flat, and there is no significant process defect risk.

[0078] In an embodiment of the present application, the transistor 120 includes a polysilicon semiconductor layer. Specifically, the transistors in the transistor array layer 12 may be low-temperature polysilicon transistors.

[0079] Figure 4 FIG. is a schematic diagram of a first substrate of another display panel provided by an embodiment of the present application. Figure 5 is along Figure 4 a schematic cross-sectional view in the N1-N2 direction in FIG.

[0080] It should be noted that, for clear illustration, the common electrode layer 14 included in the accompanying drawings of the following embodiments is located between the pixel electrode layer 13 and the substrate 11. However, unless otherwise specified, the inventive concept in the following embodiments is equally applicable to a display panel in which the pixel electrode layer 13 is located between the common electrode layer 14 and the substrate 11.

[0081] Combined with Figure 4 and Figure 5 , the common electrode layer 14 includes a plurality of common electrodes 140, and the common electrodes 140 can be reused as touch electrodes. The common electrodes 140 can be reused as touch electrodes for mutual capacitance touch detection or can be reused as touch electrodes for self-capacitance touch detection.

[0082] In an embodiment of the present application, as Figure 4 and Figure 5 shown, the first substrate 01 further includes touch traces TL, and the touch traces TL provide signals for the common electrodes 140. Among them, the touch traces TL can be electrically connected to the common electrodes 140 and provide signals related to touch detection for them.

[0083] In the embodiment of the present application, the touch traces TL are disposed on the side of the common electrode layer 14 close to the first substrate 11. Specifically, the touch traces TL can be disposed on the side of the first inorganic insulating layer 15 close to the first substrate 11.

[0084] Figure 6 A partial schematic diagram of a first substrate in a display panel provided by an embodiment of the present application. Figure 7 Along Figure 6 A cross-sectional schematic diagram in the S1 - S2 direction in

[0085] In a technical solution of the present application, in combination with Figure 6 and Figure 7 , at least part of the touch trace TL can overlap with the common electrode 140 in the direction Z perpendicular to the plane where the display panel is located. A first slit 141 is formed on the common electrode 140, and along the direction Z perpendicular to the plane where the display panel is located, at least part of the first slit 141 overlaps with part of the touch trace TL, that is, at least part of the first slit 141 on the common electrode 140 exposes a part of the touch trace TL.

[0086] Since the insulating layer between the touch trace TL and the common electrode layer 14 is mainly the first inorganic insulating layer 15 or mainly the first inorganic insulating layer 15 and the second inorganic insulating layer 16, and the distance between the touch trace TL and the common electrode layer 14 in the direction Z perpendicular to the plane where the display panel is located is small, the coupling capacitance between the touch trace TL and the common electrode 140 that overlaps with it and is not electrically connected increases, and the signal interference is enhanced.

[0087] By forming the first slit 141 that partially overlaps with the touch trace TL on the common electrode 140, the overlapping area between the common electrode 140 and the touch trace TL in the direction perpendicular to the plane where the display panel is located is reduced, the coupling capacitance between the two is reduced, and the signal interference problem between the two is effectively alleviated.

[0088] Figure 8 Another partial schematic diagram of a first substrate in a display panel provided by an embodiment of the present application. Figure 9 Along Figure 8 A cross-sectional schematic diagram in the L1 - L2 direction in

[0089] In a technical solution of the present application, in combination with Figure 8 and Figure 9 , a second slit 142 is included between adjacent common electrodes 140. Along the direction Z perpendicular to the plane where the display panel is located, the second slit 142 overlaps with at least part of at least part of the touch trace TL. That is, part of the touch trace TL is routed at the position where the second slit 142 is located, and the second slit 142 exposes at least part of this part of the touch trace TL.

[0090] By routing part of the touch trace TL at the position where the second slit 142 is located, the overlapping area between this part of the touch trace TL and the common electrode 14 can be reduced, and further the coupling capacitance and signal interference between this part of the touch trace TL and the common electrode 14 can be reduced.

[0091] In one implementation of the present technical solution, the part of the touch trace TL that overlaps with the second slit 142 is completely exposed by the second slit 142.

[0092] Figure 10 It is a partial schematic diagram of the first substrate in another display panel provided by an embodiment of the present application. Figure 11 along Figure 10 is a cross-sectional schematic diagram in the K1-K2 direction in

[0093] In one technical solution of the present application, in combination with Figure 10 and Figure 11 , a first slit 141 is formed on the common electrode 140, and a second slit 142 is included between adjacent common electrodes 140. Along the direction Z perpendicular to the plane where the display panel is located, at least part of the first slit 141 overlaps with part of the touch trace TL, and the second slit 142 overlaps with at least part of at least part of the touch trace TL.

[0094] Figure 12 It is a partial schematic diagram of the first substrate in another display panel provided by an embodiment of the present application. Figure 13 along Figure 12 is a cross-sectional schematic diagram in the V1-V2 direction in

[0095] In an embodiment of the present application, in combination with Figure 12 and Figure 13 , the first substrate 01 further includes a dummy touch trace TL', and the dummy touch trace TL' is disposed on the same layer as the touch trace TL and is electrically insulated from the common electrode 140.

[0096] In one implementation of this embodiment, as shown in Figure 12 , the dummy touch trace TL' can be in the same column as the touch trace TL.

[0097] When the first slit 141 is formed on the common electrode 140, along the direction Z perpendicular to the plane where the display panel is located, part of the first slit 141 overlaps with part of the touch trace TL, and part of the first slit 141 overlaps with part of the dummy touch trace TL', that is, part of the first slit 141 on the common electrode 140 exposes a part of the touch trace TL, and part of the first slit 141 on the common electrode 140 exposes at least a part of the dummy touch trace TL.

[0098] The lengths of multiple touch traces TL in the first substrate 01 are different. The touch traces TL with longer lengths can overlap with more common electrodes 140 relative to the touch traces TL with shorter lengths. Among the multiple common electrodes 140 arranged along the extending direction of the touch trace TL, if the number of touch traces TL respectively overlapped by at least two common electrodes 140 is different, then the number of first slits 141 respectively formed on the at least two common electrodes 140 and overlapping with the touch trace TL is different, which will result in a difference in the loads of the at least two common electrodes 140.

[0099] By providing dummy touch traces TL' and first slits 141 overlapping with the dummy touch traces TL', the above problems can be effectively solved. In addition, by providing dummy touch traces TL' and first slits 141 overlapping with the dummy touch traces TL1', the touch traces TL and the dummy touch traces TL1' can be more evenly distributed as a set, and the number of first slits 141 on each common electrode 140 is also more uniform, thereby avoiding the problem of uneven display on the display panel caused by uneven arrangement of the touch traces TL and uneven arrangement of the first slits 141.

[0100] It should be noted that in some embodiments, along the extending direction of the touch trace TL, different touch traces TL overlap with the same number of common electrodes 140, then the dummy touch electrodes TL' in the same column as the touch trace TL may not be provided. For example, as Figure 10 shown, the touch trace TL is not disconnected near the position where it is electrically connected to the first common electrode 140, and the touch trace TL can respectively overlap with the uppermost common electrode 140 and the lowermost common electrode 140 in the display panel along the column direction.

[0101] In another implementation manner of this embodiment, the dummy touch traces TL' can be arranged in the same direction as multiple touch traces TL, and the length of the dummy touch traces TL' can be basically the same as the length of the touch traces TL, then the number of common electrodes 140 overlapped by the dummy touch traces TL' can be the same as the number of common electrodes 140 overlapped by the touch traces TL.

[0102] In addition, the first slits 141 formed on the common electrode 140 can also overlap with the dummy touch traces TL'. Then the number of first slits 141 overlapped by the dummy touch traces TL' can be the same as the number of first slits 141 overlapped by the touch traces TL.

[0103] Figure 14 It is a partial schematic diagram of the first substrate in another display panel provided by the embodiment of the present application. Figure 15 Along Figure 14 the cross-sectional schematic diagram in the F1 - F2 direction in

[0104] In one embodiment of the present application, in combination with Figure 14 and Figure 15 , a second slit 142 is included between adjacent common electrodes 140. Along the direction Z perpendicular to the plane where the display panel is located, the second slit 142 at least partially overlaps with at least part of the dummy touch trace TL'. Specifically, the dummy touch trace TL' that at least partially overlaps with the second slit 142 and the touch trace TL that at least partially overlaps with the second slit 142 can be located in the same column.

[0105] Figure 16 FIG. is a partial schematic diagram of a first substrate in another display panel provided by an embodiment of the present application. Figure 17 is along Figure 16 A cross-sectional schematic diagram in the T1-T2 direction in

[0106] In one embodiment of the present application, in combination with Figure 16 and Figure 17 , the common electrode layer 14 is disposed on a side of the pixel electrode layer 13 close to the transistor array layer 12, and the touch trace TL is disposed on a side of the common electrode layer 14 close to the first substrate 11. The pixel electrode layer 13 further includes a cross-bridge electrode 131, and the cross-bridge electrode 131 is used to electrically connect the touch trace TL and the common electrode 140.

[0107] In a corresponding implementation manner of this embodiment, the first inorganic insulating layer 15 is provided with a plurality of first vias 150, and the second inorganic insulating layer 16 is provided with a plurality of second vias 160. Among them, some of the second vias 160 communicate with the first vias 150, that is, these second vias 160 overlap with the first vias 150 along the direction Z perpendicular to the plane where the display panel is located. As shown in Figure 17 , the second vias 160 that communicate with the first vias 150 are marked as second vias 161. In addition, some of the second vias 160 do not overlap with the first vias 150 along the direction Z perpendicular to the plane where the display panel is located. As shown in Figure 17 , the second vias 160 that do not overlap with the first vias 150 are marked as second vias 162.

[0108] In this implementation manner, please combine Figure 16 and Figure 17 , the cross-bridge electrode 131 is electrically connected to the common electrode 140 through the second via 160, and the cross-bridge electrode 131 is electrically connected to the touch trace TL through the through second via 160 and the first via 150. That is, the cross-bridge electrode 131 and the common electrode 140 are electrically connected through the second via 162, and the cross-bridge electrode 131 and the touch trace TL are electrically connected through the second via 161 and the first via 150.

[0109] In an embodiment of the present application, the through first via 150 and the second via 161 are obtained by etching the first inorganic insulating layer 15 and the second inorganic insulating layer 16 respectively. Since the first inorganic insulating layer 15 and the second inorganic insulating layer 16 can adopt the same etching process to form vias, the through first via 150 and the second via 161 can be completed in one etching process step. In addition, the second via 162 can also be completed in one etching process step with the second via 161.

[0110] It should be noted that the cross-bridge electrode 131 is electrically connected to the common electrode 140 through the second via 160, which means that the cross-bridge electrode 131 is electrically connected to the common electrode 140 through the conductive structure in the second via 160. Among them, the conductive structure in the second via 160 can specifically be the part deposited into the second via 162 when preparing the pixel electrode layer 130.

[0111] It should be noted that the cross-bridge electrode 131 is electrically connected to the touch trace TL through the through first via 150 and the second via 160, which means that the cross-bridge electrode 131 is electrically connected to the common electrode 140 through the conductive structures in the through first via 150 and the second via 160. Among them, the conductive structures in the through first via 150 and the second via 160 can specifically be the parts deposited into the second via 161 and the first via 150 when preparing the pixel electrode layer 130.

[0112] Figure 18 It is a partial schematic diagram of the first substrate in another display panel provided by the embodiment of the present application. Figure 19 Along Figure 18 is a cross-sectional schematic diagram in the I1-I2 direction.

[0113] In a technical solution of the present application, combining Figure 18 with Figure 19 , a first opening 143 is formed on the common electrode 140. Along the direction Z perpendicular to the plane where the display panel is located, the first opening 143 overlaps with the first via 150.

[0114] The overlap of the first via 150 and the first opening 143 on the common electrode 140 is equivalent to making an avoidance design for the common electrode 140 in the area where the first via 150 is located, reducing the coupling capacitance between the common electrode 140 and the touch trace TL.

[0115] Figure 20 It is a partial schematic diagram of the first substrate in another display panel provided by the embodiment of the present application.

[0116] In one implementation, as Figure 20 shown, the opening areas of at least two first openings 143 are different. For example, as Figure 20As shown, at least two first openings 143 include a first opening 143a and a first opening 143b, and the opening area of the first opening 143a is larger than that of the first opening 143b.

[0117] In this implementation, the area of the first opening 143 can be flexibly set according to the different positions where the first opening 143 is located. For example, when the first opening 143 needs to be opened at some positions of the common electrode 140 and there are no other functional structures (such as conductive structures) below this position, the areas of these first openings 143 can be set larger; when the first opening 143 needs to be opened at some positions of the common electrode 140 and there are other functional structures (such as conductive structures) with a certain area below this position, the areas of these first openings 143 can be set smaller to avoid damaging the above-mentioned other functional structures. In addition, when the first openings 143 are respectively opened at different positions of the common electrode 140, the surrounding environments of these different positions may be different. For example, different heights at different positions may result in different etching degrees of the first opening 143 by the etching solution, and further result in different areas of the first openings 143 at different positions.

[0118] In an embodiment of the present application, the first substrate 01 further includes data lines DL, and the data lines DL provide signals for the pixel electrodes 130. Among them, the data lines DL can be electrically connected to the pixel electrodes 130 through transistors 120, and the data lines DL provide the data signals required for the display panel to emit light for the correspondingly electrically connected pixel electrodes 130.

[0119] In an embodiment of the present application, the data lines DL are arranged on the side of the common electrode 14 close to the first substrate 11. Specifically, the data lines DL are arranged on the side of the first inorganic insulating layer 15 close to the first substrate 11.

[0120] In a technical solution of the present application, in combination Figure 6 with Figure 7 and, in combination Figure 12 with Figure 13 , at least part of the data lines DL can overlap with the common electrode 140 in the direction Z perpendicular to the plane of the display panel. The common electrode 140 is provided with a slit, and in the direction Z perpendicular to the plane of the display panel, the data lines DL do not overlap with the slit on the common electrode 140. For example, as Figure 6 with Figure 7 and, Figure 12 with Figure 13 shown, the common electrode 140 is provided with a first slit 141, and in the direction Z perpendicular to the plane of the display panel, the data lines DL do not overlap with the first slit 141. That is, in this technical solution, the overlapping part of the data lines DL and the common electrode 140 is covered by the solid conductive part of the common electrode 140.

[0121] Since the insulating layer between the data line DL and the common electrode 140 is mainly the first inorganic insulating layer 15 or mainly the first inorganic insulating layer 15 and the second inorganic insulating layer 16, and the distance between the data line DL and the common electrode layer 140 in the direction Z perpendicular to the plane of the display panel is small, the risk of interference of the signal transmitted by the data line DL with the electric field between the pixel electrode 130 and the common electrode 140 is increased.

[0122] For example, referring to Figure 6 and Figure 12 , taking the leftmost data line DL as an example for illustration, when the data line DL provides a signal to the pixel electrode 130 located in the first row and the first column, since the distance between the data line DL and the common electrode 140 is reduced, a strong electric field is generated between the signal potential transmitted by the data line DL and the potential of the common electrode 140. This strong electric field also exists at the position of the pixel electrode 130 in the first row and the second column, so the risk of interference of the signal transmitted on the data line DL with the display of multiple pixels is increased.

[0123] When the electric field between the pixel electrode 130 and the common electrode 140 is used to drive the liquid crystal to deflect, the risk that the signal transmitted by the data line DL causes the liquid crystal to be in an incorrect deflection state is increased.

[0124] In the present technical solution, the overlapping part of the data line DL and the common electrode 140 is covered by the solid conductive part of the common electrode 140, so that the common electrode 140 can shield the electric field between the data line DL and the common electrode 140 from propagating to the side of the common electrode 140 far from the first substrate 11, effectively solving the above problems.

[0125] In a technical solution of the present application, in combination with Figure 8 and Figure 9 , in combination with Figure 14 and Figure 15 , there are slits between adjacent common electrodes 140, and at least part of the slits between the data line DL and the adjacent common electrodes 140 do not overlap in the direction Z perpendicular to the plane of the display panel.

[0126] For example, as shown in Figure 8 and Figure 9 , Figure 14 and Figure 15 , there is a second slit 142 between adjacent common electrodes 140, and the data line DL does not overlap with the second slit 142 in the direction Z perpendicular to the plane of the display panel. It should be noted that the extending direction of the second slit 142 is substantially parallel to the extending direction of the data line DL.

[0127] This solution can also effectively solve the interference of the signal transmitted by the data line DL with the electric field between the pixel electrode 130 and the common electrode 140.

[0128] In one embodiment of the present application, in combination with Figure 10 and Figure 11 , along the direction Z perpendicular to the plane where the display panel is located, the data line DL does not overlap with the slit on the common electrode 140, and at least part of the slit between the data line DL and the adjacent common electrode 140 does not overlap.

[0129] Figure 21 FIG. is a partial schematic diagram of the first substrate in another display panel provided by an embodiment of the present application. Figure 22 is along Figure 21 A cross-sectional schematic diagram in the D1-D2 direction in

[0130] In one embodiment of the present application, in combination with Figure 21 and Figure 22 , the first pole 121 of the transistor 120 is electrically connected to the data line DL and the second pole 122 of the transistor 120 is electrically connected to the pixel electrode 130. For example, the source of the transistor 120 is its first pole 121 and the drain of the transistor 120 is its second pole 122. The data line DL is electrically connected to a plurality of pixel electrodes 130 through a plurality of transistors 120 respectively.

[0131] In a technical solution of the present application, in combination with Figure 21 and Figure 22 as shown, a second opening 144 is formed on the common electrode 140, and along the direction Z perpendicular to the plane where the display panel is located, the second opening 144 at least partially overlaps with the first pole 121 of the transistor 120. That is, along the direction Z perpendicular to the plane where the display panel is located, a hollowed-out portion is provided at the position on the common electrode 140 that overlaps with the first pole 121 of the transistor 120, thereby reducing the interference of the signal on the first pole 121 of the transistor 120 to the common electrode 140.

[0132] Figure 23 is along Figure 21 Another cross-sectional schematic diagram in the D1-D2 direction in

[0133] In one implementation manner, as Figure 22 shown, the common electrode layer 14 is disposed on the side of the pixel electrode layer 13 close to the first substrate 11. The effect of forming the second opening 144 on the common electrode 140 further includes: avoiding electrical conduction between the common electrode 140 and the data line DL when the first pole 121 of the transistor 120 is electrically connected to the data line DL through a via.

[0134] In one implementation manner, as Figure 23 shown, the pixel electrode layer 13 is disposed on the side of the common electrode layer 14 close to the first substrate 11. At this time, the second opening 144 can still be formed on the common electrode 140.

[0135] Figure 24 A schematic cross-sectional view along the Figure 21 J1-J2 direction in

[0136] In a technical solution of the present application, in combination with Figure 21 and Figure 24 as shown, a third opening 145 is formed in the common electrode 140, and along the direction Z perpendicular to the plane where the display panel is located, the third opening 145 at least partially overlaps with the second pole 122 of the transistor 120. That is, along the direction Z perpendicular to the plane where the display panel is located, a hollowed-out portion is provided at the position on the common electrode 140 that overlaps with the second pole 122 of the transistor 120, thereby reducing the interference of the signal on the second pole 122 of the transistor 120 to the common electrode 140.

[0137] Figure 25 A schematic cross-sectional view along the Figure 21 J1-J2 direction in

[0138] In an implementation manner, as Figure 24 shown, the common electrode layer 14 is disposed on the side of the pixel electrode layer 13 close to the first substrate 11. The effect of forming the third opening 145 in the common electrode 140 further includes: avoiding electrical conduction between the common electrode 140 and the pixel electrode 130 when the second pole 122 of the transistor 120 is electrically connected to the pixel electrode 130 through a via.

[0139] In an implementation manner, as Figure 25 shown, the pixel electrode layer 13 is disposed on the side of the common electrode layer 14 close to the first substrate 11. At this time, the third opening 145 can still be formed in the common electrode 140.

[0140] In a technical solution of the present application, as Figure 21 shown, a second opening 144 and a third opening 145 are formed in the common electrode 140, and along the direction Z perpendicular to the plane where the display panel is located, the second opening 144 at least partially overlaps with the first pole 121 of the transistor 120 and the third opening 145 at least partially overlaps with the second pole 122 of the transistor 120.

[0141] Figure 26 A partial schematic view of the first substrate in another display panel provided by an embodiment of the present application, Figure 27 A partial schematic view of the first substrate in another display panel provided by an embodiment of the present application, Figure 28 A partial schematic view of the first substrate in another display panel provided by an embodiment of the present application.

[0142] In a technical solution of the present application, as Figure 26 and Figure 28As shown, when a second opening 144 is formed in the common electrode 140, the opening areas of at least two second openings 144 are different. For example, as Figure 26 and Figure 28 shown, at least two second openings 144 include a second opening 144a and a second opening 144b, where the opening area of the second opening 144a is larger than that of the second opening 144b.

[0143] In this implementation, the area of the second opening 144 can be flexibly set according to the different positions where the second opening 144 is located. For example, when a second opening 144 needs to be formed at a certain position of the common electrode 140 and there is no other functional structure (such as a conductive structure) below this position, the area of these second openings 144 can be set to be larger; when a second opening 144 needs to be formed at a certain position of the common electrode 140 and there is a certain area of other functional structures (such as a conductive structure) below this position, the area of these second openings 144 can be set to be smaller to avoid damaging the above-mentioned other functional structures. In addition, when second openings 144 are respectively formed at different positions of the common electrode 140, the surrounding environments of these different positions may be different. For example, different heights of different positions may cause different etching degrees of the etching solution on the second opening 144, thereby resulting in different areas of the second openings 144 at different positions.

[0144] In a technical solution of the present application, as Figure 27 and Figure 28 shown, when a third opening 145 is formed in the common electrode 140, the opening areas of at least two third openings 145 are different. For example, as Figure 27 and Figure 28 shown, at least two third openings 145 include a third opening 145a and a third opening 145b, where the opening area of the third opening 145a is larger than that of the third opening 145b.

[0145] In this implementation, the area of the third opening 145 can be flexibly set according to the different positions where the third opening 145 is located. For example, when a third opening 145 needs to be formed at a certain position of the common electrode 140 and there is no other functional structure (such as a conductive structure) below this position, the area of these third openings 145 can be set to be larger; when a third opening 145 needs to be formed at a certain position of the common electrode 140 and there is a certain area of other functional structures (such as a conductive structure) below this position, the area of these third openings 145 can be set to be smaller to avoid damaging the above-mentioned other functional structures. In addition, when third openings 145 are respectively formed at different positions of the common electrode 140, the surrounding environments of these different positions may be different. For example, different heights of different positions may cause different etching degrees of the etching solution on the third opening 145, thereby resulting in different areas of the third openings 145 at different positions.

[0146] In one embodiment of the present application, as Figure 16 and Figure 17 , Figure 18 and Figure 19 shown, the first substrate 01 includes data lines DL and touch traces TL, and the data lines DL and the touch traces TL are arranged on the same layer. Among them, the data lines DL are electrically connected to the pixel electrodes 130, and the touch traces TL are electrically connected to the common electrodes 140.

[0147] The data lines DL and the touch traces TL are arranged in the same film layer. Then, the insulating layers between the data lines DL and the touch traces TL and the pixel electrodes 130 are all inorganic insulating layers, and the insulating layers between the data lines DL and the touch traces TL and the common electrodes 140 are also all inorganic insulating layers. Then, the vias for electrical connection between the touch traces TL and the common electrodes 140 can have the same preparation process as the vias for electrical connection between the data lines DL and the pixel electrodes 130, reducing the preparation difficulty. Further, the vias for electrical connection between the pixel electrodes 130 and the data lines DL and the vias for electrical connection between the common electrodes 140 and the touch traces TL can be prepared in the same etching process step. And by arranging the touch traces TL and the data lines DL in the same film layer, the touch traces TL can be prepared simultaneously with the data lines DL using the same manufacturing process and mask plate, reducing the process and saving costs.

[0148] In summary, the common electrodes 140 can be reused as touch electrodes, the touch traces TL can be prepared simultaneously with the data lines DL, and the vias for electrical connection between the touch traces TL and the common electrodes 140 and the vias for electrical connection between the data lines DL and the pixel electrodes 130 can be prepared simultaneously. Therefore, when the structure with touch function is integrated in the display panel provided by the present application, the process and mask plate are not increased at all.

[0149] Figure 29 is a partial schematic diagram of a display panel provided by an embodiment of the present application, Figure 30 is Figure 29 a schematic diagram of some structures in the X1 area in Figure 31 is Figure 30 a cross-sectional schematic diagram along the A1 - A2 direction in

[0150] In one embodiment of the present application, in combination with Figure 29 , Figure 30 and Figure 31 , the display panel further includes a second substrate 02 and support pillars 03. Among them, the second substrate 02 includes a second substrate 21. In addition, the second substrate 02 may further include structures such as a black matrix and color resist.

[0151] The support pillar 03 is disposed between the first substrate 11 and the second substrate 21 for forming a certain space between the first substrate 01 and the second substrate 02. Among them, the support pillar 03 can be disposed on the first substrate 01, that is, formed during the preparation process of the first substrate 01; the support pillar 03 can also be disposed on the second substrate 02, that is, formed during the preparation process of the second substrate 02.

[0152] In addition, the display panel may further include a display medium layer 04, and the display medium layer 04 may be located between the first substrate 01 and the second substrate 02. The display medium layer 04 may include liquid crystal, and thus the display panel provided by the embodiment of the present application may be a liquid crystal display panel.

[0153] Combined with Figure 29 、 Figure 30 and Figure 31 the first substrate 01 further includes a scanning line SL and a data line DL, and the extending direction of the scanning line SL intersects with the extending direction of the data line DL. For example, as Figure 29 shown, the scanning line SL extends in the row direction and the data line DL extends in the column direction, and then the extending directions of the scanning line SL and the data line DL are substantially perpendicular.

[0154] In the embodiment of the present application, along the direction Z perpendicular to the plane where the display panel is located, the support pillar 03 does not overlap with at least one of the scanning line SL and the data line DL. That is, the support pillar 03 does not overlap with the scanning line SL and the data line DL at the same time. It can be understood that the support pillar 03 is not disposed at the intersection position of the scanning line SL and the data line DL.

[0155] The scanning line SL is usually electrically connected to the gate of the transistor 120 and the data line DL is electrically connected to the first pole 12 of the transistor 120. Then, the scanning line SL and the data line DL are usually disposed on the same layer as a certain sub-film layer in the transistor array layer 12, that is, the scanning line SL and the data line DL are located on the side of the first inorganic insulating layer 15 facing the first substrate 11. Since the planarization effect of the inorganic insulating layer is effective, although the first inorganic insulating layer 15 and the second inorganic insulating layer 16 are disposed on the side of the scanning line SL and the data line DL away from the first substrate 11, the protrusion at the intersection position of the scanning line SL and the data line DL is still relatively obvious. If the support pillar 03 is disposed at the intersection position of the scanning line SL and the data line DL, the stability of the support pillar 03 is poor.

[0156] By disposing the support pillar 03 at a position avoiding the intersection of the scanning line SL and the data line DL, the embodiment of the present application can ensure the stability of the support pillar 03 as much as possible.

[0157] In a technical solution of the present application, combined with Figure 29 、 Figure 30 and Figure 31, along the direction Z perpendicular to the plane where the display panel is located, the support pillar 03 overlaps with at least part of the data line DL and does not overlap with the scan line SL. By setting the support pillar 03 to overlap with the data line DL in the direction Z perpendicular to the plane where the display panel is located, it is avoided that the support pillar occupies too much extra area and affects the opening area of the sub-pixels in the display panel.

[0158] As Figure 30 shown, in a technical solution of the present application, the minimum distance d1 between the orthographic projection of the support pillar 03 on the first substrate 11 and the orthographic projection of the scan line SL on the first substrate 11 is greater than 0 μm, that is, the orthographic projection of the support pillar 03 on the first substrate 11 does not overlap with the orthographic projection of the scan line SL on the first substrate 11. For example, d1 can be 0.5 μm, 1 μm, 1.5 μm, etc.

[0159] For example, when d1 is greater than or equal to 2 μm, it can make the support pillar 03 safely avoid the influence of the protrusion at the intersection position of the scan line SL and the data line DL on the position of the support pillar 03.

[0160] In a technical solution of the present application, as Figure 30 shown, the data line DL includes a first part DL1 and a second part DL2, wherein the width of the first part DL1 along the first direction X is greater than the width of the second part DL2 along the first direction X, and the first direction X is perpendicular to the extension direction of the data line DL. That is, a widening design is made for a part of the data line DL to form the first part DL1.

[0161] Along the direction Z perpendicular to the plane where the display panel is located, at least part of the support pillar 03 overlaps with the first part DL1, then at least part of the support pillar 03 is arranged above the first part DL1 with a widened design in the data line DL. Since the width of the first part DL1 is larger, the support pillar 03 overlapping with the first part DL1 can obtain a relatively flat and large bearing surface.

[0162] In addition, since the support pillar 03 does not overlap with the scan line SL, the first part DL1 also does not overlap with the scan line SL. Although the width of the first part DL1 is wider than that of the second part DL2, the coupling between the scan line SL and the data line DL can be minimized.

[0163] Figure 32 For Figure 29 another schematic diagram of part of the structure in the X1 area in

[0164] In one implementation, as Figure 32 shown, at least part of the outer contour of the first part DL is in a "cross" shape.

[0165] The outer contour of the first part of the data line DL is set to a "cross" shape. On the one hand, it can ensure that the bearing surface above it for contacting the support column 03 can effectively guarantee the stability of the support column 03; on the other hand, it can avoid the problem of resistance mutation of the data line DL at the first part DL1.

[0166] In one implementation, in combination with Figure 31 and Figure 30 , Figure 32 , when the first pole 121 of the transistor 120 is electrically connected to the data line DL and the second pole 122 of the transistor 120 is electrically connected to the pixel electrode 130, along the direction Z perpendicular to the plane of the display panel, the first part DL1 overlaps with the first pole 121 of the transistor 120, so the support column 03 overlapping with the first part DL1 also overlaps with the first pole 121 of the transistor 120.

[0167] The data line DL and the first pole 121 of the transistor 120 are arranged on the same layer, and the semiconductor layer in the first pole 121 of the transistor 120 is electrically connected. It can be understood that the part of the data line DL electrically connected to the semiconductor layer of the transistor 120 through a via forms the first pole 121 of the transistor 120. Then the support column 02 overlaps with the first pole 121 of the transistor 120 along the direction Z perpendicular to the plane of the display panel, thus optimizing the standing space of the support column 02 and reducing the influence of the support column 02 on the pixel light-emitting area.

[0168] Figure 33 FIG. is a partial schematic diagram of another display panel provided by an embodiment of the present application. Figure 34 is Figure 33 a schematic diagram of some structures in the X2 region in

[0169] In a technical solution of the present application, in combination with Figure 33 and Figure 34 , when the first substrate 01 further includes a touch control trace TL, the extending direction of the touch control trace TL is the same as the extending direction of the data line DL. For example, as Figure 33 shown, both the touch control trace TL and the data line DL extend along the column direction. Along the direction Z perpendicular to the plane of the display panel, the support column 03 overlaps with at least part of the touch control trace TL.

[0170] Among them, the touch control trace TL includes a third part TL1 and a fourth part TL2. The width of the third part TL1 along the first direction X is greater than the width of the fourth part TL2 along the first direction X, and the first direction X is perpendicular to the extending direction of the touch control trace TL. That is, a part of the touch control trace TL is widened to form the third part TL1.

[0171] In the direction Z perpendicular to the plane where the display panel is located, at least part of the support column 02 overlaps with the third part TL3, and at least part of the support column 03 is disposed above the third part TL1 with a widened design in the touch trace TL. Since the width of the third part TL1 is relatively large, the support column 03 overlapping with the third part TL1 can obtain a relatively flat and large bearing surface.

[0172] In a technical solution of the present application, in combination with Figure 33 and Figure 34 , the touch trace TL is disposed adjacent to part of the data line DL, that is, the adjacent touch trace TL and the data line DL are located within the gap of the pixel electrode 130. The gap of the pixel electrode 130 refers to the gap between adjacent pixel electrodes 130. At this time, the adjacent touch trace TL and the data line DL may respectively include a third part TL1 and a first part DL1, and the same support column 03 can overlap with the third part TL1 and the first part DL1 in the direction Z perpendicular to the plane where the display panel is located.

[0173] Due to reasons such as the brittle texture of the inorganic insulating layer, the thickness of the inorganic insulating layer should not be too thick. When the insulating layer between the touch trace TL and the data line DL and the common electrode 140 and the pixel electrode 130 is an inorganic insulating layer, the thickness of the insulating layer on the side of the touch trace TL and the data line DL facing the second substrate 02 is relatively thin, and the relatively thin insulating layer does not have an excellent flattening effect. At this time, the flatness of the surface facing the second substrate 02 in the area where the touch trace TL and the data line DL are disposed in the first substrate 01 is relatively poor. If the surface facing the second substrate 02 in this area is directly used to carry the support column 03, the standing position of the support column 03 is unstable.

[0174] In this technical solution, the setting method of the first part DL1 is equivalent to widening the part of the data line DL overlapping with the support column 03, and the setting method of the third part DL3 is equivalent to widening the part of the touch trace TL overlapping with the support column 03. Then, the area with better flatness in the surface facing the second substrate 02 in the area where the first part DL1 and the third part DL3 are disposed in the first substrate 01 is increased. Therefore, the support column 03 can obtain a stable standing position.

[0175] At the same time, the width of the third part TL1 of the data line touch trace TL does not need to be increased too much relative to the width of the fourth part TL2, avoiding the resistance mutation on the touch trace TL.

[0176] Figure 35 It is a partial schematic diagram of another display panel provided by an embodiment of the present application. Figure 36 It is a partial schematic diagram of another display panel provided by an embodiment of the present application.

[0177] In one embodiment of the present application, as Figure 35 and Figure 36 shown, the first substrate 01 further includes a black matrix 05, and / or, the second substrate 02 further includes a black matrix 05. That is to say, the display panel further includes a black matrix 05. The black matrix 05 can be disposed on the first substrate 01, or the black matrix 05 can be disposed on the second substrate 02, or the black matrix 05 includes a part disposed on the first substrate 01 and the black matrix 05 further includes a part on the second substrate 02.

[0178] Along the direction Z perpendicular to the plane where the display panel is located, the black matrix 05 covers the scan line SL, the data line DL and the touch trace TL. The black matrix 05 can prevent these signal lines from being visible and affecting the display effect of the display panel. In addition, the black matrix 05 can prevent light crosstalk between adjacent sub-pixels.

[0179] Please continue to refer to Figure 35 and Figure 36 , the black matrix 05 includes a first main body 51. The extending direction of the first main body 51 is parallel to the extending direction of the scan line SL. As Figure 35 and Figure 36 shown, the extending directions of the first main body 51 and the scan line SL are both parallel to the first direction X.

[0180] The first main body 51 includes opposite first side 511 and second side 512. The extending directions of the first side 511 and the second side 512 are both parallel to the scan line SL, and the arranging direction of the first side 511 and the second side 512 is perpendicular to the extending direction of the scan line SL. As Figure 35 and Figure 36 shown, the first side 511 and the second side 512 of the first main body 51 are respectively the upper and lower sides thereof.

[0181] In addition, the black matrix 05 further includes a plurality of first protrusions 52. The first protrusions 52 are disposed on the side of the first side 511 away from the second edge 512 and the first protrusions 52 are connected to the first side 511. Along the direction Z perpendicular to the plane where the display panel is located, the first protrusions 52 at least partially overlap with the support pillars 03. It can be understood that the first side 511 in the first main body 51 is closer to the support pillars 03 than the second side 512, and the first protrusions 52 overlapping with the support pillars 03 are disposed on the side of the first side 511 away from the second side 512.

[0182] Then the support pillars 03 can be covered by the black matrix 05, preventing the support pillars 03 from being visible to the human eye and affecting the display effect of the display panel.

[0183] In addition, the black matrix 05 may further include a plurality of second protrusions 53. The second protrusions 53 are disposed on a side of the second side 512 away from the first side 511 and the second protrusions 53 are connected to the second side 512. And along the direction Z perpendicular to the plane where the display panel is located, the second protrusions 53 do not overlap with the support pillars 03. Then it can be understood that the second side 512 in the first main body portion 51 is farther away from the support pillars 03 than the first side 511.

[0184] In an embodiment of the present application, as Figure 35 and Figure 36 shown, along the direction perpendicular to the extending direction of the scanning line SL, the width of the first protrusion 52 is greater than the width of the second protrusion 53. That is, the width of the first protrusion 52 overlapping with the support pillar 03 bulging towards the area where the support pillar 03 is located is wider, while the width of the second protrusion 52 not overlapping with the support pillar 03 bulging away from the area where the support pillar 03 is located is narrower. The wider width of the first protrusion 52 bulging can effectively block the support pillar 03, and the narrower width of the second protrusion 53 bulging can effectively ensure the opening area of the sub-pixels in the display panel.

[0185] It should be noted that the black matrix 05 further includes a parallel portion 54 whose extending direction is parallel to the extending directions of the data line DL and the touch trace TL. Among them, the difference between the first protrusion 52 and the second protrusion 52 and the parallel portion 54 is that the width of the first protrusion 52 along the first direction X and the width of the second protrusion 52 along the first direction X are both greater than the width of the parallel portion 54 along the first direction X.

[0186] In one implementation, as Figure 35 shown, along the direction perpendicular to the extending direction of the scanning line SL, the width of the second protrusion 53 is equal to 0, that is, no protrusion is provided on the side of the second side 512 away from the first side 511

[0187] In one implementation, as Figure 36 shown, along the direction perpendicular to the extending direction of the scanning line SL, the width of the second protrusion 53 is greater than 0, that is, a protrusion is provided on the side of the second edge 512 away from the first side 511.

[0188] Figure 37 It is a schematic diagram of a display device provided by an embodiment of the present application.

[0189] In an embodiment of the present application, as Figure 37 shown, the present application provides a display device, including the display panel 001 provided in any one of the above embodiments. Exemplarily, the display device may be an electronic device such as a mobile phone, a computer, a smart wearable device (for example, a smart watch), and a vehicle-mounted display device, etc., and the embodiments of the present invention do not limit this.

[0190] The display device adopting the inventive concept of the present application can have a relatively thin body thickness, and has simple process steps and low manufacturing costs.

[0191] The above are only the preferred embodiments of the present application and are not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present application shall be included within the scope of protection of the present application.

Claims

1. A display panel, characterized in that, it includes a first substrate, and the first substrate includes: a first substrate; a transistor array layer disposed on one side of the first substrate; the transistor array layer includes transistors; a pixel electrode layer and a common electrode layer, both disposed on the side of the transistor array layer away from the first substrate; the pixel electrode layer includes pixel electrodes, and the common electrode layer includes common electrodes; a first inorganic insulating layer, the insulating layer between the transistor array layer and the one of the pixel electrode layer and the common electrode layer closer to the transistor array layer is the first inorganic insulating layer; a second inorganic insulating layer disposed between the pixel electrode layer and the common electrode layer; the display panel further includes: a second substrate, the second substrate includes a second substrate; support pillars disposed between the first substrate and the second substrate; wherein, the first substrate further includes scan lines and data lines, the extending direction of the scan lines intersects with the extending direction of the data lines; along the direction perpendicular to the plane where the display panel is located, the support pillars do not overlap with at least one of the scan lines and the data lines.

2. The display panel according to claim 1, characterized in that, the film thickness of the first inorganic insulating layer is less than or equal to 6000 angstroms; and / or, the film thickness of the second inorganic insulating layer is less than or equal to 6000 angstroms.

3. The display panel according to claim 1, characterized in that, the first inorganic insulating layer includes at least one of silicon oxide and silicon nitride; and / or, the second inorganic insulating layer includes at least one of silicon oxide and silicon nitride.

4. The display panel according to claim 1, characterized in that, the transistor includes a polysilicon semiconductor layer.

5. The display panel according to claim 1, characterized in that, the first substrate further includes touch traces, the touch traces are disposed on the side of the first inorganic insulating layer close to the first substrate, and the touch traces provide signals for the common electrodes; a first slit is formed on the common electrode, along the direction perpendicular to the plane where the display panel is located, at least part of the first slit overlaps with at least part of the touch traces; and / or, a second slit is included between adjacent common electrodes, along the direction perpendicular to the plane where the display panel is located, at least part of the second slit overlaps with at least part of the touch traces.

6. The display panel according to claim 5, characterized in that, the first substrate further includes dummy touch traces, the dummy touch traces are disposed on the same layer as the touch traces and are electrically insulated from the common electrodes; a first slit is formed on the common electrode, along the direction perpendicular to the plane where the display panel is located, at least part of the first slit overlaps with at least part of the dummy touch traces; and / or, a second slit is included between adjacent common electrodes, along the direction perpendicular to the plane where the display panel is located, at least part of the second slit overlaps with at least part of the dummy touch traces.

7. The display panel according to claim 1, characterized in that, The first substrate further includes data lines, which are disposed on a side of the first inorganic insulating layer close to the first substrate, and the data lines provide signals for the pixel electrodes; A first slit is formed in the common electrode, and in a direction perpendicular to the plane of the display panel, the data lines do not overlap with the first slit; and / or, A second slit is included between adjacent common electrodes, and in a direction perpendicular to the plane of the display panel, the data lines do not overlap with the second slit.

8. The display panel according to claim 1, wherein, the first substrate further includes touch traces, which are disposed on a side of the common electrode layer close to the first substrate; a plurality of first vias are formed in the first inorganic insulating layer, and a plurality of second vias are formed in the second inorganic insulating layer; wherein, the common electrode layer is disposed on a side of the pixel electrode layer close to the transistor array layer, and the pixel electrode layer further includes a cross-bridge electrode; the cross-bridge electrode is electrically connected to the common electrode through the second via, and the cross-bridge electrode is electrically connected to the touch traces through the through second via and first via.

9. The display panel according to claim 8, wherein, a first opening is formed in the common electrode; in a direction perpendicular to the plane of the display panel, the first opening overlaps with the first via.

10. The display panel according to claim 9, wherein, the opening areas of at least two of the first openings are different.

11. The display panel according to claim 1, wherein, a first pole of the transistor is electrically connected to the data line, and a second pole of the transistor is electrically connected to the pixel electrode; a second opening is formed in the common electrode; in a direction perpendicular to the plane of the display panel, the second opening at least partially overlaps with the first pole of the transistor; and / or, a third opening is formed in the common electrode; in a direction perpendicular to the plane of the display panel, the third opening at least partially overlaps with the second pole of the transistor.

12. The display panel according to claim 11, wherein, when a second opening is formed in the common electrode, the opening areas of at least two of the second openings are different; and / or, when a third opening is formed in the common electrode, the opening areas of at least two of the third openings are different.

13. The display panel according to claim 1, wherein, in a direction perpendicular to the plane of the display panel, the support pillar overlaps with at least part of the data lines and does not overlap with the scan lines.

14. The display panel according to claim 13, wherein, the data line includes a first part and a second part, and in a direction perpendicular to the plane of the display panel, at least part of the support pillar overlaps with the first part; wherein, the width of the first part in a first direction is greater than the width of the second part in the first direction, and the first direction is perpendicular to the extending direction of the data line.

15. The display panel according to claim 14, wherein, At least part of the outer contour of the first part is in a "plus" shape.

16. The display panel according to claim 14, wherein, the first pole of the transistor is electrically connected to the data line, and the second pole of the transistor is electrically connected to the pixel electrode; wherein, along a direction perpendicular to the plane where the display panel is located, the first part overlaps with the first pole of the transistor.

17. The display panel according to claim 13, wherein, the first substrate further includes touch traces, and the extending direction of the touch traces is the same as the extending direction of the data lines; along a direction perpendicular to the plane where the display panel is located, the support pillars overlap with at least part of the touch traces; wherein, the touch traces include a third part and a fourth part, and along a direction perpendicular to the plane where the display panel is located, at least part of the support pillars overlap with the third part; the width of the third part along a first direction is greater than the width of the fourth part along the first direction, and the first direction is perpendicular to the extending direction of the touch traces.

18. The display panel according to claim 13, wherein, the minimum distance between the orthographic projection of the support pillar on the first substrate and the orthographic projection of the scan line on the substrate is greater than or equal to 2 μm.

19. The display panel according to claim 13, wherein, the first substrate further includes a black matrix, and / or, the second substrate further includes a black matrix; the black matrix includes: a first main body part, the extending direction of the first main body part is parallel to the extending direction of the scan line; along a direction perpendicular to the plane where the display panel is located, the first main body part covers the scan line; the first main body part includes opposite first and second sides, and the extending directions of both the first side and the second side are parallel to the scan line and the arrangement direction of the first side and the second side is perpendicular to the extending direction of the scan line; a plurality of first protrusions, arranged on a side of the first side away from the second side, and the first protrusions are connected to the first side; a plurality of second protrusions, arranged on a side of the second side away from the first side, and the second protrusions are connected to the second side; wherein, along a direction perpendicular to the plane where the display panel is located, the first protrusions overlap with at least part of the support pillars and the second protrusions do not overlap with the support pillars; along a direction perpendicular to the extending direction of the scan line, the width of the first protrusions is greater than the width of the second protrusions.

20. The display panel according to claim 1, wherein, the first substrate further includes data lines and touch traces, the data lines are electrically connected to the pixel electrodes, the touch traces are electrically connected to the common electrodes, and the touch traces and the data lines are arranged on the same layer.

21. A display device, wherein, it includes the display panel according to any one of claims 1-20.

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