A data processing method, a memory, an electronic device, and a storage medium

Abstract

The present application provides a data processing method, a memory, an electronic device, and a storage medium, belonging to the field of computer technology. The method includes: obtaining a data processing request, where the data processing request includes at least one target access address; identifying the address type of each target access address; if the address type is the first address type, dividing a first memory area according to the access heat of each target access address to the first memory area to obtain at least two sub-memory areas, and the access heat of the target access address to different sub-memory areas is different; if the address type is the second address type, determining a second memory area according to each target access address, where the first address type is different from the second address type; determining a corresponding data processing policy according to the memory area corresponding to each target access address, and processing the data processing request based on the data processing policy to obtain target access data. By adopting this method, the latency is reduced while controlling the cost.

Description

Technical Field

[0001] This application relates to the field of computer technologies, and in particular, to a data processing method, a memory, an electronic device, and a storage medium. Background Art

[0002] CXL-SSD refers to a solid-state storage device (Solid State Drive, SSD) that supports the Compute Express Link (CXL) standard. CXL-SSD has characteristics such as high storage density and non-volatile properties of flash media, and can be used as storage-class memory and persistent memory. However, due to the large read / write latency of flash pages in flash media, the access speed of CXL-SSD is restricted. Currently, by mainly using a large-capacity dynamic random access memory (Dynamic Random Access Memory, DRAM) as a cache for the backend flash media, the latency of CXL-SSD is reduced. However, the cost of large-capacity DRAM is high and it is difficult to be widely applied. Therefore, how to reduce the latency of CXL-SSD while controlling the cost has become an urgent technical problem to be solved. Summary of the Invention

[0003] This application provides a data processing method, a memory, an electronic device, and a storage medium.

[0004] In a first aspect of this application, there is provided a data processing method, which is applied to a main control chip of a memory. The method includes:

[0005] Obtain a data processing request, where the data processing request includes at least one target access address;

[0006] Identify the address type of each of the target access addresses;

[0007] If the address type is a first address type, divide a first memory area according to the access heat of each of the target access addresses to the first memory area, and obtain at least two sub-memory areas, where the access heat of the target access address to different sub-memory areas is different;

[0008] If the address type is a second address type, determine a second memory area according to each of the target access addresses, where the first address type is different from the second address type;

[0009] Determine a corresponding data processing strategy according to the memory area corresponding to each of the target access addresses, and process the data processing request based on the data processing strategy to obtain target access data.

[0010] In one implementable manner, determining a corresponding data processing policy according to the memory area corresponding to each of the target access addresses, and processing the data processing request based on the data processing policy to obtain target access data includes:

[0011] Determining a target physical address area corresponding to the target access address according to a preset address mapping relationship between the memory area and the physical address area;

[0012] Determining a target data encoding policy corresponding to the target physical address area according to a preset correspondence between different physical address areas and different data encoding policies;

[0013] Processing the data in the target physical address area based on the target data encoding policy and the data processing request to obtain target access data.

[0014] In one implementable manner, processing the data in the target physical address area based on the target data encoding policy and the data processing request to obtain target access data includes:

[0015] Reading the data in the target physical address area as target access data according to the target data encoding policy and the data processing request;

[0016] Storing the target access data into the memory area corresponding to the target access address.

[0017] In one implementable manner, the sub-memory areas of the first memory area include a hot list memory area, a warm list memory area, and a cold list memory area;

[0018] Processing the data in the target physical address area based on the target data encoding policy and the data processing request to obtain target access data includes:

[0019] If the target data encoding policy is the first data encoding policy, according to the data processing request, performing one read operation on the data pages in the physical address area corresponding to the hot list memory area in the target physical address area to obtain hot data, and performing a first preset number of read operations on the data pages in the physical address area corresponding to the warm list memory area in the target physical address area to obtain warm data, and performing a second preset number of read operations on the data pages in the physical address area corresponding to the cold list memory area in the target physical address area to obtain cold data, and taking the hot data, the warm data, and the cold data as target access data; the first preset number and the second preset number are different;

[0020] If the target data encoding policy is the second data encoding policy, according to the data processing request, use the second data encoding policy to perform a third preset number of read operations on the data in the target physical address area to obtain target access data.

[0021] In an implementable manner, it further includes:

[0022] Write the hot data, the warm data, and the cold data into the hot list memory area, the warm list memory area, and the cold list memory area respectively.

[0023] In an implementable manner, the if the address type is the first address type, dividing the first memory area according to the access heat of each target access address to the first memory area to obtain at least two sub-memory areas includes:

[0024] If the address type is the first address type, count the access heat of each target access address to each memory unit of the first memory area;

[0025] Determine the memory area corresponding to each memory unit with a corresponding access heat greater than the first heat threshold as the hot list memory area, determine the memory area corresponding to each memory unit with a corresponding access heat greater than the second heat threshold and less than or equal to the first heat threshold as the warm list memory area, and determine the memory area corresponding to each memory unit with a corresponding access heat greater than the third heat threshold and less than or equal to the second heat threshold as the cold list memory area, where the hot list memory area, the warm list memory area, and the cold list memory area are sub-memory areas of the first memory area, the first heat threshold is greater than the second heat threshold, and the second heat threshold is greater than the third heat threshold.

[0026] In an implementable manner, the identifying the address type of each target access address includes:

[0027] Determine the device interconnection protocol type included in the data processing request;

[0028] If the device interconnection protocol type is the target input / output communication protocol, determine that the address type of the target access address is the first address type;

[0029] If the device interconnection protocol type is the target memory access protocol, determine that the address type of the target access address is the second address type.

[0030] In a second aspect of the present application, a memory is provided, including a main control chip and a flash memory;

[0031] The master control chip is used to obtain a data processing request, where the data processing request includes at least one target access address; identify the address types of each of the target access addresses; if the address type is the first address type, divide the first memory area according to the access heat of each of the target access addresses to the first memory area, obtaining at least two sub-memory areas, and the access heat of the target access address to different sub-memory areas is different; if the address type is the second address type, determine a second memory area according to each of the target access addresses, where the first address type is different from the second address type; determine corresponding data processing policies according to the memory areas corresponding to each of the target access addresses, and process the data processing request based on the data processing policies to obtain target access data from the flash memory.

[0032] In an implementable manner, the master control chip includes an address identification unit and a flash memory control unit;

[0033] The address identification unit is used to determine the target physical address area corresponding to the target access address according to a preset address mapping relationship between the memory area and the physical address area; determine the target data encoding policy corresponding to the target physical address area according to a preset corresponding relationship between different physical address areas and different data encoding policies;

[0034] The flash memory control unit is used to process the data in the target physical address area based on the target data encoding policy and the data processing request to obtain target access data.

[0035] In an implementable manner, the flash memory control unit is used to read the data in the target physical address area as target access data according to the target data encoding policy and the data processing request; store the target access data into the memory area corresponding to the target access address.

[0036] In an implementable embodiment, the sub - memory regions of the first memory region include a hot list memory region, a warm list memory region, and a cold list memory region; the flash control unit is configured to, if the target data encoding policy is the first data encoding policy, according to the data processing request, perform a single read operation on the data pages in the physical address region corresponding to the hot list memory region in the target physical address region to obtain hot data, and perform a first preset number of read operations on the data pages in the physical address region corresponding to the warm list memory region in the target physical address region to obtain warm data, and perform a second preset number of read operations on the data pages in the physical address region corresponding to the cold list memory region in the target physical address region to obtain cold data, and use the hot data, the warm data, and the cold data as target access data; the first preset number and the second preset number are different; if the target data encoding policy is the second data encoding policy, according to the data processing request, perform a third preset number of read operations on the data in the target physical address region to obtain target access data.

[0037] In an implementable embodiment, the flash control unit is further configured to write the hot data, the warm data, and the cold data into the hot list memory region, the warm list memory region, and the cold list memory region, respectively.

[0038] In an implementable embodiment, the main control chip includes a heat perception unit;

[0039] The heat perception unit is configured to, if the address type is the first address type, count the access heat of each of the target access addresses to each memory unit in the first memory region; determine the memory regions corresponding to the memory units with the corresponding access heat greater than the first heat threshold as the hot list memory region, determine the memory regions corresponding to the memory units with the corresponding access heat greater than the second heat threshold and less than or equal to the first heat threshold as the warm list memory region, and determine the memory regions corresponding to the memory units with the corresponding access heat greater than the third heat threshold and less than or equal to the second heat threshold as the cold list memory region, where the hot list memory region, the warm list memory region, and the cold list memory region are sub - memory regions of the first memory region, the first heat threshold is greater than the second heat threshold, and the second heat threshold is greater than the third heat threshold.

[0040] In one implementable manner, the main control chip includes an address arbitration unit, and the address arbitration unit is configured to determine the type of device interconnection protocol included in the data processing request; if the device interconnection protocol type is the target input / output communication protocol, determine that the address type of the target access address is the first address type; if the device interconnection protocol type is the target memory access protocol, determine that the address type of the target access address is the second address type.

[0041] In a third aspect of the present application, there is provided an electronic device, including: a memory, a processor, and a computer program stored on the memory and executable on the processor, where the processor implements the method described in the present application when executing the program.

[0042] In a fourth aspect of the present application, there is provided a storage medium containing computer-executable instructions, and the computer-executable instructions are used to execute the method described in the present application when executed by a computer processor.

[0043] By using the data processing method provided in the embodiments of the present application, a data processing request is obtained. The data processing request includes at least one target access address. The address type of each target access address is identified. If the address type is the first address type, the first memory area is divided according to the access heat of each target access address to the first memory area, and at least two sub-memory areas are obtained. The access heat of the target access address to different sub-memory areas is different. If the address type is the second address type, a second memory area is determined according to each target access address. The first address type is different from the second address type. A corresponding data processing strategy is determined according to the memory area corresponding to each target access address, and the data processing request is processed based on the data processing strategy to obtain target access data. In the embodiments of the present application, for each target access address, the target access addresses can be classified and stored according to the address type of the target access address. For the target access addresses of the first address type, the target access addresses can be further classified and managed according to the corresponding access heat. The data processing method provided in the present application does not require a large-capacity DRAM. Instead, through refined classification management, for data processing requests with high latency requirements, a fast read / write processing strategy can be adopted to improve the access speed, achieving a reduction in CXL-SSD latency while controlling costs.

[0044] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present application, nor is it used to limit the scope of the present application. Other features of the present application will become easily understood through the following description. Description of the Drawings

[0045] By reading the following detailed description with reference to the accompanying drawings, the above and other objects, features, and advantages of the exemplary embodiments of the present application will become readily understood. In the drawings, several embodiments of the present application are shown in an exemplary rather than restrictive manner, wherein:

[0046] In the drawings, the same or corresponding reference numerals denote the same or corresponding parts.

[0047] Figure 1 FIG. shows a schematic diagram of an implementation process of a data processing method provided by an embodiment of the present application;

[0048] Figure 2 FIG. shows another schematic diagram of an implementation process of a data processing method provided by an embodiment of the present application;

[0049] Figure 3 FIG. shows a schematic structural diagram of a memory provided by an embodiment of the present application;

[0050] Figure 4 FIG. shows another schematic structural diagram of a memory provided by an embodiment of the present application;

[0051] Figure 5 FIG. shows a partial schematic structural diagram of a memory provided by an embodiment of the present application;

[0052] Figure 6 FIG. shows another partial schematic structural diagram of a memory provided by an embodiment of the present application;

[0053] Figure 7 FIG. shows yet another partial schematic structural diagram of a memory provided by an embodiment of the present application;

[0054] Figure 8 FIG. shows a coding schematic diagram of a memory provided by an embodiment of the present application;

[0055] Figure 9 FIG. shows a data writing schematic diagram of a memory provided by an embodiment of the present application;

[0056] Figure 10 FIG. shows a schematic diagram of the system architecture corresponding to a memory provided by an embodiment of the present application;

[0057] Figure 11 FIG. shows a configuration schematic diagram of the power-on stage of a memory provided by an embodiment of the present application;

[0058] Figure 12 FIG. shows a schematic diagram of hot / warm / cold data partition write operation of a memory provided by an embodiment of the present application;

[0059] Figure 13 FIG. shows a schematic diagram of hot / warm / cold data partition read operation of a memory provided by an embodiment of the present application;

[0060] Figure 14 Shows a schematic diagram of the composition structure of an electronic device according to an embodiment of the present application. Specific embodiments

[0061] To make the purpose, features, and advantages of the present application more obvious and understandable, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work belong to the scope of protection of the present application.

[0062] Due to the large read / write latency of flash pages in flash memory media, the access speed of CXL-SSDs is restricted. Currently, DRAM is mainly used to reduce the latency of CXL-SSDs. However, the cost of large-capacity DRAM is relatively high, making it difficult to be widely applied. Therefore, to reduce the latency of CXL-SSDs while controlling costs, the present application provides a data processing method, a memory, an electronic device, and a storage medium. The electronic device provided by the present application can be devices such as mobile phones, computers, and tablet computers.

[0063] The technical solutions in the embodiments of the present application will be described below in conjunction with the accompanying drawings in the embodiments of the present application.

[0064] Figure 1 Shows a schematic implementation flow diagram of the data processing method provided by an embodiment of the present application. This data processing method is applied to the main control chip of a memory. As Figure 1 shown, the data processing method includes:

[0065] S101, obtain a data processing request, where the data processing request includes at least one target access address.

[0066] In an embodiment of the present application, the main control chip of the memory can be used to receive a data processing request from a computer and manage flash memory, etc. The main control chip can also perform data processing tasks such as transferring computer data to flash memory or reading data from flash memory.

[0067] In an embodiment of the present application, the CPU of the electronic device can initiate a data processing request to the memory. The data processing request can include a flash data read request and / or a data write request, etc. The CPU of the electronic device can include structures such as a CPU, a RAM, a GPU, and a motherboard.

[0068] In an embodiment of the present application, the memory may include a protocol multiplexing unit, and the protocol multiplexing unit may configure a CXL.io (Compute Express Link I / O) protocol access path and a CXL.mem (Compute Express Link Memory) protocol access path. The CXL.io protocol may be used for I / O communication between the CPU and the memory of an electronic device, and the CXL.mem protocol may be used for the CPU of the electronic device to access the memory. The memory may perform data interaction with the CPU of the electronic device through the CXL.io protocol access path and the CXL.mem protocol access path.

[0069] The CXL.mem protocol stack and the CXL.io protocol stack may use Flit (the smallest unit in the data transfer protocol) for data transfer. After the data processing request transmitted from the CPU of the electronic device passes through the protocol multiplexing unit, it may be arbitrated by the protocol multiplexing unit to different protocol stacks, and thus routed to different control layers. For example, if the data processing request is a request for I / O communication between the CPU and the memory, the protocol multiplexing unit may arbitrate the data processing request to the CXL.io protocol stack. If the data processing request is a request for the CPU to access the memory, the protocol multiplexing unit may arbitrate the data processing request to the CXL.mem protocol stack.

[0070] S102, identify the address types of the respective target access addresses.

[0071] The data processing request may include one or more target access addresses. The address type of the target access address may be the type of the protocol stack corresponding to the arbitration by the protocol multiplexing unit for the data processing request. For example, the address type of the target access address may be the CXL.mem address type or the CXL.io address type.

[0072] S103, if the address type is the first address type, divide the first memory area according to the access heat of the respective target access addresses to the first memory area, and obtain at least two sub-memory areas, and the access heat of the target access addresses to different sub-memory areas is different.

[0073] In the embodiments of the present application, the first memory area may be a partial memory area or the entire memory area of the DRAM in the memory. The access frequency of each memory cell in the DRAM memory area by the target access address can be counted, and the access frequency can be used as the access heat of the target access address to each memory cell in the DRAM memory area. Alternatively, the access duration of each memory cell in the DRAM memory area by the target access address can also be used, and the access duration can be used as the access heat of the target access address to each memory cell in the DRAM memory area.

[0074] In the embodiments of the present application, if the address type is the first address type, the memory areas corresponding to the respective target access addresses in the DRAM memory area can be marked as the first memory area. The first memory area can be divided into one, two or more sub-memory areas with different corresponding access heats according to the access heat of each target access address to each memory cell in the DRAM memory area. For example, the first memory area can be divided into a hot list memory area, a warm list memory area and a cold list memory area according to the order of the corresponding access heats from high to low.

[0075] S104. If the address type is the second address type, determine the second memory area according to each target access address, where the first address type is different from the second address type.

[0076] In the embodiments of the present application, the second memory area may be a partial area or the entire area of the DRAM in the memory. For example, if the address type is the second address type, the memory areas corresponding to the respective target access addresses in the DRAM memory area can be marked as the second memory area. The first address type is different from the second address type. For example, the first address type can be the CXL.mem address type, and the second address type can be the CXL.io address type.

[0077] S105. Determine the corresponding data processing policy according to the memory area corresponding to each target access address, and process the data processing request based on the data processing policy to obtain the target access data.

[0078] In the embodiments of the present application, different data processing strategies can be formulated according to the differences in the memory areas corresponding to the target access addresses. For example, if the memory area corresponding to the target access address is the first memory area and the data processing request is a flash data reading request, the flash data can be read according to the reading strategy corresponding to the first memory area. For example, for the flash data corresponding to each sub-memory area in the first memory area, the flash data can be partitioned into hot-page, warm-page, and cold-page flash data according to the access heat of each sub-memory area in the first memory area corresponding to the target access address from large to small. A hot page, a warm page, or a cold page refers to a data page. A data page is the basic structure for managing data in storage systems such as databases or memories. Each data page can contain multiple data. For example, the size of a data page can be 4 kB (Kilobyte) or 8 kB, etc. Then, for the hot-page, warm-page, and cold-page flash data, the flash data reading of the hot page, warm page, and cold page can be completed by one read operation, three read operations, and seven read operations respectively. If the memory area corresponding to the target access address is the second memory area and the data processing request is a flash data reading request, the flash data of different data pages can be evenly read according to the reading strategy corresponding to the second memory area. Even reading means that the number of times to read each data page can be 2 times or 3 times, etc. For example, if the flash data includes data pages such as upper page, middle page, and lower page, for the upper page, middle page, and lower page, 3 read operations can be used to complete the flash data of the upper page, 3 read operations can be used to complete the flash data of the middle page, and 2 read operations can be used to complete the flash data of the lower page; or, 2 read operations can be used to complete the flash data of the upper page, 2 read operations can be used to complete the flash data of the middle page, and 3 read operations can be used to complete the flash data of the lower page.

[0079] Using the data processing method provided by the embodiments of the present application, a data processing request is obtained. The data processing request includes at least one target access address. The address type of each target access address is identified. If the address type is the first address type, the first memory area is divided according to the access heat of each target access address to the first memory area, and at least two sub-memory areas are obtained. The access heat of the target access address to different sub-memory areas is different. If the address type is the second address type, a second memory area is determined according to each target access address. The first address type is different from the second address type. A corresponding data processing policy is determined according to the memory area corresponding to each target access address, and the data processing request is processed based on the data processing policy to obtain target access data. In the embodiments of the present application, for each target access address, the target access addresses can be classified and stored according to the address type of the target access address. For the target access addresses of the first address type, the target access addresses can be further classified and managed according to the corresponding access heat. The data processing method provided by the present application does not require a large-capacity DRAM. Instead, through refined classification management, for data processing requests with high latency requirements, a fast read-write processing policy can be adopted to improve the access speed, and the CXL-SSD latency is reduced while controlling the cost.

[0080] In a possible implementation manner, if the address type is the first address type, dividing the first memory area according to the access heat of each target access address to the first memory area to obtain at least two sub-memory areas may include steps A1 - A2:

[0081] Step A1, if the address type is the first address type, count the access heat of each target access address to each memory unit in the first memory area.

[0082] In the embodiments of the present application, the frequency of target access addresses falling within the memory address range of each unit size within a preset time period can be counted as the access heat corresponding to the memory address range of the unit size. Among them, the memory address range of the unit size can be configured according to user requirements. For example, the Nth memory address range of the unit size can be configured as [base address + 4×N×kB: base address + 2×N×kB - 1], and 1kB is equal to 1024 bytes. The preset time period can be set to 10 minutes or 20 minutes, etc.

[0083] Alternatively, the access duration of the target access address within the memory address range of each unit size within a preset time period can be counted as the access heat corresponding to the memory address range of the unit size.

[0084] Step A2: Determine the memory regions corresponding to each memory cell with an access heat greater than the first heat threshold as the hot list memory regions, determine the memory regions corresponding to each memory cell with an access heat greater than the second heat threshold and less than or equal to the first heat threshold as the warm list memory regions, and determine the memory regions corresponding to each memory cell with an access heat greater than the third heat threshold and less than or equal to the second heat threshold as the cold list memory regions. Among them, the hot list memory regions, the warm list memory regions, and the cold list memory regions are sub-memory regions of the first memory region, the first heat threshold is greater than the second heat threshold, and the second heat threshold is greater than the third heat threshold.

[0085] In the embodiments of the present application, the first heat threshold, the second heat threshold, and the third heat threshold can be freely set according to user requirements under the condition that the first heat threshold is greater than the second heat threshold and the second heat threshold is greater than the third heat threshold. For example, the first heat threshold can be set to an access frequency of 30, the second heat threshold can be set to an access frequency of 20, and the third heat threshold can be set to an access frequency of 10.

[0086] In the embodiments of the present application, for all memory regions corresponding to each memory cell with an access heat greater than the first heat threshold, the minimum memory address and the maximum memory address of all memory regions can be determined, and the memory address range determined by the minimum memory address and the maximum memory address is determined as the hot list memory region. Similarly, for all memory regions corresponding to each memory cell with an access heat greater than the second heat threshold and less than or equal to the first heat threshold, the warm list memory region can be determined, and for all memory regions corresponding to each memory cell with an access heat greater than the third heat threshold and less than or equal to the second heat threshold, the cold list memory region can be determined.

[0087] In the embodiments of the present application, in the DRAM memory of the memory, the hot list memory region, the warm list memory region, and the cold list memory region can be divided. In a possible implementation manner, if the address type is the second address type, the memory region corresponding to the target access address in the DRAM memory of the memory can be divided into an undivided memory area. The undivided memory area can be used to store the target access data obtained from the flash memory based on each target access address when the address type is the second address type.

[0088] In the embodiments of the present application, a mapping table representing a preset address mapping relationship can also be pre-stored in the DRAM memory of the memory. The mapping table can store the address mapping relationship between each LBA (Logical - Block - address) in the DRAM memory and the PBA (Physical Block Address) in the flash memory.

[0089] In the embodiments of the present application, by counting the access popularity of each memory unit in the first memory area by each target access address, the first memory area can be divided into multiple sub-memory areas. Different sub-memory areas can store different data obtained from the flash memory, realizing the partitioned reading and storage of flash memory data. Users can configure the reading speed and latency of the flash memory data in different partitions according to their needs, meeting the personalized needs of flash memory data reading and storage.

[0090] In a possible implementation manner, identifying the address types of each target access address may include steps B1 - B3:

[0091] Step B1, determining the type of device interconnection protocol included in the data processing request.

[0092] In the embodiments of the present application, after the data processing request passes through the protocol multiplexing unit of the memory, it can be arbitrated by the protocol multiplexing unit to different protocol stacks, such as being arbitrated to the CXL.io protocol stack or the CXL.mem protocol stack. The protocol stack obtained after arbitration by the protocol multiplexing unit can be used as the type of device interconnection protocol included in the data processing request and associated with the data processing request.

[0093] Step B2, if the type of device interconnection protocol is the target input / output communication protocol, determining that the address type of the target access address is the first address type.

[0094] In the embodiments of the present application, the target input / output communication protocol can be the CXL.io protocol stack or other IO communication protocols between the CPU and the memory.

[0095] Step B3, if the type of device interconnection protocol is the target memory access protocol, determining that the address type of the target access address is the second address type.

[0096] In the embodiments of the present application, the target memory access protocol can be the CXL.mem protocol stack or other memory access protocols between the CPU and the memory.

[0097] In the embodiments of the present application, by identifying the type of device interconnection protocol included in the data processing request, the data processing request can be classified and processed. Through classification and processing, it is possible to select to read the flash memory data in partitions or not in partitions, reducing the overall data processing latency while meeting the personalized processing needs of users.

[0098] In a possible implementation manner, Figure 2 shows another schematic flowchart of the data processing method provided by the embodiments of the present application. As Figure 2As shown, determining a corresponding data processing policy according to the memory area corresponding to each target access address and processing a data processing request based on the data processing policy to obtain target access data may include:

[0099] S201. Determine a target physical address area corresponding to the target access address according to a preset address mapping relationship between the memory area and the physical address area.

[0100] The memory provided in the embodiment of the present application may include a DRAM memory. A mapping table representing the preset address mapping relationship may be pre-stored in the DRAM memory, and the mapping table may store the address mapping relationship between each LBA in the DRAM memory and the PBA in the flash memory.

[0101] In the embodiment of the present application, the PBA address corresponding to the target access address in the flash memory can be obtained according to the LBA address corresponding to the target access address in the DRAM memory and the mapping table, and used as the target physical address area corresponding to the target access address.

[0102] S202. Determine a target data encoding policy corresponding to the target physical address area according to a preset correspondence between different physical address areas and different data encoding policies.

[0103] If the address type of the target access address is the first address type, the memory area corresponding to each target access address in the DRAM memory can be marked as the first memory area. If the address type of the target access address is the second address type, the memory area corresponding to each target access address in the DRAM memory can be marked as the second memory area. The data encoding policy corresponding to the physical address area corresponding to the first memory area in the flash memory can be the first data encoding policy, and the data encoding policy corresponding to the physical address area corresponding to the second memory area in the flash memory can be the second data encoding policy, and the second data encoding policy is different from the first data encoding policy.

[0104] For example, if the target physical address area is the physical address corresponding to the second memory area, the second memory area can be determined as the target data encoding policy.

[0105] S203. Process the data in the target physical address area based on the target data encoding policy and the data processing request to obtain the target access data.

[0106] In a possible implementation manner, the sub-memory areas of the first memory area include a hot list memory area, a warm list memory area, and a cold list memory area; processing the data in the target physical address area based on the target data encoding policy and the data processing request to obtain the target access data may include steps C1-C2:

[0107] Step C1, if the target data encoding policy is the first data encoding policy, according to the data processing request, perform a single read operation on the data pages in the physical address area corresponding to the hot list memory area in the target physical address area to obtain hot data, and perform a first preset number of read operations on the data pages in the physical address area corresponding to the warm list memory area in the target physical address area to obtain warm data, and perform a second preset number of read operations on the data pages in the physical address area corresponding to the cold list memory area in the target physical address area to obtain cold data. Use the hot data, warm data, and cold data as target access data; the first preset number and the second preset number are different.

[0108] In the embodiments of the present application, the first preset number can be set to 3 or 4, and the second preset number can be set to 6 or 7. For example, if the first preset number is set to 3 and the second preset number is set to 7, then a single read operation can be performed on the data pages in the physical address area corresponding to the hot list memory area in the target physical address area to complete the reading of the data page and obtain hot data; perform 3 read operations on the data pages in the physical address area corresponding to the warm list memory area in the target physical address area to complete the reading of the data page and obtain warm data; perform 7 read operations on the data pages in the physical address area corresponding to the cold list memory area in the target physical address area to complete the reading of the data page and obtain cold data.

[0109] When the target data encoding policy is the first data encoding policy, by partitioning the flash memory data and using the first data encoding policy to perform a single read operation on the data pages in the physical address area corresponding to the hot list memory area with high access heat to obtain hot data, the latency of high-access data can be reduced, while for warm data and cold data with lower access heat, 3 read operations or 7 read operations can be performed to obtain them. By partitioning the data, the flash memory data can be read reasonably and the read latency can be reduced.

[0110] Step C2, if the target data encoding policy is the second data encoding policy, according to the data processing request, perform a third preset number of read operations on the data in the target physical address area to obtain the target access data.

[0111] In the embodiments of the present application, the third preset number can be set to 3 or 4, etc. When the target data encoding policy is the second data encoding policy, that is, when the overall access heat of the flash memory data is not high, it is not necessary to partition the flash memory data. Using the second data encoding policy, the data in the target physical address area can be read evenly. For example, the flash memory data can be obtained through 3 or 4 read operations.

[0112] In a possible implementation, the data in the target physical address area is processed based on the target data encoding strategy and the data processing request to obtain the target access data, which may include steps D1 - D2:

[0113] Step D1, according to the target data encoding strategy and the data processing request, read the data in the target physical address area as the target access data.

[0114] Step D2, store the target access data into the memory area corresponding to the target access address.

[0115] In a possible implementation, hot data, warm data, and cold data can be written into the hot list memory area, warm list memory area, and cold list memory area respectively.

[0116] In the embodiments of the present application, after the flash memory data is read, the read flash memory data can be stored in the DRAM memory. For example, if the first data encoding strategy is adopted, the read hot data can be written into the hot list memory area in the DRAM memory, the read warm data can be written into the warm list memory area in the DRAM memory, and the read cold data can be written into the cold list memory area in the DRAM memory. If the second data encoding strategy is adopted, the read flash memory data can be written into the unseparated memory area in the DRAM memory.

[0117] By using the data processing method provided in the embodiments of the present application, the target access address in the data processing request is classified according to the address type. For different types of target access addresses, it is possible to choose whether to partition the memory according to the data processing requirements. Differentiated encoding processing and reading are performed on the partitioned and unpartitioned flash memory data. Hot data with high access heat can be quickly read, and for data with balanced access heat, an equalized reading method can be adopted. This not only meets the personalized processing requirements of users in different data processing situations, but also effectively utilizes the remaining capacity in the flash memory medium, realizing effective classification management of data.

[0118] Another embodiment of the present application further provides a memory, the structural schematic diagram of which is as Figure 3 shown. The memory 300 includes a main control chip 301 and a flash memory 302:

[0119] The main control chip 301 is configured to obtain a data processing request, where the data processing request includes at least one target access address; identify the address type of each target access address; if the address type is the first address type, divide the first memory area according to the access heat of each target access address to the first memory area, so as to obtain at least two sub-memory areas, and the access heat of the target access address to different sub-memory areas is different; if the address type is the second address type, determine the second memory area according to each target access address, and the first address type is different from the second address type; determine the corresponding data processing policy according to the memory area corresponding to each target access address, and process the data processing request based on the data processing policy, and obtain the target access data from the flash memory 302.

[0120] By using the memory provided in the embodiment of the present application, the main control chip can obtain a data processing request, where the data processing request includes at least one target access address, identify the address type of each target access address, if the address type is the first address type, divide the first memory area according to the access heat of each target access address to the first memory area, so as to obtain at least two sub-memory areas, and the access heat of the target access address to different sub-memory areas is different, if the address type is the second address type, determine the second memory area according to each target access address, the first address type is different from the second address type, determine the corresponding data processing policy according to the memory area corresponding to each target access address, and process the data processing request based on the data processing policy, and obtain the target access data from the flash memory. In the embodiment of the present application, for each target access address, the memory can classify and store the target access address according to the address type of the target access address, and for the target access address of the first address type, the target access address can be further classified and managed according to the corresponding access heat. The memory provided in the present application does not require a large-capacity DRAM, but through refined classification management, for data processing requests with high latency requirements, a fast read / write processing policy can be adopted to improve the access speed, and the CXL-SSD latency is reduced while controlling the cost.

[0121] In the embodiment of the present application, the memory 300 may adopt a CXL-SSD.

[0122] In a possible implementation manner, the main control chip 301 includes an address recognition unit and a flash memory control unit;

[0123] The address recognition unit is configured to determine the target physical address area corresponding to the target access address according to the preset address mapping relationship between the memory area and the physical address area; determine the target data encoding policy corresponding to the target physical address area according to the preset corresponding relationship between different physical address areas and different data encoding policies;

[0124] A flash memory control unit is configured to process data in a target physical address region based on a target data encoding policy and a data processing request to obtain target access data.

[0125] In a possible implementation, the flash memory control unit is configured to read data in the target physical address region as target access data according to the target data encoding policy and the data processing request; and store the target access data into a memory region corresponding to the target access address.

[0126] In a possible implementation, the sub-memory regions of the first memory region include a hot list memory region, a warm list memory region, and a cold list memory region; the flash memory control unit is configured to, if the target data encoding policy is the first data encoding policy, according to the data processing request, perform a single read operation on data pages in the physical address region corresponding to the hot list memory region in the target physical address region to obtain hot data, and perform a first preset number of read operations on data pages in the physical address region corresponding to the warm list memory region in the target physical address region to obtain warm data, and perform a second preset number of read operations on data pages in the physical address region corresponding to the cold list memory region in the target physical address region to obtain cold data, and use the hot data, warm data, and cold data as target access data; the first preset number and the second preset number are different; if the target data encoding policy is the second data encoding policy, according to the data processing request, perform a third preset number of read operations on the data in the target physical address region to obtain target access data.

[0127] In a possible implementation, the flash memory control unit is further configured to write the hot data, warm data, and cold data into the hot list memory region, the warm list memory region, and the cold list memory region respectively.

[0128] In a possible implementation, the main control chip includes a heat perception unit;

[0129] The heat perception unit is configured to, if the address type is the first address type, count the access heat of each target access address to each memory unit of the first memory region; determine the memory regions corresponding to the memory units with the corresponding access heat greater than the first heat threshold as the hot list memory region, determine the memory regions corresponding to the memory units with the corresponding access heat greater than the second heat threshold and less than or equal to the first heat threshold as the warm list memory region, and determine the memory regions corresponding to the memory units with the corresponding access heat greater than the third heat threshold and less than or equal to the second heat threshold as the cold list memory region, where the hot list memory region, the warm list memory region, and the cold list memory region are sub-memory regions of the first memory region, the first heat threshold is greater than the second heat threshold, and the second heat threshold is greater than the third heat threshold.

[0130] In a possible implementation, the main control chip further includes a memory control unit;

[0131] The memory control unit is configured to, if the address type is the second address type, determine a second memory area according to each target access address, where the first address type is different from the second address type.

[0132] In a possible implementation, the main control chip includes an address arbitration unit. The address arbitration unit is configured to determine the device interconnection protocol type included in the data processing request; if the device interconnection protocol type is the target input / output communication protocol, determine that the address type of the target access address is the first address type; if the device interconnection protocol type is the target memory access protocol, determine that the address type of the target access address is the second address type.

[0133] By using the memory provided in the embodiments of the present application, the target access addresses in the data processing request are classified according to the address type. For different types of target access addresses, memory partitioning or non-partitioning can be selected according to the data processing requirements. Differential encoding processing and reading are performed on the partitioned and non-partitioned flash data. Hot data with high access heat can be quickly read, and balanced reading can be adopted for data with balanced access heat. This not only meets the personalized processing requirements of users in different data processing scenarios, but also effectively utilizes the remaining capacity in the flash medium, realizing effective classification management of data.

[0134] In a possible implementation, Figure 4 shows another structural schematic diagram of the memory provided in the embodiments of the present application. As Figure 4 shown, the memory may include an SSD main control chip and flash memory. The SSD main control chip may include a CXL controller, a cache controller, a flash memory controller, DRAM, and an ARM processor. As Figure 4 shown, the DRAM includes a hot area, a warm area, a cold area, an unseparated area, and an FTL (Flash Translation Layer) mapping table LBA to PBA address mapping, a hot list, a warm list, and a cold list. The hot area is the memory area of the hot list, the warm area is the memory area of the warm list, the cold area is the memory area of the cold list, and the FTL mapping table LBA to PBA address mapping refers to the address mapping table between LBA and PBA. As Figure 4As shown, the LBA to FLASH page address mapping table in the flash memory is a data structure used to manage the relationship between the LBA and the physical flash page address. The CXL controller includes a protocol multiplexing unit, a local address arbitration unit, a heat perception unit, an NVMe (Non-Volatile Memory Express, non-volatile memory CPU controller interface) unit, and a NIC (Network Interface Card, interface card between the computer and the network) bus, and can implement the access paths of the CXL.io protocol and the CXL.mem protocol. The CXL.io protocol is used for general I / O communication between devices, and the CXL.mem protocol is used for accessing and sharing the main memory.

[0135] The protocol multiplexing unit can be used to implement the functions of the CXL physical layer. For example, it is used to perform functions such as serial-to-parallel conversion of data and clock recovery. The CXL.mem protocol and the CXL.io protocol can send and receive data by multiplexing the physical layer. The CXL.io protocol can be used for functions such as device configuration, initialization, I / O virtualization, and direct memory access using non-uniform cache load / store semantics. In the embodiment of the present application, during the initial power-on stage of the electronic device, the CXL-SSD memory and configuration registers, etc. will be enumerated to implement the configuration process of the CXL-SSD device. During the flash read / write stage, the memory can transmit data with the CPU through the CXL.io protocol.

[0136] The CXL.mem protocol can make the memory on the electronic device side become the memory managed by the CPU. The CPU manages and accesses this memory just like accessing the local DRAM connected to the CPU. The CXL.mem protocol is independent of the medium used. Read and write operations can be performed through a set of CPU physical addresses. The CXL.mem protocol has two channels in each direction, and the two channels refer to the direction from the CPU of the electronic device to the memory and the direction from the memory to the CPU. The CXL.mem protocol can simplify the data read and write operations required for the I / O queue transaction type in the embodiment of the present application.

[0137] The flash controller includes an address recognition and encoding switching unit, an encoding unit, an ONFI-Ctrl (Open NAND Flash Interface-Ctrl), and an ONFI-Phy (Open NAND Flash Interface-Phy) unit, and the encoding unit can perform encoding processing on the data.

[0138] In a possible implementation manner, Figure 5 shows a partial structural schematic diagram of the memory provided by the embodiment of the present application. As Figure 5As shown in the figure, the protocol multiplexing unit of the memory transmits data to and from the local address arbitration unit through the CXL.mem protocol and the CXL.io protocol. After passing through the protocol multiplexing unit, the access address can be arbitrated to different protocol stacks and thus routed to different control layers. The local address arbitration unit can transmit the CXL control layer input address and data to different data processing units according to the memory space addresses defined by the CXL.io protocol and the CXL.mem protocol on the CPU side, such as the heat perception unit or the NVMe unit.

[0139] As Figure 5 shown in the figure, after being arbitrated by the local address arbitration unit, the CXL control layer input address and data in the local address arbitration unit can be transmitted to different data processing units according to the address type. Specifically, the local address arbitration unit can match the CXL control layer input address with the memory address register and the base address register. If the CXL control layer input address belongs to the address range of the memory address register, the address type can be determined as the first address type, and then the CXL control layer input address can be transmitted to the heat perception unit; if the CXL control layer input address belongs to the address range of the base address register, the address type can be determined as the second address type, and then the CXL control layer input address can be transmitted to the NVMe unit. The CXL control layer input data can be input to the heat perception unit or the NVMe unit. The CXL control layer input data can include the input address data.

[0140] The heat perception unit can identify hot / warm / cold data regions based on the access frequencies of different addresses. The NVMe unit can be used to parse the NVMe protocol and transmit data packets to the NIC unit. The DRAM includes a hot region, a warm region, a cold region, an unallocated region, and an FTL (Flash Translation Layer) mapping table. The hot region is the hot list memory region, the warm region is the warm list memory region, the cold region is the cold list memory region, and the FTL mapping table is the address mapping table between the LBA and the PBA.

[0141] In the embodiment of this application, the heat perception unit can place the data exceeding the first heat threshold in the hot region based on the address access heat on the CPU side. The data in the hot region is transcoded by the encoding unit in the flash controller and then transmitted to the hot region of the flash medium; the data greater than the second heat threshold and less than or equal to the first heat threshold is placed in the warm region based on the address access heat on the CPU side. The data in the warm region is transcoded by the encoding unit in the flash controller and then transmitted to the warm region of the flash medium; the data greater than the third heat threshold and less than or equal to the second heat threshold is placed in the cold region based on the address access heat on the CPU side. The data in the cold region is transcoded by the encoding unit in the flash controller and then transmitted to the warm region of the flash medium.

[0142] In a possible implementation,Figure 6 Another partial structural schematic diagram of the memory provided by the embodiment of the present application is shown. As Figure 6 shown, the heat perception unit may include a heat counting unit and a hot / warm / cold decision unit. The heat counting unit may count the access frequencies of memory blocks of each unit size of the target access address. The unit size may be flexibly configured by the device side according to the memory capacity. Specifically, the unit size may be determined through a unit size register. The unit size adopted by the embodiment of the present application may be 4 kB. The address of each memory block in the memory may be composed of multiple base addresses. For example, it may be composed of 4 base addresses. As Figure 6 shown, the memory may include N memory blocks: "base address + 0 - base address + 4×kB - 1" refers to a 4-kB memory block with a start address of base address 0 and an end address of base address 4×kB - 1; "base address + 4×kB - base address + 2×4×kB - 1" refers to a memory block with a start address of base address 4×kB and an end address of base address 2×4×kB - 1; "base address + 2×4×kB - base address + 3×4×kB - 1" refers to a memory block with a start address of base address 2×4×kB and an end address of base address 3×4×kB - 1; "base address + 3×4×kB - base address + 4×4×kB - 1" refers to a memory block with a start address of base address 3×4×kB and an end address of base address 4×4×kB - 1; "base address + 4×4×kB - base address + 4×5×kB - 1" refers to a memory block with a start address of base address 4×4×kB and an end address of base address 4×5×kB - 1; "base address + 4×5×kB - base address + 4×6×kB - 1" refers to a memory block with a start address of base address 5×4×kB and an end address of base address 4×6×kB - 1; "base address + (N - 1)×4×kB - base address + N×4×kB - 1" refers to a memory block with a start address of base address (N - 1)×4×kB and an end address of base address N×4×kB - 1. The size of N is determined by the overall memory size. As Figure 6 shown, Unit Size 0 Counter, Unit Size 2 Counter,..., Unit Size N Counter are all counters. The heat counting unit may map multiple Counters (counters) to the memory blocks of each unit size to obtain a counter-address mapping relationship. Through the counter-address mapping relationship, each counter may record the number of times the corresponding unit-size memory block is accessed within a fixed time interval. For example, as Figure 6 shown, Unit Size 0 Counter may correspondingly record the number of times the memory block "base address + 0 - base address + 4×kB - 1" is accessed, and Unit Size N Counter may correspondingly record the number of times the memory block "base address + (N - 1)×4×kB - base address + N×4×kB - 1" is accessed.

[0143] As Figure 6 shown, the target access address output by the local address arbitration unit is counted. When the target access address falls within the memory address range of the Nth memory block, the counter corresponding to this memory block can be incremented by 1. The hot / warm / cold decision unit can compare the count values of all unit sizes with each heat threshold at preset intervals and record the starting addresses of the unit sizes whose count values are greater than the first heat threshold to obtain a hot address list. Similarly, a warm address list and a cold address list are obtained. The preset interval can be determined by an interval time register.

[0144] As Figure 6 shown, the unit size Counter, i.e., the counter. When the count of the unit size Counter is greater than or equal to the heat threshold, it indicates that the address in the memory block of the corresponding unit size belongs to the address in the hot list, and then the address of the memory block of this unit size can be stored in the hot list; when the count of the unit size Counter is greater than or equal to the warm threshold and less than the heat threshold, it indicates that the address of the memory block of the corresponding unit size belongs to the address in the warm list, and then the address of the memory block of this unit size can be stored in the warm list; when the count of the unit size Counter is greater than or equal to 0 and less than the warm threshold, it indicates that the address of the memory block of the corresponding unit size belongs to the address in the cold list, and then the address of the memory block of this unit size can be stored in the cold list. The heat threshold can be determined by a heat threshold register. Specifically, the size of the heat threshold can be set according to application requirements. The warm threshold can be determined by a warm threshold register, and the size of the warm threshold can be set according to application requirements. The hot / warm / cold list storage addresses include a hot list, a warm list, and a cold list. The hot list storage address register can access the memory address stored in the hot list, the warm list storage address register can access the memory address stored in the warm list, and the cold list storage address register can access the memory address stored in the cold list. By partitioning and managing the memory addresses through counting, the memory access efficiency is improved. The list address / data address selector can be used to select and manage memory addresses and data to enhance the efficiency of the system. The list / data selector can improve the memory access efficiency by selecting addresses from different lists.

[0145] Figure 7 shows another partial structural schematic diagram of the memory provided by the embodiment of the present application. As Figure 7As shown, the DRAM memory includes a hot list and a hot area, which are respectively used to store the hot list transmitted by the heat perception unit and the data corresponding to the hot list; the DRAM memory also includes a warm list and a warm area, which are respectively used to store the warm list transmitted by the heat perception unit and the data corresponding to the warm list; the DRAM memory also includes a cold list and a cold area, which are respectively used to store the cold list transmitted by the heat perception unit and the data corresponding to the cold list; the DRAM memory also includes an unpartitioned area, which can store the data transmitted by the NVMe unit and the data transmitted by the heat perception unit before partitioning; the DRAM memory also includes an FTL mapping table, which can store the mapping table of the LBA and PBA addresses. The heat perception unit can first place the transmitted data in the unpartitioned area of the DRAM memory. After the hot data list, warm data list, and cold data list are generated, the corresponding data can be migrated to the hot area, warm area, and cold area respectively. The FTL mapping table can also include an unpartitioned address mapping unit, which can map the data transmitted by the NVMe unit in the unpartitioned area to the PBA address, rather than mapping all the data in the unpartitioned area.

[0146] Figure 8 It shows a coding schematic diagram of a memory provided by an embodiment of the present application. As Figure 8 shown, in the DRAM memory, the FTL mapping table can also include a hot / warm / cold partition address mapping unit. Through the hot / warm / cold partition address mapping unit and the unpartitioned address mapping unit, different memory partition addresses can be mapped to different PBA address areas. For different PBA address areas, different coding schemes can be used to read flash data. For example, Figure 8 It shows another partial structural schematic diagram of a memory provided by an embodiment of the present application. As Figure 8 shown, the range of PBA address area 1 is [0: hot / warm / cold partition maximum PBA address - 1], and PBA address area 1 can correspond to coding scheme 1; the range of PBA address area 2 is [hot / warm / cold partition maximum PBA unpartitioned maximum PBA address - 1], and PBA address area 2 can correspond to coding scheme 2. As Figure 8As shown, the encoding unit in the memory can select different encoding schemes for the original data according to the PBA address area input to the flash controller. Encoding scheme 1 can be used to encode hot / warm / cold partition data. In encoding scheme 1, the flash data of the Lower page can be hot data, and all the flash data of the Lower page can be read with only 1 read operation; the flash data of the Middle page can be warm data, and all the flash data of the Middle page need 3 read operations to be read; the flash data of the Upper page can be cold data, and all the flash data of the Upper page need 7 read operations to be read. Encoding scheme 2 can be used to read the flash page data where the data is not stratified, and all the flash page data can be read through 3 or 2 reads, which is a balanced media encoding scheme. As Figure 8 shown, in encoding scheme 2, all the flash data of the Lower page can be read with 3 read operations, all the flash data of the Middle page can be read with 2 read operations, and all the flash data of the Upper page can be read with 2 read operations. Figure 8 Among them, "000", "001", "010", "011", "100", "101", "110" and "111" refer to the encodings corresponding to the data.

[0147] Figure 9 FIG. shows a schematic diagram of data writing of a memory provided by an embodiment of the present application. As Figure 9 shown, the hot page corresponds to the hot zone data, the warm page corresponds to the warm zone data, and the cold page corresponds to the warm zone data. When writing data, hot / warm / cold three-page overlapping encoding can be respectively extracted. As Figure 9 shown, the size of the flash data of each page can be 4 kB. For example, the data from base address 0 to base address 4 kB - 1 can form a page of flash data with a size of 4 kB. The corresponding bit positions of each page can form a 3-bit data, and each 3-bit data corresponds to a storage unit, and the 3-bit data is written into the storage unit. For example, it takes 7 write operations to write a physical page. When writing, three pages, two pages or a single page can be written, and when reading, a single page can be read.

[0148] Figure 10 FIG. shows a schematic diagram of the system architecture corresponding to the memory provided by an embodiment of the present application. As Figure 10As shown, the CXL-SSD memory can be compatible with the CXL ecosystem. Flash data can be partitioned into hot pages / warm pages / cold pages. Therefore, the CXL-SSD can be used compatibly with the CPU and the Root Port. The CPU can include an L1 cache, an L2 cache, and an L3 shared cache. The CXL-SSD can be applied as a CXL product form in the CXL ecosystem. The CXL-SSD memory can communicate with components such as the Home Agent (CPU management), the CXL-Fabric (computer interconnection) protocol, the NVMe drive, the CXL.mem controller, the PCXL.io controller, and the protocol multiplexing unit in the CXL ecosystem through the CXL.io protocol or the CXL.mem protocol. The PCXL.io controller is a controller for high-performance computing and storage solutions in the CXL ecosystem. The PCXL.io controller can communicate with components such as the Home Agent, the NVMe drive, the CXL.mem controller, and the protocol multiplexing unit in the CXL ecosystem through the CXL.io protocol or the CXL.mem protocol. The Home Agent, the NVMe drive, and the CXL.mem controller in the CXL ecosystem can communicate with the memory controller. The memory controller can interact with the DRAM through the CompletionQueue and the SubmissionQueue.

[0149] In a possible implementation, since the CPU of the electronic device involves an unpartitioned flash data reading strategy through the CXL.io protocol and a hot / warm / cold data reading strategy through the CXL.mem protocol, and the corresponding memories for different strategies are different, it is necessary to configure the electronic device at the initial power-on stage of the electronic device. Figure 11 The configuration schematic diagram of the power-on stage of the memory provided by the embodiment of the present application is shown. As Figure 11As shown, during the power-on startup phase of the CXL-SSD, the SSD memory needs to request the CPU to allocate two parts of memory address space. One part is the first memory area for storing hot / warm / cold partition data, and the other part is the second memory area for storing unpartitioned data. The memory address capacity and address range corresponding to the hot / warm / cold partitions are determined by the capacity of the hot / warm / cold data stored in the flash memory, and the address range can be recorded in the memory address register. The memory address space of the second memory area for storing unpartitioned data is determined by the capacity in the base address space register. During the power-on process, the memory can request the CPU, and the CPU allocates the first memory area and the second memory area. Data processing requests related to the CXL.io protocol can be transmitted through the address range defined in the base address space register, and data processing requests related to the CXL.mem protocol can be transmitted through the address range defined in the memory address register. The address ranges of the base address space register and the memory address register can be continuous or discontinuous, but cannot overlap.

[0150] As Figure 11 shown, the CXL-SSD memory can include an SSD main control chip and flash memory. The SSD main control chip can include a CXL controller, a cache controller, a flash memory controller, DRAM, and an ARM processor. The CXL controller contains a protocol multiplexing unit, a local address arbitration unit, a heat perception unit, an NVMe unit, and a NIC bus, and can implement the access paths of the CXL.io protocol and the CXL.mem protocol. The flash memory controller contains an address recognition and encoding switching unit, an encoding unit, an ONFI-Ctrl unit, and an ONFI-Phy unit. The encoding unit can perform encoding processing on the data. The DRAM includes a hot area, a warm area, a cold area, an unseparated area, a hot list, a warm list, a cold list, and an FTL mapping table. The hot area is the hot list memory area, the warm area is the warm list memory area, the cold area is the cold list memory area, and the FTL mapping table is the address mapping table between the LBA and the PBA. The LBA and FLASH page address mapping table in the flash memory is a data structure for managing the relationship between the LBA and the physical flash page address.

[0151] As Figure 11As shown, during the power-on stage of the CXL-SSD, the CPU issues a request to read data through the Root Port, and the Root Port forwards the request to the CXL-SSD through the CXL link. The CXL-SSD can partition the flash data to be read according to the access heat involved in the request, and divide the flash data into hot pages, warm pages, cold pages, and unseparated area data. Different encoding methods are adopted for the flash data in different partitions through the address recognition and encoding switching unit, and the flash data in different partitions is read. The read hot page, warm page, and cold page flash data are temporarily stored in the hot area, warm area, and cold area of the first memory area of the DRAM respectively, and the read unseparated area data is stored in the unseparated area. The CPU can obtain the flash data temporarily stored in the DRAM through the CXL link. The CPU can also interact with the DRAM through the completion queue and the submission queue to obtain the flash data temporarily stored in the physical area pages of the DRAM.

[0152] In a possible implementation manner, Figure 12 The schematic diagram of the hot / warm / cold data partition write operation of the memory provided by the embodiment of the present application is shown. As Figure 12 shown, the CXL-SSD memory can include an SSD main control chip and flash memory. The SSD main control chip can include a CXL controller, a cache controller, a flash memory controller, DRAM, and an ARM processor. The CXL controller contains a protocol multiplexing unit, a local address arbitration unit, a heat perception unit, an NVMe unit, and a NIC bus, and can implement the CXL.io protocol and the CXL.mem protocol access paths. The flash memory controller contains an address recognition and encoding switching unit, an encoding unit, an ONFI-Ctrl unit, and an ONFI-Phy unit, and the encoding unit can perform encoding processing on the data. The DRAM includes a hot area, a warm area, a cold area, an unseparated area, a hot list, a warm list, a cold list, and an FTL mapping table. The hot area is the memory area of the hot list, the warm area is the memory area of the warm list, the cold area is the memory area of the cold list, and the FTL mapping table is the address mapping table between the LBA and the PBA. The LBA and FLASH page address mapping table in the flash memory is a data structure for managing the relationship between the LBA and the physical flash page address. The CPU can issue a request to write data through the Root Port, and the Root Port forwards the request to the CXL-SSD through the CXL link. The CPU can interact with the DRAM through the completion queue and the submission queue to obtain the flash data temporarily stored in the physical area pages of the DRAM.

[0153] As Figure 12 shown, the CPU can access the unseparated memory area through the CXL.io protocol. As Figure 12 shown, the write operation process of accessing the unseparated mode through the CXL.io protocol can include:

[0154] ①The CPU sends data processing instructions to the submission queue buffer in the memory; ②The CPU initiates a CXL.io to establish a communication channel with the SSD to inform the SSD to obtain data processing instructions from the submission queue buffer; ③The SSD initiates a read command to the CPU through the CXL.io channel to request data via the read command; ④The CPU returns data to the CXL-SSD device, and the returned data is the data processing instruction located in the memory submission queue buffer. The data processing instruction is to write the PRP0x# data in the CPU memory to the LBA address %%%%%; ⑤Read the data with the memory address of PRP0x# through the CXL.io channel; ⑥The CPU sends a message indicating the completion of the read to the SSD; ⑦Through the local address arbitration unit, after arbitration, it is transferred to the NVMe unit in the unpartitioned mode, and then the data is placed in the unseparated area of the SSD on-board DRAM; ⑧Write the data corresponding to the LBA to the PBA of the flash medium as @@@@@ through the flash controller, where the data is encoded by encoding scheme 2, and the mapping relationship between the LBA and the PBA is recorded in the flash medium; ⑨The SSD writes the completion status information to the completion queue of the CPU through the CXL.io channel; ⑩The SSD uses the interrupt method to tell the CPU that the command has been executed and let the CPU process the completion queue; ⑪After receiving the interrupt, the CPU processes the corresponding completion queue; ⑫After the CPU processes the corresponding completion queue, it updates the command of the completion queue on the SSD side through the CXL.io.

[0155] As Figure 12As shown, the CPU can access the hot / warm / cold data partition mode through the CXL.mem protocol. The write operation process for accessing the hot / warm / cold data partition mode through the CXL.mem protocol can include: ⑴ The CPU sends a request with data through M2S (Microcontroller to System) to the CXL-SSD. The data is: 0x$$$$$$, and the address is: 0x##; ⑵ After the address is arbitrated by the local address arbitration, it is the hot / warm / cold data partition mode. The address is transmitted to the heat perception unit for counting, and then the data will be placed in the unseparated area in the SSD board-mounted DRAM; ⑶ The completion status is restored to the CPU through the non-data response channel of S2M; ⑷ After a fixed time interval, the heat perception unit updates the hot / warm / cold list to the DRAM, and the data in the unseparated area is placed in the hot / warm / cold areas respectively according to the hot / warm / cold list. The corresponding address becomes 0#!!!!!!, and the original address and the mapping relationship after the address change are recorded. This mapping relationship will exist in the corresponding hot / warm / cold areas of the DRAM; ⑸ The data corresponding to the address 0x!!!!!! is written into the PBA of the flash memory medium through the flash memory controller. The data corresponding to the address 0x!!!!!! is encoded by encoding scheme 1, and the mapping relationship between the address and the PBA is recorded in the flash memory medium.

[0156] Figure 13 FIG. shows a schematic diagram of the hot / warm / cold data partition read operation of the memory provided by the embodiment of the present application. As Figure 13 shown, the CXL-SSD memory can include an SSD main control chip and a flash memory. The SSD main control chip can include a CXL controller, a cache controller, a flash memory controller, a DRAM, and an ARM processor. The CXL controller contains a protocol multiplexing unit, a local address arbitration unit, a heat perception unit, an NVMe unit, and a NIC bus, and can implement the access paths of the CXL.io protocol and the CXL.mem protocol. The flash memory controller contains an address recognition and encoding switching unit, an encoding unit, an ONFI-Ctrl unit, and an ONFI-Phy unit. The encoding unit can perform encoding processing on the data. The DRAM includes a hot area, a warm area, a cold area, an unseparated area, a hot list, a warm list, a cold list, and an FTL mapping table. The hot area is the memory area in the hot list, the warm area is the memory area in the warm list, the cold area is the memory area in the cold list, and the FTL mapping table is the address mapping table between the LBA and the PBA. The LBA and FLASH page address mapping table in the flash memory is a data structure for managing the relationship between the LBA and the physical flash page address. The CPU can send a request to read data through the Root Port, and the Root Port forwards the request to the CXL-SSD through the CXL link. The CPU can interact with the DRAM through the completion queue and the submission queue to obtain the flash memory data temporarily stored in the physical area page of the DRAM.

[0157] As shown Figure 13 in the figure, the CPU can access the unpartitioned mode through the CXL.io protocol. The read operation process of accessing the unpartitioned mode through the CXL.io protocol may include: ① The CPU sends a data read instruction to the submission queue buffer in the memory; ② The CPU initiates a CXL.io channel connection to the SSD to inform the memory to read the instruction from the submission queue buffer; ③ The SSD initiates a read command to the CPU through the CXL.io channel, and the read command will request data; ④ The CPU returns the data to the CXL-SSD device, and the returned data is the data read instruction located in the memory submission queue buffer. The content of the data read instruction is to read the data with the LBA address of 0xXXXX in the SSD to the memory PRP0x#; ⑤ Look up the address in the address mapping table in the device DRAM, convert the LBA address to the corresponding address PBA0x%%%% of the SSD internal flash, retrieve the data corresponding to the PBA through the flash controller and place it in the unpartitioned area inside the SSD, where the data is decoded by encoding scheme 2; ⑥ The SSD sends the CXL.io protocol to the CPU and writes the protocol data to the CPU memory PRP0x#; ⑦ The SSD writes the completion status information to the CPU's completion queue through the CXL.io protocol; ⑧ The SSD uses the interrupt method to tell the CPU that the command has been executed and let the CPU process the completion queue; ⑨ After receiving the interrupt, the CPU processes the corresponding completion queue; ⑩ After the CPU processes the corresponding completion queue, it updates the data read of the completion queue on the SSD side through the CXL.io protocol.

[0158] In the embodiment of the present application, the memory can also access the hot / warm / cold data partition through the CXL.mem protocol. Specifically, the read operation process of the CPU accessing the hot / warm / cold data partition through the CXL.mem protocol may include: ⑴ The CPU sends a request without data to the CXL-SSD, and the address is: 0x; ⑵ After local address arbitration, the address is in the hot / warm / cold data partition mode, and the address is transmitted to the heat perception unit for counting; ⑶ Search for the hot / warm / cold area mapping table with the address 0x in the hot / warm / cold area in the DRAM through the local address arbitration unit, and then search for the PBA address 0x@@@@@ on the flash media side through the FTL mapping table; ⑷ Read the data corresponding to 0x@@@@@ into the unpartitioned area of the device DRAM through the flash controller, where the data is decoded by encoding scheme 1; ⑸ Transmit the data and the completion status in the unpartitioned area on the SSD side to the CPU through the data response channel and the non-data response channel of S2M (System to Microcontroller).

[0159] In the embodiments of the present application, the hot / warm / cold data partition memory supports data reading and writing in two modes. In the hot / warm / cold data partition mode, the hot data is placed in the hot list memory area through the heat perception unit and the differential encoding scheme, effectively reducing the read latency. The warm / cold data is stored in the warm list memory area and the cold list memory area respectively, making use of the remaining capacity in the medium.

[0160] The present application also provides an electronic device and a readable storage medium.

[0161] Figure 14 FIG. shows a schematic block diagram of an example electronic device 1400 that can be used to implement the embodiments of the present disclosure. The electronic device is intended to represent various forms of digital computers, such as, a laptop computer, a desktop computer, a workbench, a personal digital assistant, a server, a blade server, a mainframe computer, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as, a personal digital processor, a cellular phone, a smart phone, a wearable device, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0162] As Figure 14 shown, the device 1400 includes a computing unit 1401, which can perform various appropriate actions and processes according to the computer program stored in the read-only memory (ROM) 1402 or the computer program loaded from the storage unit 1408 into the random access memory (RAM) 1403. In the RAM 1403, various programs and data required for the operation of the device 1400 can also be stored. The computing unit 1401, the ROM 1402, and the RAM 1403 are connected to each other through a bus 1404. The input / output (I / O) interface 1405 is also connected to the bus 1404.

[0163] A plurality of components in the device 1400 are connected to the I / O interface 1405, including: an input unit 1406, such as a keyboard, a mouse, etc.; an output unit 1407, such as various types of displays, speakers, etc.; a storage unit 1408, such as a disk, an optical disc, etc.; and a communication unit 1409, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 1409 allows the device 1400 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0164] The computing unit 1401 can be various general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 1401 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 1401 executes the various methods and processes described above, such as the data processing method. For example, in some embodiments, the data processing method can be implemented as a computer software program that is tangibly contained in a machine-readable medium, such as the storage unit 1408. In some embodiments, part or all of the computer program can be loaded and / or installed onto the device 1400 via the ROM 1402 and / or the communication unit 1409. When the computer program is loaded into the RAM 1403 and executed by the computing unit 1401, one or more steps of the data processing method described above can be executed. Alternatively, in other embodiments, the computing unit 1401 can be configured to execute the data processing method in any other suitable manner (e.g., by means of firmware).

[0165] Various embodiments of the technologies described above herein can be implemented in digital electronic circuitry, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), system-on-a-chip (SOCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. The program code for implementing the methods of the present disclosure can be written in any combination of one or more programming languages. In the context of the present disclosure, a machine-readable medium can be a tangible medium. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices, or apparatuses, or any suitable combination of the foregoing. A computer system can include a client and a server. The client and the server are generally far from each other and typically interact via a communication network. The server can be a cloud server, can also be a server of a distributed system, or is a server incorporating a blockchain. Additionally, the terms "first" and "second" are used for descriptive purposes only and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. In the description of the present disclosure, "a plurality" means two or more unless otherwise specifically defined.

[0166] The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present disclosure can easily think of changes or substitutions, which should all be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A data processing method, characterized in that, A host chip applied to a memory, the method comprising: Obtaining a data processing request, the data processing request including at least one target access address; Identifying the address type of each of the target access addresses; If the address type is a first address type, dividing the first memory area according to the access heat of each of the target access addresses to the first memory area, obtaining at least two sub-memory areas, and the access heat of the target access address to different sub-memory areas is different; If the address type is a second address type, determining a second memory area according to each of the target access addresses, the first address type being different from the second address type; Determining a corresponding data processing strategy according to the memory area corresponding to each of the target access addresses, and processing the data processing request based on the data processing strategy to obtain target access data; The determining a corresponding data processing strategy according to the memory area corresponding to each of the target access addresses, and processing the data processing request based on the data processing strategy to obtain target access data includes: Determining a target physical address area corresponding to the target access address according to a preset address mapping relationship between the memory area and the physical address area; Determining a target data encoding strategy corresponding to the target physical address area according to a preset corresponding relationship between different physical address areas and different data encoding strategies; Processing the data in the target physical address area based on the target data encoding strategy and the data processing request to obtain target access data; The identifying the address type of each of the target access addresses includes: Determining the device interconnection protocol type included in the data processing request; If the device interconnection protocol type is a target input / output communication protocol, determining that the address type of the target access address is a first address type; If the device interconnection protocol type is a target memory access protocol, determining that the address type of the target access address is a second address type.

2. The method according to claim 1, wherein The processing the data in the target physical address area based on the target data encoding strategy and the data processing request to obtain target access data includes: Reading the data in the target physical address area as target access data according to the target data encoding strategy and the data processing request; Storing the target access data into the memory area corresponding to the target access address.

3. The method according to claim 1, characterized in that The sub-memory areas of the first memory area include a hot list memory area, a warm list memory area, and a cold list memory area; The processing the data in the target physical address area based on the target data encoding strategy and the data processing request to obtain target access data includes: If the target data encoding policy is the first data encoding policy, according to the data processing request, use the first data encoding policy to perform a single read operation on the data pages in the physical address area corresponding to the hot list memory area in the target physical address area to obtain hot data, and perform a first preset number of read operations on the data pages in the physical address area corresponding to the warm list memory area in the target physical address area to obtain warm data, and perform a second preset number of read operations on the data pages in the physical address area corresponding to the cold list memory area in the target physical address area to obtain cold data, and use the hot data, the warm data, and the cold data as target access data; the first preset number and the second preset number are different; If the target data encoding policy is the second data encoding policy, according to the data processing request, use the second data encoding policy to perform a third preset number of read operations on the data in the target physical address area to obtain target access data.

4. The method according to claim 3, wherein It further includes: Write the hot data, the warm data, and the cold data into the hot list memory area, the warm list memory area, and the cold list memory area respectively.

5. The method according to claim 1, characterized in that, If the address type is the first address type, divide the first memory area according to the access hotness of each target access address to the first memory area, and obtain at least two sub-memory areas, including: If the address type is the first address type, count the access hotness of each target access address to each memory cell in the first memory area; Determine the memory area corresponding to each memory cell with a corresponding access hotness greater than the first hotness threshold as the hot list memory area, determine the memory area corresponding to each memory cell with a corresponding access hotness greater than the second hotness threshold and less than or equal to the first hotness threshold as the warm list memory area, and determine the memory area corresponding to each memory cell with a corresponding access hotness greater than the third hotness threshold and less than or equal to the second hotness threshold as the cold list memory area, where the hot list memory area, the warm list memory area, and the cold list memory area are sub-memory areas of the first memory area, the first hotness threshold is greater than the second hotness threshold, and the second hotness threshold is greater than the third hotness threshold.

6. A memory, characterized in that, It includes a main control chip and a flash memory; The main control chip is used to obtain a data processing request, where the data processing request includes at least one target access address; identify the address types of each of the target access addresses; if the address type is the first address type, divide the first memory area according to the access heat of each of the target access addresses to the first memory area, obtaining at least two sub-memory areas, and the access heat of the target access address to different sub-memory areas is different; if the address type is the second address type, determine a second memory area according to each of the target access addresses, where the first address type is different from the second address type; determine a corresponding data processing strategy according to the memory area corresponding to each of the target access addresses, and process the data processing request based on the data processing strategy, and obtain target access data from the flash memory; The main control chip includes an address recognition unit and a flash memory control unit; The address recognition unit is used to determine the target physical address area corresponding to the target access address according to a preset address mapping relationship between the memory area and the physical address area; determine the target data encoding strategy corresponding to the target physical address area according to a preset corresponding relationship between different physical address areas and different data encoding strategies; The flash memory control unit is used to process the data in the target physical address area based on the target data encoding strategy and the data processing request to obtain target access data; The main control chip includes an address arbitration unit, and the address arbitration unit is used to determine the type of device interconnection protocol included in the data processing request; If the type of device interconnection protocol is the target input / output communication protocol, determine that the address type of the target access address is the first address type; if the type of device interconnection protocol is the target memory access protocol, determine that the address type of the target access address is the second address type.

7. The memory according to claim 6, characterized in that, The flash memory control unit is used to read the data in the target physical address area as target access data according to the target data encoding strategy and the data processing request; store the target access data into the memory area corresponding to the target access address.

8. The memory according to claim 6, wherein The sub - memory regions of the first memory region include a hot list memory region, a warm list memory region, and a cold list memory region; the flash memory control unit is configured to, if the target data encoding policy is the first data encoding policy, according to the data processing request, perform a single read operation on the data pages in the physical address region corresponding to the hot list memory region in the target physical address region to obtain hot data, and perform a first preset number of read operations on the data pages in the physical address region corresponding to the warm list memory region in the target physical address region to obtain warm data, and perform a second preset number of read operations on the data pages in the physical address region corresponding to the cold list memory region in the target physical address region to obtain cold data, and use the hot data, the warm data, and the cold data as target access data; the first preset number and the second preset number are different; if the target data encoding policy is the second data encoding policy, according to the data processing request, perform a third preset number of read operations on the data in the target physical address region to obtain target access data.

9. The memory according to claim 8, wherein The flash memory control unit is further configured to write the hot data, the warm data, and the cold data into the hot list memory region, the warm list memory region, and the cold list memory region respectively.

10. The memory according to claim 6, wherein The main control chip includes a heat perception unit; The heat perception unit is configured to, if the address type is the first address type, count the access heat of each of the target access addresses to each memory unit of the first memory region; determine the memory regions corresponding to the memory units with corresponding access heat greater than the first heat threshold as the hot list memory region, determine the memory regions corresponding to the memory units with corresponding access heat greater than the second heat threshold and less than or equal to the first heat threshold as the warm list memory region, and determine the memory regions corresponding to the memory units with corresponding access heat greater than the third heat threshold and less than or equal to the second heat threshold as the cold list memory region, where the hot list memory region, the warm list memory region, and the cold list memory region are sub - memory regions of the first memory region, the first heat threshold is greater than the second heat threshold, and the second heat threshold is greater than the third heat threshold.

11. An electronic device, characterized in that, Comprising: A memory, a processor, and a computer program stored on the memory and executable on the processor, where the processor implements the method according to any one of claims 1 - 5 when executing the program.

12. A storage medium containing computer-executable instructions, characterized in that, The computer - executable instructions are used to execute the method according to any one of claims 1 - 5 when executed by a computer processor.

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