Server and processor error processing method and device, medium and program product

Abstract

The invention discloses a server and processor error processing method and device, a medium and a program product, and relates to the technical field of servers. The method comprises the following steps: when a correctable error occurs in a processor, displaying a setting interface containing error parameter configuration options, and setting a target fault-tolerant allowable value corresponding to the correctable error for the error parameter configuration options; in an execution environment corresponding to the system management mode, selecting error degree data corresponding to the processor from the multi-device error collection information according to error type identifiers allocated for different errors by an error register; and determining whether to generate an error reporting and clearing instruction according to the processor error degree data and the target fault tolerance allowable value. According to the method and the device, the problem that CPU CE faults cannot be found in time due to the fact that decoupling cannot be carried out when errors are reported in related technologies can be solved, a user can perceive CE error types, fault recognition accuracy and efficiency can be improved, the occurrence probability of CE storm can be reduced, and the reliability of a server can be improved.

Description

Technical Field

[0001] The present invention relates to the technical field of servers, and in particular, to a processor error handling method, an electronic device, a computer-readable storage medium, a computer program product, and a server. Background Art

[0002] The stable operation of a server depends on an accurate fault diagnosis strategy. Based on the RAS (Reliability, Availability, Serviceability) characteristics, CPU (Central Processing Unit) faults have the greatest impact on the server. CPU errors include CPU CE (Corrected Error), and CPU CE can be handled by the built-in error correction mechanism of the system. In related technologies, in order to facilitate the detection and handling of CE alarms by the CPU, all CE alarms in the current computer system are aggregated, and then a larger error reporting threshold is set for handling. Users cannot perceive the types of reported CEs, and it is easy to accumulate a large number of CPU CEs, which may lead to the phenomenon of CE storms, and is not conducive to the timely discovery of faults. Summary of the Invention

[0003] The present invention provides a processor error handling method, an electronic device, a computer-readable storage medium, a computer program product, and a server. Users can perceive the CE error type, which is beneficial to improving the accuracy and efficiency of fault identification, effectively reducing the probability of CE storms, and enhancing the stability and reliability of the server.

[0004] To solve the above technical problems, the present invention provides the following technical solutions: The present invention provides a processor error handling method, including: When a processor has a correctable error, display a setting interface including error parameter configuration options, and set a target fault tolerance allowable value corresponding to the correctable error for the error parameter configuration options; the target fault tolerance allowable value is the maximum number of correctable errors that can occur within an allowable time period; in the execution environment corresponding to the system management mode, obtain multi-device error collection information stored in different error type partitions by each error register at the current moment, and determine the number of correctable error generations of the processor within a target time period in the multi-device error collection information according to the error type of the correctable error of the processor, as processor error degree data; determine whether to generate an error reporting instruction and an error clearing instruction according to the processor error degree data and the target fault tolerance allowable value, so as to send the correctable error to the management controller through the error reporting instruction, and clear the record data of the correctable error from the target register through the error clearing instruction.

[0005] The present invention also provides an electronic device, including a memory and a processor. When the processor executes a computer program stored in the memory, the steps of any one of the above-mentioned processor error handling methods are implemented.

[0006] The present invention also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of any one of the above-mentioned processor error handling methods are implemented.

[0007] The present invention finally also provides a computer program product, including a computer program / instructions. When the computer program / instructions are executed by a processor, the steps of any one of the above-mentioned processor error handling methods are implemented.

[0008] The present invention finally also provides a server, including a basic input / output system, a central processing unit, and a baseboard management controller. Among them, the central processing unit includes at least one register for storing hardware error information, and the basic input / output system includes a setting interface, which is used to implement the steps of any one of the above-mentioned processor error handling methods when executing a computer program, and send the generated error reporting instruction to the baseboard management controller.

[0009] The advantages of the technical solution provided by the present invention are as follows: when storing various errors, the error register will identify according to different error types. In this way, after obtaining all the error reporting information of the computer system at the current moment, it is possible to identify which errors belong to the CE errors of the processor according to the error type. Then, by setting the target fault tolerance allowable value of the CE of the processor on the setting page, the CE errors of the processor can be reported and processed separately in combination with their own unique corresponding target fault tolerance allowable values. This can not only decouple the CE reporting process of the processor from the memory CE reporting process, enabling the customer to effectively perceive whether the reported CE is from the processor or the memory, locate the error reporting device in a timely and accurate manner, and improve reliability and stability, but also allow the user to customize the target fault tolerance allowable value, which not only improves flexibility but also can obtain error reporting data that better conforms to the actual situation of the device. Further, according to the comparison between the processor error degree data and the target fault tolerance allowable value, the user can promptly identify a large number of CPU CE error reports occurring in a short period of time, promptly investigate the cause of the error, and effectively clear the CE in a timely manner, effectively reducing the risk of a CE storm and filtering out the phenomenon of a small number of CPU CE occurring within a long period of time. This not only saves a large amount of investment by operation and maintenance personnel but also reduces the risk of serious abnormalities in the machine.

[0010] In addition, the present invention also provides corresponding electronic devices, computer-readable storage media, computer program products, and servers for the processor error handling method, further making the method more practical, and the electronic devices, computer-readable storage media, computer program products, and servers have corresponding advantages. Brief Description of the Drawings

[0011] To more clearly illustrate the technical solutions of the present invention or related technologies, the following will briefly introduce the drawings required for use in the description of the embodiments or related technologies. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0012] Figure 1 It is a framework schematic diagram of an exemplary application scenario of the processor error handling method provided by the present invention; Figure 2 It is a flowchart of a processor error handling method provided by the present invention; Figure 3 It is a flowchart of another processor error handling method provided by the present invention; Figure 4 It is a structural framework diagram under an exemplary embodiment of the processor error handling device provided by the present invention; Figure 5 It is a structural diagram of an exemplary embodiment of the server provided by the present invention. Detailed Embodiments

[0013] To enable those skilled in the art to better understand the technical solutions of the present invention, the present invention will be further described in detail below in conjunction with the drawings and specific embodiments. Among them, the terms "first", "second", "third", "fourth", etc. in the specification and the above drawings are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion. The term "exemplary" means "serving as an example, embodiment, or illustration". Any embodiment described herein as "exemplary" does not have to be construed as superior to or better than other embodiments.

[0014] The stable operation of a computer system and the occurrence of fewer problems during operation are issues that need to be considered in the process of computer production and research and development. To ensure that the computer system runs as long and reliably as possible without going offline, a system with RAS (Reliability Availability Serviceability) characteristics will be built in, such as the systems used in servers and data center environments. Based on the efficient diagnosis of the overall machine failures of RAS, the downtime of the computer system can be minimized, and the integrity of the data and the continuous operation of the system can be ensured.

[0015] Currently, common RAS fault diagnosis strategies include predictive fault analysis, such as using built-in sensors to monitor the status of components such as the CPU (Central Processing Unit), and giving early warnings of possible faults. It also includes a detailed review of log files generated by the operating system, BIOS (Basic Output and Input System), application programs, etc. to find error messages or alerts. It also includes using redundant design to improve the reliability and availability of the system. When a component fails, a standby component is enabled to continue providing services. It also includes operations and maintenance personnel accessing the server status through remote management, such as BMC (Baseboard Management Controller), and performing diagnostic tests, system restarts, component replacements, etc. It also includes timely updating of software and firmware to fix known vulnerabilities and improve performance, keeping the latest versions of the BIOS, operating system, and application programs, and ensuring that all security patches are correctly installed. It also includes implementing error detection and filtering of devices such as the CPU, memory, and PCIe (peripheral component interconnect express) through relevant registers built into the CPU.

[0016] Among them, the CPU is one of the core components of a computer system, used to execute instruction sets in computer programs, perform arithmetic and logical operations, control data streams, and process input / output operations. Considering the RAS characteristics, compared with errors in devices such as memory and PCIe, when the CPU has an error, it has a greater impact on the stability of the system. Common CPU errors include CPU CE and CPU UCE (UnCorrected Error). Among them, CE errors can be handled by the built-in error correction mechanism of the system, such as ECC (Error Checking and Correcting) memory, and will not cause system crashes or data loss. However, UCE errors exceed the self-repair ability of the computer system and may lead to service interruptions or other serious consequences. Compared with UCE, CE is very common in RAS. A small number of CPU CEs will not affect the normal operation of the computer system. Correspondingly, customers usually do not perceive CPU CE error reports. However, a storm of CPU CE error reports is very likely to cause a CPU failure and evolve into CPU UCE in a short time. In addition, recording and analyzing CPU CE can help identify potential problems and take preventive measures. In order to avoid CE storms, it becomes an issue that the CPU CE RAS mechanism needs to focus on to identify a large number of CE error reports within a certain period of time and report them to the BMC and OS (operating system) in a timely manner.

[0017] Currently, after a CPU CE error occurs, the error will be stored in the MCA (Machine Check Architecture, which detects and reports hardware errors) register. During the boot process, the BIOS will read the error information from the CPU MCA register through an SMI handler that processes specific RAS events and report it to the BMC and the OS. To better control the number of CEs in the MCA register, a related technology has built a register in the CPU to control the number of CPU CEs. According to the customer's requirements, when the number of CPU CEs accumulates to a threshold, the error is written into the MCA register. Another related technology for handling CPU CEs is to set a threshold for reporting CEs to the BMC and the OS, and no processing is done on writing CEs into the MCA register.

[0018] Thus, by setting a relatively large reporting threshold or simply masking the CE reports, generally it will not cause serious or fatal harm to the computer system. However, the processing solutions of related technologies will lead to the accumulation of CEs. Sometimes, a large number of CE accumulations or CE storms will affect the CPU processing process and become uncorrectable errors. After the CPU recognizes them, it will shut down or restart the machine, affecting the operation of the machine. Therefore, too many CPU CEs are very disadvantageous and need to be cleared regularly. In addition, the occurrence of CPU CEs is generally due to information processing timeouts in the CPU's own firmware or hardware, or abnormal CPU contacts. For a sophisticated device like the CPU, minute changes such as internal bus processing timeouts or current jitters in the CPU hardware itself will cause CPU CEs to occur, and such errors can be recovered by the CPU itself, so there is no need for customers to be aware of such errors. However, the instability of the firmware will directly affect the accuracy of the CPU in processing customer services. Seriously, security vulnerabilities may occur, resulting in the loss of customer service data; abnormal CPU contacts will affect the normal use of some registers and also affect the CPU's heat dissipation. In scenarios with high requirements for heat dissipation and service processing accuracy, these CPU CE errors need to be processed as soon as possible. However, users of related technologies are not aware of CPU CE errors, which is not conducive to the normal use of users. Therefore, for different scenarios where CPU CEs occur, users need to be aware of CPU CE errors so as to achieve the effect of not misreporting or missing reports. In addition, for the convenience of the CPU to detect and process CE alarms, when setting the threshold, related technologies do not distinguish between CPUs, memory, and PCIe devices. That is to say, the CPUs of related technologies will aggregate all CE alarms on the current computer system and report them without classifying and identifying the error types. This makes it impossible for server manufacturers to effectively identify the error types, and thus impossible to select CPU CE errors and report them separately. This is very disadvantageous for handling faults.

[0019] In view of this, the present invention aims to solve the problems in the related art that a large amount of CE accumulates and CE storms occur, leading to the risk of the computer system stopping running, and simply shielding the reporting of CPU CE cannot let the customer perceive the current state of the whole machine, resulting in the inability to effectively and timely handle CE errors and affecting the user's business. When the CPU can normally write CPU CE into the MCA register, a target fault tolerance allowable value is set for CPU CE to identify the threshold for reporting to the OS and BMC, that is, the maximum number of correctable errors that can occur within the allowable time period. It is confirmed whether the accumulated number of CPU CE has reached the threshold of the user-requested accumulated number, and the cleaning rules required by the customer are executed according to the performance of the CE number. Based on this technical solution, first, in combination with Figure 1 Some possible application scenarios related to the technical solution of the present invention are introduced by way of example. Figure 1 It is a schematic diagram of the hardware composition framework applicable to a processor error handling method provided by the present invention. This embodiment is an improved implementation scheme for timing and quantifying the cleaning of CPU CE error reports on the AMD (Advanced Micro Devices) platform, that is, an improvement for the current AMD platform, which may include the following content: The hardware composition framework may include a first electronic device 11 and a second electronic device 12, which are connected by a network 13. The first electronic device 11 deploys a processor for executing the processor error handling method described in any one of the above embodiments, and the second electronic device 12 deploys a user terminal for providing a human-computer interaction interface. One of the application scenarios of the embodiments of the present invention can be realized through the interaction between the second electronic device 12 and the user. In this application scenario, when a correctable error occurs in the processor of the first electronic device 11, a setting interface including error parameter configuration options is displayed. The second electronic device 12 inputs a target fault tolerance allowable value, which is transmitted to the first electronic device 11 through the network 13. The first electronic device 11 sets the target fault tolerance allowable value corresponding to the correctable error for the error parameter configuration option. The error register of the processor of the first electronic device 11 will pre-assign a unique identifier to different error types. Whenever an error occurs, the error register determines the corresponding error type identifier according to the error type to which the current error belongs, and stores the currently generated error and its error type identifier. In the execution environment corresponding to the system management mode, during the process of obtaining the multi-device error collection information at the current moment from each error register, according to the error type identifier of the correctable error of the processor, the correctable error of the processor is selected from each error register, and the correctable error of the processor is separately accumulated to the target area of the corresponding error register. The number of times of correctable error generation of the processor within the target time period is determined according to the accumulated data in the target area, as the processor error degree data; according to the processor error degree data and the target fault tolerance allowable value, it is determined whether to generate an error reporting instruction and an error clearing instruction, so as to send the correctable error to the management controller through the error reporting instruction, clear the record data of the correctable error from the target register through the error clearing instruction, and at the same time send the error reporting instruction to the second electronic device 12, so that the user perceives the CPU CE error report.

[0020] It should be noted that the above application scenario is only shown for the convenience of understanding the ideas and principles of the present invention, and the embodiments of the present invention are not limited in this regard. On the contrary, the embodiments of the present invention can be applied to any applicable scenario. After introducing the technical solutions of the present invention, the various non-limiting embodiments of the present invention will be described in detail below with reference to the accompanying drawings and specific embodiments. Please refer to Figure 2 , Figure 2The flowchart shows a method for handling processor errors provided in this embodiment. In this embodiment, an error register that stores multi-device errors in a computer system assigns a unique identifier to different error types. Whenever an error occurs, the error register determines the corresponding error type identifier based on the error type to which the current error belongs, and stores the currently generated error and its error type identifier. In this way, each error register stores the corresponding error type identifier when storing an error. During the processor error handling process, a hardware device that executes the processor error handling method, such as the BIOS, can identify the error type corresponding to each error when obtaining the error. The processor error handling process may include the following:

[0021] S201: When a correctable error occurs in the processor, display a setting interface that includes error parameter configuration options, and set the target fault tolerance allowable value corresponding to the correctable error for the error parameter configuration options.

[0022] In this embodiment, a correctable error refers to a correctable error of the processor. A correctable error occurring in the processor can be a CPU CE of the computer system. Of course, if there are other processors in the computer system that also have CE errors, the processor here also includes the processors in such cases. The setting interface is a page that allows users to perform basic settings on the computer hardware configuration during the startup process of the computer system, such as the setting interface of the BIOS or UEFI (Unified Extensible Firmware Interface). The error parameter configuration options refer to the options for configuring and reporting the CE errors of the processor to the OS and BMC, including the cumulative time threshold and the cumulative quantity threshold. The setting interface will pre-join the error parameter configuration options and set the trigger display condition, which is that a correctable error occurs in the processor. Users can set the target fault tolerance allowable value in advance according to actual needs. The target fault tolerance allowable value is the maximum number of correctable errors that can occur within the allowable time period, and is stored at a specified location. When the setting page displays the error parameter configuration options, the operation of reading the target fault tolerance allowable value is triggered at the same time, and the value setting page is filled according to the read target fault tolerance allowable value. Of course, the target fault tolerance allowable value can also be directly input by the user to the corresponding location after the setting interface that includes the error parameter configuration options, which does not affect the implementation of the present invention.

[0023] S202: In the execution environment corresponding to the system management mode, during the process of obtaining the multi-device error collection information at the current moment from each error register, according to the error type identifier of the correctable error of the processor, select the correctable error of the processor from each error register, and separately accumulate the correctable error of the processor to the target area of the corresponding error register. Determine the number of times of correctable error generation of the processor within the target time period based on the accumulated data in the target area, as the processor error degree data.

[0024] When a CE occurs in the processor, the computer system will call the RAS fault diagnosis driver to handle the processor CE fault. First, it determines whether the computer system supports the PFEH (Platform First Error Handling) function. If this condition is met, by loading the SMM (System Management Mode) software scheduling protocol, it ensures that the system can effectively manage and respond to underlying hardware events. Entering the SMM mode by executing the SMI (System Management Interrupt) handler, that is, entering the execution environment corresponding to the system management mode. In this execution environment, errors occurring in multiple devices of the computer system will be obtained, including all types of errors in multiple devices such as memory, PCIe, and CPU. That is, the multi-device error collection information includes various types of errors occurring in multiple devices of the computer system. Since the present invention is for the handling of processor CE errors, in order to enable users to perceive the processor CE and decouple the reporting of processor CE and memory CE, it is necessary to identify the CE of the processor from the multi-device error collection information and continuously count the number of occurrences of the processor CE. The target time period is the duration of accumulating the processor CE. The processor error degree data can be used to measure whether the correctable error is a small number of processor CEs occurring for a long time or a large number of processor CEs occurring in a short time. The error register is a register for storing errors reported by the computer system, such as the MCA Bank. When storing an error in the error register, it will store the corresponding error type identifier, such as ID. In this embodiment, when obtaining errors from each error register, the obtained are various errors of multiple devices. The devices include but are not limited to the CPU, memory device, and PCIe device. The error types include but are not limited to LS (Load Store, load store error), IF (Instruction Fetch, instruction fetch error), L2 (Level 2 Cache, second-level cache error), DE (Data Error, data error), EX (Execution Unit, execution unit error), FP (Floating Point, floating-point operation error), L3 (Level 3 Cache, third-level cache error), CS (Cache Subsystem, cache subsystem error), PIE (Processor Integrated Error, integrated processor error), UMC (Unified Memory Controller, unified memory controller), PB (Processor Bus, processor bus error).Taking the error register as an example of MCA Bank, MCA Bank assigns a unique ID to each type of error for differentiation. For example, the ID of UMC can be MCA_UMC_ID, and the ID of PCIe can be MCA_PCIE_ID. In this way, the BIOS can identify the error type by polling the IDs of all error types in the MCA Bank register. When the identified error type is a correctable error of the processor, in order to achieve separate reporting of the correctable errors of the processor, a storage area will be pre-set in the error register specifically for storing the correctable errors of the processor. For the convenience of description, it is defined as the target area. Whenever an error is identified as a correctable error of the processor, it will be separately accumulated in the target area. Separate accumulation can only count the correctable errors of the processor, and at the same time set a pointer to directly find the correctable errors of the processor. Separate accumulation can also directly copy the correctable errors of the processor to the target area. In this way, according to the accumulated data in the target area of each error register, the error degree data of the processor can be separately determined so that when its threshold reaches the target fault tolerance allowable value, the CPU CE error information can be reported separately.

[0025] S203: Determine whether to generate an error reporting instruction and an error clearing instruction according to the processor error degree data and the target fault tolerance allowable value.

[0026] Among them, the target fault tolerance allowable value is used to measure the maximum number of correctable errors that can occur within an allowable time period. The processor error degree data can indicate how long the correctable errors that have occurred have lasted. By comparing these two parameters, taking into account not having a large number of CE accumulations or CE storms, and being able to effectively prompt the user that a processor CE has occurred, it is determined whether to generate an error reporting instruction and an error clearing instruction. The error reporting instruction sends the correctable error to the management controller, such as BMC, and can also be sent to the operating system and the user client. The error clearing instruction clears the recorded data of the correctable error from the target register. The target register refers to the register that stores the correctable error, and all or part of the correctable errors stored in the target register can be deleted.

[0027] In the technical solution provided in this embodiment, the error register will identify different error types when storing various errors. In this way, after obtaining all the error reporting information of the computer system at the current moment, it is possible to identify which errors belong to the CE errors of the processor according to the error types. Then, by setting the target fault tolerance allowable value of the CE of the processor on the setting page, the CE errors of the processor can be reported and processed separately in combination with their own unique corresponding target fault tolerance allowable values. This can not only decouple the CE reporting process of the processor from the memory CE reporting process, enabling the customer to effectively perceive whether the reported CE is from the processor or the memory, timely and accurately locate the faulty device, and improve reliability and stability, but also allow the user to customize the target fault tolerance allowable value, which not only improves flexibility but also enables obtaining error reporting data that better conforms to the actual situation of the device. Further, based on the comparison between the processor error degree data and the target fault tolerance allowable value, the user can promptly identify a large number of CPU CE error reports occurring in a short period of time, promptly investigate the cause of the error reports, promptly and effectively clear the CE, effectively reduce the risk of a CE storm, and filter out the phenomenon of a small number of CPU CEs occurring within a long period of time. This not only saves a large amount of investment by the operation and maintenance personnel but also reduces the risk of serious anomalies in the machine.

[0028] In the above embodiment, there is no limitation on how to set the target fault tolerance allowable value corresponding to the correctable error for the error parameter configuration option. Based on the above embodiment, the present invention also provides an exemplary implementation method, which may include the following content:

[0029] In this embodiment, the target fault tolerance allowable value may include a number fault tolerance allowable value and a corresponding duration value. Correspondingly, a setting interface including the error parameter configuration option is displayed; in the error parameter configuration option of the setting interface, the error type is selected as the correctable error, and a setting interface including an error occurrence times option and a corresponding error cumulative time option is displayed; the number fault tolerance allowable value corresponding to the correctable error is set for the error occurrence times option, and the duration value corresponding to the correctable error is set for the error cumulative time option.

[0030] In this embodiment, the CPU CE error reports are cleared regularly and quantitatively through double judgment of the number tolerance allowable value and the corresponding duration value. The computer system uses the number tolerance allowable value set by the BIOS for CPU CE clearing as the cumulative time threshold, which can be represented as CPUCECountThrottle for example. Generally, users choose 2000 as the standard, and this value will be opened as a BIOS option in Setup for customers to modify the cumulative number of CEs. The corresponding duration value can also be set as the cumulative quantity threshold, which can be represented as CPUCETimeThrottle for example. Generally, users choose 24 hours as the standard, and this value will be opened as a BIOS option in Setup for customers to modify the cumulative time. During the computer system process, the computer system can execute an initialization assignment program through the BIOS, thus forming BIOS options with multiple selectable values displayed in Setup. The initialization can be set to 0 or a pre-set value. During this process, according to the requirements of the customer, it can be set how many CPU CEs need to be accumulated within a certain time before the BIOS reports the CE error to the BMC and the OS.

[0031] As can be seen from the above, this embodiment uses double judgment of the time threshold and the number threshold to clear the CPU CE error reports regularly and quantitatively. When a large number of CPU CE error reports occur in the computer system in a short period of time, they can be reported in time within a certain time. After the user perceives it, the cause of the error can be checked in time, effectively reducing the risk of CE storms. In addition, for a small number of CPU CEs that occur within a long period of time, there is no need for the customer to perceive them, realizing selective perception of CPU errors by the user. After filtering out some normal scenarios, the scenarios that need more attention are reported to the user in time, thus saving a large amount of investment of operation and maintenance personnel and reducing the risk of serious anomalies in the computer. Further, the original CPU CE reporting mechanism and the memory CE reporting mechanism are decoupled, and the user can effectively perceive whether the CE error reported by the system is from the CPU or the memory, facilitating the user to locate the error device. Through the dynamic intelligent reporting of CPUCE, users have more choices and higher flexibility.

[0032] Further, for the pre-stored situation, it is also supported to be adjusted according to the application scenario. For example, in the scenario where the heat dissipation requirement and the business processing accuracy requirement are high, the maximum number of times that a correctable error can occur can be adjusted downwards, or the allowed time period can be shortened, or both can be adjusted downwards. Exemplarily, the user can send an error parameter adjustment instruction to the computer. When the error parameter adjustment instruction is detected, a setting interface including the number tolerance allowed value and the corresponding duration value is displayed, and the newly stored new number tolerance allowed value and the corresponding new duration value are read and then automatically filled into the corresponding positions. Of course, when the user issues an error parameter adjustment instruction, the error parameter adjustment instruction carries the new number tolerance allowed value and the corresponding duration value. Correspondingly, the computer system receives the error parameter input instruction input by the user, and through parsing the error parameter input instruction, obtains the new number tolerance allowed value and the corresponding new duration value; according to the new number tolerance allowed value and the new duration value, the local number tolerance allowed value and the corresponding duration value are updated.

[0033] As can be seen from the above, this embodiment supports real-time adjustment of the number tolerance allowed value and the corresponding duration value, matches more application scenarios, and effectively improves the effectiveness of the processor CE error reporting.

[0034] The above embodiments do not make any limitation on how to determine the number of correctable errors generated by the processor within the target time period. Based on the above embodiments, the present invention also gives an exemplary implementation manner, which may include the following contents: The target tolerance allowed value of this embodiment includes the number tolerance allowed value and the corresponding duration value. When the processor has the platform error priority processing function, an error information collection thread is triggered through the callback interface of the system management interrupt; through the error information collection thread, the error type identifiers of the errors in each error register storing the hardware error information are polled; if the error type identifier of the current error is not the error type identifier of the first type of error and is not the error type identifier of the second type of error either, then the current error is marked as an error generated by the processor itself, and the current error is accumulated to the target area of the corresponding error register; the correctable errors of the processor are identified from each target area according to the error type of the correctable errors of the processor, and the number of occurrences of the correctable errors is counted; when the number of occurrences of the correctable errors is greater than or equal to the number tolerance allowed value, the current time is determined through the address of the clock processor, and the current duration is determined according to the current time and the time initial value; the current duration and the total number of occurrences of the correctable errors corresponding to the current moment are used as the processor error degree data at the current moment.

[0035] In this embodiment, when the SMI handler enters the SMM mode, it will determine whether the PFEH function is supported. If not, it will confirm the processor model and the RAS policy used, and end the entire process. If supported, the system can be ensured to effectively manage and respond to underlying hardware events by loading the SMM software scheduling protocol. Then, by calling the software SMI callback interface, the SMI program is triggered to poll the error information in the registers inside all storage hardware error information, such as the CPU Bank (a set of registers for storing hardware error information) registers. The errors polled include all types of errors of devices such as memory, PCIe, and CPU. That is, the multi-device error collection information includes at least the error information of two hardware devices. In the present invention, in order to improve the overall efficiency, improve the efficiency of the error register when storing errors, and improve the efficiency of finding correctable errors of the processor, when the error register allocates error identification information, the errors can be divided into three categories. The first type of error and the second type of error include all error types except the correctable errors of the processor, which is applicable to scenarios with high requirements for the reporting accuracy of the correctable errors of the processor, or all error types except the errors of the processor itself, which is applicable to scenarios where the errors of the processor need to be reported separately, such as the scenario where the CE error of the memory and the CE error of the processor are reported separately. In this way, there is no need to set an error type identifier for the errors of the processor itself. If the error type identifier of the current error is not the error type identifier of the first type of error and is not the error type identifier of the second type of error, the current error is marked as an error generated by the processor itself, and the current error is accumulated to the target area of the corresponding error register. In the first scenario, the errors accumulated here refer to the correctable errors of the processor. For the second scenario, what is accumulated here is all the errors of the processor stored in the error register. If in the second scenario, it is necessary to further identify the CE error of the processor, the error register only needs to set the corresponding error type identification information for the CE error of the processor, and there is no need to allocate, generate, and store the error type identification for other types of errors of the processor. For example, in the error register MCA Bank, a unique ID is assigned to each type of error for distinction. The ID of UMC can be MCA_UMC_ID, and the ID of PCIe can be MCA_PCIE_ID. In this way, the BIOS can identify the stored error types by polling the IDs of all error types in the MCA Bank register. When the detected error information ID is not MCA_UMC_ID and MCA_PCIE_ID, it can be marked as an error generated by the CPU itself, and then it is separately accumulated in the specified area of the target register so that when its threshold reaches the target fault tolerance allowable value, the CPU CE error information can be reported separately.When the total number of occurrences of the processor CE reaches CPUCECountThrottle, the current time is read according to the address of the clock processor to determine the duration accumulated to CPUCECountThrottle. Exemplarily, the initial time can be the timestamp recorded when the computer system is powered on. According to the timestamp corresponding to the power-on operation, the initial value of the time for correctable errors is determined; according to the day parameter and hour parameter corresponding to the current time, the current moment value is determined; according to the day parameter and hour parameter corresponding to the initial time value, the initial moment value is determined; the difference between the current moment value and the initial moment value is used as the current duration value.

[0036] As can be seen from the above, in this embodiment, the judgment of the duration is triggered only after the number of CE times accumulates to the maximum allowable value, which can not only effectively improve the effectiveness of CE error reporting, but also shorten the comparison operation of S203 and improve the overall processor error handling.

[0037] Further, in order to accurately determine the current time, the clock processor of the present invention uses RTC (Real-time Clock). The RTC processor communicates with the computer system through specific I / O ports. Its register addresses are located at 0x70 and 0x71. The register addresses are used to access the control register and data register of the RTC processor. That is, the address of the control register is 0x70 and the data register is 0x71. The address port is 0x70 and the data port is 0x71. The present invention also provides a way to determine the current time, which may include the following content: When receiving the current time acquisition instruction, the BIOS generates an SMI event to access the RTC through the SMM protocol. The RTC processor is accessed through the address port and data port of the I / O port. Based on the control register address, the BIOS writes a specific command byte to the control register of the RTC processor to specify the register address to be read. After sending the read command, the BIOS obtains the time data stored in the RTC processor by reading the data register and converts the read current time data into target format data.

[0038] In this embodiment, the CPU can be switched to the SMM mode by writing to the APM (Advanced Power Management Port) control port, such as 0xB2, or by configuring a register to generate an SMI event. At this time, the CPU saves the current context, jumps to the SMM handler for execution, and the CPU runs the predefined SMM handler code in the SMM memory area. For example, to read the seconds register, the BIOS writes 0x00 to port 0x70. When writing, the highest bit can be set, such as 0x80, to disable NMI (Non-Maskable Interrupt) to ensure atomicity of the operation. Read the register value from port 0x71, such as: minutes register: address 0x02; hours register: address 0x04; day register: address 0x07; month register: address 0x08; year register: address 0x09. The RTC processor will return each part of the current time, such as seconds, minutes, hours, date, month, and year. The time data in the RTC processor is usually stored in BCD (Binary Coded Decimal) format, and the BIOS needs to convert this BCD format data into binary format for further processing. After reading and converting the time data, the BIOS stores this data in memory and passes this time information to the operating system during the system startup process. Then, read the UIP (Update In Progress) bit of status register A (address 0x0A). If UIP = 1, the RTC is updating data and it is necessary to wait for it to complete. After it completes, that is, after the time reading is completed, the BIOS exits the SMM mode and resumes normal system operations, such as exiting the SMM through the RSM instruction, restoring the CPU context, and returning to the original execution flow.

[0039] As can be seen from the above, the BIOS of this embodiment can utilize the SMM protocol and the address of the RTC processor to accurately read the current time and pass it to the computer system, so as to obtain the accurate time interval when the cumulative time reaches the customer's required time threshold. Based on the customer's demand for cleaning the CPU CE regularly and quantitatively, the function of dynamically cleaning the CPU CE by opening the Setup option is realized, which not only reduces the risk of generating a CE storm, but also selectively makes the operation and maintenance personnel aware of the CPU exceptions in time, reducing the ineffective investment of the customer's operation and maintenance personnel.

[0040] To further improve the processor error handling efficiency, after polling the error type identifier of the error in each error register storing hardware error information through the error information collection thread, the obtained error data can also be stored in a specified data structure to facilitate more quickly determining the number of CPU CEs. The following contents can be included: Pre-construct an error storage structure; if the currently queried register is a target register that stores at least correctable errors, update the register parameters; update the processor parameters according to the physical parameter information of the processor to which the target register belongs; update the error information according to the correctable errors stored in the target register. If the register parameters in the error storage structure are not empty, construct a correctable error loop screening thread; use the correctable error loop screening thread to identify correctable errors by querying the error information in the error storage structure and count the occurrence times of correctable errors.

[0041] In this embodiment, the error storage structure can be represented as RAS_MCA_ERROR_INFO for example. The error storage structure at least includes processor parameters, register parameters and error information. The processor parameters can at least include the identification information of the processor where the CE occurs. The register parameters at least include the error type information corresponding to the correctable errors of the processor, such as the error type identifier uniquely corresponding to the error type. Of course, it can also include the corresponding target area, register identifier and the number of registers belonging to the correctable error corresponding to the error type information of the processor. For example, this structure contains the CPU ID (identification number), the number of MCA Bank registers with correctable errors of the processor, and all error information in the MCA Bank registers. The BIOS will judge whether the number of MCA Bank registers in this structure is 0. If it is 0, then the CPU has not detected error information at this time; if it is not 0, the BIOS will use a for loop to screen out the CPU CE error information by judging the value of the MCA register. This value is the data that can identify the correctable errors of the processor, and its number is recorded as CPUCECount. That is, the occurrence times of correctable errors can be represented by CPUCECount.

[0042] The above embodiments do not make any limitations on how to generate error reporting instructions and error clearing instructions. Based on the above embodiments, the present invention also gives an exemplary implementation method, which may include the following content: The target fault tolerance allowable values in this embodiment include the number of times fault tolerance allowable value and the corresponding duration value. When it is determined according to the processor error degree data that the number of correctable errors occurring in the processor is greater than or equal to the duration of the number of times fault tolerance allowable value and within the duration value, an error reporting instruction and an error clearing instruction are generated simultaneously. At this time, the logging function is triggered to record the target correctable errors exceeding the number of times fault tolerance allowable value into the target error file; the target error file is a file that records the error information during the startup process and participates in the statistics of the number of correctable errors in the next round; an error update instruction is generated to enable the management controller to display the target correctable error record in the system log; based on the error clearing instruction, the register clearing function is called to clear the correctable error in the target register. When it is determined according to the processor error degree data that the number of correctable errors occurring in the processor is greater than or equal to the duration of the number of times fault tolerance allowable value and exceeds the duration value, only the error clearing instruction is generated. At this time, based on the error clearing instruction, the register clearing function is called to clear the correctable error in the target register.

[0043] In this embodiment, for example, the initial time can be expressed as T0D * 24 + T0H, the current time can be expressed as T2D * 24 + T2H, and the duration value can be (T2D * 24 + T2H) - (T0D * 24 + T0H). When CPUCECount is greater than or equal to CPUCECountThrottle, calculate whether the time of (T2D * 24 + T2H) - (T0D * 24 + T0H) exceeds CPUCETimeThrottle to confirm whether this CPU CE error needs to be reported. When the value of (T2D * 24 + T2H) - (T0D * 24 + T0H) is less than or equal to CPUCETimeThrottle, calculate the value of CPUCECount – CPUCECountThrottle, which can trigger the logging function to record the CE quantities exceeding the threshold one by one into the BERT table of the operating system (a mechanism for recording and reporting the error information occurring during the system startup process), and simultaneously trigger the SMI to report to the BMC, and then the BMC displays it in the system log of the BMC. Finally, use the register clearing function to subtract the CPU CE errors within the MCA register threshold, and the remaining CPU CE errors enter the next round of accumulation. When the value of (T2D * 24 + T2H) - (T0D * 24 + T0H) is greater than CPUCETimeThrottle, the current number of CPU CE is not sufficient to threaten the normal operation of the CPU, and the register clearing function can be directly called to completely clear the CPU CE errors in the MCA register and start the next round of accumulation.

[0044] To make the technical solution of the present invention clearer to those skilled in the art, the present invention also provides an implementation manner of an example. In this embodiment, the processor CE is the CPU CE, the setting interface is the Setup (setting page) of the BIOS, and the target fault tolerance allowable values may include the number fault tolerance allowable value CPUCECountThrottle and the corresponding duration value CPUCETimeThrottle, as Figure 3 shown, the central processing unit error handling process may include the following: After the CPU CE occurs, the BIOS calls the RAS fault diagnosis driver to perform fault handling for the CPU CE. At this stage, the BIOS executes the program for initializing and assigning values to CPUCETimeThrottle and CPUCECountThrottle, forming BIOS options with multiple selectable values displayed on the Setup. During this process, it is possible to set according to user requirements how many CPU CEs need to accumulate within a certain time before the BIOS reports the CE error to the BMC and the OS.

[0045] The BIOS executes the SMI handler for entering the SMM mode: determines whether the CPU supports the PFEH function. If it does not support, the CPU model and the corresponding RAS policy are recorded, and then the entire process ends. If it supports, the BIOS loads the SMM software scheduling protocol to manage and respond to underlying hardware events, triggers the SMI program to poll the error information inside all CPU Bank registers by calling the software SMI callback interface. After all the errors are polled, the BIOS creates RAS_MCA_ERROR_INFO that stores all the error information in the MCA register. This structure contains CPU information, the number of MCA Bank registers with error information, and all the error information in the MCA Bank registers. The BIOS determines whether the number of MCA Bank registers in RAS_MCA_ERROR_INFO is 0. If it is 0, then at this time the CPU has not detected error information; if it is not 0, the BIOS uses a for loop to screen out the CPU CE error information by judging the value of the MCA status register, and records the CPU CE count through CPUCECount.

[0046] When the computer system is just powered on, the BIOS records the timestamp including day, hour, minute, and second based on the power-on action as the initial time, which can be expressed as T0D, T0H, T0M, and T0S. When the CPUCECount collected by the BIOS is greater than or equal to CPUCECountThrottle, the BIOS obtains the current time according to the address of the RTC clock processor, which can be expressed as T2D, T2H, T2M, and T2S. The BIOS calculates whether the time of (T2D * 24 + T2H) - (T0D * 24 + T0H) exceeds CPUCETimeThrottle. When the value of (T2D * 24 + T2H) - (T0D * 24 + T0H) is less than or equal to CPUCETimeThrottle, calculate the value of CPUCECount – CPUCECountThrottle, which can trigger the logging function to record the exceeded CE count item by item into the BERT table of the operating system, and at the same time trigger the SMI to report to the BMC, and then the BMC displays it in the system log of the BMC. Finally, the BIOS uses the register clearing function to subtract the CPU CE errors within the MCA register threshold, and the remaining CPU CE errors enter the next round of accumulation. When the value of (T2D * 24 + T2H) - (T0D * 24 + T0H) is greater than CPUCETimeThrottle, the current CPU CE count is not sufficient to threaten the normal operation of the CPU, and the register clearing function can be directly called to completely clear the CPUCE errors in the MCA register and start the next round of accumulation. At the same time, the BIOS assigns T2D, T2H, T2M, and T2S to T0D, T0H, T0M, and T0S to start a new cycle count.

[0047] As can be seen from the above, this embodiment can effectively reduce the probability of the occurrence of the CPU CE storm, and users can perceive the CE error type, which is beneficial to improving the accuracy and efficiency of fault identification and enhancing the stability and reliability of the server.

[0048] Through the description of the above implementation manners, those skilled in the art can clearly understand that the method according to the above embodiments can be implemented by means of software plus a necessary general hardware platform. Of course, it can also be implemented by hardware, but in many cases, the former is a better implementation manner. The present invention also provides a corresponding device for the processor error handling method, which further makes the method more practical. Among them, the device can be described from the perspective of functional modules and the perspective of hardware respectively. The following introduces the language task processing device provided by the present invention, which is used to implement the processor error handling method provided by the present invention. The description of the features in the corresponding embodiments of the language task processing device can refer to the relevant descriptions of the corresponding embodiments of the processor error handling method, and the device embodiments will not be repeated one by one.

[0049] From the perspective of functional modules, please refer to Figure 4 , Figure 4 which is a structural diagram of the processor error handling device provided in this embodiment in an exemplary implementation manner. The device may include: A parameter configuration module 401, configured to, when a correctable error occurs in the processor, display a setting interface including error parameter configuration options, and set a target fault tolerance allowable value corresponding to the correctable error for the error parameter configuration options; the target fault tolerance allowable value is the maximum number of correctable errors that can occur within an allowable time period.

[0050] An error level determination module 402, configured to, in an execution environment corresponding to the system management mode, during the process of obtaining multi-device error collection information at the current moment from each error register, select the correctable error of the processor from each error register according to the error type identifier of the correctable error of the processor, and separately accumulate the correctable error of the processor to a target area of the corresponding error register, and determine the number of times of correctable error generation of the processor within a target time period based on the accumulated data in the target area as the processor error level data. Among them, the error register will pre-assign a unique identifier to different error types. Whenever an error occurs, the error register determines the corresponding error type identifier according to the error type to which the current error belongs, and stores the currently generated error and its error type identifier.

[0051] An instruction generation module 403, configured to determine whether to generate an error reporting instruction and an error clearing instruction according to the processor error level data and the target fault tolerance allowable value, so as to send the correctable error to the management controller through the error reporting instruction, and clear the record data of the correctable error from the target register through the error clearing instruction.

[0052] Exemplarily, in some embodiments of the present embodiment, the above error degree determination module 402 may further be configured to: The target fault tolerance allowable value includes a number fault tolerance allowable value and a corresponding duration value. When the processor has a platform error priority handling function, trigger an error information collection thread through the callback interface of the system management interrupt; through the error information collection thread, poll the error type identifiers of the errors in each error register storing hardware error information. If the error type identifier of the current error is not the error type identifier of the first type of error and is also not the error type identifier of the second type of error, then mark the current error as an error generated by the processor itself and accumulate the current error to the target area of the corresponding error register; identify the correctable errors of the processor from each target area according to the error types of the correctable errors of the processor, and count the occurrence times of the correctable errors; when the occurrence times of the correctable errors are greater than or equal to the number fault tolerance allowable value, determine the current time through the address of the clock processor, and determine the current duration according to the current time and the time initial value; use the current duration and the total number of occurrences of the correctable errors corresponding to the current moment as the processor error degree data at the current moment.

[0053] As an exemplary implementation manner of the above embodiment, the above error degree determination module 402 may be configured to: determine the time initial value of the correctable error according to the time stamp corresponding to the power-on operation; determine the current moment value according to the day parameter and hour parameter corresponding to the current time; determine the initial moment value according to the day parameter and hour parameter corresponding to the time initial value; use the difference between the current moment value and the initial moment value as the current duration value.

[0054] Exemplarily, in some embodiments of the present embodiment, the above device may further include a data storage module, and this module may be configured to: pre-construct an error storage structure; the error storage structure at least includes processor parameters, register parameters, and error information; the register parameters at least include the error type information corresponding to the correctable errors of the processor; if the currently queried register is a target register that stores at least the correctable errors of the processor, then update the register parameters; update the processor parameters according to the physical parameter information of the processor to which the target register belongs; update the error information according to the correctable errors stored in the target register.

[0055] As an exemplary implementation manner of the above embodiment, the above error degree determination module 402 may further be configured to: if the register parameters in the error storage structure are not empty, then construct a correctable error loop screening thread; use the correctable error loop screening thread to identify the correctable errors by querying the error information in the error storage structure, and count the occurrence times of the correctable errors.

[0056] Exemplarily, in some other embodiments of this embodiment, the above instruction generation module 403 may further be configured to: The target fault tolerance allowable value includes a number of times fault tolerance allowable value and a corresponding duration value. When it is determined according to the processor error degree data that the number of correctable errors occurring in the processor is greater than or equal to the duration of the number of times fault tolerance allowable value within the duration value, an error reporting instruction and an error clearing instruction are generated simultaneously. When it is determined according to the processor error degree data that the number of correctable errors occurring in the processor is greater than or equal to the duration of the number of times fault tolerance allowable value and exceeds the duration value, only an error clearing instruction is generated.

[0057] As an exemplary implementation manner of the above embodiment, the above instruction generation module 403 may be configured to: When an error reporting instruction and an error clearing instruction are generated simultaneously, trigger a log recording function to record the target correctable error exceeding the number of times fault tolerance allowable value into a target error file; the target error file is a file for recording error information during the startup process and participates in the statistics of the number of correctable errors in the next round; generate an error update instruction to enable the management controller to display the target correctable error record in the system log; based on the error clearing instruction, call a register clearing function to clear the correctable error in the target register. When only an error clearing instruction is generated, based on the error clearing instruction, call a register clearing function to clear the correctable error in the target register.

[0058] Exemplarily, in some other embodiments of this embodiment, the above parameter configuration module 401 may further be configured to: When an error parameter adjustment instruction is detected, display a setting interface including the number of times fault tolerance allowable value and the corresponding duration value; receive a user input error parameter input instruction, and obtain a new number of times fault tolerance allowable value and a corresponding new duration value by parsing the error parameter input instruction; update the local number of times fault tolerance allowable value and the corresponding duration value according to the new number of times fault tolerance allowable value and the new duration value.

[0059] Exemplarily, in some other embodiments of this embodiment, the above parameter configuration module 401 may further be configured to: The target fault tolerance allowable value includes a number of times fault tolerance allowable value and a corresponding duration value, display a setting interface including error parameter configuration options; select the error type as a correctable error in the error parameter configuration options of the setting interface, and display a setting interface including an option for the number of error occurrences and an option for the corresponding error accumulation time; set the number of times fault tolerance allowable value corresponding to the correctable error for the option of the number of error occurrences, and set the duration value corresponding to the correctable error for the option of the error accumulation time.

[0060] The processor error handling device mentioned above is described from the perspective of functional modules. Further, the present invention also provides an electronic device, which is described from the perspective of hardware. The electronic device includes a memory and a processor. A computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any of the above-described embodiments of the processor error handling method.

[0061] An embodiment of the present application also provides a computer-readable storage medium, in which a computer program is stored. The computer program is configured to execute the steps in any of the above-described embodiments of the processor error handling method when running.

[0062] In an exemplary embodiment, the above computer-readable storage medium may include, but is not limited to: various media such as USB flash drives, read-only memories (ROMs), random access memories (RAMs), external hard drives, magnetic disks, or optical discs that can store computer programs.

[0063] An embodiment of the present application also provides a computer program product. The computer program product includes a computer program, and when the computer program is executed by a processor, it implements the steps in any of the above-described embodiments of the processor error handling method.

[0064] An embodiment of the present application also provides another computer program product, including a non-volatile computer-readable storage medium. The non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, it implements the steps in any of the above-described embodiments of the processor error handling method.

[0065] Finally, the present invention also provides a server, as Figure 5 shown, the server may include a basic input / output system 501, a central processing unit 502, and a baseboard management controller 503.

[0066] Among them, the central processing unit 502 includes cores, caches, and registers. It usually contains multiple cores, each of which can execute instructions independently; the cache can be divided into different levels such as L1, L2, and L3, which are used to store recently or most frequently used data to speed up access; the registers are high-speed storage units inside the CPU, which are used to temporarily store the data required during the execution of instructions. At least one register stores the error information of the hardware device, such as the MAC register. The central processing unit 502 performs arithmetic and logical operations, controls the data flow, and processes input / output operations by executing the instruction set in the computer program. The instruction cycle includes three basic stages: instruction fetching, decoding, and execution; the pipeline improves efficiency by decomposing instructions into several small steps and simultaneously processing different parts of multiple instructions; hyper-threading allows a physical core to simulate two logical cores, thereby improving the concurrent processing ability. The performance indicators of the CPU include: the clock frequency (Clock Speed), which measures how many clock cycles the CPU can complete per second, and the unit is usually GHz; IPC (Instructions Per Cycle): the number of instructions that can be executed within each clock cycle; the number of cores and threads: more cores and threads mean stronger parallel processing ability; TDP (Thermal Design Power, power consumption): represents the maximum thermal design power of the CPU, which affects the heat dissipation design and power supply requirements. The maintenance and optimization of the CPU include: the need for heat dissipation management to ensure good heat dissipation conditions and avoid frequency reduction or even damage caused by overheating; keep the operating system and related driver programs up-to-date through driver updates to obtain the best compatibility and performance. By reasonably configuring the BIOS options, such as adjusting parameters such as the working frequency and voltage of the CPU, the performance can be improved or energy can be saved to a certain extent.

[0067] In this embodiment, the basic input / output system 501 includes a setup interface, which is used to implement the steps in any one of the above-mentioned processor error handling method embodiments when executing a computer program. When the CPU can normally write the CPU CE into the MCA register, the BIOS 501 sets two Setup options on the Setup page for the CPU CE to identify the cumulative time threshold and the cumulative quantity threshold for reporting to the OS and the BMC 503. The BIOS obtains the time interval when the cumulative time reaches the customer-requested time threshold by means of the RTC clock processor according to the SMM-related protocol. When the number of CPU CEs accumulated in the MCA register reaches the fault tolerance allowable value of the customer-requested number of times, a time judgment is triggered. When the duration is less than the fault tolerance allowable value of the number of times and the corresponding duration value, an error reporting instruction and an error clearing instruction are generated, and the generated error reporting instruction is sent to the baseboard management controller 503, and the data in the MAC register is cleared through the error clearing instruction.

[0068] The above has introduced in detail a processor error handling method, an electronic device, a computer-readable storage medium, and a computer program product provided by the present invention. Each embodiment in this specification is described in a progressive manner, and the key point of each embodiment is the difference from other embodiments. For the same or similar parts among the embodiments, reference can be made to each other. Whether the units and algorithm steps of each example described in the disclosed embodiments are executed in the form of electronic hardware or computer software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods for each specific application to implement the described functions, and such implementation should not be considered to exceed the scope of the present invention. Without departing from the principle of the present invention, several improvements and modifications can be made to the present invention, and these improvements and modifications also fall within the protection scope of the present invention.

Claims

1. A processor error handling method, characterized in that: include: The error register assigns unique identifiers to different error types in advance. Whenever an error occurs, the error register determines the corresponding error type identifier according to the error type to which the current error belongs, and stores the current error and its error type identifier; When a correctable error occurs in the processor, a setting interface including an error parameter configuration option is displayed, and a target fault tolerance allowable value corresponding to the correctable error of the processor is set for the error parameter configuration option; The target fault tolerance allowable value is the maximum number of correctable errors of the processor that occur within the allowed time period; In an execution environment corresponding to the system management mode, in a process of obtaining multi-device error collection information at the current moment from each error register, a correctable error of the processor is selected from each error register according to an error type identifier of the correctable error of the processor, and the correctable errors of the processor are separately accumulated to a target area of ​​the corresponding error register, and the number of correctable errors generated by the processor within a target time period is determined according to the accumulated data of the target area as the processor error degree data; According to the processor error degree data and the target fault tolerance allowable value, determine whether to generate an error reporting instruction and an error clearing instruction, so as to send the correctable error to the management controller through the error reporting instruction and clear the record data of the correctable error from the target register through the error clearing instruction.

2. The processor error handling method according to claim 1, characterized in that: The target fault tolerance allowable value includes a number of fault tolerance allowable values ​​and a corresponding duration value, and determining the number of correctable errors generated by the processor within a target time period according to the accumulated data of the target area. Determining the number of correctable errors generated by the processor within a target time period includes: When the processor has a platform error priority processing function, an error information collection thread is triggered through a callback interface of a system management interrupt; Polling, through the error information collection thread, error type identifiers of errors in the error registers storing hardware error information; If the error type identifier of the current error is neither the error type identifier of the first type of error nor the error type identifier of the second type of error, marking the current error as an error generated by the processor itself, and accumulating the current error to a target area of ​​a corresponding error register; identifying the correctable errors of the processor from each target area according to the error type of the correctable errors of the processor, and counting the number of occurrences of the correctable errors; When the number of occurrences of the correctable errors is greater than or equal to the number tolerance allowable value, the current time is determined by the address of the clock processor, and the current duration is determined according to the current time and the initial time value; The current duration and the total number of correctable errors corresponding to the current moment are used as the processor error degree data at the current moment.

3. The processor error handling method according to claim 2, characterized in that: Determining the current duration according to the current time and the initial time value includes: Determining an initial time value of the correctable error according to a timestamp corresponding to the power-on action; Determine the current time value according to the day parameter and the hour parameter corresponding to the current time; Determine the initial time value according to the day parameter and the hour parameter corresponding to the initial time value; The difference between the current time value and the initial time value is used as the current duration value.

4. The processor error handling method according to claim 1, characterized in that: After polling the error type identifiers of the errors in the error registers storing the hardware error information through the error information collection thread to obtain the multi-device error collection information, the method further includes: Pre-constructing an error storage structure; the error storage structure at least includes processor parameters, register parameters and error information; the register parameters at least include error type information corresponding to the correctable errors of the processor; If the register currently being queried is a target register storing at least a correctable error of the processor, updating the register parameter; The processor parameters are updated according to the physical parameter information of the processor to which the target register belongs; and the error information is updated according to the correctable error stored in the target register.

5. The processor error handling method according to claim 4, characterized in that: Determining the number of correctable errors generated by the processor within a target time period according to the accumulated data of the target area includes: If the register parameter in the error storage structure is not empty, constructing a correctable error loop screening thread; The correctable error loop screening thread is utilized to identify the correctable error by querying the error information in the error storage structure, and the number of occurrences of the correctable error is counted.

6. The processor error handling method according to claim 1, characterized in that: The target fault tolerance allowable value includes a number of fault tolerance allowable values ​​and a corresponding duration value, and determining whether to generate an error reporting instruction and an error clearing instruction according to the processor error degree data and the target fault tolerance allowable value includes: When it is determined based on the processor error degree data that the number of times the processor has the correctable errors is greater than or equal to the duration of the fault tolerance allowable value and is within the duration value, an error reporting instruction and an error clearing instruction are simultaneously generated.

7. The processor error handling method according to claim 6, characterized in that: After generating the error clear instruction, it also includes: Triggering the logging function to record the target correctable errors exceeding the fault tolerance allowable value into the target error file; the target error file is a file that records the error information during the startup process and participates in the statistics of the number of correctable errors in the next round; generating an error update instruction so that the management controller displays the target correctable error record in a system log; Based on the error clearing instruction, a register clearing function is called to clear the correctable error in the target register.

8. The processor error handling method according to claim 1, characterized in that: The target fault tolerance allowable value includes a number of fault tolerance allowable values ​​and a corresponding duration value, and determining whether to generate an error reporting instruction and an error clearing instruction according to the processor error degree data and the target fault tolerance allowable value includes: When it is determined based on the processor error degree data that the number of times the processor has the correctable errors is greater than or equal to the duration of the fault tolerance allowable value, and exceeds the duration value, only an error clearing instruction is generated.

9. The processor error handling method according to claim 8, characterized in that: Only after the error clearing instruction is generated, it also includes: Based on the error clearing instruction, a register clearing function is called to clear the correctable error in the target register.

10. The processor error handling method according to claim 1, characterized in that: Before setting the target fault tolerance allowable value corresponding to the correctable error for the error parameter configuration option, the method further includes: When an error parameter adjustment instruction is detected, a setting interface including a number of error tolerance allowable values ​​and a corresponding duration value is displayed; Receiving an error parameter input instruction input by a user, and obtaining a new number of fault tolerance allowable values ​​and a corresponding new duration value by parsing the error parameter input instruction; According to the new number of fault tolerance allowable values ​​and the new duration value, the local number of fault tolerance allowable values ​​and the corresponding duration value are updated.

11. The processor error handling method according to any one of claims 1 to 10, characterized in that: The target fault tolerance allowable value includes a number of fault tolerance allowable values ​​and a corresponding duration value, displaying a setting interface including an error parameter configuration option, and setting a target fault tolerance allowable value corresponding to the correctable error for the error parameter configuration option, including: Displays the settings interface with incorrect parameter configuration options; In the error parameter configuration option of the setting interface, the error type is selected as the correctable error, and a setting interface including an error occurrence count option and a corresponding error accumulation time option is displayed; The error occurrence number option is set with a fault tolerance allowable value for the number of correctable errors, and the error accumulation time option is set with a duration value for the correctable errors.

12. An electronic device, characterized in that: include: Memory for storing computer programs; A processor, configured to implement the steps of the processor error handling method according to any one of claims 1 to 11 when executing the computer program.

13. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the processor error handling method according to any one of claims 1 to 11 are implemented.

14. A computer program product comprising a computer program / instructions, characterized in that When the computer program / instruction is executed by a processor, the steps of the processor error handling method according to any one of claims 1 to 11 are implemented.

15. A server, characterized in that: Includes basic input and output system, central processing unit and baseboard management controller; Wherein, the central processing unit includes at least one register for storing hardware error information, and the basic input and output system includes a setting interface for implementing the steps of the processor error handling method as described in any one of claims 1 to 11 when executing a computer program, and sending the generated error reporting instruction to the baseboard management controller.

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