A memory and firmware optimization method thereof

Abstract

The present invention provides a memory and a method for optimizing its firmware. The memory includes: at least one flash memory control unit, on which at least one flash memory unit is configured; an interface flash memory unit for storing firmware to be tested; a trigger control unit for generating corresponding test instructions according to preset test items; a main control unit for modifying data in the firmware to be tested according to the test instructions, and controlling the flash memory unit to perform corresponding operations according to the test instructions and the firmware to be tested after the modified data; the main control unit is further used to identify operation information of the flash memory unit when performing an operation, and optimize the firmware to be tested according to the operation information to obtain an optimized firmware; and a read-only storage unit for storing the optimized firmware. The memory and the method for optimizing its firmware provided by the present invention can perform test optimization on the firmware.

Description

Technical Field

[0001] The present invention relates to the field of storage, and in particular to a memory and a firmware optimization method thereof. Background Art

[0002] With the widespread adoption of memory in consumer electronics devices such as smart TVs, set-top boxes, and mobile devices, memory must strike a balance between data reliability, stability, and operational efficiency. Memory utilizes a collaborative architecture combining an ARM architecture controller and NAND flash memory, with core functions such as bad block management, garbage collection, and performance optimization implemented through firmware. Its highly integrated nature creates a complex system environment with multiple modules operating in parallel.

[0003] Traditional white-box testing uses limited testing conditions, making it difficult to simulate real-world scenarios involving multiple modules concurrently, unusual attacks, and the varying characteristics of different flash memories. This results in insufficient firmware verification of core functions like bad block management and garbage collection. Therefore, optimizing memory firmware testing is a pressing technical challenge. Summary of the Invention

[0004] The purpose of the present invention is to provide a memory and a firmware optimization method thereof, which can perform test optimization on the firmware.

[0005] To solve the above technical problems, the present invention is achieved through the following technical solutions:

[0006] The present invention provides a memory, comprising:

[0007] at least one flash memory control unit, on which at least one flash memory unit is configured;

[0008] An interface flash memory unit for storing the firmware to be tested;

[0009] A trigger control unit is used to generate corresponding test instructions according to preset test items;

[0010] a main control unit, configured to modify data in the firmware to be tested according to the test instruction, and control the flash memory unit to perform corresponding operations according to the test instruction and the firmware to be tested after the modified data; the main control unit is further configured to identify operation information of the flash memory unit when performing the operation, and optimize the firmware to be tested according to the operation information to obtain optimized firmware;

[0011] A read-only storage unit is used to store the optimized firmware.

[0012] In one embodiment of the present invention, the test instruction includes a reset instruction; the main control unit optimizes the firmware to be tested according to the following steps:

[0013] Setting different reset durations according to the reset instruction;

[0014] At each reset time, a reset operation is performed on the flash memory control unit, and it is determined whether the logic unit in the flash memory unit responds normally:

[0015] When all logic units can respond normally, the reset duration is retained;

[0016] Otherwise, the reset duration is eliminated;

[0017] Sort the reserved reset durations and obtain the minimum reset duration, which is expressed as the target reset time;

[0018] The reset time of the firmware configuration table of the firmware to be tested is updated according to the target reset time to obtain optimized firmware.

[0019] In one embodiment of the present invention, the test instruction includes an identity recognition instruction; the main control unit optimizes the firmware to be tested according to the following steps:

[0020] Modify the identity information of at least one logical unit in the identity configuration table of the firmware to be tested according to the identity identification instruction;

[0021] After the flash memory control unit performs a reset operation, identifying identity information of each of the logic units;

[0022] Determine whether each changed identity information matches the corresponding identified identity information:

[0023] When there is at least one changed identity information that matches the corresponding identified identity information, a reset operation is performed on the flash memory control unit, the identity configuration table is restored, and the identity verification mechanism in the firmware to be tested is optimized to obtain the optimized firmware.

[0024] In one embodiment of the present invention, the test instruction includes a bad block identification instruction; the main control unit optimizes the firmware to be tested according to the following steps:

[0025] Modify bad block information of at least one physical block in at least one logical unit in the bad block table of the firmware to be tested according to the bad block identification instruction;

[0026] After the flash memory control unit performs a reset operation, identifying bad block information of each physical block in each logical unit in each of the flash memory units;

[0027] Determine whether each modified bad block information matches the corresponding identified bad block information:

[0028] When there is at least one modified bad block information that matches the corresponding identified bad block information, a reset operation is performed on the flash memory control unit, the bad block table is restored, and the bad block check mechanism in the firmware to be tested is optimized to obtain the optimized firmware.

[0029] In one embodiment of the present invention, the test instruction includes a phase adjustment instruction; the main control unit optimizes the firmware to be tested according to the following steps:

[0030] adjusting the phases of the data strobe signal and the data bus signal of the flash memory control unit according to the phase adjustment instruction;

[0031] After the flash memory control unit performs a reset operation, adjusting a communication protocol of the flash memory control unit;

[0032] Under each of the communication protocols, determining whether the flash memory control unit switches normally between the high-speed mode and the low-speed mode:

[0033] When the flash memory control unit cannot switch normally between high-speed mode and low-speed mode under at least one communication protocol, a reset operation is performed on the flash memory control unit to restore the data selection signal and the data bus signal, and the memory training mechanism in the firmware to be tested is optimized to obtain the optimized firmware.

[0034] In one embodiment of the present invention, the test instruction includes an error correction algorithm adjustment instruction; the main control unit optimizes the firmware to be tested according to the following steps:

[0035] adjusting the error correction algorithm of the memory according to the error correction algorithm adjustment instruction, and changing the number of error bits of at least one physical block in at least one logical unit in the flash memory unit in the error statistics table of the firmware to be tested;

[0036] After the flash memory control unit performs a reset operation, identifying the number of error bits of each physical block in each of the logical units;

[0037] Determine whether the number of each modified error bit matches the corresponding number of identified error bits:

[0038] When there is at least one changed error bit number that matches the corresponding identified error bit number, a reset operation is performed on the flash memory control unit, the error correction algorithm and the error statistics table are restored, and the error correction mechanism in the firmware to be tested is optimized to obtain an optimized firmware.

[0039] In one embodiment of the present invention, when multiple flash memory units are configured on the same flash memory control unit, the flash memory units include the same number of logic units; the test instruction includes a mapping test instruction; and the main control unit optimizes the firmware to be tested according to the following steps:

[0040] Modify mapping data of at least one flash memory unit and its logic unit in a data mapping table of the firmware to be tested according to the mapping test instruction;

[0041] After the flash memory control unit performs a reset operation, mapping data of the logic unit in the data mapping table is read so that the logic unit performs a wear leveling operation and a garbage collection operation;

[0042] Determine whether the logical unit whose mapping data is changed performs wear leveling and garbage collection operations normally:

[0043] When there is at least one logic unit whose mapping data is changed and cannot perform wear leveling operations and / or garbage collection operations, the mapping data in the data mapping table is restored, and the wear leveling mechanism and garbage collection mechanism in the firmware to be tested are optimized to obtain optimized firmware.

[0044] In one embodiment of the present invention, the memory further includes a voltage adjustment unit, the voltage adjustment unit being configured to provide core power supplies of different voltages; the test instructions include voltage adjustment instructions; and the main control unit optimizes the firmware to be tested according to the following steps:

[0045] The voltage adjustment unit provides core power supply with different voltages according to the voltage adjustment instruction;

[0046] After the flash memory control unit performs a reset operation, reading data of the logic unit under each of the core power supplies;

[0047] Determine whether the flash memory control unit reads the data of the logic unit normally:

[0048] When the data of the logic unit cannot be read, adjusting the core power supply of the logic unit until the data of the logic unit can be read normally, and recording the voltage of the core power supply of the logic unit;

[0049] When the data of the logic unit is read normally, recording the voltage of the core power supply of the logic unit;

[0050] The corresponding voltage table is updated according to the recorded voltage of the core power supply of each logic unit to obtain optimized firmware.

[0051] In one embodiment of the present invention, the memory further includes a timeout test instruction; and the main control unit optimizes the firmware to be tested according to the following steps:

[0052] Modify the read and write timeout information of at least one physical block in at least one logical unit in the bad block table of the firmware to be tested according to the timeout test instruction;

[0053] After the flash memory control unit performs a reset operation, performing a random read and write operation on the physical block;

[0054] Determine whether the physical block with the changed read / write timeout information can perform random read / write operations normally:

[0055] When the physical block whose read / write timeout information has been changed cannot perform random read / write operations, a reset operation is performed on the flash memory control unit to restore the bad block table, and the read / write timeout mechanism in the firmware to be tested is optimized to obtain the optimized firmware.

[0056] The present invention also discloses a firmware optimization method for a memory, wherein the memory includes at least one flash memory control unit, and the flash memory control unit is configured with at least one flash memory unit; the firmware optimization method includes:

[0057] storing the firmware to be tested via the interface flash memory unit;

[0058] The trigger control unit generates corresponding test instructions according to the preset test items;

[0059] The main control unit modifies the data in the firmware to be tested according to the test instruction, and controls the flash memory unit to perform corresponding operations according to the test instruction and the firmware to be tested after the modified data;

[0060] identifying, by the main control unit, operation information of the flash memory unit when performing an operation, and optimizing the firmware to be tested according to the operation information to obtain an optimized firmware;

[0061] The optimized firmware is stored in a read-only storage unit.

[0062] As described above, the present invention provides a memory and firmware optimization method. Through a systematic firmware testing approach (including error correction algorithms, mapping management, voltage regulation, and timeout testing), this method significantly improves firmware processing capabilities, addressing issues such as insufficient coverage and poor compatibility associated with traditional testing. By dynamically simulating abnormal scenarios (such as voltage fluctuations, mapping errors, and timeout failures), it comprehensively identifies potential risks in the firmware processing flow and optimizes firmware stability and adaptability.

[0063] Of course, any product implementing the present invention does not necessarily need to achieve all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0065] Figure 1 is a schematic diagram of a memory according to an embodiment of the present invention;

[0066] Figure 2 Flowchart of a memory firmware optimization method according to an embodiment of the present invention.

[0067] In the figure: 10, main control unit; 20, flash memory control unit; 30, flash memory unit; 31, logic unit; 40, power supply unit; 50, voltage adjustment unit; 60, trigger control unit; 70, read-only memory unit; 80, random access memory unit; 90, interface flash memory unit; 100, first interface unit; 110, second interface unit. DETAILED DESCRIPTION

[0068] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0069] See also Figure 1 The present application discloses a memory, which may be an embedded MultiMediaCard (eMMC) or a universal flash storage (UFS). The memory may communicate with an electronic device via a CMD line and DATA0~7 lines, and receive instructions from the electronic device to perform operations such as reading, writing, and erasing. The electronic device may send instructions via the CMD line and transmit data via the DATA0~7 lines. The communication protocol between the memory and the electronic device may follow the JEDEC protocol. The memory may include a main control unit 10, a flash memory control unit 20, a flash memory unit 30, a power supply unit 40, a voltage adjustment unit 50, a trigger control unit 60, a read-only memory unit 70, a random access memory unit 80, an interface flash memory unit 90, a first interface unit 100, and a second interface unit 110.

[0070] In some embodiments, the main control unit 10 may be a microcontroller unit (MCU). The main control unit 10 may be used to perform specific control tasks, such as reading data and processing instructions from electronic devices. The CPU core of the main control unit 10 may be designed based on the RISC-V architecture to perform various control and computing tasks.

[0071] In some embodiments, there can be at least one flash memory control unit 20 (FPGA NAND Flash Controller). The flash memory control unit 20 can manage the operations of the flash memory unit 30 and support multiple models of flash memory units 30. The flash memory control unit 20 can have four independent channels, each of which can connect to a flash memory unit 30. A channel refers to the data transmission channel between the flash memory control unit 20 and the flash memory unit 30. Each channel can operate independently, thereby improving data transmission parallelism and efficiency.

[0072] In some embodiments, the flash memory unit 30 refers to a packaged NAND flash memory. Packaging involves encapsulating the logic unit 31 (DIE) and other necessary components (such as pins and heat sinks) together to form a complete, ready-to-use flash memory unit 30. A flash memory unit 30 may contain at least one logic unit 31 (DIE), and may include, for example, one, two, or four logic units 31. The DIE is the core component of the flash memory unit 30 and serves as the actual storage medium. The DIE may consist of a large number of physical blocks. Each DIE can operate independently, performing operations such as read, write, and erase. In a flash memory unit 30, one or more logic units 31 (DIEs) share a set of data signals. Multiple DIEs communicate with the outside world through the same set of data pins, reducing the number of pins required for packaging, lowering cost and complexity.

[0073] In some embodiments, for different memories, the number of flash memory control units 20 therein may be different, and the number of flash memory units 30 configured on each flash memory control unit 20 may also be different. However, in the same flash memory control unit 20, when multiple flash memory units 30 are configured thereon, the number of logic units 31 included in the flash memory unit 30 needs to be the same.

[0074] In some embodiments, when testing and optimizing the firmware of the memory, it is necessary to combine and arrange different numbers of flash memory units 30 and different numbers of logic units 31 to obtain multiple test modes, and in each test mode, test and optimize the firmware of the memory to verify the compatibility of the firmware. For example, the four channels of the flash memory control unit 20 can be represented as Channel 0~3, the four logic units 31 of the first flash memory unit 30 can be represented as DIE 00~03, the four logic units 31 of the second flash memory unit 30 can be represented as DIE 10~13, the four logic units 31 of the third flash memory unit 30 can be represented as DIE 20~23, and the four logic units 31 of the fourth flash memory unit 30 can be represented as DIE 30~33, where DIE ab can be represented as the b+1th logic unit of the a+1th channel. At this time, by combining and arranging different numbers of flash memory units 30 and different numbers of logic units 31, the following multiple test modes can be obtained:

[0075] First test mode (Mode 1): Channel 0 is connected to DIE 00, Channel 1 is connected to DIE 10, Channel 2 is connected to DIE 20, and Channel 3 is connected to DIE 30.

[0076] Second test mode (Mode 2): Channel 0 is connected to DIE 01, Channel 1 is connected to DIE 11, Channel 2 is connected to DIE 21, and Channel 3 is connected to DIE 31.

[0077] The third test mode (Mode 3): Channel 0 is connected to DIE 02, Channel 1 is connected to DIE 12, Channel 2 is connected to DIE 22, and Channel 3 is connected to DIE 32.

[0078] Mode 4: Channel 0 is connected to DIE 03, Channel 1 is connected to DIE 13, Channel 2 is connected to DIE 23, and Channel 3 is connected to DIE 33.

[0079] Fifth test mode (Mode 5): Channel 0 is connected to DIE 01 and DIE 03, Channel 1 is connected to DIE 11 and DIE 13, Channel 2 is connected to DIE 21 and DIE 23, and Channel 3 is connected to DIE 31 and DIE33.

[0080] Mode 6: Channel 0 is connected to DIE 00 and DIE 01, Channel 1 is connected to DIE 10 and DIE 11, Channel 2 is connected to DIE 20 and DIE 21, and Channel 3 is connected to DIE 30 and DIE31.

[0081] Seventh test mode (Mode 7): Channel 0 is connected to DIE 00 and DIE 02, Channel 1 is connected to DIE 10 and DIE 12, Channel 2 is connected to DIE 20 and DIE 22, and Channel 3 is connected to DIE 30 and DIE32.

[0082] Eighth test mode (Mode 8): Channel 0 is connected to DIE 01 and DIE 02, Channel 1 is connected to DIE 11 and DIE 12, Channel 2 is connected to DIE 21 and DIE 22, and Channel 3 is connected to DIE 31 and DIE32.

[0083] Ninth test mode (Mode 9): Channel 0 is connected to DIE 00, DIE 01, DIE 02, and DIE 03.

[0084] Mode 10: DIE 10, DIE 11, DIE 12, and DIE 13 are connected to Channel 1.

[0085] Mode 11: DIE 20, DIE 21, DIE 22, and DIE 23 are connected to Channel 2.

[0086] Mode 12: Channel 3 is connected to DIE 30, DIE 31, DIE 32, and DIE 33.

[0087] Mode 13: Channel 0 is connected to DIE 00, DIE 01, DIE 02, and DIE 03, and Channel 1 is connected to DIE 10, DIE 11, DIE 12, and DIE 13.

[0088] Fourteenth test mode (Mode 11): Channel 2 is connected to DIE 20, DIE 21, DIE 22, and DIE 23, and Channel 3 is connected to DIE 30, DIE 31, DIE 32, and DIE 33.

[0089] Mode 15: Channel 0 is connected to DIE 00, DIE 01, DIE 02, and DIE 03; Channel 2 is connected to DIE 20, DIE 21, DIE 22, and DIE 23.

[0090] Mode 16: Channel 1 is connected to DIE 10, DIE 11, DIE 12, and DIE 13, and Channel 3 is connected to DIE 30, DIE 31, DIE 32, and DIE 33.

[0091] Seventeenth test mode (Mode 17): Channel 0 is connected to DIE 00, DIE 01, DIE 02, and DIE 03; Channel 1 is connected to DIE 10, DIE 11, DIE 12, and DIE 13; Channel 2 is connected to DIE 20, DIE 21, DIE 22, and DIE 23; and Channel 3 is connected to DIE 30, DIE 31, DIE 32, and DIE 33.

[0092] In some embodiments, within the same flash memory unit 30 (packaged NAND flash memory), the multiple logic units 31 (DIEs) can be of the same or different models. For logic units 31 of different models, the primary differences lie in page size, physical block size, plane, speed, error correction code (ECC), and power supply voltage (VCC / VCCQ). For logic units 31 of the same model, the primary differences lie in different iterations of the same model.

[0093] In some embodiments, a page is the smallest programmable (writable) and readable unit in flash memory cell 30. Different DIE models may have different page sizes, such as 4KB, 8KB, or 16KB. Different page sizes affect data read and write efficiency, controller management, and memory performance.

[0094] In some embodiments, a physical block is the smallest erasable unit in flash memory cell 30 and consists of multiple pages. Different DIE models may have different block sizes, such as 256KB, 512KB, or 1MB. Different block sizes affect erase efficiency, memory lifespan, and controller management strategies.

[0095] In some embodiments, a plane is a logical partition within the flash memory unit 30. Each plane can independently perform certain operations (such as read and write). Different DIE models may have different numbers of planes, such as 1, 2, or 4. The number of planes affects the parallel operation capability of the memory, thereby affecting performance.

[0096] In some embodiments, "Speed" refers to the read and write speed of the DIE, typically expressed as a data transfer rate (e.g., MB / s). Different DIE models may have different read and write speeds. This difference in speed can affect the overall performance of the memory, especially under high load or multitasking scenarios.

[0097] In some embodiments, Error Correction Code (ECC) is used to detect and correct data errors in flash memory cells 30. Different DIE models may support different ECC strengths, such as 1-bit ECC, 4-bit ECC, or higher. ECC variations can affect memory reliability and data integrity.

[0098] In some embodiments, VCC is the core operating power supply for the DIE, and VCCQ is the interface power supply for the I / O interface. Different DIE models may have different VCC / VCCQ voltages, such as 1.8V, 3.3V, or other voltages. These voltage differences affect the DIE's power consumption, compatibility, and interface design with other components.

[0099] In some embodiments, the power supply unit 40 may be a memory power management module responsible for providing the interface power supply (VCCQ) and the core power supply (VCC). The voltage adjustment unit 50 may be configured to dynamically adjust the voltage values of VCCQ and VCC. The voltage adjustment unit 50 may utilize an internal voltage regulation circuit (such as a DC-DC converter or LDO regulator) to provide different VCCQ and VCC voltages as needed. Different models of flash memory cells 30 may require different VCCQ and VCC voltage values. The voltage adjustment unit 50 is adaptable to a variety of flash memory cells 30.

[0100] In some embodiments, the trigger control unit 60 can set corresponding trigger conditions based on different verification purposes and conditions. For example, a test can be triggered at a specific time point, under a specific signal state (such as an error signal or a completion signal), or under specific input conditions (such as a specific data pattern or a specific command). The trigger control unit 60 can automatically generate corresponding test instructions based on preset test items. These test instructions can be used to drive the flash memory control unit 20 to perform specific operations, such as reading data, writing data, erasing blocks, and performing ECC checks. By generating test instructions, the trigger control unit 60 can fully cover the compatibility testing requirements of the firmware. The test instructions may include reset instructions, identity identification instructions, bad block identification instructions, phase adjustment instructions, error correction algorithm adjustment instructions, mapping test instructions, voltage adjustment instructions, timeout test instructions, etc. The test items may also include testing the memory firmware using all test instructions in each of the above test modes.

[0101] In some embodiments, the read-only storage unit 70 may be a non-volatile memory (ROM) for long-term data storage. The read-only storage unit 70 may store a program, such as firmware. This program may be a set of pre-programmed instructions that direct the main control unit 10 on how to start up and operate. These instructions include device initialization, peripheral configuration, and a possible boot loader. The boot loader can be used to load updated programs or an operating system, for example.

[0102] In some embodiments, the random access memory 80 may be a volatile memory (Random Access Memory, RAM) that temporarily stores data and program code. The random access memory 80 may be used to temporarily store data. When the main control unit 10 executes a program, the program code may be loaded from the read-only memory unit 70 into the random access memory 80 for execution.

[0103] In some embodiments, the interface flash memory unit (SPI Flash) 90 can be a flash memory unit based on the SPI (Serial Peripheral Interface) interface for storing data. The firmware to be tested refers to the firmware that may need to undergo multiple tests and verifications during the development or debugging phase to ensure its functional correctness and performance meet the standards. The interface flash memory unit 90 can store the firmware to be tested and provide a data source for the test. During the test process, the firmware to be tested in the interface flash memory unit 90 can be loaded into the random access memory unit 80 to verify its functionality. If the firmware to be tested needs to be modified or upgraded, it can be stored and updated through the interface flash memory unit 90.

[0104] In some embodiments, the first interface unit 100 (Universal Asynchronous Receiver / Transmitter UART) can be an asynchronous serial communication interface used for data transmission between devices. The first interface unit 100 can use two signal lines (TX and RX) for full-duplex communication. The first interface unit 100 can be used to implement serial communication between a memory device and an external device (such as a PC or microcontroller).

[0105] In some embodiments, the second interface unit 110 (Universal Serial Bus USB) can be a universal serial bus that supports high-speed data transmission and device connection. The second interface unit 110 can be used to achieve high-speed data transmission between the memory and external devices (such as PCs and smartphones).

[0106] In some embodiments, the main control unit 10 can modify data in the firmware to be tested according to the test instructions, and control the flash memory unit 30 to perform corresponding operations based on the test instructions and the modified firmware to be tested. The main control unit 10 is also used to identify operational information of the flash memory unit 30 when performing the operation, and optimize the firmware to be tested based on the operational information to obtain the optimized firmware. The read-only memory unit 70 can be used to store the optimized firmware.

[0107] In some embodiments, when the test instruction is a reset instruction, the main control unit 10 can optimize the firmware to be tested according to the following steps: set reset durations of different sizes according to the reset instruction; perform a reset operation on the flash memory control unit 20 at each reset duration, and determine whether the logic unit responds normally: when all logic units 31 can respond normally, retain the reset duration; otherwise, eliminate the reset duration; sort the retained reset durations, and obtain the minimum reset duration, which is expressed as the target reset time; update the reset time of the firmware configuration table of the firmware to be tested according to the target reset time to obtain the optimized firmware.

[0108] In some embodiments, a reset instruction can be used to reset the flash memory control unit 20, restoring it to its initial state. This reset instruction can be used to verify the flash memory control unit 20's responsiveness under different reset durations to ensure its reliability and stability. The main control unit 10 can generate a series of different reset durations (e.g., 1ms, 2ms, 5ms, etc.) based on the reset instruction for testing. At each reset duration, the main control unit 10 can perform a reset operation on the flash memory control unit 20 and determine whether the logic unit 31 responds normally.

[0109] In some embodiments, the main control unit 10 can sequentially perform reset operations on the flash memory control unit 20, each time using a set reset duration. After the reset operation is completed, the main control unit 10 checks whether the logic unit 31 of the flash memory control unit 20 is responding normally. If a logic unit 31 responds normally, it indicates that the logic unit 31 is able to initialize correctly and perform subsequent operations. If a logic unit 31 responds abnormally, it indicates that the logic unit 31 cannot be initialized correctly or an error has occurred.

[0110] In some embodiments, when all logic units 31 are able to respond normally, the reset duration is retained. If all logic units 31 are able to respond normally within a certain reset duration, the reset duration is considered valid and retained. If one or some logic units 31 are unable to respond normally within a certain reset duration, the reset duration is considered invalid and is discarded.

[0111] In some embodiments, the main control unit 10 can sort all retained reset durations and select the shortest reset duration as the target reset time. The target reset time represents the shortest reset duration that the flash memory control unit 20 can normally respond to. The main control unit 10 can write the target reset time into the firmware configuration table of the firmware to be tested, thereby updating the reset time parameter. The updated firmware is the optimized firmware, whose reset time is optimized to the shortest effective value, thereby improving the efficiency and performance of the firmware.

[0112] In some embodiments, when the test instruction is a copy identification instruction, the main control unit 10 can optimize the firmware to be tested according to the following steps: change the identity information of at least one logical unit 31 in the identity configuration table of the firmware to be tested according to the identity identification instruction; after the flash memory control unit 20 performs a reset operation, identify the identity information of each logical unit 31; determine whether each changed identity information matches the corresponding identified identity information: when there is at least one changed identity information that matches the corresponding identified identity information, perform a reset operation on the flash memory control unit 20 to restore the identity configuration table, and optimize the identity verification mechanism in the firmware to be tested to obtain the optimized firmware.

[0113] In some embodiments, the identification instruction can be used to verify the identity information of the logic unit 31 of the flash memory unit 30 to ensure that its identity information is consistent with the configuration information. The identification instruction can verify whether the firmware's identity verification mechanism is effective and optimize the identity verification mechanism in the firmware.

[0114] In some embodiments, the main control unit 10 can modify the identity information (such as identity ID, verification code, etc.) of at least one logical unit 31 in the identity configuration table. The purpose of this step is to simulate changes in identity information to test the responsiveness of the identity verification mechanism. The main control unit 10 performs a reset operation on the flash memory control unit to restore it to its initial state. After the reset is complete, the main control unit 10 reads the identity information of each logical unit 31. The main control unit 10 compares the modified identity information in the identity configuration table with the read identity information. If there is a match, it can be indicated that the modified identity information is consistent with the recognized identity information. If there is a mismatch, it can be indicated that the modified identity information is inconsistent with the recognized identity information.

[0115] In some embodiments, if the altered identity information of at least one logic unit 31 matches the recognized identity information, a problem exists in the identity verification mechanism. The main control unit 10 resets the flash memory control unit to restore the identity configuration table to its original state. Based on the test results, the main control unit 10 optimizes the identity verification mechanism in the firmware under test. This optimization may include improving the accuracy of identity verification, adding identity information protection measures, optimizing the identity verification algorithm, and so on. After the optimization is complete, the optimized firmware can be generated.

[0116] In some embodiments, when the test instruction is a bad block identification instruction, the main control unit 10 can optimize the firmware to be tested according to the following steps: changing the bad block information of at least one physical block in at least one logical unit in the bad block table of the firmware to be tested according to the bad block identification instruction; identifying the bad block information of each physical block in each logical unit after the flash memory control unit performs a reset operation; judging whether each changed bad block information matches the corresponding identified bad block information: when there is at least one changed bad block information that matches the corresponding identified bad block information, performing a reset operation on the flash memory control unit to restore the bad block table, and optimizing the bad block check mechanism in the firmware to be tested to obtain the optimized firmware.

[0117] In some embodiments, the bad block identification instruction can be used to verify the bad block information of the physical blocks in the logical unit 31 of the flash memory unit 30 to ensure the effectiveness of the bad block management mechanism. The bad block identification instruction verifies the accuracy of the bad block check mechanism and optimizes the bad block management function in the firmware.

[0118] In some embodiments, the master control unit 10 can modify the bad block flag of at least one physical block in the logical unit 31 in the bad block table (e.g., marking a normal block as a bad block, or vice versa). This step simulates changes in bad block information and tests the fault tolerance and recovery capabilities of the bad block management mechanism. The master control unit 10 resets the flash memory control unit 20, triggering the reloading of bad block information. After the reset is complete, the master control unit 10 rescans all physical blocks to obtain actual bad block status information.

[0119] In some embodiments, the main control unit 10 compares the modified bad block mark in the bad block table with the actual scanned bad block status: if they match, it means that the modified bad block mark is consistent with the actual status (for example, the physical block marked as a bad block is indeed unusable). If they do not match, it means that the modified bad block mark is inconsistent with the actual status (for example, the physical block marked as a bad block is actually usable).

[0120] In some embodiments, when at least one altered bad block matches the corresponding identified bad block, a reset operation is performed on the flash memory control unit 20, restoring the bad block table to its original state (undoing the modifications made during the test). Subsequently, the bad block check mechanism in the firmware is optimized based on the matching results, for example, by improving the accuracy of the bad block detection algorithm, enhancing the fault tolerance of the bad block table, and optimizing the bad block flag update strategy. Finally, the optimized firmware is generated to ensure more reliable bad block management.

[0121] In some embodiments, when the test instruction is a phase adjustment instruction, the main control unit 10 can optimize the firmware to be tested according to the following steps: adjust the phase of the data selection signal and the data bus signal of the flash memory control unit according to the phase adjustment instruction; adjust the communication protocol of the flash memory control unit after the flash memory control unit performs a reset operation; under each communication protocol, determine whether the flash memory control unit switches normally between high-speed mode and low-speed mode: when the flash memory control unit cannot switch normally between high-speed mode and low-speed mode under at least one communication protocol, perform a reset operation on the flash memory control unit to restore the data selection signal and the data bus signal, and optimize the memory training mechanism in the firmware to be tested to obtain the optimized firmware.

[0122] In some embodiments, the phase adjustment instruction can be used to optimize the phase relationship between the data select signal (DQS) and the data bus signal (DQ) of the flash memory control unit to ensure the timing stability of the flash memory interface of the flash memory control unit 20 in different operating modes and improve data transmission reliability.

[0123] In some embodiments, the master control unit 10 can adjust the sampling phase of the data strobe signal and the transmission phase of the data bus signal according to the phase adjustment instruction to find the optimal phase relationship and ensure signal stability when switching between high and low speed modes. After performing the reset operation, the master control unit 10 can reconfigure the communication protocol parameters of the flash memory control unit 20 and adjust settings such as timing parameters and drive strength.

[0124] In some embodiments, the main control unit 10 needs to test under each protocol configuration: switching from high-speed mode to low-speed mode, switching from low-speed mode to high-speed mode, and check whether the data transmission is complete during the switching process, whether the timing meets the requirements, and whether there are any signal integrity issues.

[0125] In some embodiments, when the main control unit 10 detects a switching anomaly, it performs a reset operation to restore the original signal phase, analyzes the cause of the failure (e.g., insufficient setup / hold time), and optimizes the memory training mechanism in the firmware. For example, the memory training mechanism in the firmware can be optimized by improving the phase calibration algorithm, optimizing the mode switching timing, and enhancing the error detection mechanism, thereby obtaining the optimized firmware.

[0126] In some embodiments, when the test instruction is an error correction algorithm adjustment instruction, the main control unit 10 can optimize the firmware to be tested according to the following steps: adjust the error correction algorithm of the memory according to the error correction algorithm adjustment instruction, and change the number of error bits of at least one physical block in at least one logical unit in the error statistics table of the firmware to be tested; after the flash memory control unit performs a reset operation, identify the number of error bits of each physical block in each logical unit; determine whether each changed error bit number matches the corresponding identified error bit number: when there is at least one changed error bit number that matches the corresponding identified error bit number, perform a reset operation on the flash memory control unit to restore the error correction algorithm and the error statistics table, and optimize the error correction mechanism in the firmware to be tested to obtain the optimized firmware.

[0127] In some embodiments, error correction algorithm adjustment instructions can be used to verify and optimize the error correction code (ECC) algorithm to evaluate the effectiveness of the current error correction mechanism and optimize error detection and correction capabilities. The main control unit 10 can adjust the parameters of the currently used ECC algorithm (such as the error correction capability of the BCH code or the number of iterations of the LDPC code) and manually modify the number of error bits in a specific physical block in the error statistics table to simulate different error scenarios and test the adaptability of the error correction mechanism.

[0128] In some embodiments, after the flash memory control unit 20 performs a reset, it is necessary to rescan all physical blocks and use the adjusted ECC algorithm to count the actual number of error bits and record it in the error statistics table. Subsequently, the two sets of data can be compared: the manually modified number of error bits (expected value) and the actual number of error bits detected (measured value).

[0129] In some embodiments, when at least one altered error bit count matches the corresponding identified error bit count, the algorithm may be deemed to have misjudged or missed a detection. In this case, a reset may be performed to restore the original ECC algorithm. Subsequently, the firmware's error handling mechanism may be optimized, for example, by improving error detection thresholds, optimizing ECC algorithm selection strategies, enhancing error prediction mechanisms, adjusting read retry strategies, and other aspects to produce the optimized firmware.

[0130] In some embodiments, when the test instruction is a mapping test instruction, the main control unit 10 can optimize the firmware to be tested according to the following steps: changing the mapping data of at least one flash memory unit and its logical unit in the data mapping table of the firmware to be tested according to the mapping test instruction; after the flash memory control unit performs a reset operation, reading the mapping data of the logical unit in the data mapping table so that the logical unit performs wear leveling operations and garbage collection operations; judging whether the logical unit with the changed mapping data performs wear leveling operations and garbage collection operations normally: when there is at least one logical unit with the changed mapping data that cannot perform wear leveling operations and / or garbage collection operations, restoring the mapping data in the data mapping table, and optimizing the wear leveling mechanism and garbage collection mechanism in the firmware to be tested to obtain optimized firmware.

[0131] In some embodiments, the mapping test instruction may be used to verify the validity of the firmware's logical-physical address mapping mechanism to evaluate the reliability of two core functions: wear leveling and garbage collection.

[0132] In some embodiments, the master control unit 10 can manually modify the mapping relationship between specific logical blocks (LUNs) and physical blocks in the Flash Translation Layer (FLT) to simulate test scenarios. Test scenarios can include simulating block mapping under extreme wear conditions, creating a severely fragmented mapping state, and setting atypical address mapping relationships.

[0133] In some embodiments, after the flash memory control unit 20 performs a reset, the main control unit 10 reloads the mapping table and automatically triggers background processing, including wear leveling and garbage collection. Wear leveling refers to the reallocation of high-usage blocks. Garbage collection refers to the recovery of blocks occupied by invalid data. The main control unit 10 can then monitor system behavior, including whether data migration is successful, whether high-wear blocks are correctly identified, whether invalid data space is effectively recovered, and whether data consistency is maintained, to verify whether the mapping table is updated correctly, whether bad blocks are accurately marked, and whether spare blocks are used appropriately.

[0134] In some embodiments, when at least one logical unit with altered mapping data fails to perform wear leveling and / or garbage collection operations, the original mapping table data can be restored, and the cause of the failure can be deeply analyzed, including defects in the wear leveling algorithm, unreasonable GC triggering conditions, and resource allocation policy issues. Subsequently, the firmware's wear leveling and garbage collection mechanisms can be optimized, for example, by improving the wear assessment algorithm, optimizing the GC trigger threshold, enhancing the ability to handle abnormal mappings, and improving the efficiency of background task scheduling, thereby optimizing the firmware's error handling mechanism to obtain the optimized firmware.

[0135] In some embodiments, when the test instruction is a voltage adjustment instruction, the main control unit 10 can optimize the firmware to be tested according to the following steps: the voltage adjustment unit provides core power supplies of different voltages according to the voltage adjustment instruction; after the flash memory control unit performs a reset operation, the data of the logic unit is read under each core power supply; it is determined whether the flash memory control unit reads the data of the logic unit normally: when the data of the logic unit cannot be read, the core power supply of the logic unit is adjusted until the data of the logic unit is read normally, and the voltage of the core power supply of the logic unit is recorded; when the data of the logic unit is read normally, the voltage of the core power supply of the logic unit is recorded; according to the recorded core power supply voltage of each logic unit, the voltage table of the corresponding firmware to be tested is updated to obtain the optimized firmware.

[0136] In some embodiments, voltage adjustment instructions can be used to dynamically adjust the core power supply voltage of the flash memory unit 30 to optimize read / write stability and power consumption. This test can determine the operating stability of each logic unit 31 under different voltages and establish an optimal voltage table. This allows for adaptive voltage adjustment, improving data reliability in different environments (temperature, aging, etc.).

[0137] In some embodiments, the voltage adjustment unit provides different core power supply voltages (e.g., 1.8V, 2.5V, 3.3V, etc.) according to instructions. This simulates the impact of voltage fluctuations on the flash memory unit 30 to test the data readability of the logic unit 31 under low voltage / high voltage conditions.

[0138] In some embodiments, after the flash memory control unit 20 performs a reset (ensuring that the voltage setting is effective), an attempt is made to read the data of the logic unit 31 at each voltage level, and the data integrity is checked (whether the ECC check passes), while recording the read success / failure status.

[0139] In some embodiments, the main control unit 10 can determine the read result and adjust the voltage. For example, if the data of a certain logic unit cannot be read (failed), the voltage can be gradually adjusted (increased or decreased) until the data can be read normally (the lowest feasible voltage is found), and the optimal voltage value of the logic unit is recorded. If the data of a certain logic unit can be read normally, the current voltage value is directly recorded.

[0140] In some embodiments, the main control unit 10 can update the voltage table based on the test results, recording the optimal operating voltage for each logic unit 31. Subsequently, the firmware can also be optimized, for example, by optimizing the firmware from aspects such as adaptive voltage scaling (AVS), low-power optimization, and error recovery mechanisms, to obtain the optimized firmware. Adaptive voltage scaling (AVS) refers to dynamically adjusting the voltage based on the environment or aging level. Low-power optimization refers to using the lowest feasible voltage while ensuring stability. Error recovery mechanisms refer to backup strategies (such as retries and error correction) when voltage adjustment fails.

[0141] In some embodiments, when the test instruction is a timeout test instruction, the main control unit 10 can optimize the firmware to be tested according to the following steps: changing the read and write timeout information of at least one physical block in at least one logical unit in the bad block table of the firmware to be tested according to the timeout test instruction; performing random read and write operations on the physical block after the flash memory control unit performs a reset operation; judging whether the physical block with the changed read and write timeout information can perform random read and write operations normally: when the physical block with the changed read and write timeout information cannot perform random read and write operations, performing a reset operation on the flash memory control unit to restore the bad block table, and optimizing the read and write timeout mechanism in the firmware to be tested to obtain the optimized firmware.

[0142] In some embodiments, a timeout test instruction can be used to verify the effectiveness of the read and write timeout mechanism of the flash memory unit. This test can be used to check the Bad Block Management (BBM)'s ability to handle abnormal timeout blocks, thereby optimizing the firmware's read and write timeout strategy and improving data reliability.

[0143] In some embodiments, the main control unit 10 can manually modify the read and write timeout information of certain physical blocks in the Bad Block Table (BBT), for example, setting the timeout period of a normal block to an extremely short time (simulating a timeout failure) or setting the timeout period of a bad block to normal time (testing the recovery mechanism).

[0144] In some embodiments, after the flash memory control unit 20 performs a reset (to ensure that the bad block table update takes effect), it can perform random read / write operations on the target physical block to check whether the read / write failure is caused by the timeout setting. The target physical block is the physical block whose read / write timeout information is modified.

[0145] In some embodiments, when a target physical block cannot be read or written (a timeout triggers), it indicates that the bad block table's timeout setting is affecting normal operation. In this case, the original data in the bad block table must be restored, and the firmware's timeout detection mechanism must be optimized (e.g., by adjusting the timeout threshold). Subsequently, the firmware's read and write timeout mechanism can be optimized from aspects such as dynamic timeout adjustment, intelligent bad block marking, and error recovery strategies to produce the optimized firmware. Dynamic timeout adjustment refers to adjusting the timeout threshold based on the physical block's state (e.g., wear level). Intelligent bad block marking avoids misidentifying normal blocks as bad blocks. Error recovery strategies refer to automatic retry or data recovery mechanisms after a timeout.

[0146] As can be seen, the above solution significantly improves firmware processing capabilities through a systematic firmware testing approach (including error correction algorithms, mapping management, voltage regulation, and timeout testing), resolving issues such as insufficient coverage and poor compatibility associated with traditional testing. By dynamically simulating abnormal scenarios (such as voltage fluctuations, mapping errors, and timeout failures), potential risks in the firmware processing flow are fully identified, optimizing firmware stability and adaptability.

[0147] See also Figure 2 The present invention also provides a memory firmware optimization method, which can be applied to the above-mentioned memory, and the firmware optimization method includes:

[0148] Step S10: storing the firmware to be tested through the interface flash memory unit;

[0149] Step S20: triggering the control unit to generate corresponding test instructions according to the preset test items;

[0150] Step S30: The main control unit modifies the data in the firmware to be tested according to the test instruction, and controls the flash memory unit to perform corresponding operations according to the test instruction and the firmware to be tested after the modified data;

[0151] Step S40: identifying, by the main control unit, operation information of the flash memory unit when performing an operation, and optimizing the firmware to be tested according to the operation information to obtain an optimized firmware;

[0152] Step S50: storing the optimized firmware in a read-only storage unit.

[0153] The embodiments of the present invention disclosed above are intended only to illustrate the present invention. They do not describe all details in detail, nor do they limit the present invention to the specific embodiments described. Obviously, many modifications and variations are possible based on the content of this specification. These embodiments are selected and described in detail in this specification to better explain the principles and practical applications of the present invention, thereby enabling those skilled in the art to better understand and utilize the present invention. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A memory, characterized in that: include: at least one flash memory control unit, on which at least one flash memory unit is configured; An interface flash memory unit for storing the firmware to be tested; A trigger control unit is used to generate corresponding test instructions according to preset test items; a main control unit, configured to modify data in the firmware to be tested according to the test instruction, and control the flash memory unit to perform corresponding operations according to the test instruction and the firmware to be tested after the modified data; the main control unit is further configured to identify operation information of the flash memory unit when performing the operation, and optimize the firmware to be tested according to the operation information to obtain optimized firmware; a read-only storage unit, configured to store the optimized firmware; Wherein, the test instruction includes an identity recognition instruction and a phase adjustment instruction; The main control unit is used to change the identity information of at least one logical unit in the identity configuration table of the firmware to be tested according to the identity identification instruction; after the flash memory control unit performs a reset operation, identify the identity information of each of the logical units; determine whether each changed identity information matches the corresponding identified identity information; when there is at least one changed identity information that matches the corresponding identified identity information, perform a reset operation on the flash memory control unit, restore the identity configuration table, and optimize the identity verification mechanism in the firmware to be tested; The main control unit is used to adjust the phase of the data selection signal and the data bus signal of the flash memory control unit according to the phase adjustment instruction; after the flash memory control unit performs a reset operation, adjust the communication protocol of the flash memory control unit; under each of the communication protocols, determine whether the flash memory control unit switches normally between the high-speed mode and the low-speed mode: when the flash memory control unit cannot switch normally between the high-speed mode and the low-speed mode under at least one communication protocol, perform a reset operation on the flash memory control unit to restore the data selection signal and the data bus signal, and optimize the memory training mechanism in the firmware to be tested to obtain the optimized firmware.

2. The memory according to claim 1, wherein The test instruction includes a reset instruction; the main control unit optimizes the firmware to be tested according to the following steps: Setting different reset durations according to the reset instruction; At each reset time, a reset operation is performed on the flash memory control unit, and it is determined whether the logic unit in the flash memory unit responds normally: When all logic units can respond normally, the reset duration is retained; Otherwise, the reset duration is eliminated; Sort the reserved reset durations and obtain the minimum reset duration, which is expressed as the target reset time; The reset time of the firmware configuration table of the firmware to be tested is updated according to the target reset time to obtain optimized firmware.

3. The memory according to claim 1, wherein: The test instruction includes a bad block identification instruction; the main control unit optimizes the firmware to be tested according to the following steps: Modify bad block information of at least one physical block in at least one logical unit in the bad block table of the firmware to be tested according to the bad block identification instruction; After the flash memory control unit performs a reset operation, identifying bad block information of each physical block in each logical unit in each of the flash memory units; Determine whether each modified bad block information matches the corresponding identified bad block information: When there is at least one modified bad block information that matches the corresponding identified bad block information, a reset operation is performed on the flash memory control unit, the bad block table is restored, and the bad block check mechanism in the firmware to be tested is optimized to obtain the optimized firmware.

4. The memory according to claim 1, wherein: The test instruction includes an error correction algorithm adjustment instruction; the main control unit optimizes the firmware to be tested according to the following steps: adjusting the error correction algorithm of the memory according to the error correction algorithm adjustment instruction, and changing the number of error bits of at least one physical block in at least one logical unit in the flash memory unit in the error statistics table of the firmware to be tested; After the flash memory control unit performs a reset operation, identifying the number of error bits of each physical block in each of the logical units; Determine whether each modified error bit number matches the corresponding identified error bit number: When there is at least one changed error bit number that matches the corresponding identified error bit number, a reset operation is performed on the flash memory control unit, the error correction algorithm and the error statistics table are restored, and the error correction mechanism in the firmware to be tested is optimized to obtain an optimized firmware.

5. The memory according to claim 1, wherein: In the same flash memory control unit, when multiple flash memory units are configured thereon, the flash memory units include the same number of logic units; the test instruction includes a mapping test instruction; the main control unit optimizes the firmware to be tested according to the following steps: Modify mapping data of at least one flash memory unit and its logic unit in a data mapping table of the firmware to be tested according to the mapping test instruction; After the flash memory control unit performs a reset operation, mapping data of the logic unit in the data mapping table is read so that the logic unit performs a wear leveling operation and a garbage collection operation; Determine whether the logical unit whose mapping data is changed performs wear leveling and garbage collection operations normally: When there is at least one logic unit whose mapping data is changed and cannot perform wear leveling operations and / or garbage collection operations, the mapping data in the data mapping table is restored, and the wear leveling mechanism and garbage collection mechanism in the firmware to be tested are optimized to obtain optimized firmware. The memory according to claim 1 , wherein: The memory further includes a voltage adjustment unit, which is used to provide core power supplies with different voltages; the test instructions include voltage adjustment instructions; and the main control unit optimizes the firmware to be tested according to the following steps: The voltage adjustment unit provides core power supply with different voltages according to the voltage adjustment instruction; After the flash memory control unit performs a reset operation, reading data of the logic unit under each of the core power supplies; Determine whether the flash memory control unit reads the data of the logic unit normally: When the data of the logic unit cannot be read, adjusting the core power supply of the logic unit until the data of the logic unit can be read normally, and recording the voltage of the core power supply of the logic unit; When the data of the logic unit is read normally, recording the voltage of the core power supply of the logic unit; The corresponding voltage table is updated according to the recorded voltage of the core power supply of each logic unit to obtain optimized firmware.

7. The memory according to claim 1, wherein: The memory further includes a timeout test instruction; the main control unit optimizes the firmware to be tested according to the following steps: Modify the read and write timeout information of at least one physical block in at least one logical unit in the bad block table of the firmware to be tested according to the timeout test instruction; After the flash memory control unit performs a reset operation, performing a random read and write operation on the physical block; Determine whether the physical block with the changed read / write timeout information can perform random read / write operations normally: When the physical block whose read / write timeout information has been changed cannot perform random read / write operations, a reset operation is performed on the flash memory control unit to restore the bad block table, and the read / write timeout mechanism in the firmware to be tested is optimized to obtain the optimized firmware.

8. A method for optimizing memory firmware, characterized in that: The memory includes at least one flash memory control unit, and the flash memory control unit is configured with at least one flash memory unit; the firmware optimization method includes: storing the firmware to be tested via the interface flash memory unit; The trigger control unit generates corresponding test instructions according to the preset test items; The main control unit modifies the data in the firmware to be tested according to the test instruction, and controls the flash memory unit to perform corresponding operations according to the test instruction and the firmware to be tested after the modified data; identifying, by the main control unit, operation information of the flash memory unit when performing an operation, and optimizing the firmware to be tested according to the operation information to obtain an optimized firmware; Storing the optimized firmware in a read-only storage unit; Wherein, the test instruction includes an identity recognition instruction and a phase adjustment instruction; The main control unit changes the identity information of at least one logical unit in the identity configuration table of the firmware to be tested according to the identity identification instruction; after the flash memory control unit performs a reset operation, identifies the identity information of each of the logical units; determines whether each changed identity information matches the corresponding identified identity information; when there is at least one changed identity information that matches the corresponding identified identity information, performs a reset operation on the flash memory control unit, restores the identity configuration table, and optimizes the identity verification mechanism in the firmware to be tested; The main control unit adjusts the phase of the data selection signal and the data bus signal of the flash memory control unit according to the phase adjustment instruction; adjusts the communication protocol of the flash memory control unit after the flash memory control unit performs a reset operation; and determines whether the flash memory control unit switches normally between the high-speed mode and the low-speed mode under each of the communication protocols: when the flash memory control unit cannot switch normally between the high-speed mode and the low-speed mode under at least one communication protocol, performs a reset operation on the flash memory control unit to restore the data selection signal and the data bus signal, and optimizes the memory training mechanism in the firmware to be tested to obtain the optimized firmware.

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