Multi-core architecture satellite navigation SoC, chip and receiver based on RISC-V vector processor

Abstract

The present invention relates to a multi-core architecture satellite navigation SoC, a chip and a receiver based on a RISC-V vector processor; belonging to the field of satellite navigation and chip design, the SoC includes: an instruction memory for storing a navigation receiver program rewritten from a parallel algorithm; a main processor for obtaining and running the navigation receiver program from the instruction memory, performing receiver control and processing, and navigation control and processing functions to output a positioning result, and a vector co-processor for assisting the main processor in executing vector instructions when the main processor runs the navigation receiver program; for vector instructions that need to return scalar values, the vector co-processor feeds back the instruction execution result to the main processor, and for the remaining instructions, the vector co-processor writes the instruction execution result into the data memory for the main processor to call. Through the coupled processing of the main processor and the vector co-processor, the present invention enhances the processing ability of multi-channel satellite navigation signals and improves the response speed of the system.

Description

Technical Field

[0001] The present invention relates to the fields of satellite navigation and chip design, and in particular to a multi-core architecture satellite navigation SoC, chip and receiver based on a RISC-V vector processor. Background Art

[0002] With the development of technologies such as autonomous driving, precision agriculture, and mobile Internet of Things, people's demand for precise positioning information is becoming increasingly strong. Compared with low-cost satellite navigation receivers that only support single-frequency, the advantage of satellite navigation receivers that support multi-mode and multi-frequency is that they can obtain more observation information and optimize the geometric structure of satellite observations, and their positioning accuracy, availability, and reliability are greatly improved.

[0003] The reception of multi-mode and multi-frequency satellite navigation signals places higher requirements on the performance of satellite navigation chip processors. If a higher-performance processor is used in the navigation chip, or multiple processor cores are integrated, it is the most direct way to improve performance, but it will inevitably increase costs, area, and power consumption. RISC-V is an instruction set architecture with the characteristics of modularity and scalability. While having strong flexibility, it allows designers to add custom instructions to optimize specific reference scenarios. RISC-V Vector Extension is a vector instruction set extension of RISC-V. Existing research shows that it exhibits high performance and high energy efficiency advantages in parallel data processing, and can also maintain software cross-platform compatibility. Therefore, designing a satellite navigation processor around the RISC-V instruction set architecture and RISC-V Vector Extension can make full use of the modularity, flexibility, scalability of RISC-V, and the high performance and high energy efficiency characteristics of RVV in parallel data operations to solve the above problems. Summary of the Invention

[0004] In view of the above analysis, the present invention aims to disclose a multi-core architecture satellite navigation SoC, chip and receiver based on a RISC-V vector processor, realizing high-performance and high-energy efficiency design of satellite navigation receivers.

[0005] On the one hand, the present invention discloses a multi-core architecture satellite navigation SoC based on a RISC-V vector processor, including: an instruction memory, a main processor, and a vector coprocessor; wherein,

[0006] The instruction memory is used to store a navigation receiver program rewritten with vector instructions specified in RISC-V Vector Extension for algorithms with data parallelism;

[0007] The main processor is connected to the instruction memory through a bus, and the vector coprocessor is connected to the main processor through a vector coprocessor interface;

[0008] The main processor adopts the RISC-V architecture and is used to obtain and run the navigation receiver program from the instruction memory; by using the read satellite baseband data, it performs receiver control and processing as well as navigation control and processing functions, and outputs the positioning result.

[0009] The vector coprocessor supports RISC-V Vector Extension and is used to assist the main processor in executing vector instructions when the main processor runs the navigation receiver program; for vector instructions that need to return scalar values, the vector coprocessor feeds back the instruction execution result to the main processor, and for the remaining instructions, it writes the instruction execution result into the data memory for the main processor to call.

[0010] Furthermore, the process of vectorizing and rewriting an algorithm with data parallelism using the vector instructions specified in RISC-V Vector Extension includes:

[0011] 1) Decompose the general C / C++ navigation receiver program to extract the code of the algorithm with data parallelism therein;

[0012] 2) Rewrite the extracted code of the algorithm with data parallelism using the vector instructions specified in RISC-V Vector Extension through methods including inline assembly, RVV Intrinsic, and compiler auto-vectorization;

[0013] 3) Rearrange the data elements called by the rewritten vector instructions to make them continuous in memory, and compile the navigation receiver software optimized by vectorization through toolchains that support RISC-V vector extension, including GCC and LLVM / Clang;

[0014] 4) Download the compiled navigation processing receiver program into the instruction memory.

[0015] Furthermore, the SoC also includes a baseband coprocessor; the baseband coprocessor cooperates with the main processor to perform baseband signal processing. The baseband coprocessor receives the intermediate frequency signal from outside the SoC and, under the control of the navigation receiver program running in the main processor, preprocesses, captures, tracks, and loops the intermediate frequency signal to output baseband data including channel correlation values and receiver status.

[0016] After the main processor reads data such as channel - related values and receiver status output by the baseband coprocessor, it is responsible for the receiver control and processing functions as well as the navigation control and processing functions in the navigation receiver program, and only independently processes the non - vector operation part thereof; the vector operation part is processed with the assistance of the vector coprocessor, and finally the positioning result is output through the peripheral interface.

[0017] Furthermore, the main processor internally includes a custom instruction processing unit, which is used to accelerate the frequently reused operators in the navigation receiver program, including the FFT operations frequently required in the parallel code - phase search and Doppler frequency - shift estimation during capture by the baseband coprocessor.

[0018] The custom instruction processing unit executes user - defined instructions including 8 - point FFT instructions. These custom instructions are not included in the RISC - V architecture specification. The main processor reads the custom instructions from the instruction memory, decodes them, and then sends them to the custom instruction processing unit for operation to accelerate the key operators that are highly reused in the baseband signal processing process.

[0019] Furthermore, the vector coprocessor is connected to the main processor through the vector coprocessor interface; when the main processor runs the navigation receiver program optimized by vectorization, after the vectorized instructions are decoded twice in the main processor and the vector coprocessor respectively, the vectorized instructions are executed in the vector coprocessor. For vector instructions that need to return scalar values, the vector coprocessor feeds back the instruction execution results to the main processor. For the remaining instructions, the instruction execution results are written into the data memory for the main processor to call.

[0020] Furthermore, in the two - stage decoding

[0021] The first - stage decoding is a preliminary decoding operation performed in the main processor. After the main processor reads the vector - optimized vector instructions from the instruction memory, it performs the preliminary decoding operation; in the preliminary decoding operation, data hazard processing is performed, the instruction type and the required scalar operands are decoded, and it is determined whether the currently running instruction is a vector instruction; if so, the vector instruction execution request and the corresponding instruction decoding information are sent to the vector coprocessor. After completing the handshake operation with the vector coprocessor, the vector instruction is successfully dispatched to the vector coprocessor for execution.

[0022] The second decoding is a further decoding operation performed in the vector coprocessor. The vector coprocessor receives the vector instruction execution request from the main processor and the preliminary decoding information of the instruction, and performs a further decoding operation on the instruction; in the further decoding operation, all the information of the instruction is decoded according to the RVV instruction set specification and dispatched to different hardware processing units according to the instruction type; the vector coprocessor also determines whether it is necessary to read data elements from the data memory according to the decoding result, and if so, accesses the data memory.

[0023] Further, a shared scoreboard structure is also included inside the main processor;

[0024] The scoreboard records the write-back status of the scalar registers and floating-point registers inside the main processor, and marks the memory access status of the main processor and the vector coprocessor. The scoreboard is visible to both the main processor and the vector coprocessor, and plays a role in coordinating register calls, so as to solve pipeline hazards and ensure the strict order of memory access.

[0025] Further, a dual-bus structure is adopted, including a system bus and a dedicated data bus;

[0026] The main processor, baseband coprocessor, instruction memory, data memory, and peripheral modules are interconnected through the system bus;

[0027] The system bus includes a system bus interface and a low-speed expansion interface, where,

[0028] The system bus interface is used for data interaction with the baseband coprocessor, main processor, data memory, and instruction memory mounted on the system bus;

[0029] The low-speed expansion interface is used for data interaction with the peripheral modules mounted on the system bus;

[0030] The vector coprocessor is interconnected with the data memory through the dedicated data bus; the dedicated data bus is used to transmit the requests for the vector coprocessor to read and write the data memory;

[0031] The dedicated data bus and the data memory each have configuration registers; the access bandwidth of the dedicated data bus and the data memory is configured through the configuration registers; enabling the vector coprocessor to send read and write control signals and data through the dedicated data bus to simultaneously access multiple data elements in the data memory; overcoming the memory wall problem faced when executing vector instructions.

[0032] On the other hand, the present invention also discloses a satellite navigation chip, which includes the multi-core architecture satellite navigation SoC based on the RISC-V vector processor as described above.

[0033] On the other hand, the present invention also discloses a satellite navigation receiver, which includes the satellite navigation chip as described above.

[0034] One of the beneficial effects that the present invention can achieve is as follows:

[0035] The present invention discloses a multi-core architecture satellite navigation SoC, chip and receiver based on a RISC-V vector processor;

[0036] Compared with traditional SoC designs, the new SoC includes a main processor with a RISC-V architecture and a vector coprocessor that supports the RISC-V Vector Extension. It can run a vectorized-optimized navigation receiver program, support custom instructions to accelerate key operators with large-scale reuse in navigation applications, thereby achieving high-performance and high-energy-efficiency designs for satellite navigation receivers. The new architecture also includes a large-bandwidth vector coprocessor dedicated data bus and corresponding data memories that support concurrent access to multiple data elements, overcoming the memory access wall problem when executing vector instructions. While improving the energy efficiency ratio of the SoC when processing navigation receiver applications, it can reduce the code size and thus the demand for the on-chip storage capacity of the SoC. Moreover, due to the generality of RVV, there are many application scenarios for vector optimization in navigation receiver software, which can be applied to multiple processing modules in navigation receiver software, significantly enhancing the adaptability and processing ability of the SoC in complex navigation scenarios. Description of the Drawings

[0037] The drawings are only for the purpose of showing specific embodiments and are not considered as limiting the present invention. Throughout the drawings, the same reference signs denote the same components;

[0038] Figure 1 Schematic diagram of the multi-core architecture satellite navigation SoC in an embodiment of the present invention;

[0039] Figure 2 Schematic diagram of the multi-core architecture satellite navigation SoC with a dual-bus structure in an embodiment of the present invention. Detailed Embodiments

[0040] The following will specifically describe the preferred embodiments of the present invention in conjunction with the drawings, where the drawings form a part of this application and are used together with the embodiments of the present invention to explain the principles of the present invention.

[0041] Embodiment 1

[0042] An embodiment of the present invention discloses a multi-core architecture satellite navigation SoC based on a RISC-V vector processor, as Figure 1 shown, including: an instruction memory, a main processor, and a vector coprocessor; wherein,

[0043] An instruction memory for storing a navigation receiver program obtained by vectorizing an algorithm with data parallelism using vector instructions defined in the RISC-V Vector Extension (RVV).

[0044] The main processor is connected to the instruction memory via a bus, and the vector coprocessor is connected to the main processor via a vector coprocessor interface.

[0045] The main processor adopts the RISC-V architecture and is used to fetch and run the navigation receiver program from the instruction memory; using the read satellite baseband data, it performs receiver control and processing as well as navigation control and processing functions, and outputs positioning results.

[0046] The vector coprocessor supports the RISC-V Vector Extension and is used to assist the main processor in executing vector instructions when the main processor runs the navigation receiver program; for vector instructions that need to return scalar values, the vector coprocessor feeds back the instruction execution results to the main processor, and for the remaining instructions, it writes the instruction execution results into the data memory for the main processor to call.

[0047] Specifically, the process of vectorizing an algorithm with data parallelism using vector instructions defined in the RISC-V Vector Extension includes:

[0048] 1) Decompose the general C / C++ navigation receiver program and extract the code of the algorithm with data parallelism therein.

[0049] The algorithms with data parallelism include loop filtering used in multiple tracking channels in parallel and algorithms involving matrix operations; these algorithms with data parallelism are frequently used in the navigation receiver program.

[0050] For example, the loop filtering algorithm; during the operation of the algorithm, the main processor performs digital signal processing on the correlation values of multiple tracking channels in the baseband data. Since loop filtering needs to perform almost exactly the same operations on the correlation values of multiple channels, it has data parallelism and is very suitable for acceleration by vector operations.

[0051] Another example is that algorithms such as the Newton iteration method and Kalman filtering used in PVT solution contain a large number of matrix operations, and matrix operations have parallelism and are also very suitable for acceleration by vector operations.

[0052] In this embodiment, by vectorizing and optimizing the algorithms frequently used in navigation applications and accelerating them by vector operations, the GNSS navigation processing efficiency can be greatly improved.

[0053] 2) Rewrite the code of the extracted algorithm with data parallelism using vector instructions specified by the RISC-V Vector Extension through methods including inline assembly, RVV Intrinsic, and automatic compiler vectorization;

[0054] 3) Rearrange the data elements called by the rewritten vector instructions to keep them continuous in memory, and compile the navigation receiver software optimized by vectorization through toolchains that support the RISC-V vector extension, including GCC and LLVM / Clang;

[0055] 4) Download the compiled navigation processing receiver program to the instruction memory.

[0056] In a specific solution of this embodiment, the SoC further includes a baseband coprocessor;

[0057] The baseband coprocessor cooperates with the main processor to perform baseband signal processing. The baseband coprocessor receives the intermediate frequency signal from outside the SoC and, under the control of the navigation receiver program running in the main processor, preprocesses, captures, tracks, and performs loop processing on the intermediate frequency signal to output baseband data including channel correlation values and receiver status;

[0058] After the main processor reads data such as channel correlation values and receiver status output by the baseband coprocessor, it is responsible for the receiver control and processing functions and navigation control and processing functions in the navigation receiver program, and only independently processes the non-vector operation part thereof; the vector operation part is processed with the assistance of the vector coprocessor, and finally outputs the positioning result through the peripheral interface.

[0059] Specifically, the main processor internally includes a custom instruction processing unit for accelerating the operators frequently reused in the navigation receiver program, including the parallel code phase search during capture by the baseband coprocessor and the Doppler frequency shift estimation that require frequent FFT operations;

[0060] The custom instruction processing unit executes user-defined instructions including 8-point FFT instructions. These custom instructions are not included in the RISC-V architecture specification. The main processor reads the custom instructions from the instruction memory, decodes them, and sends them to the custom instruction processing unit for operation to accelerate the key operators that are heavily reused in the baseband signal processing process.

[0061] Specifically, the vector co-processor is connected to the main processor through a vector co-processor interface; when the main processor runs the navigation receiver program optimized by vectorization, after the vectorized instructions are decoded twice in the main processor and the vector co-processor respectively, the vectorized instructions are executed in the vector co-processor. For vector instructions that need to return scalar values, the vector co-processor feeds back the instruction execution results to the main processor. For the remaining instructions, the instruction execution results are written into the data memory for the main processor to call;

[0062] During the two decodings,

[0063] The first decoding is a preliminary decoding operation performed in the main processor. After the main processor reads the vector instructions optimized by vectorization from the instruction memory, it performs a preliminary decoding operation; during the preliminary decoding operation, data hazard processing is performed, the instruction type is decoded, and the required scalar operands are obtained to determine whether the currently running instruction is a vector instruction; if so, the vector instruction execution request and the corresponding instruction decoding information are sent to the vector co-processor. After completing the handshake operation with the vector co-processor, the vector instruction is successfully dispatched to the vector co-processor for execution.

[0064] The second decoding is a further decoding operation performed in the vector co-processor. The vector co-processor receives the vector instruction execution request from the main processor and the preliminary decoding information of the instruction, and performs a further decoding operation on the instruction; during the further decoding operation, all the information of the instruction is decoded according to the RVV instruction set specification and dispatched to different hardware processing units according to the instruction type; the vector co-processor also determines whether it is necessary to read data elements from the data memory according to the decoding result, and if so, accesses the data memory.

[0065] Preferably, the main processor also includes a shared scoreboard structure internally;

[0066] The scoreboard records the pending write-back status of the scalar registers and floating-point registers inside the main processor, and marks the memory access status of the main processor and the vector co-processor. The scoreboard is visible to both the main processor and the vector co-processor, and plays a role in coordinating register calls to solve pipeline hazards and ensure a strict order of memory access.

[0067] Specifically, in the solution of this embodiment, there is also a peripheral module, and the peripheral module includes any one interface or a combination of any several of the USB interface, I2C interface, UART interface, SPI interface, and GPIO interface;

[0068] The peripheral module is connected to the system bus and connected to the main processor through the system bus, and is used to output the data including the positioning result to the external positioning data using device through the interface included in the peripheral module.

[0069] Preferably, in one solution of this embodiment, as Figure 2 shown, a dual-bus structure is adopted, including a system bus and a dedicated data bus;

[0070] The main processor, baseband coprocessor, instruction memory, data memory, and peripheral modules are interconnected through the system bus;

[0071] The system bus includes a system bus interface and a low-speed expansion interface, where

[0072] The system bus interface is used for data interaction with the baseband coprocessor, main processor, data memory, and instruction memory mounted on the system bus;

[0073] For example, the data memory is connected to the system bus through the system bus interface and can process read and write requests from the system bus;

[0074] The low-speed expansion interface is used for data interaction with the peripheral modules mounted on the system bus;

[0075] The vector coprocessor is interconnected with the data memory through the dedicated data bus; the dedicated data bus is used to transmit the requests of the vector coprocessor to read and write the data memory;

[0076] The dedicated data bus and the data memory each have configuration registers; the access bandwidth of the dedicated data bus and the data memory is configured through the configuration registers; enabling the vector coprocessor to send read and write control signals and data through the dedicated data bus to simultaneously access multiple data elements in the data memory; overcoming the memory wall problem faced when executing vector instructions.

[0077] During the configuration process, when the vector coprocessor accesses the data memory, it sends the bus bit width required for this access through the vector coprocessor dedicated data bus interface, so that the value in the configuration register changes according to the real-time access demand. If the data width accessed by the vector instruction does not need to occupy the full bus bandwidth, then the value in the configuration register is reduced, causing some bus bit widths to stop working, thereby reducing power consumption. Conversely, the value of the configuration register increases until all the bus bit widths are in the working state.

[0078] After a vector instruction is executed, the vector coprocessor feeds back the result to the main processor. After completing the handshake with the main processor, the instruction is considered to be completed and delivered, that is, the instruction ends its life cycle.

[0079] In summary, the multi-core architecture satellite navigation SoC based on the RISC-V vector processor of this embodiment;

[0080] Compared with traditional SoC designs, the new SoC includes a main processor with the RISC-V architecture and a vector coprocessor that supports the RISC-V Vector Extension. It can run a navigation receiver program optimized by vectorization, support custom instructions to accelerate key operators with large-scale reuse in navigation applications, thus achieving a high-performance and energy-efficient design for satellite navigation receivers. The new architecture also includes a dedicated data bus with large bandwidth for the vector coprocessor that supports concurrent access to multiple data elements and the corresponding data memory, overcoming the memory access wall problem when executing vector instructions. While improving the energy efficiency ratio of the SoC when processing navigation receiver applications, it can reduce the code size and thus the demand for on-chip storage capacity of the SoC. Moreover, due to the generality of RVV, there are many application scenarios for vector optimization in navigation receiver software, which can be applied to multiple processing modules in navigation receiver software, significantly enhancing the adaptability and processing ability of the SoC in complex navigation scenarios.

[0081] Embodiment 2

[0082] An embodiment of the present invention discloses a satellite navigation chip, which includes the multi-core architecture satellite navigation SoC based on the RISC-V vector processor as described in Embodiment 1. In the satellite navigation chip, it can run a navigation receiver program optimized by vectorization, support custom instructions to accelerate key operators with large-scale reuse in navigation applications, and enhance the processing ability of multi-channel satellite navigation signals and improve the system response speed through the coupling and processing of the main processor and the vector coprocessor.

[0083] The specific technical details and beneficial effects in this embodiment are the same as those disclosed in Embodiment 1. Please refer to them specifically and will not be elaborated here one by one.

[0084] Embodiment 3

[0085] An embodiment of the present invention discloses a satellite navigation receiver, which includes the satellite navigation chip as described in Embodiment 2; enabling the satellite navigation receiver to run a navigation receiver program optimized by vectorization, achieving a high-performance and energy-efficient design for the satellite navigation receiver.

[0086] The specific technical details and beneficial effects in this embodiment are the same as those disclosed in Embodiment 1. Please refer to them specifically and will not be elaborated here one by one.

[0087] The above is only a preferred specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention.

Claims

1. A multi-core architecture satellite navigation SoC based on a RISC-V vector processor, characterized in that including: an instruction memory, a main processor, and a vector coprocessor; wherein, the instruction memory is used to store a navigation receiver program obtained by vectorizing and rewriting an algorithm with data parallelism using the vector instructions specified in the RISC-V Vector Extension; the main processor is connected to the instruction memory through a bus, and the vector coprocessor is connected to the main processor through a vector coprocessor interface; the main processor adopts the RISC-V architecture and is used to obtain and run the navigation receiver program from the instruction memory; by using the read satellite baseband data, it performs receiver control and processing as well as navigation control and processing functions, and outputs a positioning result; the vector coprocessor supports the RISC-V Vector Extension and is used to assist the main processor in executing vector instructions when the main processor runs the navigation receiver program; for vector instructions that need to return scalar values, the vector coprocessor feeds back the instruction execution result to the main processor, and for the remaining instructions, it writes the instruction execution result into the data memory for the main processor to call; the process of vectorizing and rewriting an algorithm with data parallelism using the vector instructions specified in the RISC-V Vector Extension includes: decomposing and extracting the code of the algorithm with data parallelism from a general C / C++ navigation receiver program; rewriting the extracted code of the algorithm with data parallelism using the vector instructions specified in the RISC-V Vector Extension through methods including inline assembly, RVV Intrinsic, and automatic compiler vectorization; rearranging the data elements called by the rewritten vector instructions to keep them continuous in memory, and compiling the navigation receiver software optimized by vectorization through a tool chain that supports the RISC-V vector extension, including GCC and LLVM / Clang; downloading the compiled navigation processing receiver program into the instruction memory.

2. The multi-core architecture satellite navigation SoC based on the RISC-V vector processor according to claim 1, wherein a baseband coprocessor is further included in the SoC; the baseband coprocessor cooperates with the main processor to perform baseband signal processing. The baseband coprocessor receives an intermediate frequency signal from outside the SoC and, under the control of the navigation receiver program running in the main processor, performs preprocessing, acquisition, tracking, and loop processing on the intermediate frequency signal and outputs baseband data including channel correlation values and receiver status; after the main processor reads the status data including channel correlation values and receiver output from the baseband coprocessor, it is responsible for the receiver control and processing functions and navigation control and processing functions in the navigation receiver program, and only independently processes the non-vector operation part thereof; the vector operation part is processed with the assistance of the vector coprocessor, and finally outputs the positioning result through a peripheral interface.

3. The multi-core architecture satellite navigation SoC based on the RISC-V vector processor according to claim 2, wherein The main processor internally contains a custom instruction processing unit, which is used to accelerate the frequently reused operators in the navigation receiver program, including the parallel code phase search during capture by the baseband coprocessor and the Doppler frequency shift estimation that requires frequent FFT operations. The custom instruction processing unit executes user-defined instructions including 8-point FFT instructions, which are not included in the RISC-V architecture specification. The main processor reads the custom instructions from the instruction memory, decodes them, and then sends them to the custom instruction processing unit for operation, accelerating the key operators that are heavily reused in the baseband signal processing process.

4. The multi-core architecture satellite navigation SoC based on the RISC-V vector processor according to claim 1, characterized in that The vector coprocessor is connected to the main processor through the vector coprocessor interface; when the main processor runs the navigation receiver program optimized by vectorization, after decoding the vectorized instructions separately in the main processor and the vector coprocessor, the vectorized instructions are executed in the vector coprocessor. For vector instructions that need to return scalar values, the vector coprocessor feeds back the instruction execution results to the main processor. For the remaining instructions, the instruction execution results are written into the data memory for the main processor to call.

5. The multi-core architecture satellite navigation SoC based on the RISC-V vector processor according to claim 4, characterized in that In the two decodings, The first decoding is a preliminary decoding operation performed in the main processor. After the main processor reads the vectorized instructions optimized by vectorization from the instruction memory, a preliminary decoding operation is performed; in the preliminary decoding operation, data hazard processing is performed, the instruction type is decoded, and the required scalar operands are obtained, and it is judged whether the currently running instruction is a vector instruction; if so, the vector instruction execution request and the corresponding instruction decoding information are sent to the vector coprocessor. After completing the handshake operation with the vector coprocessor, the vector instruction is successfully dispatched to the vector coprocessor for execution. The second decoding is a further decoding operation performed in the vector coprocessor. The vector coprocessor receives the vector instruction execution request and the preliminary decoding information of the instruction from the main processor, and performs a further decoding operation on the instruction; in the further decoding operation, all the information of the instruction is decoded according to the RVV instruction set specification and dispatched to different hardware processing units according to the instruction type; the vector coprocessor also judges whether it is necessary to read data elements from the data memory according to the decoding result, and if so, accesses the data memory.

6. The multi-core architecture satellite navigation SoC based on the RISC-V vector processor according to claim 5, characterized in that The main processor also internally includes a shared scoreboard structure; The scoreboard records the write-back status of the scalar registers and floating-point registers inside the main processor, and marks the memory access status of the main processor and the vector coprocessor. The scoreboard is visible to both the main processor and the vector coprocessor, playing a role in coordinating register calls, solving pipeline hazards, and ensuring a strict order of memory access.

7. The multi-core architecture satellite navigation SoC based on the RISC-V vector processor according to any one of claims 1-6, characterized in that it adopts a dual-bus structure, including a system bus and a dedicated data bus; the main processor, the baseband coprocessor, the instruction memory, the data memory, and the peripheral modules are interconnected through the system bus; the system bus includes a system bus interface and a low-speed expansion interface, where the system bus interface is used for data interaction with the baseband coprocessor, the main processor, the data memory, and the instruction memory mounted on the system bus; the low-speed expansion interface is used for data interaction with the peripheral modules mounted on the system bus; the vector coprocessor is interconnected with the data memory through the dedicated data bus; the dedicated data bus is used to transmit the requests of the vector coprocessor to read and write the data memory; both the dedicated data bus and the data memory have configuration registers; the access bandwidths of the dedicated data bus and the data memory are configured through the configuration registers; enabling the vector coprocessor to send read and write control signals and data through the dedicated data bus to simultaneously access multiple data elements in the data memory; overcoming the memory wall problem faced when executing vector instructions.

8. A satellite navigation chip, characterized in that, The chip includes the multi-core architecture satellite navigation SoC based on the RISC-V vector processor according to any one of claims 1-7.

9. A satellite navigation receiver, characterized in that, The receiver includes the satellite navigation chip according to claim 8.

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