map cache

Abstract

A graph cache memory for efficiently storing graph structures. The graph cache memory can be used in computing systems to accelerate graph processing via graph neural networks, and differs from the general-purpose memory of the computing system. The embeddings of the graph nodes are stored in the computing system's memory, while the graph structure is stored in the graph cache memory. The graph cache memory may include a content-addressable memory array, which can be adapted for efficiently representing graph structures.

Description

Technical Field

[0001] This disclosure relates to a graph cache memory, and more specifically to a graph cache memory for efficiently storing graph structures. Background Technology

[0002] Graph Neural Networks (GNNs) are a class of machine learning algorithms designed to process and analyze data represented as graphs. They have gained prominence in various fields, such as traffic analysis, social networks, recommender systems, and biology. GNNs operate by aggregating information from neighboring nodes in a graph, enabling them to identify relationships and patterns in the data. GNNs consist of multiple layers, each refining the node embeddings of the graph through a combination of node features and information from neighboring nodes. GNNs are useful for tasks such as node classification, link prediction, and graph classification. Summary of the Invention

[0003] According to one aspect of the present disclosure, a graph cache memory is provided, comprising: a content-addressable memory (CAM) array, the CAM array including CAM rows and matching lines corresponding to the CAM rows, the CAM array being configured to receive an identifier of a target node of a graph structure, search for the identifier in the CAM rows, and activate the matching lines in the matching lines corresponding to the CAM rows storing the identifier; a random access memory (RAM) array, the RAM array including RAM rows and word lines corresponding to the RAM rows; and a multi-match parser connected to the CAM array and the RAM array, the multi-match parser being configured to serially activate word lines of the RAM array corresponding to the activated matching lines of the CAM array.

[0004] According to another aspect of the embodiments of this disclosure, a method for a graph cache memory based on the above embodiments implemented by a computing system is provided. The method includes: obtaining the memory addresses of neighboring nodes of a target node from the graph cache memory of the computing system, the graph cache memory storing a graph structure including the target node and neighboring nodes, the neighboring nodes being connected to the target node in the graph structure, the memory addresses being the location of the computing system's memory, and the memory being different from the graph cache memory; accessing the neighbor embeddings of the neighboring nodes at the memory addresses in the memory; updating the target embedding of the target node by aggregating the neighbor embeddings of the neighboring nodes; and storing the target embedding of the target node in the memory.

[0005] According to another aspect of the present disclosure, a computing system is provided, comprising: a processor; a graph cache memory, wherein the graph cache memory is the graph cache memory according to the above embodiment; and a memory, different from the graph cache memory, the memory including a non-transitory computer-readable medium storing instructions, which, when executed by the processor, cause the processor to: store a graph structure to the graph cache memory; provide an identifier of a target node of the graph structure to the graph cache memory; receive from the graph cache memory the memory addresses of neighboring nodes of the target node, the neighboring nodes being connected to the target node in the graph structure, the memory addresses being locations in the memory; access the neighbor embeddings of the neighboring nodes at the memory addresses in the memory; update the target embedding of the target node by aggregating the neighbor embeddings of the neighboring nodes; and store the target embedding of the target node in the memory. Attached Figure Description

[0006] When with attachment Figure 1 When reading this disclosure, the best understanding of its various aspects can be obtained from the following detailed description.

[0007] Figure 1 It is a block diagram of a computing system according to some implementation methods.

[0008] Figure 2 This is a block diagram of a cache memory according to some implementation methods.

[0009] Figures 3A-3B An example of storing a graph structure in a graph cache is shown.

[0010] Figure 4 This is a flowchart of a graph search method based on some implementation methods.

[0011] Figure 5 It is a flowchart of a graphical programming method based on some implementation methods.

[0012] Figure 6 It is a flowchart of a graph processing method according to some implementation methods.

[0013] Unless otherwise stated, corresponding numbers and symbols in the different figures generally refer to corresponding parts. These figures are drawn to clearly illustrate relevant aspects of this disclosure and are not necessarily drawn to scale. Detailed Implementation

[0014] The following disclosure provides numerous examples for implementing different features. Specific examples of components and layouts are described below to simplify the content of this disclosure. Of course, these are merely examples and are not intended to be limiting.

[0015] A graph represents the relationships between sets of entities. Specifically, a graph includes nodes (corresponding to entities) and edges (corresponding to the relationships between entities). Each of these elements of a graph may include an embedding. A node embedding includes one or more pieces of information about that node.

[0016] Graph Neural Networks (GNNs) consist of multiple layers. When processing graphs using GNNs, the network runs in multiple iterations, where each layer updates the embeddings of nodes in the graph. At each layer, the GNN aggregates information from neighboring nodes, updates the embedding of each node, and then moves to the next layer. This process continues for a fixed number of layers, or until a convergence criterion is met.

[0017] During processing using GNNs, the graph structure remains unchanged. In other words, the graph structure (represented by edges connecting nodes) does not change as node embeddings are updated. One way to represent the graph structure used for processing is to use an adjacency matrix. However, adjacency matrices can consume a lot of memory and may be sparsely filled (especially for large graph structures), leading to inefficient memory utilization.

[0018] This disclosure describes a cache for efficiently storing graph structures, also referred to as a "graph structure cache" or simply a "graph cache." The graph structure cache can be used in computing systems to accelerate graph processing via GNNs. The graph cache differs from the general-purpose memory of a computing system. While the embeddings of graph nodes are stored in the computing system's memory, the graph structure is stored in the graph cache. The graph cache may include a Content Addressable Memory (CAM) array, which is suitable for efficiently representing graph structures. Notably, representing graph structures in a CAM array can be more efficient than in an adjacency matrix. Therefore, the amount of memory used by the computing system to process graphs using GNNs can be reduced.

[0019] In some implementations, the graph cache includes a content-addressable memory (CAM) array and a random access memory (RAM) array. The CAM array stores the edge values ​​of the graph structure, and the RAM array stores the memory addresses of the embeddings of neighboring nodes in the graph structure. The memory addresses are the locations of the computation system's memory. During GNN processing, the identifier of the target node of the graph structure is provided to the CAM array. The respective word lines of the RAM array are activated by the CAM array, causing the graph cache to output the memory addresses of the embeddings of the target node's neighboring nodes. The embeddings of the neighboring nodes can then be accessed directly at the memory addresses in the computation system's memory. The graph cache may also include a multiple match resolver (MMR). When multiple match lines of the CAM array are activated, the MMR can serially activate the corresponding word lines of the RAM array, thereby serially outputting the corresponding memory addresses through the RAM.

[0020] Figure 1 This is a block diagram of a computing system 100 according to some embodiments, which can be used to process graphs using a GNN. The computing system 100 can be implemented in an electronic device. Examples of electronic devices include servers, desktop computers, laptop computers, mobile devices, gaming systems, etc.

[0021] The computing system 100 can be used in any data processing scenario, including standalone hardware, mobile applications, or combinations thereof. Furthermore, the computing system 100 can be used in computing networks, such as public cloud networks, private cloud networks, hybrid cloud networks, other forms of networks, or combinations thereof. In one example, the method provided by the computing system 100 may be provided as a service on the network by a third party, for example. The computing system 100 can be implemented on one or more hardware platforms, wherein modules within the system can execute on one or more platforms. Such modules can run on various forms of cloud and hybrid cloud technologies, or be provided as Software-as-a-Service (SaaS) that can be implemented in the cloud or on-premises.

[0022] To achieve its desired functionality, the computing system 100 includes various hardware components. These hardware components may include a processor 102, one or more interfaces 104, a memory 106, and a graph cache memory 200. These hardware components may be interconnected via multiple buses and / or network connections. In one example, the processor 102, interface 104, memory 106, and graph cache memory 200 may be communicatively coupled via bus 108.

[0023] Processor 102 retrieves executable code from memory 106 and executes the executable code. When the executable code is executed by processor 102, the executable code enables processor 102 to perform any of the functions described herein. Processor 102 may be a microprocessor, application-specific integrated circuit, microcontroller, etc.

[0024] Interface 104 enables processor 102 to interface with various other hardware components external to and internal to computing system 100. For example, interface 104 may include interfaces for input / output devices such as display devices, mice, keyboards, etc. Additionally or alternatively, interface 104 may include interfaces for external storage devices or multiple network devices such as servers, switches and routers, client devices, other types of computing devices, and combinations thereof.

[0025] Memory 106 may include various types of memory, including volatile and non-volatile memory. For example, memory 106 may include random access memory (RAM), read-only memory (ROM), hard disk drive (HDD), and / or similar devices. Different types of memory can be used for different data storage needs. For example, in some examples, processor 102 may boot from ROM, maintain non-volatile storage in HDD, execute program code stored in RAM, and store data being processed in RAM. Memory 106 may include non-transitory computer-readable media storing instructions executed by processor 102. One or more modules in computing system 100 may be embodied, in part or in whole, as software and / or hardware for performing any of the functions described herein. Memory 106 may include general-purpose memory for storing data for processor 102.

[0026] Graph cache 200 is an accelerator for processing graphs using GNNs. Graph cache 200 differs from processor 102 and memory 106, specifically, it differs from the caches of processor 102 and memory 106. Furthermore, the architecture of graph cache 200 differs from that of memory 106. In some embodiments, graph cache 200 includes a content-addressable memory (CAM) array and a random access memory (RAM) array. The CAM array can be programmed with values ​​corresponding to the edges of the graph structure. Therefore, the graph structure can be stored in the CAM array. The CAM array is capable of storing graph structures more efficiently than general-purpose memory (e.g., memory 106). Therefore, using graph cache 200 can improve the efficiency of computing system 100.

[0027] As described in more detail later, the graph cache 200 can be used by the processor 102 to accelerate graph processing using GNNs. The processor 102 can store the graph structure in the graph cache 200 and also store the node embeddings of the graph in memory 106. During processing, the processor 102 can update the embedding of the target node by aggregating the embeddings of neighboring nodes adjacent to the target node in the graph structure. The processor 102 can obtain the embeddings of neighboring nodes using the graph cache 200. Specifically, the processor 102 can provide the target node identifier to the graph cache 200. In response, the graph cache 200 returns the memory address for the neighboring node embeddings to the processor 102. This memory address is the location of memory 106. The processor 102 can then directly access the neighboring node embeddings at the memory address provided by the graph cache 200 (from memory 106). Therefore, the graph cache 200 can be used for lookup operations, where the memory address of the neighboring embedding can be looked up once based on the target node identifier.

[0028] Figure 2 This is a block diagram of a cache memory 200 according to some implementation methods. Figure 1 An implementation example of a graph cache memory 200 in a computing system 100 is shown. In this embodiment, the graph cache memory 200 includes a CAM array 202, a register 204, a multi-match parser 206, and a RAM array 208. Furthermore, the graph cache memory 200 may also include peripheral circuitry (not shown separately) for operating different components of the graph cache memory 200. Example peripheral circuitry includes read / write circuitry for the CAM array 202, read / write circuitry for the RAM array 208, a clock circuitry for performing timing operations in the graph cache memory 200, control circuitry for controlling the components of the graph cache memory 200, etc.

[0029] As previously mentioned, an edge is a connection between two adjacent nodes in a graph structure. The graph cache 200 stores the graph structure by storing the values ​​of the edges representing the graph structure. Specifically, the graph cache 200 stores multiple edge connections. Each edge connection is a mapping between the identifier of a first node and the memory address of a second node. Therefore, each edge connection represents an edge between the first node and the second node. During operation, a target node is provided to the graph cache 200. In response to receiving the identifier of the target node, the graph cache 200 returns the memory addresses of the mapped nodes connected to the target node via edges in the graph structure.

[0030] CAM array 202 includes CAM cells 210, search lines SL, and matching lines ML. CAM cells 210 are arranged in rows and columns. Search lines SL are arranged along the columns of CAM cells 210 and correspond to the columns of CAM cells 210. Matching lines ML are arranged along the rows of CAM cells 210 and correspond to the rows of CAM cells 210. CAM cells 210 can be ternary CAM (TCAM) cells. TCAM cells are suitable for storing low values ​​(such as binary 0), high values ​​(such as binary 1), or wildcard values. Examples of TCAM cells include SRAM-based TCAM cells, ReRAM-based TCAM cells, memristor-based TCAM cells, etc.

[0031] A row of CAM cells 210 can be referred to as CAM row 212. Each CAM row 212 stores a vector containing multiple values ​​(stored in CAM cells 210 of CAM row 212). The matching line ML corresponds to CAM row 212. The search line SL corresponds to CAM cells 210 of CAM row 212.

[0032] During a write operation, a write vector of a value (e.g., voltage) is applied to the CAM cells 210 of CAM row 212 via bit lines. Based on the corresponding value of the write vector, each CAM cell 210 of CAM row 212 can be set to a low value, a high value, or (optionally) a wildcard value. Thus, a vector of values ​​is stored in each CAM row 212.

[0033] During a read operation, a read vector of a value (e.g., voltage) is applied to CAM row 212 via search line SL. Each CAM cell 210 in CAM row 212 compares its stored value with the corresponding value of the read vector. CAM row 212 with a stored value that matches the corresponding value of the read vector activates its corresponding match line ML. In other words, during a read operation, CAM array 202 receives a read vector, searches for the read vector in CAM row 212, and activates the match line ML of the CAM row 212 that stores the read vector. The match line ML of the CAM row 212 that stores a vector different from the read vector is deactivated.

[0034] As described in more detail later, the identifiers of the nodes in the graph structure are stored in CAM rows 212 of the CAM array 202. The identifiers can be vectors of values ​​stored in CAM cells 210 of CAM row 212. The CAM array 202 is adapted to receive the identifiers of target nodes in the graph structure (on search line SL). Furthermore, the CAM array 202 is adapted to search for the received identifiers in CAM rows 212 and activate matching lines ML corresponding to the CAM row 212 where the identifier is stored. Each of the CAM rows 212 storing the identifiers of the target nodes corresponds to an edge connecting the target node to an adjacent node.

[0035] Register 204 is connected to CAM array 202, specifically to the match line ML of CAM array 202. Register 204 may include multiple latches, such as latches for each CAM row 212. Register 204 is configured to store match vectors corresponding to the match lines ML of CAM array 202. Each value of the match vector corresponds to the match line ML and can be a low value (e.g., binary 0) or a high value (e.g., binary 1). Therefore, the match vector includes high values ​​(corresponding to active match lines ML) and low values ​​(corresponding to deactivated match lines ML). Register 204 is used to latch the result of the read operation when a vector is searched in CAM array 202 during a read operation. Therefore, the match vector (reflecting the result of the read operation) stored in register 204 can persist even if the search line SL is reset.

[0036] A multi-match parser 206 is connected to register 204. The output of register 204 can be connected to the input of multi-match parser 206. Multi-match parser 206 is suitable for resolving conflicts that may arise when multiple matching lines ML of CAM array 202 are activated during a read operation. In some implementations, multi-match parser 206 is a match token multi-match parser. However, any suitable logic gate network can be used to implement multi-match parser 206. To resolve conflicts during a read operation, multi-match parser 206 converts the matching vector stored in register 204 into one or more output vectors.

[0037] The multi-match parser 206 is adapted to serially generate output vectors corresponding to the high values ​​of the matching vectors. For each high value in the matching vector, one output vector is generated. Each value of the output vector is a low value except for the high value of the matching vector to which it corresponds. For example, if the matching vector includes a first high value and a second high value (corresponding to two activated matching lines ML), then two output vectors are generated: a first output vector with a high value corresponding to the first high value of the matching vector, and a second output vector with a high value corresponding to the second high value of the matching vector. The output vectors are (serially) provided to the RAM array 208.

[0038] RAM array 208 includes RAM cells 214, word lines WL, and bit lines BL. RAM cells 214 are arranged in rows and columns. Word lines WL are arranged along the rows of RAM cells 214 and correspond to the rows in RAM cells 214. Bit lines BL are arranged along the columns of RAM cells 214 and correspond to the columns in RAM cells 214. RAM cells 214 may be static random access memory (SRAM) cells.

[0039] A row of RAM cells 214 can be referred to as RAM row 216. Each RAM row 216 stores a vector containing multiple values ​​(stored in RAM cells 214 of RAM row 216). Word line WL corresponds to RAM row 216. Bit line BL corresponds to RAM cells 214 of RAM row 216.

[0040] During a write operation, a write vector of a value (e.g., voltage) is applied to RAM cells 214 of RAM row 216 via bit line BL and word line WL. Based on the corresponding value of the write vector, each RAM cell 214 of RAM row 216 can be set to a low or high value. Therefore, a vector is stored in each RAM row 216.

[0041] During a read operation, the word line WL of RAM row 216 is activated. The RAM cell 214 of RAM row 216 outputs its stored vector on the bit line BL.

[0042] The match line ML of CAM array 202 is connected (via register 204 and multi-match parser 206) to the respective word line WL of RAM array 208. Multi-match parser 206 is adapted to serially activate the word lines WL of RAM array 208, which correspond to the activated match line ML of CAM array 202. In other words, when the match line ML of CAM row 212 is activated, the corresponding word line WL of RAM row 216 is activated, causing RAM row 216 to output its stored vector on bit line BL.

[0043] As described in more detail later, memory addresses are stored in RAM row 216 of RAM array 208. Each memory address is a location of memory outside the graph cache memory 200, where the node embedding is stored. When the identifier of a node in the graph structure is stored in CAM row 212 of CAM array 202, the memory address stored in RAM row 216 of RAM array 208 points to the embedding of the corresponding neighboring node. Specifically, CAM row 212 may store the identifier of a target node, and the corresponding RAM row 216 may store the memory address pointing to the embedding of the neighboring node of the target node. Therefore, when the identifier of the target node is provided to CAM array 202, CAM row 212 including the identifier activates its matching line ML, causing the word line WL of the corresponding RAM row 216 to be activated, which causes RAM row 216 (on bit line BL) to output the memory address of the neighboring node of the target node.

[0044] The graph cache 200 may include ports for external connections. In some embodiments, the graph cache 200 further includes an input port 218 and an output port 220. The input port 218 is connected to the search lines SL of the CAM array 202. The output port 220 is connected to the bit lines BL of the RAM array 208.

[0045] Figures 3A-3B An example of storing a graph structure in the graph cache is shown. Figure 3A is a schematic diagram of an example graph structure 300, Figure 3B is a schematic diagram of the value stored in the graph cache 200 (representing the graph structure 300). The CAM array 202 stores the identifiers of the nodes of the graph structure 300, while the RAM array 208 stores the memory addresses of the adjacent embeddings of the nodes.

[0046] Figure 3B An example of a read operation is also shown. In this example, the target node is node 1 of the graph structure 300. The identifier of the target node (e.g., 1) is provided to the CAM array 202. The row including this identifier activates its match line. The match outputs of the CAM array 202 are shown as dashed lines. As a result of these outputs being activated, the corresponding rows of the RAM array 208 are serially activated (by the multi-match resolver 206), which causes the RAM array 208 to serially output the memory addresses of the adjacent nodes of the target node. In the example where node 1 is connected to node 2 and node 3 in the graph structure 300, providing the identifier of node 1 to the CAM array 202 causes the RAM array 208 to serially output the memory address ADDR2 (k) and the memory address ADDR3 of node 3 (k) . The embeddings of node 2 and node 3 are stored at these memory addresses.

[0047] Figure 4 is a flowchart of a graph search method 400 according to some embodiments. The graph search method 400 will be described in conjunction with Figure 1 and Figure 2 The graph search method 400. The graph search method 400 may be executed by the graph cache 200. Specifically, the graph cache 200 may execute the graph search method 400 to search for edge connections in the stored graph structure. In response to receiving the identifier of the target node, the memory addresses of each adjacent node of the target node will be returned by the graph cache 200.

[0048] The high-speed cache memory 200 can perform step 402 of searching for the identifier of the target node in the CAM array 202. The identifier can be received from input port 218 and can therefore be provided on the search line SL of the CAM array 202. The identifier can be a vector provided on the search line SL during a read operation. The matching vector is output by the CAM array 202.

[0049] The high-speed cache memory 200 can perform step 404 of storing the matching vector in register 204. The matching vector has high values ​​corresponding to CAM row 212 storing received identifiers and low values ​​corresponding to CAM row 212 storing different identifiers. Each high value in the matching vector corresponds to an edge connection between the target node and its neighboring nodes. The matching vector is provided by register 204 to at most match parsers 206.

[0050] The high-speed cache memory 200 can perform step 406 of generating the output vector. The output vector can be generated by the multi-match parser 206. The output vector corresponds to a high value in the matching vector. In some embodiments, the output vector corresponds to the lowest spatially lowest high value in the matching vector. Except for the high value of the matching vector to which the output vector corresponds, each value of the output vector is a low value.

[0051] The cache memory 200 can perform step 408 of providing an output vector to the RAM array 208. The output vector can be provided to word lines WL of the RAM array 208 by a multi-match parser 206. Since the output vector includes only one high value, only one word line WL is activated by the multi-match parser 206. The RAM row 216 corresponding to the activated word line WL outputs its stored value (e.g., the memory address of an adjacent node) on bit line BL. Therefore, the memory address can be provided at output port 220.

[0052] The high-speed cache memory 200 can perform step 410, which removes the high value of the output vector from the matching vector stored in register 204. The high value can be removed from the matching vector by performing a bitwise AND operation using the inverse of the output vector, and then the result of the operation is stored back in register 204.

[0053] The graph cache 200 can perform step 412 to determine whether any high values ​​still exist in the matching vector. In response to the matching vector including additional high values, the graph cache 200 repeats steps 406-412. These steps can be performed iteratively until there are no more high values ​​in the matching vector. The number of iterations can be equal to the number of high values ​​in the matching vector.

[0054] Examples of matching vectors and corresponding output vectors are shown in Table 1. In this example, the target node identifier matches three CAM rows 212 of the CAM array 202. Therefore, the matching vector initially stored in register 204 includes three high values ​​(corresponding to the three active matching lines ML in CAM row 212), so three iterations of steps 406-412 are performed. The output vector generated by the multi-match parser 206 is different in each iteration. The matching vector stored in register 204 is modified in each iteration.

[0055]

[0056] Figure 5 This is a flowchart of a graphical programming method 500 based on some implementation methods. (Combined with...) Figure 1 and Figure 2 A graph programming method 500 is described. The graph programming method 500 can be executed by a computing system 100. Specifically, a processor 102 can execute the graph programming method 500 to store the edges of the graph structure (e.g., the mapping from target nodes to adjacent nodes) in a graph cache memory 200.

[0057] Processor 102 can execute step 502 of programming the CAM array 202 of graph cache memory 200 with the identifier of the target node. The identifier can be a vector stored in CAM row 212 during a write operation to CAM array 202. CAM array 202 can be programmed with the identifier of the target node as described above. Figure 2 Program in a similar manner as described.

[0058] Processor 102 can execute step 504 of programming the RAM array 208 of the graph cache memory 200 using the memory addresses of adjacent nodes. The memory address is the location of memory 106. The memory address can be a vector stored in RAM row 216 during a write operation to RAM array 208. RAM array 208 can be programmed with the previously defined memory address. Figure 2 Program in a similar manner as described.

[0059] Multiple edges of the graph structure can be stored in the graph cache memory 200. Specifically, when the target node has multiple neighboring nodes, the memory addresses of each neighboring node can be stored in their respective RAM rows 216, and the identifier of the target node can be stored in each CAM row 212 corresponding to these RAM rows 216. In other words, when multiple memory addresses are stored in the RAM array 208 (in step 504), the multiple CAM rows 212 of the CAM array 202 can be programmed with the identifier of the target node (in step 502).

[0060] Figure 6This is a flowchart of a graph processing method 600 according to some implementation methods. (The text will be combined with...) Figure 1 and Figure 2 Graph processing method 600 is described. Graph processing method 600 can be executed by computing system 100. Specifically, processor 102 can execute graph processing method 600 when processing a graph whose structure is stored in graph cache memory 200 (using GNN).

[0061] Processor 102 may execute step 602, which retrieves the memory addresses of the neighboring nodes of the target node from graph cache 200. As previously described, graph cache 200 stores a graph structure including the target node and its neighboring nodes. Processor 102 may provide the identifier of the target node to graph cache 200, and in response, may receive the memory addresses of the neighboring nodes from graph cache 200. The received memory addresses are the location of memory 106. As previously described, memory 106 is different from graph cache 200.

[0062] In some implementations, obtaining the memory address includes searching for an identifier of the target node in the CAM array 202 of the graph cache memory 200. In response to the CAM row 212 storing the identifier, some match lines ML of CAM row 212 are activated. Corresponding word lines WL of RAM row 216 are activated. The activated word lines WL of RAM row 216 correspond to the activated match lines ML of CAM row 212. The RAM row 216 with the activated word lines WL stores the memory address. The word lines WL of RAM row 216 can be activated serially (e.g., by the multi-match parser 206).

[0063] Processor 102 can execute step 604, which accesses the adjacent embeddings of adjacent nodes at memory addresses in memory 106. As previously described, the memory addresses returned by graph cache 200 are locations in memory 106. Processor 102 can directly access node embeddings at these locations in memory 106.

[0064] Processor 102 can perform step 606 of updating the target embedding of the target node by aggregating the neighbor embeddings of neighboring nodes. One layer of the GNN can be used to update the target embedding. The updated target embedding of the target node can be based on the previous embeddings of the target node and the neighbor embeddings of neighboring nodes.

[0065] Processor 102 can perform step 608, storing the updated target embedding of the target node in memory 106. The updated target embedding can be stored back in memory 106 at the location of the target node's previous embedding. Then, when aggregating the neighboring embeddings of other nodes in a layer of the GNN, the updated embedding can be used.

[0066] The implementation method offers advantages. The graph structure can be stored in the graph cache 200 by storing edge connections. Each edge connection is a mapping between the identifier of the first node and the memory address of the second node. The graph structure can be stored in the CAM array 202 and the RAM array 208. In this way, the graph structure can be represented more efficiently than an adjacency matrix. Therefore, the amount of memory used by the computing system 100 when processing graphs using a GNN can be reduced.

[0067] The foregoing outlines features of several examples to enable those skilled in the art to better understand various aspects of this disclosure. Various modifications and combinations of the illustrative examples and other examples will be apparent to those skilled in the art upon reference to the specification. Therefore, the appended claims cover any such modifications.

Claims

1. A graph cache, comprising: a content addressable memory (CAM) array including CAM rows and match lines corresponding to the CAM rows, the CAM array configured to receive an identifier of a target node of a graph structure, search the identifier in the CAM rows, and activate the match line in the match lines corresponding to the CAM row storing the identifier; a random access memory (RAM) array including RAM rows and word lines corresponding to the RAM rows; and a multi-match resolver connected to the CAM array and the RAM array, the multi-match resolver configured to serially activate the word lines of the RAM array corresponding to the activated match lines of the CAM array.

2. The graph cache memory of claim 1, wherein, The CAM array further includes a search line, and the CAM rows receive the identifier on the search line.

3. The graph cache of claim 2, further comprising: an input port connected to the search line.

4. The graph cache of claim 1, wherein, The RAM array further includes bit lines, and the RAM array is configured to output memory addresses of neighboring nodes of the target node on the bit lines when the word lines are activated.

5. The graph cache of claim 4, further comprising: an output port connected to the bit lines.

6. The graph cache of claim 1, further comprising: a register connected to the match lines of the CAM array, an output of the register connected to an input of the multi-match resolver.

7. The graph cache of claim 6, wherein, The register is configured to store a match vector including high values corresponding to the activated match lines of the CAM array.

8. The graph cache of claim 7, wherein, The multi-match resolver is configured to serially generate an output vector corresponding to the high values of the match vector, and provide the output vector to the RAM array.

9. The graph cache of claim 1, wherein, The multi-match resolver includes a match token multi-match resolver.

10. The graph cache of claim 1, wherein, The CAM array includes ternary content addressable memory cells, and the RAM rows include static random access memory cells.

11. A method based on the graph cache of claim 1 implemented by a computing system, the method comprising: obtaining a memory address of a neighboring node of a target node from a graph cache of the computing system, the graph cache storing a graph structure including the target node and the neighboring node, the neighboring node connected to the target node in the graph structure, the memory address a location of a memory of the computing system, the memory different from the graph cache; accessing a neighboring embedding of the neighboring node at the memory address of the memory; updating a target embedding of the target node by aggregating the neighboring embedding of the neighboring node; and storing the target embedding of the target node to the memory.

12. The method of claim 11, further comprising: storing the graph structure to the graph cache.

13. The method of claim 12, wherein, Storing the graph structure to the graph cache includes: programming a content addressable memory array of the graph cache with the identifier of the target node; and programming a random access memory array of the graph cache with the memory address.

14. The method of claim 11, wherein, obtaining the memory address includes: searching for the identifier of the target node in a content addressable memory (CAM) array of the graph cache, a match line of a CAM row of the CAM array being activated in response to a CAM row storing the identifier; and activating a word line of a random access memory (RAM) row of a RAM array of the graph cache, the word line of the RAM row corresponding to the match line of the CAM row, the RAM row storing the memory address.

15. The method of claim 14, wherein, the word line of the RAM row is activated serially.

16. The method of claim 11, wherein, obtaining the memory address includes: providing an identifier of the target node to the graph cache; and receiving the memory address from the graph cache.

17. A computing system comprising: a processor; a graph cache, wherein the graph cache is the graph cache of claim 1; a memory, the memory being different from the graph cache, the memory comprising a non-transitory computer readable medium storing instructions that, when executed by the processor, cause the processor to: store a graph structure to the graph cache; provide an identifier of a target node of the graph structure to the graph cache; receive a memory address of a neighboring node of the target node from the graph cache, the neighboring node being connected to the target node in the graph structure, the memory address being a location of the memory; access a neighboring embedding of the neighboring node at the memory address of the memory; update a target embedding of the target node by aggregating the neighboring embedding of the neighboring node; and store the target embedding of the target node to the memory.

18. The computing system of claim 17, wherein, the graph cache has a different architecture than the memory.

19. The computing system of claim 17, wherein, the graph cache comprises: a content addressable memory (CAM) array comprising a match line; a register connected to the match line of the CAM array; a random access memory (RAM) array comprising a word line; and a multi-match resolver connected to the word line of the RAM array, the register being connected to the multi-match resolver.

20. The computing system of claim 19, wherein, the instructions to store the graph structure to the graph cache comprise: programming the CAM array with the identifier of the target node; and programming the RAM array with the memory address of the neighboring node. the instructions to store the graph structure to the graph cache comprise: programming the CAM array with the identifier of the target node; and programming the RAM array with the memory address of the neighboring node.

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