Method for removing residues from surface of substrate

Abstract

The invention relates to the removal of a temporary polymeric bonding layer (16) from a dielectric or hybrid bonding surface of a process wafer (1) comprising a plurality of dies (3) bonded to other dies or to a substrate by hybrid bonding or direct dielectric-to-dielectric bonding. An auxiliary layer (15) is generated before a polymer bonding layer (16) is generated on the die side of the wafer, i.e. On the bonding surface of the die (3). According to the invention, the auxiliary layer (15) is formed from a nitride or carbide of a transition metal, such as titanium nitride or tungsten carbide. These materials enable removal of the auxiliary layer (15) comprising any polymer residue without negatively affecting the dielectric or mixed dielectric / metal bonding surface (8) of the die (3).

Description

Technical Field

[0001] The present invention relates to semiconductor processing, and more particularly to cleaning steps applied during various stages of semiconductor manufacturing and processing. Background Art

[0002] Semiconductor processing utilizes different types of polymers. Two applications of polymer layers are as photoresist (PR) layers [primarily deep ultraviolet (DUV) photoresist layers] and temporary bonding material (TBM) layers. The properties and thicknesses of such polymer layers vary with the type of DUV PR, which range from 1 μm to about 150 μm, and also with the type of TBM (whether thermoplastic or elastomeric), which range from 1 μm to about 100 μm. These polymers can be coated on a target 300 mm wafer for different purposes: lithography, temporary bonding between the target wafer and the carrier wafer, dicing protection layer, etc. Such polymers are sacrificial and must be stripped before subsequent steps are performed, such as before hybrid bonding between metal-metal (e.g., Cu-Cu, Al-Al) and dielectric-dielectric (e.g., SiO 2 -SiO 2 、SiCN-SiCN、SiN-SiN). The stripping of such polymers is carried out using one or more organic solvents or aqueous chemicals, but polymer residues may remain on the surface after these stripping steps. For example, when such residues remain on the bonding surface used for hybrid bonding or direct dielectric-to-dielectric bonding, they may be the cause of microvoids in the bonding area.

[0003] However, it is very difficult to remove such residues without etching the surface. For example, when the surface is a hybrid bonding surface (including dielectric material having a metal contact pad coplanar therewith), the applicable chemicals for removing the temporary bonding layer from such a surface are restricted by strictly defined conditions to avoid damaging the metal and / or dielectric. Under such conditions, it is essentially inevitable that polymer residues remain on the surface. The stripping of the polymer also causes surface modification of the metal, which will manifest as corrosion in downstream integration steps.

[0004] Known solutions to these problems include providing the sacrificial layer on the surface before directly generating the polymer layer on the sacrificial layer and stripping the polymer relative to the sacrificial layer such that polymer residues remain on the sacrificial layer. Removal of the sacrificial layer also removes the polymer residues. Patent publications EP3563411 and EP1936678 describe such methods in the context of dielectric-to-dielectric or hybrid bonding methods. In these documents, sacrificial layers formed of silicon oxide, aluminum, or titanium are cited. However, these materials cannot meet the increasingly stringent requirements for low roughness and flatness of the bonding layer in today's bonding technologies. This is because removal of these materials may cause the dielectric bonding layer of the hybrid bonding surface to become rough and / or oxidation of the metal pads. Summary of the Invention

[0005] The present invention relates to a method as disclosed in the appended claims. According to the present invention, a temporary polymer layer required on a substrate in a semiconductor processing step is generated on an auxiliary layer, which is generated on the substrate before the temporary polymer layer is formed. The auxiliary layer is removable from the substrate surface and substantially leaves no residue on the surface. After performing several processing steps on the substrate, the polymer layer and the auxiliary layer are removed. Removal of the polymer layer may leave residues on the auxiliary layer, but removal of the latter leaves the surface substantially residue-free. The present invention specifically relates to removing a temporary polymer bonding layer from a dielectric or hybrid bonding surface of a processed wafer, the processed wafer including a plurality of dies bonded to other dies or to a substrate by means of hybrid bonding or direct dielectric-to-dielectric bonding. An auxiliary layer is generated on the die side of the wafer, i.e., on the bonding surface of the die, before the polymer bonding layer is generated. According to the present invention, the auxiliary layer is formed of a nitride or carbide of a transition metal, such as titanium nitride or tungsten carbide. These materials can remove the auxiliary layer including any polymer residues without negatively affecting the dielectric or hybrid dielectric / metal bonding surface of the die. Therefore, the present invention can remove the temporary bonding material from the dielectric or hybrid bonding surface, leaving substantially no polymer residues, thereby avoiding voids during hybrid bonding or dielectric-to-dielectric bonding and not increasing the roughness of the dielectric bonding surface or oxidizing the metal regions in the bonding surface.

[0006] The present invention generally relates to a semiconductor processing method, which includes a coating step in which a temporary polymer layer is generated on a substrate, and a removal step after the coating step and after performing one or more additional processing steps on the substrate, in which the temporary layer is removed, or in which a remaining portion of the layer is removed after performing the one or more additional processing steps, wherein:

[0007] - Prior to the coating step, an auxiliary layer is directly generated on the surface of the substrate, and the auxiliary layer can be removed from the surface, leaving substantially no residue on the surface.

[0008] - A temporary polymer layer is directly generated on the auxiliary layer.

[0009] - The removal step includes:

[0010] o Selectively removing the temporary polymer layer or a portion thereof relative to the auxiliary layer.

[0011] o Selectively removing or substantially removing the auxiliary layer relative to the surface of the substrate, thereby producing a substrate surface substantially free of residue. The phrase "removing or substantially removing" includes completely removing the polymer or removing most of the polymer with only a small amount remaining, for example, in the form of polymer residues.

[0012] Specifically, the method according to the present invention includes:

[0013] - Providing the substrate in the form of a processed wafer, the processed wafer including a die side and a back side and including a plurality of dies on the die side, the dies including bonding surfaces adapted to directly dielectric-to-dielectric or hybrid bond the dies to a target substrate.

[0014] - Thereafter, an auxiliary layer is directly generated on the bonding surface (8) of the die (i.e., the surface of the substrate), and the auxiliary layer can be removed from the bonding surface, leaving substantially no residue on the bonding surface.

[0015] - Thereafter, a temporary polymer layer in the form of a temporary polymer bonding layer is directly generated on the auxiliary layer.

[0016] - Thereafter, the processed wafer is temporarily bonded to the carrier substrate by removably bonding the temporary bonding layer to the carrier substrate, processing steps are performed on the back side of the processed wafer, and the processed wafer is released from the carrier substrate such that the auxiliary layer and the temporary bonding layer remain on the die side of the processed wafer.

[0017] - Thereafter, the temporary polymer layer is selectively removed or substantially removed relative to the auxiliary layer.

[0018] - Thereafter, the auxiliary layer is selectively removed relative to the bonding surface, thereby producing a bonding surface substantially free of residue.

[0019] Wherein, the auxiliary layer is formed of a nitride or carbide of a transition metal.

[0020] According to an embodiment of the present invention, the auxiliary layer is formed of a material selected from the group consisting of titanium nitride, hafnium nitride, tungsten nitride, molybdenum nitride, and tungsten carbide.

[0021] According to one embodiment, the bonding surface of the die is suitable for hybrid bonding and includes metal contact pads embedded in a dielectric material layer.

[0022] According to one embodiment, the metal contact is a Cu contact pad and the dielectric material layer is a SiCN layer.

[0023] According to one embodiment, the temporary polymer bonding layer is removed or substantially removed by applying a solvent to the polymer layer.

[0024] According to one embodiment, after selectively removing the temporary polymer bonding layer or a portion thereof relative to the auxiliary layer, a residue of the polymer layer remains on the auxiliary layer.

[0025] According to one embodiment, the auxiliary layer is removed by wet etching.

[0026] According to one embodiment, the thickness of the auxiliary layer is between 5 nm and 100 nm. Brief Description of the Drawings

[0028] Figures 1a to 1c Shows a processed wafer and the layout of a plurality of dies on the wafer.

[0029] Figures 2 to 9 Shows the method steps illustrating an exemplary embodiment of the present invention. Detailed Description

[0030] The present invention will be described based on exemplary embodiments, but it does not limit the scope of the present invention. All references to shapes, dimensions or materials are cited by way of example only.

[0031] Figure 1a Shows a processed wafer 1, which may be a crystalline silicon wafer as is well known in the art, for example, a standard processed wafer with a diameter of 300 mm and a thickness of several hundred micrometers. A scribe line 2 divides the wafer surface into a plurality of die regions on the front side of the wafer, and the underside of the front side of the wafer is also referred to as the die side of the wafer. Each die region includes a semiconductor die 3, which may be an integrated circuit produced according to a given processing sequence, and includes contacts on its upper surface for electrically connecting the integrated circuit. Four adjacent dies 3 are shown in the magnified image in Figure 1b . The surface area of each die 3 may be approximately several tens of square millimeters. Details of the front surface of the die 3 are not shown because these details are indistinguishable at the scale of the image in Figure 1b . The scribe line 2 is wide enough to be able to divide the finished chips and can also be used as an area for printing auxiliary features (such as metrology marks).

[0032] As shown in Figure 1cAs shown in the enlarged view of point 5 in the surface area of the die, the method of the exemplary embodiment of the present invention is described based on a micron-sized cross-section along line A-A in a die 3. In Figure 1c it can be seen that the upper surface of the die is formed by an array of copper contact pads 6 embedded in a dielectric layer 7. Figure 2 The cross-sectional view along line A-A is further enlarged in. Only the thin upper part of the wafer 1 is shown, and the thickness of this part is about a few microns.

[0033] As Figure 2 shown in, the die 3 is an integrated circuit die, which includes a bulk Si part 10, a front-end-of-line (FEOL) part 11 including active devices (such as transistors or diodes), and a back-end-of-line (BEOL) part 12, which is a multi-layer structure of interconnecting electrical conductors and vias, designed to provide signal routing to the active devices and embedded in an electrically isolating dielectric material. The Cu contact pads 6 and the dielectric layer 7 are located on top of the BEOL part 12, where the contact pads 6 are electrically connected to the top layer of the BEOL part. Hereinafter, the dielectric layer 7 is regarded as a SiCN layer, but other materials are also possible, such as silicon oxide. The layer 7 is coplanar with the top surface of the Cu contact pads 6. The coplanar surface of the pads 6 and the layer 7 is hereinafter referred to as the bonding surface 8 of the die 3.

[0034] In the plane of the wafer 1, the pads 6 have a rectangular cross-section with a width of about 2 μm. The thickness of the pads 6 is less than 1 μm. The distance between adjacent contact pads 6 is of the same order of magnitude as the width of the pads 6. As described above, these shapes and dimensions do not limit the scope of the present invention, but are only used as examples.

[0035] The pads 6 can be processed by well-known damascene-type processing techniques for producing BEOL-type interconnect structures. Generally, there is a diffusion barrier (not shown in Figure 2 ) between the pads 6 and the dielectric layer 7.

[0036] The bonding surface 8 is intended to be bonded to a similar bonding surface of another die by a bonding technique called hybrid bonding, in which direct Cu-Cu bonds are formed between the corresponding Cu contacts and direct SiCN-SiCN bonds are formed between the respective SiCN layers. However, before performing this bonding step, another processing step is also carried out, which includes thinning the bulk Si wafer 10 from the back side. For this purpose, a temporary bonding material (TBM) layer is coated on the die side of the wafer 1. According to the present invention, as Figure 3As shown, the TBM layer is not directly deposited on the bonding surface 8. Instead, an auxiliary layer 15 is first deposited on the bonding surface, and then the TBM layer 16 is deposited. The TBM layer is typically an organic polymer layer that can form a strong temporary bond and can be removed by a solvent. Elastomers or thermoplastic polymers are suitable materials for this purpose. The thickness of the TBM layer 16 shown in the exemplary embodiment is about 4 μm. Generally, the thickness of this layer can be, for example, between 1 μm and 100 μm, as is known in the art. The TBM layer can be applied by spin-coating a polymer material onto the auxiliary layer 15.

[0037] According to the present invention, the auxiliary layer is formed of a nitride or carbide of a transition metal. For example, the auxiliary layer 15 can be a TiN layer, but other materials are also applicable when applied to a dielectric or hybrid bonding surface (such as a hybrid Cu / SiCN surface). In addition to titanium nitride, preferred materials include hafnium nitride, molybdenum nitride, tungsten nitride, and tungsten carbide. These materials can be removed from the hybrid surface (such as a Cu / SiCN surface) with substantially no erosion of the constituent materials of the hybrid surface, i.e., without increasing the roughness of the dielectric bonding portion of the hybrid bonding layer and without oxidizing the metal bonding pads in the hybrid bonding layer. These materials can also be applied to the dielectric bonding layer for direct dielectric-to-dielectric bonding. For example, the auxiliary layer 15 can be applied by sputter deposition, which is a form of physical vapor deposition (PVD). The thickness of the auxiliary layer 15 can be a few tens of nanometers, preferably between 5 nm and 100 nm.

[0038] After applying the stack of layers 15 and 16, the wafer 1 is inverted and bonded face-down to the temporary carrier wafer 17, as Figure 4 shown, where the TBM layer 16 achieves a temporary adhesive bond along the bonding interface 18.

[0039] Then, the bulk Si wafer 10 is thinned from the back side, which can be done by grinding and / or wet etching until the bulk Si is reduced to the thickness T as Figure 5 shown.

[0040] Referring to Figure 6 , then the components of the carrier 17 and the processed wafer 1 are inverted and the back side of the thinned Si wafer 10 is bonded to another carrier 20, which can be another temporary carrier or a permanent carrier, i.e., a carrier to which the thinned wafer is bonded by an irreversible bond or adhesion force. Alternatively, the back side of the Si wafer 10 can be further thinned and subjected to processing steps, such as including fabricating through-silicon vias and backside contacts.

[0041] Then, the temporary carrier 17 is removed by releasing the temporary bond along the interface 18. If the TBM layer 16 is formed of a thermoplastic polymer, this can be done, for example, by heating. AsFigure 7 As shown in, the stack of the auxiliary layer 15 and the TBM layer 16 remains on the hybrid bonding surface 8.

[0042] Thereafter and with reference to Figure 8 , the TBM layer 16 is selectively removed relative to the underlying auxiliary layer 15. This can be done by applying a solvent by techniques known in the art, such as by immersing the wafer or a batch of wafers in a solvent bath for a given time. Alternatively, on a single wafer, the solvent can be spin-coated onto the wafer surface and subsequently the wafer surface is dried. Depending on the type of solvent and the time allowed to dissolve the TBM, after this TBM removal step, residues of the temporary bonding material may or may not remain on the surface of the auxiliary layer 15.

[0043] As Figure 9 shown in, the auxiliary layer 15 is then removed. In the case of the TiN layer, this can be done by a wet etching step using an aqueous mixture that does not etch Cu and SiCN. Such mixtures are known per se in the art. Even if TBM residues remain on the TiN layer 15, this keeps the hybrid bonding surface 8 clean and substantially residue-free, does not increase the roughness of the dielectric and does not oxidize the metal. The same result can be obtained using other nitrides or carbides of transition metals (such as molybdenum nitride or tungsten carbide).

[0044] Thus, the provision of the auxiliary layer 15 enables the substantially complete removal of the TBM layer 16 without leaving any residual material and without negatively affecting the bonding surface. Thus, the hybrid bonding surface 8 is desirably prepared for the hybrid bonding process with another die or wafer. After the wafer 1 is divided along the dividing line 2, this can be done in a wafer-to-wafer bonding process or in a die-to-wafer bonding process.

[0045] The method is applicable to different types of surfaces where a temporary polymer layer needs to be removed without leaving residues. The method is applicable, for example, to dielectric bonding surfaces and hybrid bonding surfaces, such as to SiCN surfaces in a direct SiCN-SiCN bonding process.

[0046] A practical embodiment and proof of concept will be described hereinafter.

[0047] A TiN layer with a thickness of 10 nm is deposited on a wafer having a SiCN overlay on its surface. The TiN deposition is carried out by sputter deposition. Thereafter, a TBM layer with a thickness of 30 μm is spin-coated on the TiN layer. The TBM is 305. The TBM layer is dissolved using mesitylene as a solvent at 40 °C, and the static dissolution time is 50 minutes. Thereafter, the residue of the TBM material remains on the TiN surface. The TiN layer is removed by wet etching using an aqueous mixture at 55 °C, and the etching time is 60 seconds. After this, the TiN and the residue are completely removed, leaving a clean SiCN surface.

[0048] Although the invention has been described in detail in the drawings and the foregoing description, such description and illustration should be considered illustrative or exemplary, rather than restrictive. By studying the drawings, the disclosure, and the appended claims, those skilled in the art can understand and achieve other variations of the disclosed embodiments in practicing the claimed invention. In the claims, the word "comprising" does not exclude other elements or steps, and the indefinite article "a" or "an" does not exclude a plurality. The fact that certain measures are recited in mutually different dependent claims does not mean that a combination of these measures cannot be used. Any reference signs in the claims should not be construed as limiting the scope.

Claims

1. A semiconductor processing method, comprising: - providing a processed wafer (1) comprising a die side and a back side and comprising a plurality of dies (3) on the die side, said dies comprising bonding surfaces (8) suitable for direct dielectric-to-dielectric or hybrid bonding of said dies to a target substrate, - thereafter, directly on the bonding surface (8) of the die, an auxiliary layer (15) is produced, said auxiliary layer being removable from said bonding surface (8) without leaving substantially any residue on said bonding surface (8), - thereafter, directly on the auxiliary layer (15) a temporary polymer bonding layer (16) is produced, - thereafter, temporarily bonding the processed wafer to the carrier substrate (17) by removably joining the temporary bonding layer (16) to the carrier substrate (17), performing processing steps on the back side of the processed wafer (1), and releasing the processed wafer from the carrier substrate (17) so that the auxiliary layer (15) and the temporary bonding layer (16) remain on the die side of the processed wafer (1), - thereafter, removing the temporary polymer layer (16) selectively or substantially with respect to the auxiliary layer (15), - thereafter, removing the auxiliary layer (15) selectively with respect to the bonding surface (8), thereby producing a bonding surface (8) which is substantially free of residues, Wherein, the auxiliary layer (15) is formed of nitride or carbide of transition metal.

2. The method of claim 1, wherein: The auxiliary layer is formed of a material selected from the group consisting of titanium nitride, hafnium nitride, tungsten nitride, molybdenum nitride, and tungsten carbide.

3. The method according to claim 1 or 2, wherein: The bonding surface (8) is suitable for hybrid bonding, the bonding surface comprising a metal contact pad (6) embedded in a layer of dielectric material (7).

4. The method of claim 3, wherein: The metal contact (6) is a Cu contact pad and the dielectric material layer (7) is a SiCN layer.

5. A method as claimed in any one of the preceding claims, wherein: The temporary polymer bonding layer (16) is removed or substantially removed by applying a solvent to the polymer layer.

6. A method as claimed in any one of the preceding claims, wherein: After the temporary polymer bonding layer (16) is removed selectively relative to the auxiliary layer (15), residues of the polymer layer (16) remain on the auxiliary layer (15).

7. A method as claimed in any one of the preceding claims, wherein: The auxiliary layer (15) is removed by wet etching.

8. A method as claimed in any one of the preceding claims, wherein: The thickness of the auxiliary layer (15) is between 5 nm and 100 nm.

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