Clock redundancy circuit with reinforced design and latch

Abstract

The invention relates to a reinforced clock redundant circuit and a latch, a clock signal transmission part of the clock redundant circuit is redesigned, a delay unit is introduced, and obvious delay is generated for external transient pulse input, so that when no external transient pulse is input at a clock signal CK end, the clock signal CK end can be delayed, and the clock signal CK end can be delayed. When a transient pulse is input at the clock signal CK end, the first transmission unit and the second transmission unit are normally started, and the clock signal output is normally provided for the latch; signal delay provided by the delay unit will cause inconsistency of two inputs of Miller capacitors in phase inverters of the first transmission unit and the second transmission unit, and circuit output is converted into a high resistance state, so that an external input transient state of a clock signal CK end is effectively filtered out, and the influence of the transient state on a storage state of the latch is eliminated; the purpose of effectively reinforcing the external input transient state of the clock signal CK end is achieved.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuit design, and relates to a clock redundancy circuit and a latch with enhanced design. Background Art

[0002] In the space environment, various radiation particles (such as heavy ions, protons, neutrons, and electrons, etc.) and high-energy rays (such as γ-rays and x-rays, etc.) widely exist. Bombardment of semiconductor devices by high-energy particles or rays can cause various types of failures of the devices, seriously reducing the reliability of integrated circuits in spacecraft control systems, shortening the service life of spacecraft or even damaging the spacecraft, resulting in irreparable losses. Therefore, it is necessary to carry out radiation-hardening design for integrated circuits to improve their reliability in the space environment.

[0003] Standard cells are the basis of chip design. Strengthening the design of standard cells can effectively improve the reliability of aerospace-grade chips. The sequential logic cells in standard cells are the key to storing data. The DICE (Dual Interlocked Storage Cell) hardening design is most commonly used for sequential logic cells, and delay filtering is often performed on their data terminals and set / reset terminals to achieve the purpose of anti-single-event transient and anti-single-event upset. However, the external input transients of the clock signal terminals of sequential logic cells can also cause abnormal sampling of the latch circuit, resulting in single-event upset errors in sequential logic cells. Therefore, how to carry out hardening design for the external input transients of the clock signal terminals has become a technical problem to be solved. Summary of the Invention

[0004] Aiming at the problems existing in the above traditional technologies, the present invention proposes a clock redundancy circuit with enhanced design, and a latch with anti-single-event transient and anti-single-event upset functions, which can effectively achieve the enhanced design for the external input transients of the clock signal CK terminal.

[0005] To achieve the above object, the embodiments of the present invention adopt the following technical solutions: On the one hand, a clock redundancy circuit with enhanced design and a latch are provided, including a delay unit, a first transmission unit, a second transmission unit, a first inverter, and a second inverter; The input terminal of the delay unit is used to access the clock signal CK. The output terminal of the delay unit is respectively connected to the second input terminals of the first transmission unit and the second transmission unit. The first input terminals of the first transmission unit and the second transmission unit are used to access the clock signal CK. The output terminal of the first transmission unit is connected to the input terminal of the first inverter, and the output terminal of the second transmission unit is connected to the input terminal of the second inverter; The first transmission unit and the second transmission unit are respectively used to receive the clock signal CK and the output signal of the clock signal CK after passing through the delay unit, and then output the first clock signal after inverting processing. The first inverter is used to receive the first clock signal output by the first transmission unit and then output the second clock signal to the latch. The second inverter is used to receive the first clock signal output by the second transmission unit and then output the second clock signal to the latch. The delay unit is used to provide signal delay when a transient pulse is input at the clock signal CK terminal, so that the first transmission unit and the second transmission unit are turned into high impedance states, and when the transient pulse at the clock signal CK terminal disappears, the first transmission unit and the second transmission unit are restored to low impedance states.

[0006] On the other hand, a latch resistant to single event transients and single event upsets is also provided, which includes a latch main circuit and the above-mentioned clock redundancy circuit with enhanced design.

[0007] One of the above technical solutions has the following advantages and beneficial effects: For the above-mentioned clock redundancy circuit with enhanced design and the latch, by redesigning the clock signal transmission part of the clock redundancy circuit and introducing a delay unit, the delay of the clock signal CK can be negligible by selecting the delay unit, while obvious delay is generated for external transient pulse inputs. When there is no external transient pulse input at the clock signal CK terminal, the first transmission unit and the second transmission unit are normally turned on, and the clock signal is normally provided to the latch for output. When there is a transient pulse input at the clock signal CK terminal, the signal delay provided by the delay unit will cause the two inputs of the Miller capacitance in the inverters of the first transmission unit and the second transmission unit to be inconsistent, and the circuit output will be turned into a high impedance state, effectively filtering out the external input transient at the clock signal CK terminal, eliminating the influence of this transient on the storage state of the latch, and achieving the purpose of effectively implementing the enhanced design for external input transients at the clock signal CK terminal. Description of the Drawings

[0008] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or in the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0009] Figure 1 It is a schematic diagram of the existing circuit design at the clock signal CK terminal; Figure 2 It is a schematic diagram of the structure of the clock redundancy circuit with enhanced design in an embodiment; Figure 3Schematic diagram of the latch body circuit structure of a latch for single-event transient and single-event upset resistance in an embodiment. Detailed implementation manners

[0010] In order to make the objectives, technical solutions and advantages of the present invention more clear and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which the present invention belongs. The terms used in the description of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0011] It should be noted that referring to "embodiment" herein means that a specific feature, structure or characteristic described in connection with the embodiment may be included in at least one embodiment of the present invention. Displaying this phrase at various positions in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art can understand that the embodiments described herein can be combined with other embodiments. The term "and / or" used in the description and claims of the present invention refers to any combination and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0012] The embodiments of the present invention will be described in detail below with reference to the accompanying drawings in the embodiments of the present invention.

[0013] As Figure 1 shown in the circuit design of the clock signal CK terminal, it cannot effectively shield the transient input from the outside of the clock signal CK terminal, so that when such a transient occurs, the subsequent nclk and bclk will be abnormally turned on, causing the latch to sample incorrectly. Among them, the P transistor represents a P-type MOS transistor, the N transistor represents an N-type MOS transistor, nclk represents the first clock signal after the clock signal passes through an inverter (composed of a pair of P and N transistors), and bclk represents the second clock signal after the first clock signal nclk passes through an inverter (composed of a pair of P and N transistors). The same applies hereinafter. For the circuit design of the clock signal CK terminal as Figure 1 shown, the present invention proposes a new reinforcement design for the clock signal CK terminal, so that the improved clock redundancy circuit can effectively filter out the external input transients of the clock signal CK terminal, so that the latch to which it is applied can resist both single-event transients and single-event upsets, further improving the radiation resistance of the latch, so as to enhance the reliability of the latch in a complex space environment and meet the application requirements of actual aerospace engineering.

[0014] In one embodiment, as Figure 2As shown, a clock redundancy circuit with a reinforced design is provided, including a delay unit 101, a first transmission unit C1, a second transmission unit C2, a first inverter INV1, and a second inverter INV2. The input end of the delay unit 101 is used to access the clock signal CK, and the output end of the delay unit 101 is respectively connected to the second input ends of the first transmission unit C1 and the second transmission unit C2. The first input ends of the first transmission unit C1 and the second transmission unit C2 are used to access the clock signal CK. The output end of the first transmission unit C1 is connected to the input end of the first inverter INV1, and the output end of the second transmission unit C2 is connected to the input end of the second inverter INV2.

[0015] After the first transmission unit C1 and the second transmission unit C2 respectively receive the clock signal CK and the output signal of the clock signal CK after passing through the delay unit 101, they perform an inverting process and output the first clock signal. The first inverter INV1 is used to output the second clock signal to the latch after receiving the first clock signal output by the first transmission unit C1. The second inverter INV2 is used to output the second clock signal to the latch after receiving the first clock signal output by the second transmission unit C2. The delay unit 101 is used to provide signal delay when a transient pulse is input at the clock signal CK end, so that the first transmission unit C1 and the second transmission unit C2 are turned into a high-impedance state, and to restore the first transmission unit C1 and the second transmission unit C2 to a low-impedance state when the transient pulse at the clock signal CK end disappears.

[0016] It can be understood that the clock signal CK and the latch are both existing signal and circuit parts in the art. The improvement point of this embodiment lies in the structural design of the clock redundancy circuit. Among them, the delay unit 101 can, for example, adopt a buffer or other delay circuits with similar delay functions, such as a delay chain, as long as it can ensure that when there is no transient pulse input at the clock signal CK end, the first transmission unit C1 and the second transmission unit C2 are normally turned on, and when there is a transient pulse input at the clock signal CK end, signal delay is provided, resulting in inconsistent two inputs of the Miller capacitance existing in the first transmission unit C1 and the second transmission unit C2, so that the first transmission unit C1 and the second transmission unit C2 are turned into a high-impedance state, achieving the purpose of isolating the transient from the latch.

[0017] Specifically, existing such as Figure 1In the shown clock redundancy circuit, when the clock signal CK is at a low level, the first clock signals nclk and nclk1 are at a high level state, and the drains of the N transistors connected to the first clock signals nclk and nclk1 are sensitive points. When this sensitive point is bombarded (assuming the drain of the N transistor connected to the first clock signal nclk is bombarded), the state of the first clock signal nclk changes from high level to low level, forming a transient pulse of 101. This transient pulse propagates to the next-stage inverter, so the state of the second clock signal bclk changes from low level to high level, forming a transient pulse of 010. As a result, the P transistor controlled by the first clock signal nclk is abnormally turned on, and the N transistor controlled by the second clock signal bclk is abnormally turned on. This abnormal state will cause the latch to sample incorrectly.

[0018] Therefore, in this embodiment, by redesigning the clock signal transmission part of the clock redundancy circuit and introducing the delay unit 101, when a transient pulse is input at the clock signal CK terminal, the signal delay provided by the delay unit 101 will cause the two inputs of miller_C (i.e., the Miller capacitance, which exists in the inverters of the first transmission unit C1 and the second transmission unit C2) to be inconsistent. Since the output of miller_C is in a high-impedance state when the two inputs are inconsistent (this will cause the hardened clock redundancy circuit to be isolated from the latch, that is, no valid clock signal will be output to the latch), when the transient pulse at the clock signal CK terminal disappears, the hardened clock redundancy circuit automatically resumes the output of the valid clock signal. Therefore, this hardening design for the clock signal CK terminal can effectively filter out the external input transient at the clock signal CK terminal and eliminate the influence of this transient on the storage state of the latch.

[0019] For the above-mentioned hardened clock redundancy circuit, by redesigning the clock signal transmission part of the clock redundancy circuit and introducing the delay unit 101, the delay of the clock signal CK can be negligible by selecting the delay unit 101, while a significant delay is generated for the external transient pulse input. When there is no external transient pulse input at the clock signal CK terminal, the first transmission unit C1 and the second transmission unit C2 are normally turned on, and a clock signal output is normally provided to the latch. When a transient pulse is input at the clock signal CK terminal, the signal delay provided by the delay unit 101 will cause the two inputs of the Miller capacitance existing in the inverters of the first transmission unit C1 and the second transmission unit C2 to be inconsistent, and the circuit output will be turned into a high-impedance state, effectively filtering out the external input transient at the clock signal CK terminal, eliminating the influence of this transient on the storage state of the latch, and achieving the purpose of effectively implementing the hardening design for the external input transient at the clock signal CK terminal.

[0020] In one embodiment, as Figure 2As shown, the delay unit 101 can be a buffer BUF (Buffer). One or more cascaded buffers BUF can be used to construct the required delay unit 101, which can be specifically selected according to the delay requirement for the transient pulse input at the clock signal CK terminal. By using the buffer BUF as the delay unit 101, the circuit structure is simpler, thus effectively reducing the manufacturing cost and circuit complexity.

[0021] In one embodiment, as Figure 2 shown, the first transmission unit C1 includes a first P-type transistor, a second P-type transistor, a first N-type transistor, and a second N-type transistor. The source of the first P-type transistor is connected to the power supply voltage (such as VDD). The drain of the first P-type transistor is connected to the source of the second P-type transistor, and the drain of the second P-type transistor is connected to the drain of the first N-type transistor as a common node to output the first clock signal nclk. The source of the first N-type transistor is connected to the drain of the second N-type transistor, and the source of the second N-type transistor is grounded. The gates of the first P-type transistor and the second N-type transistor are both connected to the output terminal of the delay unit 101, and the gates of the second P-type transistor and the first N-type transistor are both used to access the clock signal CK.

[0022] It can be understood that in this embodiment, the circuit structure of the first transmission unit C1 as Figure 2 shown can be adopted. The circuit structure design of this single transmission circuit is relatively simple and efficient, and can adapt to the output signal processing of the delay unit 101 and the clock signal CK terminal with the simplest circuit structure. Those skilled in the art can also adopt the circuit structures of other more components based on the design function of the first transmission unit C1. The first transmission unit C1 given in this specification is only one typical design.

[0023] In one embodiment, the second transmission unit C2 includes a first P-type transistor, a second P-type transistor, a first N-type transistor, and a second N-type transistor. The source of the first P-type transistor is connected to the power supply voltage. The drain of the first P-type transistor is connected to the source of the second P-type transistor, and the drain of the second P-type transistor is connected to the drain of the first N-type transistor as a common node to output the first clock signal nclk1. The source of the first N-type transistor is connected to the drain of the second N-type transistor, and the source of the second N-type transistor is grounded. The gates of the first P-type transistor and the second N-type transistor are both connected to the output terminal of the delay unit 101, and the gates of the second P-type transistor and the first N-type transistor are both used to access the clock signal CK.

[0024] It can be understood that the circuit structure of the second transmission unit C2 in this embodiment can be the same as that of the first transmission unit C1, thereby improving the consistency of the circuit design, the efficiency, and the reliability of the circuit design while ensuring the normal functions required by the circuit.

[0025] In one embodiment, the first inverter INV1 includes a third P-type transistor and a third N-type transistor. The source of the third P-type transistor is connected to the power supply voltage, the drain of the third P-type transistor is connected to the drain of the third N-type transistor as a common node to output the second clock signal bclk, and the gates of the third P-type transistor and the third N-type transistor are both connected to the output terminal of the first transmission unit C1.

[0026] It can be understood that the first inverter INV1 can adopt a relatively simplified inverter circuit structure in the art to efficiently and low-costly implement the required signal inversion processing function. Those skilled in the art can also adopt other more complex inverter structures to implement the first inverter INV1 according to this function, and this specification does not make a unique limitation.

[0027] In one embodiment, the second inverter INV2 includes a third P-type transistor and a third N-type transistor. The source of the third P-type transistor is connected to the power supply voltage, the drain of the third P-type transistor is connected to the drain of the third N-type transistor as a common node to output the second clock signal bclk1, and the gates of the third P-type transistor and the third N-type transistor are both connected to the output terminal of the second transmission unit C2.

[0028] It can be understood that the second inverter INV2 can also adopt a relatively simplified inverter circuit structure in the art to efficiently and low-costly implement the required signal inversion processing function. Those skilled in the art can also adopt other more complex inverter structures to implement the second inverter INV2 according to this function, and this specification does not make a unique limitation. The first, second, third, etc. naming methods of the above transistors are only used to distinguish each transistor in a certain order (such as from top to bottom, from left to right), rather than to limit the specific models of the transistors. The types of transistors are distinguished by P-type (channel type) and N-type.

[0029] In one embodiment, as Figure 3 and Figure 2 shown, a latch for anti-single event transient and anti-single event upset is provided, including a latch main circuit and the above-mentioned hardened design clock redundancy circuit.

[0030] It can be understood that as Figure 3The latch body circuit shown has two input terminals and one output terminal. The two input terminals are the clock signal CK terminal and the data input signal D terminal respectively, and the one output terminal is the Q terminal. After the clock signal CK undergoes delay, XOR gate voting, and tri-state filtering, it outputs nclk, nclk1, bclk, and bclk1 respectively after passing through an inverter. The data D passes through inverters controlled by nclk, nclk1, bclk, and bclk1 to output ND1 and ND2, and ND1 and ND2 are inverted by an inverter to output Q. The latch body circuit is an existing circuit structure, and its specific explanation can be understood by analogy with the circuit structure of the same type of latch in the art, and will not be elaborated in this specification.

[0031] When a transient pulse is input to the clock signal CK terminal, the delay of the BUF (Buffer) causes the two inputs of miller_C to be inconsistent. Since the output of miller_C is in a high-impedance state when the two inputs are inconsistent, when the transient pulse at the clock signal CK terminal disappears, the clock redundancy circuit with enhanced design automatically resumes the output of an effective clock signal. Therefore, this enhanced design for the clock signal CK terminal can effectively filter out the external input transient of the clock signal CK terminal and eliminate the influence of this transient on the storage state of this latch.

[0032] Specifically, when the clock signal CK is at a high level, the data D is output to the existing DICE circuit structure through an inverter, forming signals ND1 and ND2 in the same state. The signals ND1 and ND2 are then sent to the output Q terminal through a stage of inverter. When the clock signal CK is at a low level, the data D cannot be output to the DICE circuit structure through an inverter, but the feedback circuit of the DICE circuit structure is still turned on, so as to keep the stored data in the circuit continuously output to the Q terminal.

[0033] In the existing clock redundancy circuit, when the clock signal CK is at a low level, the first clock signals nclk and nclk1 are in a high-level state, and the drains of the N transistors connected to the first clock signals nclk and nclk1 are sensitive points; when this sensitive point is bombarded (assuming the drain of the N transistor connected to the first clock signal nclk is bombarded), the state of the first clock signal nclk changes from high level to low level, forming a transient pulse of 101. This transient pulse propagates to the next-stage inverter, so the state of the second clock signal bclk changes from low level to high level, forming a transient pulse of 010. Therefore, the P transistor controlled by the first clock signal nclk is abnormally turned on, and the N transistor controlled by the second clock signal bclk is abnormally turned on.

[0034] Assume that the initial states of data D, signal ND1, and signal ND2 are all high. Due to the abnormal turn-on of the N transistor controlled by the second clock signal bclk, the state of signal ND1 changes, but the state of signal ND2 remains unchanged, that is, signal ND1 changes from high to low, but signal ND2 is still high. Since there is competition when the P and N transistors in the latch circuit are turned on simultaneously, the levels of node A and node Q are in an indeterminate state, but node B still maintains the normal low level state. In the feedback circuit part of the latch, the N transistor controlled by the first clock signal nclk is abnormally turned off, and the P transistor controlled by the second clock signal bclk is abnormally turned off, but the N transistor controlled by the first clock signal nclk1 is normally turned on, and the P transistor controlled by the second clock signal bclk1 is normally turned on. Therefore, the states of node B and node A cannot be further transmitted. After the above-mentioned incorrect turn-on is removed, the state of node B passes through the normally-conductive feedback circuit part, changing the state of signal ND1 from low to high. Finally, the output Q terminal returns to the normal low level state. Therefore, for this high-level triggered latch, after applying the above-mentioned enhanced clock redundancy circuit, it can further have the ability to resist single-event transients based on its own ability to resist single-event upsets, thereby achieving the purpose of further effectively improving its ability to resist single-event transients and single-event upsets, and more effectively improving the radiation resistance of the latch.

[0035] For the above latch with the ability to resist single-event transients and single-event upsets, by applying the above-mentioned enhanced clock redundancy circuit, it can further have the ability to resist single-event transients based on its own ability to resist single-event upsets, thereby achieving the purpose of further effectively improving its ability to resist single-event transients and single-event upsets, and more effectively improving the radiation resistance of the latch.

[0036] It can be understood that for the explanation of the clock redundancy circuit in the above latch with the ability to resist single-event transients and single-event upsets, specifically, it can be understood by referring to the corresponding explanations of the various embodiments of the above-mentioned enhanced clock redundancy circuit in the same way, and will not be repeated here.

[0037] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as within the scope described in this specification.

[0038] The above embodiments only represent several implementation manners of the present invention. The description is relatively specific and detailed, but it cannot be understood as a limitation on the protection scope of the invention. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several modifications and improvements can still be made, which all belong to the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the appended claims.

Claims

1. A clock redundancy circuit with a reinforced design, characterized in that: It includes a delay unit, a first transmission unit, a second transmission unit, a first inverter and a second inverter; The input end of the delay unit is used to access the clock signal CK, the output end of the delay unit is connected to the second input end of the first transmission unit and the second transmission unit respectively, the first input end of the first transmission unit and the second transmission unit is used to access the clock signal CK, the output end of the first transmission unit is connected to the input end of the first inverter, and the output end of the second transmission unit is connected to the input end of the second inverter; The first transmission unit and the second transmission unit are respectively used to receive the clock signal CK and the output signal of the clock signal CK after passing through the delay unit, and output the first clock signal after inversion processing. The first inverter is used to receive the first clock signal output by the first transmission unit and then output the second clock signal to the latch. The second inverter is used to receive the first clock signal output by the second transmission unit and then output the second clock signal to the latch. The delay unit is used to provide signal delay when there is a transient pulse input at the clock signal CK end, so that the first transmission unit and the second transmission unit are turned into a high-impedance state, and restore the first transmission unit and the second transmission unit to a low-impedance state when the transient pulse at the clock signal CK end disappears.

2. The clock redundancy circuit with a reinforced design according to claim 1, characterized in that: The delay unit is a buffer.

3. The clock redundancy circuit with a reinforced design according to claim 1 or 2, characterized in that: The first transmission unit includes a first P-type transistor, a second P-type transistor, a first N-type transistor and a second N-type transistor, and the source of the first P-type transistor is connected to a power supply voltage; The drain of the first P-type transistor is connected to the source of the second P-type transistor, the drain of the second P-type transistor is connected to the drain of the first N-type transistor as a common node to output a first clock signal nclk, the source of the first N-type transistor is connected to the drain of the second N-type transistor, and the source of the second N-type transistor is grounded; The gate of the first P-type transistor and the gate of the second N-type transistor are both connected to the output end of the delay unit, and the gate of the second P-type transistor and the gate of the first N-type transistor are both used to access the clock signal CK.

4. The clock redundancy circuit with a reinforced design according to claim 1 or 2, characterized in that: The second transmission unit includes a first P-type transistor, a second P-type transistor, a first N-type transistor and a second N-type transistor, wherein a source of the first P-type transistor is connected to a power supply voltage; The drain of the first P-type transistor is connected to the source of the second P-type transistor, the drain of the second P-type transistor is connected to the drain of the first N-type transistor as a common node to output a first clock signal nclk1, the source of the first N-type transistor is connected to the drain of the second N-type transistor, and the source of the second N-type transistor is grounded; The gate of the first P-type transistor and the gate of the second N-type transistor are both connected to the output end of the delay unit, and the gate of the second P-type transistor and the gate of the first N-type transistor are both used to access the clock signal CK.

5. The clock redundancy circuit with reinforced design according to claim 1 or 2, characterized in that: The first inverter includes a third P-type transistor and a third N-type transistor, the source of the third P-type transistor is connected to the power supply voltage, the drain of the third P-type transistor is connected to the drain of the third N-type transistor as a common node to output the second clock signal bclk, and the gate of the third P-type transistor and the gate of the third N-type transistor are both connected to the output end of the first transmission unit.

6. The clock redundancy circuit with a reinforced design according to claim 1 or 2, characterized in that: The second inverter includes a third P-type transistor and a third N-type transistor, the source of the third P-type transistor is connected to the power supply voltage, the drain of the third P-type transistor is connected to the drain of the third N-type transistor as a common node to output the second clock signal bclk1, and the gate of the third P-type transistor and the gate of the third N-type transistor are both connected to the output end of the second transmission unit.

7. A latch resistant to single-particle transients and single-particle upsets, characterized in that: The invention comprises a latch main body circuit and a clock redundancy circuit with a reinforced design as claimed in any one of claims 1 to 6.

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