Low-delay small-area level shift circuit

Abstract

The invention discloses a low-delay small-area level shift circuit, which comprises a pulse generation module, an NMOS (N-channel Metal Oxide Semiconductor) tube HMN1, an NMOS tube HMN2 and a level shift module, and is characterized in that the pulse generation module is used for carrying out signal delay on an original signal to generate a first pulse signal and a second pulse signal; the grid electrode of the NMOS transistor HMN1 receives a first pulse signal, the source electrode is connected with the grounding end, and the drain electrode is connected with the first input end of the level shift module; the grid electrode of the NMOS tube HMN2 receives a second pulse signal, the source electrode is connected with the grounding end, and the drain electrode is connected with the second input end of the level shift module; the first pulse signal is used for controlling the on-off of the NMOS tube HMN1, and the second pulse signal is used for controlling the on-off of the NMOS tube HMN2, so that the level shift of the original signal is realized. According to the invention, the pulse generation module generates the pulse signal to control the opening of the NMOS tube, so that the power loss of the circuit is effectively reduced.

Description

Technical Field

[0001] The present invention belongs to the technical field of level shifting, and particularly relates to a low-delay and small-area level shifting circuit. Background Art

[0002] A level shifting circuit converts a low-voltage control signal into a high-voltage control signal to achieve the control of a high-voltage power output stage by low-voltage logic. It belongs to the control technology field of high-voltage devices and has been widely used in aspects such as motor drive, PDP display, and OLED display. In the control technology field of high-voltage devices, a logic control circuit and a high-voltage output drive circuit can be integrated to achieve a high-voltage withstand, large current, and high-precision drive circuit. As a key circuit connecting the logic control circuit and the output drive stage, the level shifting circuit is required to have a very high driving ability on the one hand to meet the driving requirements of the output stage; on the other hand, the working voltage of the level shifting circuit is relatively high, so it is required to have a low static operating current to reduce power consumption. A conventional level shifting circuit converts a 0 - V DD (V DD is a common level) low-voltage control signal into a 0 - V PP (V PP is a high-voltage level) high-voltage control signal for driving an output-stage MOS transistor operating at a high voltage. Therefore, a motor drive circuit requires a low-delay and low-power level shifting circuit.

[0003] There are mainly two defects in the existing level shifting circuits. On the one hand, the level shifter in the level shifting circuit has a large propagation delay and a large layout area because high-voltage PMOS transistors are used. On the other hand, if there is a threshold mismatch of MOS transistors during the manufacturing process, it will lead to a mismatch in propagation time, and the alternating conduction of switching transistors will cause a large power loss. At the same time, MOS transistors will have mismatches during the industrial production process, which will affect the output delay of the pull-up and pull-down, slow down the transmission speed, and have poor anti-interference ability. The traditional level shifter circuit has a large propagation delay, and the alternating conduction of NMOS transistors caused by the input signal will generate a large power consumption. With the rapid development of integrated circuits, the traditional level shifter can no longer meet the requirements of high-speed and low-power systems. Therefore, it is of great significance to design a low-delay and low-power level shifter. Summary of the Invention

[0004] In order to solve the above problems existing in the prior art, the present invention provides a low-delay and small-area level shifting circuit. The technical problems to be solved by the present invention are achieved through the following technical solutions:

[0005] The present invention provides a low-delay and small-area level shifting circuit, including a pulse generation module, NMOS transistor H MN1 、NMOS transistor H MN2and a level shift module, wherein,

[0006] The pulse generation module is used to delay the input original signal IN to generate a first pulse signal IN after signal delay 1 or a second pulse signal IN 2 , wherein, the high level of the first pulse signal IN 1 and the high level of the second pulse signal IN 2 are in different time periods;

[0007] The gate of the NMOS transistor H MN1 is connected to the first output end of the pulse generation module to receive the first pulse signal IN 1 , the source of the NMOS transistor H MN1 is connected to the ground terminal, and the drain of the NMOS transistor H MN1 is connected to the first input end of the level shift module;

[0008] The gate of the NMOS transistor H MN2 is connected to the second output end of the pulse generation module to receive the second pulse signal IN 2 , the source of the NMOS transistor H MN2 is connected to the ground terminal, and the drain of the NMOS transistor H MN2 is connected to the second input end of the level shift module;

[0009] The first pulse signal IN 1 is used to control the on / off of the NMOS transistor H MN1 , and the second pulse signal IN 2 is used to control the on / off of the NMOS transistor H MN2 , so as to control the level shift module to realize the level shift of the original signal IN.

[0010] In an embodiment of the present invention, the pulse generation module includes an inverter I1, a first inverter chain, a second inverter chain, a first AND gate AND1 and a second AND gate AND2, wherein,

[0011] The input end of the first inverter chain is connected to the input end of the inverter I1, the output end of the first inverter chain is connected to the first input end of the first AND gate AND1, and the second input end of the first AND gate AND1 is connected to the input end of the inverter I1; the original signal IN is input to the input end of the inverter I1; the output end of the first AND gate AND1 is connected to the gate of the NMOS transistor H MN1 , and the output end of the first AND gate AND1 is used to output the first pulse signal IN 1 ;

[0012] The input terminal of the second inverter chain is connected to the output terminal of the inverter I1, the output terminal of the second inverter chain is connected to the first input terminal of the second AND gate AND2, and the second input terminal of the second AND gate AND2 is connected to the output terminal of the inverter I1; the output terminal of the second AND gate AND2 is connected to the gate of the NMOS transistor H MN2 The output terminal of the second AND gate AND1 is used to output the second pulse signal IN 2 ;

[0013] The first inverter chain and the second inverter chain have the same number of inverters.

[0014] In an embodiment of the present invention, the first inverter chain includes three inverters connected in series between the input terminal of the inverter I1 and the first input terminal of the first AND gate AND1, and the second inverter chain includes three inverters connected in series between the output terminal of the inverter I1 and the first input terminal of the second AND gate AND1.

[0015] In an embodiment of the present invention, the level shift module includes a level shift unit and a latch unit, wherein

[0016] The level shift module is used to perform level shifting of the original signal under the control of the NMOS transistor H MN1 and the NMOS transistor H MN2 ;

[0017] The latch unit is used to ensure the logical correctness of the level shift signal and accelerate the level inversion speed, and output the final level shift signal.

[0018] In an embodiment of the present invention, the level shift unit includes PMOS transistors P M1 , PMOS transistors P M2 , PMOS transistors P M3 , PMOS transistors P M4 , PMOS transistors P M5 , PMOS transistors P M6 , PMOS transistors P M7 , PMOS transistors P M8 , NMOS transistors N M1 , NMOS transistors N M2 , NMOS transistors N M3 , NMOS transistors N M4 , resistors R 1 , resistors R 2 , resistors R 3 and resistor R 4 , wherein

[0019] The PMOS transistor PM1 the source of, the PMOS transistor P M2 the source of, the PMOS transistor P M3 the source of, the PMOS transistor P M4 the source of, the PMOS transistor P M5 the source of, the PMOS transistor P M6 the source of, the PMOS transistor P M7 the source of and the PMOS transistor P M8 the sources of are all connected to the high - voltage terminal high level V DDH ;

[0020] the PMOS transistor P M7 the drain of, the PMOS transistor P M7 the gate of, the PMOS transistor P M1 the drain of, the PMOS transistor P M1 the gate of, the PMOS transistor P M2 the gate of and the PMOS transistor P M5 the gates of are all connected to the drain of the NMOS transistor H MN1 ;

[0021] the PMOS transistor P M2 the drain of is connected to the drain of the NMOS transistor N M1 the drain of, the NMOS transistor N M1 the gate of and the NMOS transistor N M2 the gate of; the PMOS transistor P M5 the drain of is connected to the drain of the NMOS transistor N M3 and the first input terminal of the latch unit, the PMOS transistor P M6 the drain of is connected to the drain of the NMOS transistor N M2 and the second input terminal of the latch unit; the PMOS transistor P M6 the gate of is connected to the gate of the PMOS transistor P M3 the gate of, the PMOS transistor P M4 the gate of, the PMOS transistor P M4 the drain of, the PMOS transistor P M8 the gate of, the PMOS transistor P M8 the drain of and the drain of the NMOS transistor H MN2 ;

[0022] the PMOS transistor P M3 the drain of is connected to the drain of the NMOS transistor N M4 the drain of, the NMOS transistor N M4 the gate of, the NMOS transistor N M3 the gate of; the NMOS transistor N M1The source of, the NMOS transistor N M2 The source of, the NMOS transistor N M3 The source of and the NMOS transistor N M4 The sources of are all connected to the low level of the high voltage terminal V SSH ;

[0023] The resistor R 1 Is connected between the high level of the high voltage terminal V DDH And the gate of the PMOS transistor P M1 The resistor R 2 Is connected between the high level of the high voltage terminal V DDH And the gate of the PMOS transistor P M3 The resistor R 3 Connects the gate and the source of the NMOS transistor N M1 The resistor R 4 Connects the gate and the source of the NMOS transistor N M3 Between the gate and the source.

[0024] In an embodiment of the present invention, the high level of the high voltage terminal V DDH And the low level of the high voltage terminal V SSH Are respectively the highest level and the lowest level of the signal after level shifting.

[0025] In an embodiment of the present invention, the latch unit includes inverters INV 1 , inverters INV 2 , inverters INV 3 And inverters INV 4 , wherein,

[0026] The input terminal of the inverter INV 1 Serves as the first input terminal of the latch unit and is connected to the drain of the NMOS transistor N M2 The power supply terminal of the inverter INV 1 Inputs the high level of the high voltage terminal V DDH The ground terminal of the inverter INV 1 Inputs the low level of the high voltage terminal V SSH The output terminal of the inverter INV 1 Serves as the second input terminal of the latch unit and is connected to the drain of the NMOS transistor N M3 ;

[0027] The power supply terminal of the inverter INV 2 Inputs the high level of the high voltage terminal V DDH The ground terminal of the inverter INV 2 Inputs the low level of the high voltage terminal V SSH, the input terminal of the inverter INV 2 is connected to the output terminal of the inverter INV 1 , and the output terminal of the inverter INV 2 is connected to the input terminal of the inverter INV 1 ;

[0028] The power supply terminal of the inverter INV 3 inputs the high-level voltage V of the high-voltage terminal DDH , and the ground terminal of the inverter INV 3 inputs the low-level voltage V of the high-voltage terminal SSH , and the input terminal of the inverter INV 3 is connected to the output terminal of the inverter INV 1 , and the output terminal of the inverter INV 3 serves as the second output terminal of the level shift module for outputting the level-shifted second output signal OUT~;

[0029] The power supply terminal of the inverter INV 4 inputs the high-level voltage V of the high-voltage terminal DDH , and the ground terminal of the inverter INV 4 inputs the low-level voltage V of the high-voltage terminal SSH , and the input terminal of the inverter INV 4 is connected to the output terminal of the inverter INV 2 , and the output terminal of the inverter INV 4 serves as the first output terminal of the level shift module for outputting the level-shifted first output signal OUT.

[0030] In an embodiment of the present invention, the first output signal OUT and the second output signal OUT~ are reverse signals.

[0031] In an embodiment of the present invention, the NMOS transistor H MN1 and the NMOS transistor H MN2 are high-voltage NMOS transistors.

[0032] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0033] 1. The present invention proposes a low-delay and low-power floating level shift circuit. Compared with the traditional level shift circuit, by using the pulse generation module to generate a rising edge to control the turn-on of the high-voltage NMOS transistor H MN1 and the high-voltage NMOS transistor H MN2 , it changes the high and low level triggering in the existing circuit structure and effectively reduces the power loss of the circuit.

[0034] 2. The present invention makes the pull-up current equal to the pull-down current by using a current mirror structure. By adding an N-type current mirror, the problem of asymmetric transmission time is solved, the output delay is reduced, and the interference to the signal at the high-voltage end is reduced, improving the anti-interference ability of the output signal. The function of resistors R SSH ~R 1 is to reduce the impedance of nodes G 4 , G 1 , and reduce the influence of current mirror mismatch. No high-voltage PMOS transistors are used in the present invention, thus effectively saving the area of the circuit. 2

[0035] 3. The present invention includes a pulse input, a high-bandwidth current mirror, and a latch. While stabilizing the output state, the influence brought by current mirror mismatch is minimized. Therefore, the present invention proposes a level-shifting circuit applicable to a motor drive circuit, which can solve some non-ideal effects existing in the prior art and improve the overall performance of the level-shifting circuit without increasing the circuit scale.

[0036] 4. The AND gate of the pulse generation module of the present invention is reasonably designed to ensure that the time delay from the original signal IN to the first pulse signal IN1 or the second pulse signal IN2 is matched. At the same time, without increasing the circuit complexity, the power loss of the circuit is reduced, the stability during the level conversion is ensured, and the adverse influence brought by current mirror mismatch is minimized.

[0037] The present invention will be further described in detail below with reference to the drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 FIG. is a schematic diagram of the modules of a low-delay and small-area level-shifting circuit provided by an embodiment of the present invention;

[0039] Figure 2 FIG. is a specific circuit diagram of a low-delay and small-area level-shifting circuit provided by an embodiment of the present invention;

[0040] Figure 3 FIG. is a signal timing diagram provided by an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0041] In order to further illustrate the technical means and effects adopted by the present invention to achieve the predetermined invention purpose, a low-delay and small-area level-shifting circuit according to the present invention will be described in detail below with reference to the drawings and specific embodiments.

[0042] ​The foregoing and other technical contents, features and effects of the present invention will be clearly presented in the following detailed description in conjunction with the accompanying drawings. Through the description of the specific embodiments, a more in-depth and specific understanding of the technical means and effects adopted by the present invention to achieve the predetermined purpose can be obtained. However, the accompanying drawings are only for reference and illustration, and are not used to limit the technical solution of the present invention.

[0043] It should be noted that in this text, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant is intended to cover non-exclusive inclusion, so that an article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed. Without further limitation, an element defined by the statement "including one..." does not exclude the presence of another identical element in the article or device including the said element.

[0044] The present invention provides a low-latency and small-area level-shifting circuit, which can be applied to a high-speed and low-power circuit system. Please refer to Figure 1 , the level-shifting circuit includes a pulse generation module, NMOS transistor H MN1 , NMOS transistor H MN2 and a level-shifting module. Among them, the pulse generation module is used to delay the input original signal IN with a low level to generate a first pulse signal IN 1 or a second pulse signal IN 2 . Among them, the high level of the first pulse signal IN 1 and the high level of the second pulse signal IN 2 are in different time periods, as Figure 3 shown; the gate of NMOS transistor H MN1 is connected to the first output terminal of the pulse generation module to receive the first pulse signal IN 1 , the source of NMOS transistor H MN1 is connected to the ground terminal, and the drain of NMOS transistor H MN1 is connected to the first input terminal of the level-shifting module; the gate of NMOS transistor H MN2 is connected to the second output terminal of the pulse generation module to receive the second pulse signal IN 2 , the source of NMOS transistor H MN2 is connected to the ground terminal, and the drain of NMOS transistor H MN2 is connected to the second input terminal of the level-shifting module; the first pulse signal IN 1 is used to control NMOS transistor H MN1The on / off state of the second pulse signal IN 2 is used to control the NMOS transistor H MN2 to turn on and off, and further control the level shift module to achieve the level shift of the original signal IN. In this embodiment, the NMOS transistor H MN1 and the NMOS transistor H MN2 are high-voltage NMOS transistors.

[0045] Please refer to Figure 2 , Figure 2 , which is a schematic circuit diagram of a low-delay and small-area level shift circuit provided by an embodiment of the present invention. The pulse generation module of this embodiment includes an inverter I1, a first inverter chain, a second inverter chain, a first AND gate AND1, and a second AND gate AND2. Among them, the input end of the first inverter chain is connected to the input end of the inverter I1, and the original signal IN is input to the input end of the inverter I1; the output end of the first inverter chain is connected to the first input end of the first AND gate AND1, and the second input end of the first AND gate AND1 is connected to the input end of the inverter I1; the output end of the first AND gate AND1 is connected to the gate of the high-voltage NMOS transistor H MN1 , and is used to output the first pulse signal IN 1 to the gate of the high-voltage NMOS transistor H MN1 ; the input end of the second inverter chain is connected to the output end of the inverter I1, the output end of the second inverter chain is connected to the first input end of the second AND gate AND2, and the second input end of the second AND gate AND2 is connected to the output end of the inverter I1; the output end of the second AND gate AND2 is connected to the gate of the high-voltage NMOS transistor H MN2 , and is used to output the second pulse signal IN 2 to the gate of the high-voltage NMOS transistor H MN2 ; the first inverter chain and the second inverter chain have the same number of inverters.

[0046] In a specific embodiment, as Figure 2 shown, the first inverter chain includes three inverters connected in series between the input end of the inverter I1 and the first input end of the first AND gate AND1, and the second inverter chain includes three inverters connected in series between the output end of the inverter I1 and the first input end of the second AND gate AND1.

[0047] Furthermore, the level shift module of this embodiment includes a level shift unit and a latch unit. Among them, the level shift module is used to perform the level shift of the original signal under the control of the high-voltage NMOS transistor H MN1 and the high-voltage NMOS transistor H MN2 ; the latch unit is used to ensure the logical correctness of the level shift signal and accelerate the level inversion speed, and output the final level shift signal.

[0048] Specifically, the level shifter unit includes PMOS transistor P M1 , PMOS transistor P M2 , PMOS transistor P M3 , PMOS transistor P M4 , PMOS transistor P M5 , PMOS transistor P M6 , PMOS transistor P M7 , PMOS transistor P M8 , NMOS transistor N M1 , NMOS transistor N M2 , NMOS transistor N M3 , NMOS transistor N M4 , resistor R 1 , resistor R 2 , resistor R 3 and resistor R 4 , wherein the sources of PMOS transistors P M1 , PMOS transistors P M2 , PMOS transistors P M3 , PMOS transistors P M4 , PMOS transistors P M5 , PMOS transistors P M6 , PMOS transistors P M7 and the sources of PMOS transistors P M8 are all connected to the high voltage terminal high level V DDH ; the drains of PMOS transistors P M7 , the gates of PMOS transistors P M7 , the drains of PMOS transistors P M1 , the gates of PMOS transistors P M1 , the gates of PMOS transistors P M2 and the gates of PMOS transistors P M5 are all connected to the drain of the high voltage NMOS transistor H MN1 ; the drain of PMOS transistor P M2 is connected to the drain of NMOS transistor N M1 , the gate of NMOS transistor N M1 and the gate of NMOS transistor N M2 ; the drain of PMOS transistor P M5 is connected to the drain of NMOS transistor N M3 and the first input terminal of the latch unit, and the drain of PMOS transistor P M6 is connected to the drain of NMOS transistor N M2 and the second input terminal of the latch unit; the gate of PMOS transistor P M6 is connected to the gates of PMOS transistors P M3 , PMOS transistors P M4 , PMOS transistors P M4The drain of, PMOS transistor P M8 The gate of, PMOS transistor P M8 The drain of and high-voltage NMOS transistor H MN2 The drain of.

[0049] PMOS transistor P M3 The drain of is connected to NMOS transistor N M4 The drain of, NMOS transistor N M4 The gate of, NMOS transistor N M3 The gate of; NMOS transistor N M1 The source of, NMOS transistor N M2 The source of, NMOS transistor N M3 The source of and NMOS transistor N M4 The source of are all connected to the high-voltage terminal low level V SSH ; Resistor R 1 Is connected between the high-voltage terminal high level V DDH And PMOS transistor P M1 The gate of, resistor R 2 Is connected between the high-voltage terminal high level V DDH And PMOS transistor P M3 The gate of, resistor R 3 Connects NMOS transistor N M1 The gate and the source of, resistor R 4 Connects NMOS transistor N M3 The gate and the source of.

[0050] High-voltage terminal high level V DDH And high-voltage terminal low level V SSH Are respectively the highest level and the lowest level of the signal after level shifting, and are both preset according to actual requirements.

[0051] The latch unit of this embodiment includes inverter INV 1 , Inverter INV 2 , Inverter INV 3 And inverter INV 4 , Wherein, the input terminal of inverter INV 1 Serves as the first input terminal of the latch unit and is connected to the drain of NMOS transistor N M2 , The power supply terminal of inverter INV 1 Inputs the high-voltage terminal high level V DDH , The ground terminal of inverter INV 1 Inputs the high-voltage terminal low level V SSH , The output terminal of inverter INV 1 Serves as the second input terminal of the latch unit and is connected to the drain of NMOS transistor N M3 ; Inverter INV 2The high-level V of the high-voltage terminal is input to the power supply terminal DDH , the inverter INV 2 The low-level V of the high-voltage terminal is input to the ground terminal SSH , the inverter INV 2 The input terminal of the inverter INV 1 is connected to the output terminal of the inverter INV 2 The output terminal of the inverter INV 1 is connected to the input terminal of the inverter INV 3 The high-level V of the high-voltage terminal is input to the power supply terminal DDH , the inverter INV 3 The low-level V of the high-voltage terminal is input to the ground terminal SSH , the inverter INV 3 The input terminal of the inverter INV 1 is connected to the output terminal of the inverter INV 3 The output terminal of the inverter INV 4 is used as the second output terminal of the level-shifting module, and is used to output the second output signal OUT~ after level-shifting; the inverter INV DDH The high-level V of the high-voltage terminal is input to the power supply terminal 4 The low-level V of the high-voltage terminal is input to the ground terminal SSH , the inverter INV 4 The input terminal of the inverter INV 2 is connected to the output terminal of the inverter INV 4 The output terminal of the inverter INV

[0052] It should be noted that there is a parasitic capacitance C between the source and drain of the high-voltage NMOS transistor H MN1 , and there is a parasitic capacitance C between the source and drain of the high-voltage NMOS transistor H 3 , and there is a parasitic capacitance C between the gate and source of the PMOS transistor P MN2 , and there is a parasitic capacitance C between the gate and source of the PMOS transistor P 4 , and there is a parasitic capacitance C between the gate and source of the PMOS transistor P M1 , and there is a parasitic capacitance C between the gate and source of the PMOS transistor P 1 , and there is a parasitic capacitance C between the gate and source of the PMOS transistor P M4 , and there is a parasitic capacitance C between the gate and source of the PMOS transistor P 2 .

[0053] Specifically, the pulse generation module of this embodiment includes an inverter I1, a first inverter chain, a second inverter chain, a first AND gate AND1, and a second AND gate AND2. Taking the first pulse signal IN 1 as an example, the delay generated by three inverters is AND-operated with the original signal IN to obtain a rising pulse, that is, the first pulse signal IN 1, used to control the high-voltage NMOS transistor H MN1 for turning on and off. The PMOS transistors P M1 , P M2 , P M5 form a P-type current mirror circuit, and the NMOS transistors N M1 , N M2 form an N-type current mirror circuit, ensuring low-delay output of signals and reducing the interference of the low level V SSH at the high-voltage end on the output signals (i.e., the first output signal OUT and the second output signal OUT~). The PMOS transistors P M7 , P M8 play a voltage clamping role, making the gate-source voltages of P M1 ~P M6 work within the normal voltage range; the resistors R 1 ~R 4 serve to reduce the impedance of the nodes and the influence of current mirror mismatch.

[0054] Aiming at the problems of long delay time and large power consumption in the existing technical solutions, the present invention uses the pulse signals (the first pulse signal IN 1 and the second pulse signal IN 2 ) generated by the pulse generation module to perform switching control on the high-voltage NMOS transistor H MN1 and the high-voltage NMOS transistor H MN2 , greatly reducing the power loss in the circuit and not using high-voltage PMOS transistors, thus effectively saving the layout area. Combining the advantages of energy-saving pulse amplification input, high-bandwidth current mirror and full latch, while stabilizing the output state, the influence brought by current mirror mismatch is minimized to the greatest extent.

[0055] During the operation of the circuit, each time the original input signal IN is converted, only one path is triggered by the pulse generation module, and the first pulse signal IN 1 or the second pulse signal IN 2 after signal delay is generated. That is to say, the first pulse signal IN 1 or the second pulse signal IN 2 will not simultaneously appear at a high level, as shown in Figure 3 .

[0056] The PMOS transistors P M1 , P M4 are respectively connected to the high-voltage NMOS transistor H MN1 and the high-voltage NMOS transistor H MN2 in the form of diodes, forming a gate voltage clamping circuit, making the gate voltages V M1 and P M4 of P G be of the high-level voltage V at the high-voltage end in the normal stateDDH The difference from its gate-source voltage V GS When the input voltage IN goes high, under the action of the pulse generation module, the high-voltage NMOS transistor H MN1 turns on, and the high-voltage NMOS transistor H NM2 turns off, and the current flows through the PMOS transistor P M1 and the high-voltage NMOS transistor H NM1 to the ground, and the voltage at point G 1 (the gate of P M1 ) will be pulled down. When the gate-source voltages of PMOS transistors P M2 and P M5 reach their threshold voltages, PMOS transistors P M2 and P M5 turn on, and the source-drain current of PMOS transistor P M2 flows through P M2 to NMOS transistor N M1 and is copied to NMOS transistor N M2 .

[0057] Similarly, the source-drain current of PMOS transistor P M5 flows through PMOS transistor P M5 to NMOS transistor N M3 . Since NMOS transistor N M3 is not turned on, the source-drain current of PMOS transistor P M5 will flow to node N 2 , that is, the input terminal of inverter INV 3 , causing the potential of node N 2 to start rising. When its voltage reaches the threshold voltage of inverter INV 2 , the voltage at node N 1 , that is, the input terminal of inverter INV 4 , will be pulled to the high-voltage low level V SSH . Due to the feedback of inverter INV 1 , node N 2 will become the high-voltage high level V DDH , and finally outputs through inverters INV 3 and INV 4 respectively. Similarly, when the high-voltage NMOS transistor H NM2 is turned on and the high-voltage NMOS transistor H NM1 is turned off, the PMOS transistor P M6 and the NMOS transistor N M3 are turned on, and the PMOS transistor P M5 and the NMOS transistor N M2 are turned off. Therefore, node N 1 will be pulled up to the high-voltage high level V DDH , node N2 will be pulled down to the low level V of the high voltage terminal SSH . That is to say, the levels of the first output signal OUT and the second output signal OUT~ are opposite under normal circumstances, completing the function of level shift, as Figure 3 shown.

[0058] The delay of the low-delay and small-area level shift circuit proposed by the present invention is lower than that of other types of level shift circuits. Regarding the immunity to the noise of the low level V of the high voltage terminal SSH , due to the existence of the current mirror, it will be alleviated to a certain extent. When noise is generated and acts on the high level V of the high voltage terminal DDH , the PMOS transistors P M3 、P M6 and the PMOS transistors P M2 、P M5 will respectively mirror the noise current to the NMOS transistors N M2 and the NMOS transistor N M3 . If the initial state of the node N 1 is the low level V of the high voltage terminal SSH , the PMOS transistor P M6 will raise the potential of this point, while the NMOS transistor N M2 will pull down this point. At this time, the voltage of this point will decrease, and the OUT level will still remain high, basically unaffected by the V SSH noise.

[0059] For the low-delay and small-area level shift circuit of the present invention, the symmetry during the rising and falling processes of the circuit is optimized. When the rising edge of the original input signal IN arrives, the nodes N 2 and N 1 are respectively pulled up by the PMOS transistor P M5 and the NMOS transistor N M2 . When the falling edge of the original signal IN arrives, the nodes N 1 and N 2 will be pulled up and down with the same principle. This optimization eliminates the need to consider the propagation delay of the latch and reduces the influence of the V SSH fluctuation on the output signal. The fluctuation of V SSH is mapped to the PMOS transistors P M5 and the PMOS transistor P M6 , as well as the parasitic currents of the NMOS transistors N M2 and the NMOS transistor N M3 . If the initial state of the node N 1 is V SSH , then the PMOS transistor P M6 will raise the node N 1 , but the NMOS transistor N M2 will simultaneously pull down the node N1 At node N 1 the voltage will be greatly reduced while OUT remains high. When the high-voltage NMOS transistor H MN1 and the high-voltage NMOS transistor H MN2 are turned off, node G 1 (i.e., the gate of PMOS transistor P M1 ) and G 2 (i.e., the gate of PMOS transistor P M4 ) are in a high-resistance state. Resistors R 1 , R 2 , R 3 , R 4 provide a low-resistance path from V DDH to the gates of PMOS transistors P M1 ~P M6 and a low-resistance path from V SSH to the gates of NMOS transistors N M1 ~N M4 . At node G 1 , when the high-voltage MOS transistor H NM1 is turned off, the current flowing through resistor R 1 in PMOS transistor P M1 is used to discharge the parasitic capacitance C 1 , reducing the gate-source voltage V M1 of PMOS transistor P GS and accelerating the current decay of PMOS transistors P M1 , P M2 , P M5 , thus reducing the high-resistance node and current mirror mismatch problems. The circuit structure proposed by the present invention not only reduces the power loss of the circuit, but also can greatly reduce the delay during transmission. The output signal has greater anti-interference characteristics and can be applied to motor drive circuits.

[0060] The present invention proposes a low-delay and low-power floating level-shifting circuit. Compared with the traditional level-shifting circuit, by using a pulse generation module to generate a rising edge to control the turn-on of the high-voltage NMOS transistor H MN1 and the high-voltage NMOS transistor H MN2 , the high and low level triggers in the existing circuit structure are changed, effectively reducing the power loss of the circuit. The present invention uses a current mirror structure to make the pull-up current the same as the pull-down current. By adding an N-type current mirror, the problem of asymmetric transmission time is solved, the output delay is reduced, and the interference of the low level V SSH at the high-voltage end to the signal is reduced, improving the anti-interference ability of the output signal. The role of resistors R 1 ~R 4 is to reduce nodes G 1 , G 2The impedance reduces the impact of current mirror mismatch. High-voltage PMOS transistors are not used in the present invention, thus effectively saving the circuit area.

[0061] The present invention includes a pulse input, a high-bandwidth current mirror, and a latch, which minimizes the impact of current mirror mismatch while stabilizing the output state. Therefore, the present invention proposes a level shift circuit applicable to a motor drive circuit, which can solve some non-ideal effects in the prior art and improve the overall performance of the level shift circuit without increasing the circuit scale. The AND gate of the pulse generation module of the present invention is reasonably designed to ensure that the time delays from the original signal IN to the first pulse signal IN1 or the second pulse signal IN2 are matched. At the same time, it reduces the power consumption of the circuit without increasing the circuit complexity, ensures the stability during level conversion, and minimizes the adverse impact of current mirror mismatch.

[0062] In several embodiments provided by the present invention, it should be understood that the devices and methods disclosed in the present invention can be implemented in other ways. For example, the device embodiments described above are only illustrative. For example, the division of modules is only a logical function division. In actual implementation, there may be other division methods. For example, multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed.

[0063] In addition, each functional module in various embodiments of the present invention can be integrated in a processing module, or each module can exist physically alone, or two or more modules can be integrated in one module. The above integrated modules can be implemented in the form of hardware or in the form of a combination of hardware and software functional modules.

[0064] The above content is a further detailed description of the present invention in combination with specific preferred embodiments. It cannot be determined that the specific implementation of the present invention is only limited to these descriptions. For those of ordinary skill in the technical field to which the present invention belongs, without departing from the concept of the present invention, several simple deductions or substitutions can still be made, which should all be regarded as belonging to the protection scope of the present invention.

Claims

1. A low-delay, small-area level shift circuit, characterized in that: Including pulse generation module, NMOS tube H MN1 、NMOS tube H MN2 and a level shift module, wherein: The pulse generating module is used to perform signal delay on the input original signal IN to generate a first pulse signal IN1 or a second pulse signal IN2 after signal delay, wherein the high level of the first pulse signal IN1 and the high level of the second pulse signal IN2 are in different time periods; The NMOS tube H MN1 The gate of the NMOS tube H is connected to the first output terminal of the pulse generating module to receive the first pulse signal IN1. MN1 The source of the NMOS tube H is connected to the ground terminal. MN1 A drain electrode is connected to the first input terminal of the level shift module; The NMOS tube H MN2 The gate of the NMOS tube H is connected to the second output terminal of the pulse generating module to receive the second pulse signal IN2. MN2 The source of the NMOS tube H is connected to the ground terminal. MN2 A drain electrode is connected to the second input terminal of the level shift module; The first pulse signal IN1 is used to control the NMOS transistor H MN1 The second pulse signal IN2 is used to control the on / off of the NMOS tube H MN2 The on-off of the level shift module is controlled to achieve the level shift of the original signal IN.

2. The low-delay, small-area level shift circuit according to claim 1, characterized in that: The pulse generating module includes an inverter I1, a first inverter chain, a second inverter chain, a first AND gate AND1 and a second AND gate AND2, wherein: The input end of the first inverter chain is connected to the input end of the inverter I1, the output end of the first inverter chain is connected to the first input end of the first AND gate AND1, and the second input end of the first AND gate AND1 is connected to the input end of the inverter I1; the original signal IN is input to the input end of the inverter I1; the output end of the first AND gate AND1 is connected to the NMOS transistor H MN1 The gate of the first AND gate AND1, the output end of the first AND gate AND1 is used to output the first pulse signal IN1; The input end of the second inverter chain is connected to the output end of the inverter I1, the output end of the second inverter chain is connected to the first input end of the second AND gate AND2, the second input end of the second AND gate AND2 is connected to the output end of the inverter I1; the output end of the second AND gate AND2 is connected to the NMOS transistor H MN2 The gate of the second AND gate AND1, the output end of the second AND gate AND1 is used to output the second pulse signal IN2; The first inverter chain and the second inverter chain have the same number of inverters.

3. The low-delay, small-area level shift circuit according to claim 2, characterized in that: The first inverter chain includes three inverters connected in series between the input terminal of the inverter I1 and the first input terminal of the first AND gate AND1 , and the second inverter chain includes three inverters connected in series between the output terminal of the inverter I1 and the first input terminal of the second AND gate AND1 .

4. The low-delay, small-area level shift circuit according to claim 2, characterized in that: The level shift module includes a level shift unit and a latch unit, wherein: The level shift module is used to MN1 and the NMOS tube H MN2 Performing level shifting of the original signal under the control of The latch unit is used to ensure the logic correctness of the level shift signal and speed up the level flipping speed, and output the final level shift signal.

5. The low-delay, small-area level shift circuit according to claim 4, characterized in that: The level shift unit includes a PMOS tube P M1 、PMOS tube P M2 、PMOS tube P M3 、PMOS tube P M4 、PMOS tube P M5 、PMOS tube P M6 、PMOS tube P M7 、PMOS tube P M8 、NMOS tube N M1 、NMOS tube N M2 、NMOS tube N M3 、NMOS tube N M4 , resistor R1, resistor R2, resistor R3 and resistor R4, wherein, The PMOS tube P M1 The source of the PMOS tube P M2 The source of the PMOS tube P M3 The source of the PMOS tube P M4 The source of the PMOS tube P M5 The source of the PMOS tube P M6 The source of the PMOS tube P M7 The source and the PMOS tube P M8 The source of the high voltage terminal is connected to the high voltage V DDH ; The PMOS tube P M7 The drain of the PMOS tube P M7 The gate of the PMOS tube P M1 The drain of the PMOS tube P M1 The gate of the PMOS tube P M2 The gate of the PMOS tube P M5 The gates are connected to the NMOS tube H MN1 The drain; The PMOS tube P M2 The drain of the NMOS tube N M1 The drain of the NMOS tube N M1 The gate and the NMOS tube N M2 The gate of the PMOS tube P M5 The drain of the NMOS tube N M3 The drain of the latch unit and the first input terminal of the latch unit, the PMOS tube P M6 The drain of the NMOS tube N M2 The drain of the PMOS tube P M6 The gate of the PMOS tube P M3 The gate of the PMOS tube P M4 The gate of the PMOS tube P M4 The drain of the PMOS tube P M8 The gate of the PMOS tube P M8 The drain of the NMOS tube H MN2 The drain; The PMOS tube P M3 The drain of the NMOS tube N M4 The drain of the NMOS tube N M4 The gate of the NMOS tube N M3 The gate of the NMOS tube N M1 The source of the NMOS tube N M2 The source of the NMOS tube N M3 The source and the NMOS tube N M4 The source of the high voltage terminal is connected to the low voltage V SSH ; The resistor R1 is connected to the high voltage end high level V DDH With the PMOS tube P M1 The resistor R2 is connected to the high voltage end high level V DDH With the PMOS tube P M3 The resistor R3 is connected between the gates of the NMOS tube N M1 The resistor R4 is connected between the gate and source of the NMOS tube N M3 between the gate and source.

6. The low-delay, small-area level shift circuit according to claim 5, characterized in that: The high voltage end high level V DDH and the high voltage end low level V SSH They are respectively the highest level and the lowest level of the signal after level shifting.

7. The low-delay, small-area level shift circuit according to claim 5, characterized in that: The latch unit includes an inverter INV1, an inverter INV2, an inverter INV3 and an inverter INV4, wherein: The input end of the inverter INV1 is used as the first input end of the latch unit and is connected to the NMOS tube N M2 The drain of the inverter INV1 inputs the high voltage end high level V DDH The ground terminal of the inverter INV1 inputs the high voltage low level V SSH The output end of the inverter INV1 is used as the second input end of the latch unit and is connected to the NMOS tube N M3 The drain; The power supply end of the inverter INV2 inputs the high voltage end high level V DDH The ground terminal of the inverter INV2 inputs the high voltage low level V SSH , the input end of the inverter INV2 is connected to the output end of the inverter INV1, and the output end of the inverter INV2 is connected to the input end of the inverter INV1; The power supply end of the inverter INV3 inputs the high voltage end high level V DDH The ground terminal of the inverter INV3 inputs the high voltage low level V SSH , the input end of the inverter INV3 is connected to the output end of the inverter INV1, and the output end of the inverter INV3 serves as the second output end of the level shift module, for outputting the second output signal OUT~ after level shifting; The power supply end of the inverter INV4 inputs the high voltage end high level V DDH The ground terminal of the inverter INV4 inputs the high voltage low level V SSH The input end of the inverter INV4 is connected to the output end of the inverter INV2, and the output end of the inverter INV4 serves as the first output end of the level shift module, for outputting the first output signal OUT after level shifting.

8. The low-delay, small-area level shift circuit according to claim 7, characterized in that: The first output signal OUT and the second output signal OUT~ are inverted signals.

9. The low-delay small-area level shift circuit according to any one of claims 1 to 8, characterized in that: The NMOS tube H MN1 and the NMOS tube H MN2 It is a high voltage NMOS tube.

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