Analog-to-digital conversion method and device, two-stage analog-to-digital converter and storage medium

Abstract

The application provides an analog-to-digital conversion method and device, a two-stage analog-to-digital converter and a storage medium, and relates to the technical field of analog-to-digital conversion. The method comprises the following steps: sampling a first voltage signal to be converted based on a first-stage analog-to-digital converter, and controlling the lower plate of a low-bit capacitor array in the first-stage analog-to-digital converter to retain the conversion code value of the last period; converting a second voltage signal to be converted based on the first-stage analog-to-digital converter, obtaining a first conversion code value, transmitting the voltage residual after conversion to the upper plate of a second capacitor array in a second-stage analog-to-digital converter after amplification, and controlling the lower plate of the second capacitor array to retain the conversion code value of the last period in the sampling process; resetting the lower plate of the second capacitor array to obtain a third voltage signal to be converted; converting the third voltage signal to be converted based on the second-stage analog-to-digital converter to obtain a second conversion code value, and determining the digital signal after conversion based on the first conversion code value and the second conversion code value.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of analog-to-digital conversion, and in particular to an analog-to-digital conversion method and device, a two-stage analog-to-digital converter, and a storage medium. BACKGROUND

[0002] In a high-precision analog-to-digital converter, a pipelined successive approximation register (SAR) architecture is a very common architecture, but its precision is often affected by capacitor mismatch and inter-stage gain error. In order to solve the mismatch problem of the capacitor array, an off-chip calibration method based on the least mean square (LMS) algorithm is proposed in the prior art, but this method requires additional off-chip processing, which will introduce additional cost for large-scale production. The in-chip solution is mainly based on dynamic element matching (DEM), which uses a binary array composed of completely identical unit elements to scatter the mismatch error between each unit in a dynamic random manner. In addition, there is a mismatch error shaping (MES) technology, which injects the reverse mismatch error of the previous cycle by retaining the digital code value obtained by the previous cycle conversion during sampling, forming a first-order shaping of the mismatch error, thereby reducing the influence of the mismatch error.

[0003] In addition to the mismatch error, the gain error is also one of the bottlenecks that limit the precision of the pipelined architecture. In order to solve the problem of gain error, an off-chip calibration method can also be used. The in-chip solution is a calibration method based on random jitter injection, which injects a known random jitter, and after amplification, a signal component related to the random jitter will be reflected in the output, and then the autocorrelation algorithm can be used to inversely solve the actual inter-stage gain value.

[0004] However, the existing technologies are only for one of the mismatch error or the gain error, and cannot simultaneously eliminate the mismatch error and the gain error. SUMMARY

[0005] The embodiments of the present application provide an analog-to-digital conversion method and device, a two-stage analog-to-digital converter, and a storage medium, to realize the cooperative processing of the mismatch error and the gain error in the analog-to-digital converter.

[0006] In a first aspect, an embodiment of the present application provides an analog-to-digital conversion method applied to a two-stage analog-to-digital converter, the two-stage analog-to-digital converter comprising a first-stage analog-to-digital converter and a second-stage analog-to-digital converter; the method comprising: sampling, based on the first-stage analog-to-digital converter, a first voltage signal to be converted, and in the sampling process, controlling a lower plate of a low-bit capacitor array in the first-stage analog-to-digital converter to retain a conversion code value of a previous period; resetting the lower plate of a first capacitor array in the first-stage analog-to-digital converter, and adding a low-bit voltage signal corresponding to the previous period to an upper plate of the first capacitor array to obtain a second voltage signal to be converted; converting, based on the first-stage analog-to-digital converter, the second voltage signal to be converted to obtain a first conversion code value, and transmitting, after amplification, a voltage residue after conversion to the upper plate of a second capacitor array in the second-stage analog-to-digital converter, and in the sampling process, controlling a lower plate of the second capacitor array to retain the conversion code value of the previous period; resetting the lower plate of the second capacitor array, and adding a voltage signal corresponding to the previous period to the upper plate of the second capacitor array to obtain a third voltage signal to be converted; converting, based on the second-stage analog-to-digital converter, the third voltage signal to be converted to obtain a second conversion code value, and determining a digital signal after conversion based on the first conversion code value and the second conversion code value.

[0007] In some embodiments, the first capacitor array further comprises a feedback capacitor; the latch is configured to transmit a highest-bit conversion code value of the second analog-to-digital converter of a previous period to a lower plate of the feedback capacitor; and the feedback capacitor is switched according to the highest-bit conversion code value, and after the first capacitor array is switched, the voltage residue after conversion is obtained.

[0008] As a possible implementation, the controlling of the lower plate of the low-bit capacitor array in the first-stage analog-to-digital converter to retain the conversion code value of the previous period comprises: controlling the lower plate of the low-bit capacitor array and the lower plate of the feedback capacitor to each retain the conversion code value of the respective previous period; and the adding of the low-bit voltage signal corresponding to the previous period to the upper plate of the first capacitor array to obtain the second voltage signal to be converted comprises: adding the low-bit voltage signal corresponding to the previous period and a voltage signal of the feedback capacitor of the previous period to the upper plate of the first capacitor array to obtain the second voltage signal to be converted.

[0009] In some embodiments, the method further comprises, in the sampling process of the first voltage signal to be converted: determining a polarity of the first voltage signal to be converted; and switching, based on the polarity of the first voltage signal to be converted, the lower plate of a highest-bit capacitor array in the first-stage analog-to-digital converter.

[0010] As a possible implementation, the switching the lower plate of the highest bit capacitor array in the first stage analog-digital converter based on the polarity of the first voltage signal to be converted comprises: setting the lower plate of the highest bit capacitor array to 1 if the first voltage signal to be converted is greater than 0; setting the lower plate of the highest bit capacitor array to -1 if the first voltage signal to be converted is less than 0.

[0011] In some embodiments, the first stage analog-digital converter is connected with the second stage analog-digital converter through an inter-stage integrator; and in the process of receiving the amplified voltage residue at the upper plate of the second capacitor array, the method further comprises: controlling the upper plate of the second capacitor array to retain the voltage residue converted in the last cycle.

[0012] In the second aspect, the embodiments of the present application provide an analog-digital conversion device configured in a two-stage analog-digital converter, the two-stage analog-digital converter comprising a first stage analog-digital converter and a second stage analog-digital converter; the device comprises: a sampling module configured to sample a first voltage signal to be converted based on the first stage analog-digital converter, and in the sampling process, control the lower plate of a low bit capacitor array in the first stage analog-digital converter to retain a conversion code value in the last cycle; a first reset module configured to reset the lower plate of a first capacitor array in the first stage analog-digital converter, and add a low bit voltage signal corresponding to the last cycle to the upper plate of the first capacitor array to obtain a second voltage signal to be converted; a first conversion module configured to convert the second voltage signal to be converted based on the first stage analog-digital converter to obtain a first conversion code value, and transmit the converted voltage residue to the upper plate of a second capacitor array in the second stage analog-digital converter after amplification, and in the sampling process, control the lower plate of the second capacitor array to retain the conversion code value in the last cycle; a second reset module configured to reset the lower plate of the second capacitor array, and add a voltage signal corresponding to the last cycle to the upper plate of the second capacitor array to obtain a third voltage signal to be converted; and a second conversion module configured to convert the third voltage signal to be converted based on the second stage analog-digital converter to obtain a second conversion code value, and determine a converted digital signal based on the first conversion code value and the second conversion code value.

[0013] In the third aspect, the embodiments of the present application provide a two-stage analog-digital converter comprising a processor and a memory storing a computer program, and the processor implements the analog-digital conversion method of the first aspect when executing the computer program.

[0014] In the fourth aspect, the embodiments of the present application provide a non-transitory computer readable storage medium storing a computer program, and the computer program is executed by a processor to implement the analog-digital conversion method of the first aspect.

[0015] In a fifth aspect, an embodiment of the present application provides a computer program product, comprising a computer program, wherein the computer program, when executed by a processor, implements the analog-to-digital conversion method in the first aspect.

[0016] The analog-to-digital conversion method, device, two-stage analog-to-digital converter and storage medium provided by the embodiment of the present application are applied to the second analog-to-digital converter, the first voltage signal to be converted is sampled based on the first-stage analog-to-digital converter, and in the sampling process, the lower plate of the low-bit capacitor array in the first-stage analog-to-digital converter is controlled to retain the conversion code value of the last period; the lower plate of the first capacitor array in the first-stage analog-to-digital converter is reset, and the low-bit voltage signal corresponding to the last period is added to the upper plate of the first capacitor array to obtain the second voltage signal to be converted; the second voltage signal to be converted is converted based on the first-stage analog-to-digital converter to obtain the first conversion code value, and the voltage residue after conversion is transmitted to the upper plate of the second capacitor array in the second-stage analog-to-digital converter after being amplified, and in the sampling process, the lower plate of the second capacitor array is controlled to retain the conversion code value of the last period; the lower plate of the second capacitor array is reset, and the voltage signal corresponding to the last period is added to the upper plate of the second capacitor array to obtain the third voltage signal to be converted; the third voltage signal to be converted is converted based on the second-stage analog-to-digital converter to obtain the second conversion code value, and the digital signal after conversion is determined based on the first conversion code value and the second conversion code value. The gain error and the weight of the second capacitor array in the second-stage analog-to-digital converter are combined together, that is, the gain error is also regarded as a mismatch error to be eliminated, the mismatch error and the gain error are simultaneously shaped, and the conversion precision of the analog-to-digital converter is improved. BRIEF DESCRIPTION OF DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the present application or the prior art, the following will briefly introduce the drawings needed in the embodiments or prior art description. Obviously, the drawings in the following description are some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without any creative effort.

[0018] Figure 1 One of the flowcharts of the analog-to-digital conversion method provided by the embodiment of the present application;

[0019] Figure 2 The second flowchart of the analog-to-digital conversion method provided by the embodiment of the present application;

[0020] Figure 3 The third flowchart of the analog-to-digital conversion method provided by the embodiment of the present application;

[0021] Figure 4 The fourth flowchart of the analog-to-digital conversion method provided by the embodiment of the present application;

[0022] Figure 5 a circuit schematic diagram of a two-stage analog-to-digital converter in an embodiment of the present application;

[0023] Figure 6 a structural schematic diagram of an analog-to-digital conversion device provided in an embodiment of the present application;

[0024] Figure 7 a structural schematic diagram of a two-stage analog-to-digital converter provided in an embodiment of the present application. DETAILED DESCRIPTION

[0025] In order to make the objectives, technical solutions and advantages of the present application clearer, the technical solutions in the present application will be described clearly and completely below with reference to the drawings in the present application. Obviously, the described embodiments are some embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0026] In a high-precision analog-to-digital converter, a pipelined successive approximation register (SAR) architecture is a very common architecture, but its precision is often affected by capacitor mismatch and inter-stage gain error. In order to solve the mismatch problem of the capacitor array, an off-chip calibration method based on the least mean square (LMS) algorithm is proposed in the prior art, but this method requires additional off-chip processing, which will introduce additional cost for large-scale production. The in-chip solution is mainly based on dynamic element matching (DEM), which uses a binary array composed of completely identical unit elements, and uses a dynamic random method to scatter the mismatch error between each unit. In addition, there is a mismatch error shaping (MES) technology, which injects the reverse mismatch error of the previous cycle by retaining the digital code value obtained by the conversion of the previous cycle during sampling, forming a first-order shaping of the mismatch error, thereby reducing the influence of the mismatch error.

[0027] In addition to the mismatch error, the gain error is also one of the bottlenecks that limit the precision of the pipelined architecture. In order to solve the problem of gain error, an off-chip calibration method can also be used. The in-chip solution is a calibration method based on random jitter injection, which injects a known random jitter, and after amplification, a signal component related to the random jitter will be reflected in the output, and then the autocorrelation algorithm can be used to inversely solve the actual inter-stage gain value. In recent years, there have also been proposals for gain error shaping techniques, which reduce the requirement for inter-stage gain accuracy by predicting or shaping the input of the inter-stage amplifier in advance.

[0028] Dynamic element matching for mismatch error cancellation can well spread the harmonics caused by mismatch, but due to the need to use units to form an array, the additional cost required by this technology will increase exponentially as the array bit number rises, resulting in area and power loss.

[0029] In addition, the previously proposed mismatch error shaping techniques can only be limited to single-stage SAR (Successive Approximation Register) architecture and cannot be used in multi-stage architecture. The inter-stage mismatch in the multi-stage pipeline architecture cannot be shaped or eliminated, resulting in precision loss.

[0030] As for the elimination of gain error, the random dithering injection method can effectively perform gain background calibration, but since it is based on autocorrelation algorithm calibration, there is a certain convergence time, and additional digital circuits are needed for digital operation processing, which brings power consumption and area cost.

[0031] The existing gain error shaping means can effectively reduce the influence of gain error, but the early prediction of the first stage quantization margin has certain precision requirements, so additional noise shaping ADC (Analog to Digital Converter) is needed to perform coarse quantization; The practice of shaping the margin in advance requires multi-bit feedback, which is limited by the capacitor layout, and will bring truncation error. At the same time, these two methods will bring additional mismatch capacitor arrays, which need to be calibrated off-chip.

[0032] However, the existing technologies are only for one of the mismatch error or the gain error, and cannot eliminate both the mismatch error and the gain error.

[0033] To solve the above problems, the embodiments of the present application provide an analog-to-digital conversion method, device, two-stage analog-to-digital converter and storage medium.

[0034] Figure 1 The flowchart of the analog-to-digital conversion method provided by the embodiments of the present application. The analog-to-digital conversion method of the embodiments of the present application is applied to a two-stage analog-to-digital converter, which includes a first-stage analog-to-digital converter and a second-stage analog-to-digital converter. As shown in the figure, the method can include the following steps. Figure 1

[0035] Step 101, sampling the first voltage signal to be converted based on the first-stage analog-to-digital converter, and in the sampling process, the lower plate of the low-bit capacitor array in the first-stage analog-to-digital converter is controlled to retain the conversion code value of the last period.

[0036] ​That is, the analog-digital conversion method of the embodiment of the present application adopts the mismatch error shaping method to solve the mismatch problem of the capacitor array, so that the lower plate of the low-bit capacitor array in the first analog converter retains the conversion code value of the last cycle in the current cycle sampling stage.

[0037] The first voltage signal to be converted is the input signal connected to the upper plate of the first analog-digital converter.

[0038] In step 102, the lower plate of the first capacitor array in the first analog-digital converter is reset, and the low-bit voltage signal corresponding to the last cycle is added to the upper plate of the first capacitor array to obtain a second voltage signal to be converted.

[0039] In some embodiments, after sampling is completed, the sampling switch port in the first analog-digital converter is reset, and the lower plate of all capacitors returns to the VCM common-mode voltage. The first capacitor array refers to all capacitors in the first analog-digital converter. Since the lower plate of the low-bit capacitor array retains the conversion code value of the last cycle in the sampling stage, the low-bit voltage signal converted in the last cycle needs to be added back to the upper plate of the first capacitor array after reset, which is equivalent to adding the mismatch error of the last cycle back to the signal.

[0040] In some embodiments, the second voltage signal to be converted is the voltage signal received by the upper plate of the first capacitor array, i.e., the voltage signal obtained by adding the first voltage signal to be converted in the sampling stage and the low-bit voltage signal in the last cycle. That is, the voltage signal of the upper plate of the first capacitor array in the reset stage is expressed as the following formula (1).

[0041] (1);

[0042] Wherein, is the voltage signal of the upper plate of the first capacitor array in the reset stage; is the first voltage signal to be converted in the current cycle; is the low-bit voltage signal of the first analog-digital converter in the last cycle.

[0043] In step 103, the first analog-digital converter converts the second voltage signal to be converted to obtain a first conversion code value, and transmits the converted voltage residual after amplification to the upper plate of the second capacitor array in the second analog-digital converter, and controls the lower plate of the second capacitor array to retain the conversion code value of the last cycle in the sampling process.

[0044] In some embodiments, the first-stage analog-to-digital converter performs normal conversion on the second to-be-converted voltage signal to obtain a converted digital code value, i.e., a first converted code value. That is, the lower plate of the highest bit capacitor array in the first capacitor array after conversion is the highest bit converted code value, and the lower plate of the low bit capacitor array is the low bit converted code value. Based on the converted code value, all capacitors are switched to remove the voltage signal converted in the current period from the upper plate of the first capacitor array, and the voltage signal of the upper plate of the first capacitor array at this time is the converted voltage residual. Specifically, the voltage signal of the upper plate of the first capacitor array after conversion is shown in the following formula (2).

[0045] (2);

[0046] wherein, is the voltage signal converted in the current period by the first-stage analog-to-digital converter. Since the addition of is equivalent to adding the mismatch error of the previous period back to the signal, and also contains the mismatch error of the current period.

[0047] In addition, during the conversion process, the mismatch error of the current period introduced will form a first-order shaping with the mismatch error of the previous period added back, thereby achieving elimination of the mismatch error.

[0048] In some embodiments, the voltage residual can be amplified by an amplifier, and the amplified voltage residual is transmitted to the upper plate of the second capacitor array in the second-stage analog-to-digital converter to enter the sampling stage of the second-stage analog-to-digital converter.

[0049] Since the second-stage analog-to-digital converter involves gain error and mismatch error, in order to simultaneously shape the gain error and the mismatch error, the gain of the inter-stage is combined with the weight of the second capacitor array, i.e., the weight of the second capacitor array is taken as , and the gain error is also eliminated as a mismatch error.

[0050] In some embodiments, the gain error and the mismatch error are simultaneously eliminated by using a mismatch error shaping method in the second-stage analog-to-digital converter. In the sampling stage of the second-stage analog-to-digital converter, the sampling switch is closed, and all the lower plates of the capacitors are controlled to retain the converted code value of the previous period. The second capacitor array refers to all the capacitors in the second-stage analog-to-digital converter.

[0051] Step 104, reset the lower plate of the second capacitor array, and add the voltage signal corresponding to the previous period to the upper plate of the second capacitor array to obtain a third to-be-converted voltage signal.

[0052] In some embodiments, after the sampling is completed, the sampling switch is turned off, the lower plates of all the capacitors are reset to the VCM common-mode voltage, so the voltage signal corresponding to the previous period needs to be added back to the upper plates of the second capacitor array, so that the mismatch error of the previous period of the second analog-to-digital converter is also added back to the signal. Since all the bits in the second stage analog-to-digital converter participate in the shaping operation, the gain error is also added back to the signal as part of the mismatch error. In the reset phase, the voltage signal of the upper plate of the second capacitor array can be expressed by the following formula (3).

[0053] (3);

[0054] wherein, is the voltage signal of the upper plate of the second capacitor array; is the inter-stage gain; is the voltage residue transmitted by the first stage analog-to-digital converter to the second analog-to-digital converter in the current period; is the voltage signal converted by the second analog-to-digital converter in the previous period.

[0055] wherein, the third voltage signal to be converted is the voltage signal of the upper plate of the second capacitor array after the reset is completed.

[0056] Step 105, converting the third voltage signal to be converted based on the second stage analog-to-digital converter, obtaining a second conversion code value, and determining a converted digital signal based on the first conversion code value and the second conversion code value.

[0057] In some embodiments, after the reset is completed, the second stage analog-to-digital converter converts the third voltage signal to be converted to obtain a second conversion code value.

[0058] In the conversion process, the current period mismatch error and the inter-stage error introduced will form a first-order shaping with the added error signal of the previous period. When determining the final converted digital signal, the first conversion code value and the second conversion code value can be used to splice and restore using ideal weights and inter-stage gains, and then compensate for the additional converted previous period signal, so that the actual input voltage can be obtained, and the gain error and the mismatch error can be shaped cooperatively.

[0059] According to the analog-digital conversion method provided by the embodiment of the present application, the first voltage signal to be converted is sampled based on the first analog-digital converter, and during the sampling process, the lower plate of the low-bit capacitor array in the first analog-digital converter retains the conversion code value of the previous cycle; the lower plate of the first capacitor array in the first analog-digital converter is reset, and the low-bit voltage signal corresponding to the previous cycle is added to the upper plate of the first capacitor array to obtain a second voltage signal to be converted; the second voltage signal to be converted is converted based on the first analog-digital converter to obtain a first conversion code value, and the voltage residue after conversion is transmitted to the upper plate of the second capacitor array in the second analog-digital converter after being amplified, and during the sampling process, the lower plate of the second capacitor array retains the conversion code value of the previous cycle; the lower plate of the second capacitor array is reset, and the voltage signal corresponding to the previous cycle is added to the upper plate of the second capacitor array to obtain a third voltage signal to be converted; the third voltage signal to be converted is converted based on the second analog-digital converter to obtain a second conversion code value, and the digital signal after conversion is determined based on the first conversion code value and the second conversion code value. The gain error and the weight of the second capacitor array in the second analog-digital converter are combined together, that is, the gain error is also regarded as a mismatch error to be eliminated, so that the mismatch error and the gain error in the two-stage analog-digital converter are simultaneously shaped, and the conversion precision of the analog-digital converter is improved.

[0060] It can be understood that, since the upper plate of the second capacitor array is added with the voltage signal converted in the previous cycle during the reset phase of each cycle, the second analog-digital converter is saturated. In order to solve this problem, another embodiment is provided in the present application.

[0061] Figure 2 A flowchart of the analog-digital conversion method provided by the embodiment of the present application is shown in FIG. 2. In the embodiment of the present application, a feedback capacitor is introduced into the first capacitor array of the first analog-digital converter. That is, the first capacitor array of the first analog-digital converter includes a highest-bit capacitor array, a low-bit capacitor array and a feedback capacitor. The feedback capacitor is used to accept the highest-bit conversion code value of the previous cycle of the second analog-digital converter, so as to associate the first analog-digital converter and the second analog-digital converter, and solve the saturation problem faced by the second analog-digital converter. As shown in FIG. 2, based on the above embodiment, after the second voltage to be converted is converted based on the first analog-digital converter, the following steps are further included. Figure 2

[0062] Step 201: based on the latch, the highest-bit conversion code value of the previous cycle of the second analog-digital converter is transmitted to the lower plate of the feedback capacitor.

[0063] ​In some embodiments, after the second modulus converter converts the highest bit conversion code value in the last cycle, the highest bit conversion code value in the last cycle is transmitted to a latch for storage. Based on the latch, the highest bit conversion code value of the second modulus converter in the last cycle is transmitted to the lower plate of the feedback capacitor after the first modulus converter converts in the current cycle.

[0064] In step 202, the feedback capacitor is switched according to the highest bit conversion code value, and after the first capacitor array is switched, the converted voltage residue is obtained.

[0065] In some embodiments, the feedback capacitor is switched based on the highest bit conversion code value of the lower plate of the feedback capacitor, the highest bit conversion code value of the lower plate of the feedback capacitor is multiplied by the weight of the feedback capacitor to obtain the voltage signal of the feedback capacitor in the current cycle, and the voltage signal is subtracted from the upper plate of the first capacitor array. In this stage, the relevant information of the second stage mismatch is transmitted to the first stage, and the correlation between the two stages is realized. After the voltage signal of the feedback capacitor in the current cycle is subtracted from the upper plate of the first capacitor array, the obtained voltage residue is greatly reduced, thereby solving the saturation problem faced by the second modulus converter.

[0066] Since the feedback capacitor is introduced, the mismatch problem of the feedback capacitor also needs to be considered. In the two-stage modulus converter, the mismatch error shaping method is used, so in the sampling stage of the first modulus converter, the lower plate of the low bit capacitor array and the lower plate of the feedback capacitor need to retain their respective conversion code values in the last cycle. Since the feedback capacitor receives the highest bit conversion code value of the second modulus converter in the last cycle after each cycle conversion is completed, the conversion code value retained by the lower plate of the feedback capacitor in the sampling stage of the current cycle (n) is equivalent to the highest bit conversion code value of the second modulus converter in the last cycle (n-2).

[0067] Therefore, in the reset stage of the first modulus converter in the current cycle, the lower plate of the feedback capacitor is also reset to the VCM common mode voltage. In the process of adding the corresponding low bit voltage signal of the last cycle to the upper plate of the first capacitor array to obtain the second to-be-converted voltage signal, the execution process includes: adding the corresponding low bit voltage signal of the last cycle and the voltage signal of the feedback capacitor in the last cycle to the upper plate of the first capacitor array to obtain the second to-be-converted voltage signal. Adding the voltage signal of the feedback capacitor in the last cycle to the upper plate of the first capacitor array is equivalent to adding the mismatch error of the feedback capacitor in the last cycle back to the signal. After conversion, the voltage signal of the feedback capacitor in the current cycle is removed from the signal, which is equivalent to eliminating the mismatch error of all capacitors in the first modulus converter in the converted voltage residue.

[0068] Specifically, after introducing the feedback capacitor, the voltage signal of the upper plate of the first capacitor array in the reset stage is shown in the following formula (4). In the feedback stage, the voltage signal of the upper plate of the first capacitor array is shown in the following formula (5).

[0069] (4);

[0070]

[0071] (5);

[0072] wherein, is the voltage signal of the feedback capacitor in the last period; is the voltage signal of the feedback capacitor in the current period.

[0073] According to the analog-digital conversion method provided by the embodiment of the present application, by introducing the feedback capacitor in the first capacitor array, the highest bit conversion code value of the second stage analog-digital converter in the last period is accepted based on the feedback capacitor, so that the saturation problem of the second analog-digital converter can be solved, and the first stage analog-digital converter and the second stage analog-digital converter can be associated. That is, all the capacitor mismatch errors and inter-stage gain errors can be simultaneously shaped out of the effective bandwidth by the present application, so that the entire circuit architecture can achieve the target precision without additional calibration.

[0074] In the above embodiment, the voltage value actually converted by the first stage analog-digital converter is the input voltage plus the voltage value corresponding to the low bit in the last period, so that in the extreme condition, it may reach close to 1.5 times the input swing, resulting in saturation of the two-stage analog-digital converter and thus damage to the precision. In order to avoid the loss of input swing, the present application provides another embodiment.

[0075] Figure 3 Fig. 3 is a flowchart of the analog-digital conversion method provided by the embodiment of the present application. As shown in the figure, based on the above embodiment, the sampling process of the first to-be-converted voltage signal further includes the following steps: Figure 3

[0076] Step 301: determining the polarity of the first to-be-converted voltage signal.

[0077] Step 302: switching the lower plate of the highest bit capacitor array in the first stage analog-digital converter based on the polarity of the first to-be-converted voltage signal.

[0078] That is, in the sampling process of the input signal (the first to-be-converted voltage signal), the highest bit conversion code value corresponding to the first to-be-converted voltage signal is predicted.

[0079] ​In some embodiments, the polarity of the first to-be-converted voltage signal refers to whether the first to-be-converted voltage signal is greater than 0 or less than 0. In this process, a preliminary comparison can be made based on the comparator to obtain the approximate range of the first to-be-converted voltage signal and obtain the polarity of the first to-be-converted voltage signal.

[0080] In some embodiments, based on the polarity of the first to-be-converted voltage signal, the implementation process of switching the lower plate of the highest bit capacitor array in the first-stage analog-to-digital converter can include: if the first to-be-converted voltage signal is greater than 0, setting the lower plate of the highest bit capacitor array to 1; if the first to-be-converted voltage signal is less than 0, setting the lower plate of the highest bit capacitor array to -1. That is, in the sampling stage, by predicting the highest bit conversion code value, a reverse fixed voltage value is compensated in advance to ensure that the signal is within the convertible range.

[0081] In the sampling stage, if the lower plate of the highest bit capacitor array is set to 1, the voltage of the lower plate of the highest bit capacitor array is equivalent to the reference voltage V ref , and if the lower plate of the highest bit capacitor array is set to -1, the voltage of the lower plate of the highest bit capacitor array is equivalent to the reference voltage -V ref . Therefore, in the reset stage, the voltage change value of the lower plate needs to be removed from the voltage signal of the upper plate. Specifically, if the lower plate of the highest bit capacitor array is set to 1 in the sampling stage, the lower plate of the highest bit capacitor array is restored to the VCM common-mode voltage in the reset stage, so V ref / 2 needs to be subtracted from the voltage signal of the upper plate of the first capacitor array, and if the lower plate of the highest bit capacitor array is set to -1 in the sampling stage, so V ref / 2 needs to be added to the voltage signal of the upper plate of the first capacitor array.

[0082] According to the analog-to-digital conversion method of the embodiment of the application, in the sampling stage of the first-stage analog-to-digital converter, the polarity of the first to-be-converted voltage signal is determined; based on the polarity of the first to-be-converted voltage signal, the lower plate of the highest bit capacitor array in the first-stage analog-to-digital converter is switched to extract a reverse voltage compensation, so as to ensure that the signal of the first capacitor array is within the convertible range and avoid the problem of saturation of the analog-to-digital converter.

[0083] In some embodiments, the first-stage analog-to-digital converter and the second-stage analog-to-digital converter are connected through an inter-stage integrator; and in the process of receiving the amplified voltage residue on the upper plate of the second capacitor array, the upper plate of the second capacitor array is further controlled to retain the voltage residue converted in the last period. By using the inter-stage integrator to connect the two-stage analog-to-digital converters, the amplified residue information from the previous stage can be obtained while retaining the own residue, so that noise shaping can be realized and higher quantization precision can be obtained.

[0084] For the convenience of understanding the above-mentioned embodiments, the analog-digital conversion processes of the first and second analog-digital converters will be introduced by the changes of the voltage signals of the upper and lower plates of the capacitors in different stages. Figure 5 The circuit diagram of the two-stage analog-digital converter involved in the embodiments of the present application.

[0085] As shown in Figure 4 , the first and second analog-digital converters run in parallel, and the execution of the first-stage analog-digital converter is one cycle behind that of the second-stage analog-digital converter, i.e. the first analog-digital converter is in the n-th cycle and the second analog-digital converter is in the n-1-th cycle. The working procedure of the first-stage analog-digital converter is as follows.

[0086] (1) Sampling stage, the polarity of the first voltage signal to be converted (input signal Vi(n)) is judged, for example, , the lower plate of the highest bit capacitor array (MSB1) is set to 1; the lower plate of the low bit capacitor array retains the conversion code value of the last cycle , and the lower plate of the feedback capacitor also retains the conversion code value of the last cycle , i.e. the highest bit conversion code value of the second-stage analog-digital converter in the n-2-th cycle, the voltage signal of the upper plate of the first capacitor array ;

[0087] (2) Reset stage, the lower plates of all capacitors are reset to the VCM common-mode voltage, and in this stage, the voltage signal of the upper plate of the first capacitor array is . Wherein, is the voltage signal of the feedback capacitor in the last cycle; wherein, , is added to the signal, which is equivalent to introducing the reverse mismatch error of the last cycle into the signal;

[0088] (3) Conversion stage, the highest bit conversion code value and the low bit conversion code value are obtained by voltage conversion, and at this time, the voltage signal of the upper plate of the first capacitor array is . Wherein, the removal of is equivalent to the first-order shaping of the mismatch error of the low bit capacitor array in the current cycle and the reverse mismatch error of the last cycle;

[0089] (4) Feedback stage, the feedback capacitor accepts the highest bit conversion code value of the second-stage analog-digital converter in the last cycle, and switches the capacitor according to the code value, at this time, the voltage signal of the upper plate of the first capacitor array is

[0090] . Wherein, The removal of the mismatch error of the current period and the first-order shaping of the reverse mismatch error of the last period are equivalent.

[0091] (5) The inter-stage amplification stage, based on the inter-stage integrator, amplifies the voltage residual and transmits it to the second stage analog-digital converter for subsequent conversion.

[0092] For the current n-th period, the second stage analog-digital converter is performing conversion work for the n-1-th period, and the specific process is as follows:

[0093] (1) Sampling stage, the lower levels of the second capacitor array retain the conversion code value of the last period, at this time the voltage signal of the upper plate of the second capacitor array is . Wherein, is the voltage residual output by the second stage analog-digital converter at the n-2-th period;

[0094] (2) Reset stage, reset the lower levels of the second capacitor array to the VCM common-mode voltage, at this time the voltage signal of the upper plate of the second capacitor array is . Wherein, is added to the upper plate, which introduces a reverse mismatch error;

[0095] (3) Conversion stage, through voltage conversion, the highest bit conversion code value and the low bit conversion code value are obtained, and is sent to the latch for storage, and then transmitted to the lower plate of the feedback capacitor after the conversion of the first stage analog-digital converter in the next period. In this stage, the voltage signal of the upper plate of the second capacitor array is . Wherein, The removal of the mismatch error of the current period and the first-order shaping of the reverse mismatch error of the last period are equivalent.

[0096] In order to verify the effect of the analog-digital conversion method of the embodiment of the application, the method is verified by wafer verification under 55nm CMOS (Complementary Metal-Oxide-Semiconductor, complementary metal oxide semiconductor) process, and the design of calibration-free high-precision ADC is realized. Under 1.2V power voltage and 20MHz working frequency, the power consumption is 306.88uW, and the area is 0.0416mm 2, with a bandwidth of 156.25 kHz (64 times over-sampling rate). The ADC does not require any calibration, and the test results show a SNDR (Signal-to-Noise-and-Distortion Ratio) of 93.3 dB and a SFDR (Spurious-Free Dynamic Range) of 112.8 dB. Without the proposed method, the SNDR and SFDR are degraded to 76.4 dB and 80.6 dB, respectively. By adjusting the reference voltage of the second stage to simulate the gain variation between stages, the test results show that the SNDR degradation is less than 3 dB in the range of -33% to +50% gain error, which proves that the proposed method has a very good shaping effect on the gain error. The ADC scheme finally achieves a FoMs (Figure of Merit) of 180.4 dB, which realizes the highest gain error tolerance range, the highest precision and FoMs among all the gain error shaping schemes.

[0097] To achieve the above-mentioned embodiments, the embodiments of the present application further provide an analog-to-digital conversion device.

[0098] Figure 6 The structure diagram of the analog-to-digital conversion device provided by the embodiments of the present application is shown. The device is applied to a two-stage analog-to-digital converter, which includes a first-stage analog-to-digital converter and a second-stage analog-to-digital converter. As shown in the figure, Figure 6 the device includes a sampling module 610, a first reset module 620, a first conversion module 630, a second reset module 640 and a second conversion module 650.

[0099] In some embodiments, the sampling module 610 is configured to sample the first voltage signal to be converted based on the first analog-digital converter, and during the sampling process, the lower plate of the low-bit capacitor array in the first analog-digital converter retains the conversion code value of the previous cycle; the first reset module 620 is configured to reset the lower plate of the first capacitor array in the first analog-digital converter, and add the low-bit voltage signal corresponding to the previous cycle to the upper plate of the first capacitor array to obtain a second voltage signal to be converted; the first conversion module 630 is configured to convert the second voltage signal to be converted based on the first analog-digital converter, obtain a first conversion code value, and transmit the voltage residue after amplification to the upper plate of the second capacitor array in the second analog-digital converter, and during the sampling process, the lower plate of the second capacitor array retains the conversion code value of the previous cycle; the second reset module 640 is configured to reset the lower plate of the second capacitor array, and add the voltage signal corresponding to the previous cycle to the upper plate of the second capacitor array to obtain a third voltage signal to be converted; and the second conversion module 650 is configured to convert the third voltage signal to be converted based on the second analog-digital converter, obtain a second conversion code value, and determine the converted digital signal based on the first conversion code value and the second conversion code value.

[0100] In some embodiments, the first capacitor array further comprises a feedback capacitor; and the first conversion module 630 is further configured to: after the conversion of the second voltage signal to be converted, transmit the highest-bit conversion code value of the second analog-digital converter of the previous cycle to the lower plate of the feedback capacitor based on a latch; switch the feedback capacitor according to the highest-bit conversion code value, and obtain the voltage residue after conversion after the first capacitor array is switched.

[0101] In some embodiments, the sampling module 610 is further configured to: control the lower plate of the low-bit capacitor array and the lower plate of the feedback capacitor to retain the conversion code value of the previous cycle respectively; and the first reset module 620 is further configured to: add the low-bit voltage signal corresponding to the previous cycle and the voltage signal of the feedback capacitor of the previous cycle to the upper plate of the first capacitor array to obtain the second voltage signal to be converted.

[0102] In some embodiments, the sampling module 610 is further configured to: determine the polarity of the first voltage signal to be converted during the sampling process of the first voltage signal to be converted; and switch the lower plate of the highest-bit capacitor array in the first analog-digital converter based on the polarity of the first voltage signal to be converted.

[0103] As a possible implementation, the sampling module 610 is further configured to: if the first voltage signal to be converted is greater than 0, set the lower plate of the highest bit capacitor array to 1; if the first voltage signal to be converted is less than 0, set the lower plate of the highest bit capacitor array to -1.

[0104] In some embodiments, the first stage analog-to-digital converter is connected to the second stage analog-to-digital converter through an inter-stage integrator; the first conversion module 630 is further configured to: during receiving the amplified voltage residue at the upper plate of the second capacitor array, control the lower plate of the second capacitor array to retain the voltage residue converted in the last cycle.

[0105] It should be noted that the above explanation and description of the analog-to-digital conversion method embodiments can also apply to the analog-to-digital conversion device embodiments of the present application, which will not be described here again.

[0106] Figure 7 An example of a schematic diagram of a two-stage analog-to-digital converter is shown. The two-stage analog-to-digital converter can include a first stage analog-to-digital converter and a second stage analog-to-digital converter, whose circuits are shown as Figure 5 The two-stage analog-to-digital converter can include a processor 710, a communication interface 720, a memory 730, and a communication bus 740, as shown in Figure 7 The processor 710, the communication interface 720, and the memory 730 can communicate with each other through the communication bus 740. The processor 710 can invoke the computer program in the memory 730 to execute the steps of the analog-to-digital conversion method.

[0107] For example, the method includes: sampling a first voltage signal to be converted based on a first stage analog-to-digital converter, and during the sampling process, controlling the lower plate of a low bit capacitor array in the first stage analog-to-digital converter to retain the conversion code value of the last cycle; resetting the lower plate of a first capacitor array in the first stage analog-to-digital converter, and adding the corresponding low bit voltage signal of the last cycle to the upper plate of the first capacitor array to obtain a second voltage signal to be converted; converting the second voltage signal to be converted based on the first stage analog-to-digital converter to obtain a first conversion code value, and transmitting the converted voltage residue after amplification to the upper plate of a second capacitor array in a second stage analog-to-digital converter, and during the sampling process, controlling the lower plate of the second capacitor array to retain the conversion code value of the last cycle; resetting the lower plate of the second capacitor array, and adding the corresponding voltage signal of the last cycle to the upper plate of the second capacitor array to obtain a third voltage signal to be converted; converting the third voltage signal to be converted based on the second stage analog-to-digital converter to obtain a second conversion code value, and determining the converted digital signal based on the first conversion code value and the second conversion code value.

[0108] Moreover, the logic instructions in the memory 730 described above can be implemented in the form of software functional units and sold or used as independent products, and can be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the present application essentially or the parts that make contributions to the prior art or parts of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present application. The aforementioned storage medium includes various media that can store program codes, such as a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0109] In another aspect, the embodiments of the present application also provide a computer program product, which includes a computer program. The computer program can be stored in a non-transitory computer readable storage medium. When the computer program is executed by a processor, the computer can execute the steps of the analog-to-digital conversion method provided by the above-mentioned embodiments.

[0110] In another aspect, the embodiments of the present application also provide a non-transitory computer readable storage medium, which stores a computer program. When the computer program is executed by a processor, the steps of the analog-to-digital conversion method provided by the above-mentioned embodiments are implemented.

[0111] The non-transitory computer readable storage medium can be any available medium or data storage device that the processor can access, including but not limited to a magnetic storage (such as a floppy disk, a hard disk, a magnetic tape, a magneto-optical disk (MO), etc.), an optical storage (such as a CD, a DVD, a BD, a HVD, etc.), and a semiconductor memory (such as a ROM, an EPROM, an EEPROM, a NAND FLASH, a solid state disk (SSD)), etc.

[0112] The device embodiments described above are only schematic, wherein the units described as separate components can or can not be physically separate, and the components displayed as units can or can not be physical units, i.e., they can be located in one place, or distributed on a plurality of network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the embodiments. Those skilled in the art can understand and implement without creative labor.

[0113] Those skilled in the art can clearly understand the technical solutions of the various embodiments from the above description of the embodiments, and the various embodiments can be implemented by means of software with the necessary general hardware platforms, and of course, can also be implemented by hardware. Based on such understanding, the above technical solutions, essentially or in other words, the part of the prior art that makes a contribution, can be embodied in the form of a software product, which can be stored in a computer readable storage medium, such as a ROM / RAM, a magnetic disk, an optical disk, and the like, and includes a number of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0114] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, rather than limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for some technical features therein; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. An analog-to-digital conversion method, characterized in that, The method is applied to a two-stage analog-to-digital converter (ADC), which includes a first-stage ADC and a second-stage ADC; the method includes: The first voltage signal to be converted is sampled based on the first-stage analog-to-digital converter, and during the sampling process, the lower plate of the low-order capacitor array in the first-stage analog-to-digital converter is controlled to retain the conversion code value of the previous cycle. The lower stage board of the first capacitor array in the first stage analog-to-digital converter is reset, and the low-level voltage signal corresponding to the previous cycle is applied to the upper plate of the first capacitor array to obtain the second voltage signal to be converted. The first-stage analog-to-digital converter converts the second voltage signal to be converted to obtain a first conversion code value. The converted voltage margin is amplified and transmitted to the upper plate of the second capacitor array in the second-stage analog-to-digital converter. During the sampling process, the lower plate of the second capacitor array is controlled to retain the conversion code value of the previous cycle. The lower plate of the second capacitor array is reset, and the voltage signal corresponding to the previous cycle is applied to the upper plate of the second capacitor array to obtain the third voltage signal to be converted. The third voltage signal to be converted is converted using the second-stage analog-to-digital converter to obtain a second conversion code value, and the converted digital signal is determined based on the first conversion code value and the second conversion code value.

2. The method according to claim 1, characterized in that, The first capacitor array further includes a feedback capacitor; after converting the second voltage signal to be converted, the following is also included: The latch transmits the most significant bit conversion code value of the previous cycle of the second-stage analog-to-digital converter to the lower plate of the feedback capacitor. The feedback capacitor is switched according to the high-order conversion code value, and the converted voltage margin is obtained after all the first capacitor array has been switched.

3. The method according to claim 2, characterized in that, The control of the lower plate of the low-order capacitor array in the first-stage analog-to-digital converter to retain the conversion code value of the previous cycle includes: The lower plate of the low-position capacitor array and the lower plate of the feedback capacitor retain their respective conversion code values ​​from the previous cycle. The step of applying the low-level voltage signal corresponding to the previous cycle to the upper plate of the first capacitor array to obtain the second voltage signal to be converted includes: The low-level voltage signal corresponding to the previous cycle and the voltage signal of the feedback capacitor in the previous cycle are both applied to the upper plate of the first capacitor array to obtain the second voltage signal to be converted.

4. The method according to claim 1, characterized in that, The sampling process for the first voltage signal to be converted also includes: Determine the polarity of the first voltage signal to be converted; Based on the polarity of the first voltage signal to be converted, the lower plate of the highest-order capacitor array in the first-stage analog-to-digital converter is switched.

5. The method according to claim 4, characterized in that, The step of switching the lower plate of the highest-order capacitor array in the first-stage analog-to-digital converter based on the polarity of the first voltage signal to be converted includes: If the first voltage signal to be converted is greater than 0, the lower plate of the highest-order capacitor array is set to 1; If the first voltage signal to be converted is less than 0, the lower plate of the highest-order capacitor array is set to -1.

6. The method according to any one of claims 1-5, characterized in that, The first-stage analog-to-digital converter and the second-stage analog-to-digital converter are connected via an inter-stage integrator; the process of receiving the amplified voltage margin on the upper plate of the second capacitor array also includes: The upper plate of the second capacitor array is controlled to retain the voltage margin after the previous cycle conversion.

7. An analog-to-digital converter, characterized in that, Configured in a two-stage analog-to-digital converter, the two-stage analog-to-digital converter includes a first-stage analog-to-digital converter and a second-stage analog-to-digital converter; the device includes: The sampling module is used to sample the first voltage signal to be converted based on the first-stage analog-to-digital converter, and during the sampling process, it controls the lower plate of the low-order capacitor array in the first-stage analog-to-digital converter to retain the conversion code value of the previous cycle. The first reset module is used to reset the lower plate of the first capacitor array in the first stage analog-to-digital converter and apply the low voltage signal corresponding to the previous cycle to the upper plate of the first capacitor array to obtain the second voltage signal to be converted. The first conversion module is used to convert the second voltage signal to be converted based on the first-stage analog-to-digital converter to obtain the first conversion code value, and to transmit the converted voltage margin to the upper plate of the second capacitor array in the second-stage analog-to-digital converter after amplification. During the sampling process, the lower plate of the second capacitor array is controlled to retain the conversion code value of the previous cycle. The second reset module is used to reset the lower plate of the second capacitor array and apply the voltage signal corresponding to the previous cycle to the upper plate of the second capacitor array to obtain the third voltage signal to be converted. The second conversion module is used to convert the third voltage signal to be converted based on the second-stage analog-to-digital converter to obtain a second conversion code value, and to determine the converted digital signal based on the first conversion code value and the second conversion code value.

8. A two-stage analog-to-digital converter, comprising a processor and a memory storing a computer program, characterized in that, When the processor executes the computer program, it implements the analog-to-digital conversion method according to any one of claims 1 to 6.

9. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the analog-to-digital conversion method as described in any one of claims 1 to 6.

10. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the analog-to-digital conversion method according to any one of claims 1 to 6.

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