Delay chain and operation method thereof

Abstract

An embodiment of the invention provides a delay chain comprising: delay stages coupled in series, each delay stage comprising a driving device coupled between an input node and an output node of the delay stage, and a capacitor digital-to-analog converter (CDAC) coupled to the output node of the delay stage; at least one CDAC is a separately adjustable (SA) type CDAC (SACDAC), which is separately adjustable relative to at least another CDAC; and a controller configured to adjust the at least one CDAC. The embodiment of the invention also provides a method for operating the delay chain.

Description

Technical Field

[0001] Embodiments of the present invention generally relate to the field of semiconductors, and more particularly, to delay chains and methods of operating them. Background Art

[0002] The semiconductor integrated circuit (IC) industry manufactures a wide variety of analog and digital devices to solve problems in many different fields. The development of semiconductor process technology nodes has gradually reduced component sizes and shrunk pitches, thus gradually increasing transistor density. The ICs become smaller. Summary of the Invention

[0003] An embodiment of the present invention provides a delay chain, comprising: delay stages coupled in series, each delay stage including: a driving device coupled between an input node and an output node of the delay stage; and a capacitor digital-to-analog converter (CDAC) coupled to the output node of the delay stage; at least one CDAC being a separately adjustable (SA) type CDAC (SA_CDAC) capable of being adjusted separately relative to at least another CDAC; and a controller configured to adjust the at least one CDAC.

[0004] Another embodiment of the present invention provides a method of operating a delay chain, the method comprising: coupling the delay stages in series to represent the delay chain, for each of the delay stages, coupling the delay stage comprising the steps of: coupling a driving device between an input node and an output node of the delay stage; and coupling a capacitor digital-to-analog converter (CDAC) to the output node of the delay stage, wherein, for at least one of the delay stages, the corresponding CDAC is a separately adjustable (SA) type CDAC (SA_CDAC) capable of being adjusted separately relative to the CDAC of at least another delay stage; and adjusting at least one CDAC separately relative to at least another CDAC.

[0005] Another embodiment of the present invention provides a delay chain, comprising: delay stages coupled in series, each delay stage including: a driving device coupled between an input node and an output node of the delay stage; and a capacitor digital-to-analog converter (CDAC) coupled to the output node of the delay stage; at least one CDAC being a separately adjustable (SA) type CDAC (SA_CDAC) capable of being adjusted separately relative to at least another CDAC; the at least one SA_CDAC being a one-dimensional array of separately controllable capacitance (SCC) units (SCC_cell), each SCC_cell being capable of being controlled separately relative to other SCC_cells to be coupled to the output node of a corresponding delay stage, the one-dimensional array including rows and a single column, and each row including a single SCC_cell; and a controller configured to adjust the at least one CDAC by selectively coupling zero or some or all of the SCC_cells in the at least one SA_CDAC to the output node of the corresponding delay stage. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] One or more embodiments are illustrated by way of example, and not by way of limitation, in the figures, in which like reference numerals refer to similar elements throughout the description. The figures are not drawn to scale unless otherwise disclosed.

[0007] Figures 1A - 1D is a corresponding schematic diagram according to some embodiments.

[0008] Figures 2A - 2E is a corresponding schematic diagram according to some embodiments. Figure 3 is a table according to some embodiments.

[0009] Figures 4A - 4G is a corresponding schematic diagram according to some embodiments.

[0010] Figure 5 is a table according to some embodiments.

[0011] Figures 6 - 7 is a flowchart of a corresponding method according to some embodiments.

[0012] Figure 8 is a block diagram of an electronic design automation (EDA) system according to some embodiments.

[0013] Figure 9 is a block diagram of an integrated circuit (IC) manufacturing system and an associated IC manufacturing process according to some embodiments. DETAILED DESCRIPTION

[0014] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components, materials, values, steps, arrangements, etc. are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. Other components, values, operations, materials, arrangements, etc. are contemplated. For example, in the following description, forming a first component above or over a second component may include embodiments where the first component and the second component are formed in direct contact, and may also include embodiments where an attachment component may be formed between the first component and the second component such that the first component and the second component are not in direct contact. Additionally, the present invention may repeat reference numerals and / or letters in the various examples. Such repetition is for the purpose of simplicity and clarity, but does not in itself indicate a relationship between the various embodiments and / or configurations being discussed.

[0015] Furthermore, for ease of description, spatial relationship terms such as "below", "beneath", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or component to another as shown in the figures. Spatial relationship terms are intended to include different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be oriented in other ways (rotated 90 degrees or at other orientations), and the spatial relationship descriptors used herein may thus be interpreted similarly. In some embodiments, the term "standard cell structure" refers to a standardized building block included in a library of various standard cell structures. In some embodiments, various standard cell structures are selected from their library and used as components in a layout diagram representing a circuit.

[0016] In some embodiments, a delay chain includes: delay stages coupled in series, each delay stage including a drive device coupled between an input node and an output node of the delay stage, and a capacitor digital-to-analog converter (CDAC) coupled to the output node of the delay stage; at least one CDAC is a separately adjustable (SA) type of CDAC (SA_CDAC) that can be adjusted separately relative to at least another CDAC; and a controller configured to adjust at least one CDAC.

[0017] In some embodiments, at least one SA_CDAC is a one-dimensional array of separately-couplable capacitor (SCC) cells (SCC_cell). In some embodiments, "couplable" is understood to be able to couple to something, e.g., the first SCC_cell of a given SA_CDAC can couple to the output node of the given SA_CDAC. In some embodiments, for the first SCC_cell and the second SCC_cell of a given SA_CDAC, "separately-couplable" should be understood to mean that coupling / decoupling the first SCC_cell and the output node of the given SA_CDAC can be performed separately (or independently) from coupling / decoupling the second SCC_cell and the output node of the given SA_CDAC. Thus, in such embodiments, each of the first and second SCC_cells is described as separately (or independently) couplable to the output node of the given SA_CDAC. In such embodiments, the one-dimensional array includes rows and a single column, and each row includes a single SCC_cell; and the controller is further configured to selectively couple zero or a portion or all of the SCC_cells in at least one SA_CDAC to the output nodes of the corresponding delay stages. In some embodiments, at least one SA_CDAC is a one-dimensional array of separately-controllable capacitor (SCC) cells (SCC_cell). In some embodiments, describing the SCC_cell as controllable should be understood to mean that the coupling between the SA_CDAC and the output node of the given SA_CDAC can be selectively formed or broken. In some embodiments, for the first SCC_cell and the second SCC_cell of a given SA_CDAC, "separately-controllable" should be understood to mean that coupling / decoupling the first SCC_cell and the output node of the given SA_CDAC can be performed separately (or independently) from coupling / decoupling the second SCC_cell and the output node of the given SA_CDAC.

[0018] Combined with the even-row decoder (see Figure 2B and Figure 2D , Figure 4B and Figure 4D etc.) and the odd-row decoder (see Figure 2C and Figure 4C , Figure 2E and Figure 4E etc.) correspondingly included in each SCC_cell, the use of the row address signal RW(i) and the column address signal CL(i) to form a thermometer code reduces the total number of control lines required for the SA_CDAC compared to a CDAC-based delay chain according to another method, where the CDAC of the other method is not separately adjustable. The reduction in the total number of control lines of the SA_CDAC compared to a CDAC-based delay chain according to another method results in the corresponding delay chain occupying a smaller area (having a smaller footprint).

[0019] Figure 1A Schematic diagram of delay chain 102 according to some embodiments.

[0020] Delay chain 100 has an input node nd_IN and an output node nd_OUT. Delay chain 100 includes delay stages ds(0), …, ds(N - 2) and ds(N - 1) coupled in series between the input node nd_IN and the output node nd_OUT, where N is an integer and 2 ≤ N.

[0021] Representing each of the delay stages ds(0) - ds(N - 1) by delay stage ds(j), delay stage ds(j) includes: a driving device drv(j) coupled between an input node in(j) and an output node out(j) of delay stage ds(j); and a capacitor digital - to - analog converter (CDAC), more specifically a separately - adjustable (SA) type CDAC(j) (SA_CDAC(j)), coupled to the output node out(j) of delay stage ds(j). In some embodiments, describing SA_CDAC(j) as separately - adjustable should be understood that SA_CDAC(j) is separately - adjustable relative to at least one other CDAC.

[0022] In Figure 1A each CDAC is an SA_CDAC. In some embodiments, at least one but less than all of SA_CDAC(0) - SA_CDAC(N - 1) are CDAC types other than SA_CDAC.

[0023] Each of SA_CDAC(0) - SA_CDAC(N - 1) is a one - dimensional Mx1 array of separately - couplable capacitor (SCC) units (SCC_cell) (see Figures 2B - 2C 、 Figures 4B - 4C etc.). Each of SA_CDAC(0) - SA_CDAC(N - 1) is configured as and controlled as a monotonic CDAC.

[0024] In Figure 1A representing each of the delay stages ds(0) - ds(N - 1) by delay stage ds(j), driving device drv(j) includes an inverter INV coupled between an input node in(j) and an output node out(j) of delay stage ds(j). In some embodiments, driving device drv(j) includes a buffer (not shown) coupled between an input node in(j) and an output node out(j) of delay stage ds(j).

[0025] In Figure 1AIn , when the signal propagates to the output node nd_OUT of the delay chain 102, the signal provided to the input node nd_IN of the delay chain 102 experiences a total propagation delay. The total propagation delay is the sum of the incremental propagation delays introduced as the signal passes through the delay stages ds(0)-ds(N-1) of the delay chain 102 correspondingly. Where SA_CDAC(j) represents each of SA_CDAC(0)-SA_CDAC(N-1), and SA_CDAC(j) represents the controllable capacitive load on the output node out(j) of the delay stage ds(j). Adjusting the capacitive load represented by SA_CDAC(j) has the effect of adjusting the incremental propagation delay introduced by the corresponding delay stage ds(j). In some embodiments, separately adjusting the capacitive loads correspondingly represented by SA_CDAC(j)-SA_CDAC(N-1) is referred to as adjusting the overall propagation delay of the delay chain 102. Since each of SA_CDAC(0)-SA_CDAC(N-1) is monotonic, the delay chain 102 contributes to monotonic delay adjustment.

[0026] In Figure 1A , SA_CDAC(0)-SA_CDAC(N-1) are controlled by addressing with signals CL(0)-CL(N-1) and RW(0)-RW(M-1). The controller ( Figure 1B 112 in ) is configured to generate signals CL(0)-CL(N-1) and RW(0)-RW(M-1) based on a digital thermometer coding scheme (see Figures 2A - 2E , Figure 3 , Figures 4A - 4E , Figure 5 , etc.). Accordingly, the delay chain 102 is described as a digitally controlled type of delay chain.

[0027] Generally, CDACs (such as SA_CDAC(0)-SA_CDAC(N-1)) contribute to clock synchronization, general communication (e.g., circuit-to-circuit communication in a memory-in-computation (CIM) system), digital-to-analog conversion (DAC), analog-to-digital conversion (ADC), waveform generation, audio applications, etc.). Since the delay chain 102 contributes to monotonic delay adjustment, the delay chain 102 contributes to low-jitter clock generation for, for example, high-speed serializer / deserializer (SERDES) devices, chip-to-chip input / output (I / O) systems, etc.

[0028] Figure 1B is a schematic diagram of the array 104 according to some embodiments.

[0029] The array 104 includes: SCC_cell 106(0,0)-106(0,N-1); SCC_cell 108(1,0)-108(1,N-1); and SCC_cell 106(M-1,0)-106(M-1,N-1). In Figure 1B the SCC_cell is regarded as a black box; see Figures 2B - 2C 、 Figures 4B - 4C etc. to discuss the internal configuration of the SCC_cell.

[0030] SCC_cell 106(0,0), 108(1,0) and 106(M-1,0) together represent SA_CDAC(0) of delay stage ds(0). SCC_cell 106(0,N-2), 108(1,N-2) and 106(M-1,N-2) together represent SA_CDAC(1) of delay stage ds(N-2). SCC_cell 106(0,N-1), 108(1,N-1) and 106(M-1,N-1) together represent SA_CDAC(N-1) of delay stage ds(N-1).

[0031] To facilitate coordinated control of the delay line 102, according to some embodiments, Figure 1A the N SCC_cell one-dimensional Mx1 array instances in

[0032] i.e., SA_CDAC(0)-SA_CDAC(N-1) are regarded as a whole. As a whole, SA_CDAC(0)-SA_CDAC(N-1) together represent the MxN array of SCC_cell. SA_CDAC(0)-SA_CDAC(N-1) correspondingly represent columns col_0 - col_N-1 of the array 104. Figures 2A - 2E 、 Figure 3 、 Figures 4A - 4E 、 Figure 5 etc.), so as to selectively couple some, zero or all of the SCC_cell in SA_CDAC(0)-SA_CDAC(N-1) to the corresponding nodes out(0)-out(N-1) in delay stages ds(0)-ds(N-1).

[0033] In array 104, the even rows include SCC_cell 106(i,j), where i and j are corresponding non-negative integers, i is even, 0 ≤ i ≤ (M - 1) and 0 ≤ j ≤ (N - 1). The odd rows include SCC_cell 108(i,j), where i is odd. The even row rw_0 of array 104 includes SCC_cell 106(0,0) - 106(0,N - 1). The odd row rw_1 of array 104 includes SCC_cell 108(1,0) - 108(0,N - 1). The row rw_M - 1 of array 104 includes SCC_cell 106(M - 1,0) - 106(M - 1,N - 1).

[0034] Each of SCC_cell 106(i,j) and 108(i,j) has three inputs and one output. Each of SCC_cell106(i,0) - 106(i,N - 2) and 108(i,0) - 108(i,N - 2) is configured to receive three different signals correspondingly on three inputs (see Figure 2D , Figure 4D etc.). In contrast, the SCC_cells in the last column col_N - 1 receive fewer signals. Each of SCC_cell 106(i,N - 1) and 108(i,N - 1) is configured to receive two different signals on three inputs, i.e., two inputs are configured to receive the same signal (see Figure 2E , Figure 4E etc.).

[0035] In FIG. 1B, the SCC_cells in the even rows have the default SCC-cell configuration, while the SCC_cells in the odd rows have a configuration different from that of the SCC_cells in the even rows. Thus, the SCC_cells in rows rw_0, rw_2, etc. are different from the SCC_cells in rows rw_1, rw_3, etc. In some embodiments, the SCC_cells in array 104 are described as having a row number parity specific configuration. The use of the row number parity specific configuration by the SCC_cells in array 104 helps to perform a Gray code compatible adjustment of SA_CDAC(0) - SA_CDAC(N - 1) for the SCC_cells in array 104, and the Gray code compatible adjustment helps to perform a monotonic adjustment on them.

[0036] In the array 104, each SCC_cell in the even rows includes the same components. Each SCC_cell in the odd rows includes the same components as the SCC_cells in the even rows, however, one input in each SCC_cell in the even rows is inverted as indicated by the prefix inversion bubble 110. In some embodiments, each inverted input is described as an active low input. Regarding Figure 1B , in some embodiments, the SCC_cells in the odd rows have a default SCC-cell configuration, while the SCC_cells in the even rows have a configuration different from that of the SCC_cells in the odd rows, which represents Figure 1B the reverse of the even row and odd row SCC_cell configuration relationship shown in

[0037] Generally, the outputs of each of the SCC_cells 106(i,j) and 108(i,j) in column col(j) are coupled to the output node out(j) of the delay stage ds(j). The outputs of each of the SCC_cells 106(0,0), 108(1,0), and 106(M-1,0) in column col(0) are coupled to the output node out(0) of the delay stage ds(0). The outputs of each of the SCC_cells 106(0,N-2), 108(1,N-2), and 106(M-1,N-2) in column col(N-2) are coupled to the output node out(N-2) of the delay stage ds(N-2). The outputs of each of the SCC_cells 106(0,N-1), 108(1,N-1), and 106(M-1,N-1) in column col(N-1) are coupled to the output node out(N-1) of the delay stage ds(N-1).

[0038] One input of each of the SCC_cells 106(0,0), 108(1,0), and 106(M-1,0) in column col(0) is configured to receive the column addressing signal CL(0). One input of each of the SCC_cells 106(0,N-2), 108(1,N-2), and 106(M-1,N-2) in column col(N-2) is configured to receive the column addressing signal CL(N-2). One input of each of the SCC_cells 106(0,N-1), 108(1,N-1), and 106(M-1,N-1) in column col(N-1) is configured to receive the column addressing signal CL(N-1).

[0039] Each of the two inputs of each of the SCC_cells 106(0,0)-106(0,N-2) in row rw_0 is configured to receive the row addressing signal RW(0). One of the inputs of each of the SCC_cells 106(0,0)-106(0,N-2) in row rw_0 is configured to receive the row addressing signal RW(1). The two inputs of the SCC_cell 106(0,N-1) in row rw_0 are configured to receive the row addressing signal RW(1).

[0040] Each of the two inputs of each of the SCC_cells 108(1,0)-108(1,N-2) in row rw_1 is configured to receive the row addressing signal RW(1). One of the inputs of each of the SCC_cells 108(1,0)-108(1,N-2) in row rw_1 is configured to receive the row addressing signal RW(2). The two inputs of the SCC_cell 108(1,N-1) in row rw_1 are configured to receive the row addressing signal RW(2).

[0041] Each of the two inputs of each of the SCC_cells 106(M-1,0)-106(M-1,N-2) in row rw_M-1 is configured to receive the row addressing signal RW(M-1). One of the inputs of each of the SCC_cells 106(M-1,0)-106(M-1,N-2) in row rw_M-1 is configured to receive the row addressing signal RW(M). The two inputs of each of the SCC_cells 106(M-1,0)-106(M-1,N-2) in row rw_M-1 are configured to receive the row addressing signal RW(M).

[0042] In Figure 1B the row addressing signal RW(0) is coupled to the first reference voltage VDD. The row addressing signal RW(M) corresponding to the virtual row rw_M is coupled to the second reference voltage VSS. The column addressing signal CL(N-1) is coupled to the first reference voltage VDD or the second reference voltage VSS. In some embodiments, the first and second reference voltages have corresponding values other than VDD and VSS.

[0043] Figure 1C is a schematic diagram of an oscillator 114 according to some embodiments.

[0044] The oscillator 114 represents an application of the delay chain 102, where the oscillator 114 includes a digitally controlled delay chain. Thus, the oscillator 114 is described as an oscillator of the digitally controlled type. In some embodiments, the oscillator 114 is described as a phase-locked loop (PLL).

[0045] In Figure 1CIn [description], the output node nd_OUT of the delay chain 102 is coupled to the input node nd_IN of the delay chain 102 via a feedback coupling 116.

[0046] Figure 1D is a schematic diagram of a delay line 118 according to some embodiments.

[0047] The delay line 118 represents an application of the delay chain 102, where the delay line 118 includes a digitally controlled delay chain. Therefore, the delay line 118 is described as a delay line of the digitally controlled type. In some embodiments, the delay line 118 is described as a delay-locked loop (DLL).

[0048] In Figure 1D the input node nd_IN of the delay chain 102 receives a clock signal CLK, and when the signal CLK propagates to the output node nd_OUT of the delay chain 102, the clock signal CLK experiences an overall propagation delay. The delay chain 102 generates a signal CLK_dlyd at the output node nd_OUT, which represents a delayed version of the signal CLK, where the text string dlyd is an abbreviation of delayed.

[0049] Figure 2A is a schematic diagram of an array 204 according to some embodiments.

[0050] In some embodiments, Figure 2A is described as Figure 1B a simplified version of [array], so the array 204 is described as a simplified version of the array 104. Figure 2A The number of columns in the array 204 shown in Figure 1B is more than the number of columns in the array 104 shown in Figure 2A which shows three columns, namely col(0), col(N - 2), and col(N - 1). In contrast,

[0051] In Figure 2A for ease of illustration, it is assumed that the number of rows M is M = 9 and the number of columns N is N = 8. Therefore, the array 204 includes rows rw_0 - rw_8 and columns col_0 - col_8. In some embodiments, M and N have corresponding values other than M = 9 and N = 8.

[0052] The even rows include SCC_cell 206B(i,j) and 206D(i,j). The odd rows include SCC_cell 208C(i,j) and 208E(i,j), where i is odd. For example, the even row rw_0 of the array 204 includes SCC_cell 206B(0,0)-206B(0,6) and 208D(0,7). For example, the odd row rw_1 of the array 204 includes SCC_cell 208C(1,0)-208C(1,6) and 208E(1,7).

[0053] The internal configurations of the even row SCC_cell 206B(i,j) and 206D(i,j) are shown respectively in Figure 2B and Figure 2D respectively. The internal configurations of the odd row SCC_cell 208C(i,j) and 208D(i,j) are shown respectively in Figure 2C and Figure 2E respectively.

[0054] In Figure 2A , the SCC_cell 206B(i,j), 206D(i,j), 208C(i,j) and 208E(i,j) are addressed and controlled by signals CL(0)-CL(N-1) and RW(0)-RW(9). The controller (see 112 in Figure 1B ) is configured to generate signals CL(0)-CL(N-1) and RW(0)-RW(9) based on a digital thermometer coding scheme (see Figure 3 etc.).

[0055] It should be recalled that each column col(j) represents SA_CDAC(j) in the corresponding delay stage ds(j) (see Figures 1A - 1B ). In the example of Figure 2A , each of the SCC_cell 206B(i,j), 206D(i,j), 208C(i,j) and 208E(i,j) includes a capacitor (see Figures 2B - 2E etc.), and the capacitor can be individually coupled to the corresponding output nodes out(0)-out(7) of the delay stages ds(0)-ds(7) according to the digital thermometer coding scheme.

[0056] In the example of Figure 2A , MxN = 9x8 = 72 capacitors are respectively coupled to the corresponding output nodes out(0)-out(7). The signal RW(0) is coupled to the voltage VDD. The signal RW(M) corresponding to the virtual row rw_9 is coupled to the voltage VSS.

[0057] In Figure 2AIn it, the digital thermometer code is formed by signals RW(0)-RW(8) and CL(0)-CL(7).

[0058] Figure 2A The digital thermometer encoding schemes of ,

[0058] , Figure 2A couple zero, some, or all of the capacitors in SCC_cell 206B(i,j), 206D(i,j), 208C(i,j), and 208E(i,j) to the corresponding output nodes out(0)-out(7) in row order as follows: row rw(0) goes from 206B(0,0) to 206B(0,1) to... 206B(0,j) to... 206D(0,7); then row rw(1) goes from 208C(1,0) to... 208C(1,1) to... 208C(1,j) to... 208E(1,7); then row rw(2) goes from 206B(2,0) to... 206D(2,7); then row rw(3) goes from 208C(3,0) to... 208E(3,7);... then row rw(7) goes from 208C(7,0) to... 208C(7,1) to... 208C(7,j) to... 208D(7,7); then row rw(8) goes from 206B(8,0) to... 206B(8,1) to... 206B(8,j) to... 206D(8,7). This sequential row-by-row coupling of capacitors only changes the coupling state of one corresponding capacitor because the value of the thermometer code changes each time it changes, thus conforming to the Gray code and being monotonic. Gray code encoding generates a binary digit string in which any two consecutive values of the string differ only in the value of one binary digit in the string. In some embodiments, the Gray code is referred to as a reflected binary (RB) code. In some embodiments, the Gray code-compatible adjustment of SA_CDAC(0)-SA_CDAC(N-1) represents this sequential row-by-row coupling of capacitors, where only the coupling state of one corresponding capacitor changes with each change in the thermometer code value.

[0059] In some embodiments, when the capacitor of SCC_cell 206B(i,j), 206D(i,j), 208C(i,j) or 208E(i,j) is coupled to the corresponding output node out(j), then SCC_cell 206B(i,j), 206D(i,j), 208C(i,j) or 208E(i,j) is described as being on. When the capacitor of SCC_cell 206B(i,j), 206D(i,j), 208C(i,j) or 208E(i,j) is not coupled to the corresponding output node out(j), then SCC_cell 206B(i,j), 206D(i,j), 208C(i,j) or 208E(i,j) is described as being off.

[0060] In some embodiments, when the capacitor of SCC_cell 206B(i,j), 206D(i,j), 208C(i,j) or 208E(i,j) is coupled to the corresponding output node out(j), then SCC_cell 206B(i,j), 206D(i,j), 208C(i,j) or 208E(i,j) is described as being in the thermometer code ON state. When the capacitor of SCC_cell 206B(i,j), 206D(i,j), 208C(i,j) or 208E(i,j) is not coupled to the corresponding output node out(j), then SCC_cell 206B(i,j), 206D(i,j), 208C(i,j) or 208E(i,j) is described as being in the thermometer code OFF state. In Figure 2A the example of, assume the following: SCC_cell 206B(i,j), 206D(i,j), 208C(i,j) and 208E(i,j) included in the first range from SCC_cell 206B(0,0) to SCC_cell 206B(4,0) are in the thermometer code ON state; and, SCC_cell 206B(i,j), 206D(i,j), 208C(i,j) and 208E(i,j) included in the second range from SCC_cell 206B(4,1) to 206D(8,7) are in the thermometer code OFF state.

[0061] The decoder correspondingly included in SCC_cell 206B(i,j), 206D(i,j), 208C(i,j) and 208E(i,j) (see Figures 2B - 2D , Figures 4B - 4DCombined with (etc.), using signals RW(0)-RW(8) and CL(0)-CL(7) to form a thermometer code reduces the total number of control lines required for SA_CDAC corresponding to columns col(0)-col(7) compared to a CDAC-based delay chain according to another method. The reduction in the total number of control lines required for SA_CDAC corresponding to columns col(0)-col(7) compared to a CDAC-based delay chain according to another method results in the corresponding delay chain occupying a smaller area (having a smaller footprint).

[0062] Figure 2B is a schematic diagram of SCC_cell 206B(i,j) according to some embodiments, where i = even and j = {0,…,N-2).

[0063] Figure 2B extends Figure 2A example. SCC_cell 206B(i,j) is used for Figure 2A even rows of the array 204, etc. Recall that Figure 2A in the example, N = 8, and SCC_cell 206B(i,j) represents SCC_cell 206B(0,0)-206B(8,6).

[0064] SCC_cell 206B(i,j) includes a decoder 220, a switch P(i,j), and a capacitor. The switch P(i,j) is coupled between the output node out(j) of the corresponding delay stage ds(j) and the capacitor. The capacitor is coupled between the switch P(i,j) and VSS. The control input of the switch P(i,j) is coupled to the output of the decoder 220. The decoder 220 has three inputs, which are respectively coupled to the signals CL(j), RW(i), and RW(i+1).

[0065] In Figure 2B , the switch P(i,j) is a field effect transistor (FET) with P-type dopants for positive channel metal oxide semiconductor (PMOS) transistor technology, i.e., PFET. When the output of the decoder 220 is logic zero, the PFET P(i,j) conducts, i.e., the switch P(i,j) is in the closed state, and the capacitor is coupled to the output node out(j). When the output of the decoder 220 is logic 1, the PFET P(i,j) is cut off, i.e., the switch P(i,j) is in the open state, and actually, the capacitor is not coupled to the output node out(j). In some embodiments, the switch is a FET with N-type dopants for negative channel metal oxide semiconductor (NMOS) transistor technology, i.e., NFET.

[0066] Regarding Figure 2B, in some embodiments, the capacitors of each instance of SCC_cell 206B(i,j) are described as being separately couplable to output node out(j). In some embodiments, each instance of SCC_cell 206B(i,j) is described as being separately couplable to output node out(j), which is understood to mean that the first instance of switch P(i,j) controlling the first instance of SCC_cell 206B(i,j) to turn on / off is performed separately (or independently) from the second instance of switch P(α,β) controlling the second instance of SCC_cell 206B(i,j) to turn on / off. Thus, in such embodiments, the on / off state of the first instance of switch P(i,j) is described as being separately (or independently) controllable relative to the on / off state of the second instance of switch P(i,j).

[0067] Decoder 220 includes a logic AND gate and a logic NOR gate. The AND gate has two inputs which are configured to receive signals CL(j) and RW(i) respectively. The NOR gate has two inputs which are respectively configured to receive the output of the AND gate and RW(i + 1). In some embodiments, decoder 220 is described as a logic AND-OR-INVERT (AOI) gate.

[0068] In some embodiments, the thermometer code ON state is described as driving SC_cell206B(i,j), 206D(i,j), 208C(i,j) or 208E(i,j) according to a 100% duty cycle, or as having a 100% duty cycle for SC_cell 206B(i,j), 206D(i,j), 208C(i,j) or 208E(i,j). Conversely, in such embodiments, the thermometer code ON state is described as driving SC_cell 206B(i,j), 206D(i,j), 208C(i,j) or 208E(i,j) according to a 0% duty cycle, or as having a 0% duty cycle for SC_cell 206B(i,j), 206D(i,j), 208C(i,j) or 208E(i,j). In some embodiments, it is described as being controlled according to a binary coupling scheme. Figure 2C is a schematic diagram of SCC_cell208C(i,j) according to some embodiments, where i = odd and j = {0,…,N - 2).

[0069] Figure 2C extends Figure 2A the example. SCC_cell 208C(i,j) is used for Figure 2A the odd rows of array 204, etc. Recall that Figure 2AIn the example where N = 8, SCC_cell 208C(i,j) represents SCC_cell 208C(1,0) - 208C(7,6).

[0070] Figure 2C The SCC_cell 208C(i,j) is similar to Figure 2B the SCC_cell 206B(i,j). In some embodiments, the capacitors of each instance of SCC_cell 206C(i,j) are described as being individually couplable to the output node out(j). For the sake of brevity, the discussion will focus on the differences between SCC_cell 208C(i,j) and SCC_cell 206B(i,j), rather than the similarities.

[0071] SCC_cell 208C(i,j) differs from SCC_cell 206B(i,j) in that one input of SCC_cell 208C(i,j) is inverted. More specifically, one input of the AND gate of decoder 222 (i.e., the input of the AND gate configured to receive signal CL(j)) is inverted, as shown by the prefix inversion bubble 210. In some embodiments, the inverted input is described as an active - low input. In some embodiments, instead of SCC_cell 208C(j) having an inverted input, SCC_cell 206B(i,j) has an inverted input, i.e., the AND gate of decoder 220 configured to receive signal CL(j) is inverted.

[0072] and Figure 2B similar to decoder 220 of Figure 2C in some embodiments, decoder 222 of

[0073] Figure 2D is a schematic diagram of SCC_cell 206D(i,7) according to some embodiments, where i = even and j = 7.

[0074] Figure 2D extends Figure 2A the example of Figure 2A SCC_cell 206D(i,7) is used for the even rows of the last column col_N - 1 of the array, i.e.,

[0075] Figure 2D the SCC_cell 206D(i,7) is similar to Figure 2Bof SCC_cell 206B(i,j). In some embodiments, the capacitors of each instance of SCC_cell 206D(i,j) are described as being separately couplable to output node out(j). For the sake of brevity, the discussion will focus on Figure 2D the differences between SCC_cell 206D(i,7) and Figure 2B SCC_cell 206B(i,j), rather than the similarities.

[0076] Although SCC_cell 206D(i,7) has three inputs, SCC_cell 206D(i,7) is configured to receive fewer signals than Figure 2B SCC_cell 206B(i,j). SCC_cell 206D(i,7) is configured to receive two different signals on three inputs, i.e., two of the inputs are configured to receive the same signal. SCC_cell 206D(i,7) is not configured to receive signal RW(i). Specifically, not only is one of the inputs of the NOR gate of decoder 220 configured to receive signal RW(i + 1), but also one of the inputs of the AND gate of decoder 220 is configured to receive signal RW(i + 1). In contrast, Figure 2B the corresponding input of the AND gate of

[0077] Figure 2E decoder 220 is configured to receive signal RW(i).

[0078] Figure 2E extends Figure 2A the example of Figure 2A SCC_cell 208E(i,7) is for the odd rows of the last column col_N - 1 of the array, i.e.,

[0079] Figure 2E the differences between SCC_cell 208E(i,7) and Figure 2C SCC_cell 208C(i,j) are similar. In some embodiments, the capacitors of each instance of SCC_cell 206D(i,j) are described as being separately couplable to output node out(j). For the sake of brevity, the discussion will focus on Figure 2E the differences between SCC_cell 208E(i,7) and Figure 2C SCC_cell 208C(i,j), rather than the similarities.

[0080] Although SCC_cell 208E(i,7) has three inputs, SCC_cell 208E(i,7) is configured to receive fewer signals than Figure 2C the SCC_cell 208C(i,j). SCC_cell 208E(i,7) is configured to receive two different signals on three inputs, i.e., two inputs are configured to receive the same signal. SCC_cell 208E(i,7) is not configured to receive the signal RW(i). Specifically, not only one of the inputs of the NOR gate of decoder 222 is configured to receive the signal RW(i+1), but also one of the inputs of the AND gate of decoder 222 is configured to receive the signal RW(i+1). In contrast, Figure 2C the corresponding input of the AND gate of

[0081] In Figure 2D the SCC_cell 206D(i,7) and Figure 2E each of the SCC_cell 208E(i,7), configuring two inputs to receive the signal RW(i+1) has the corresponding effect of causing decoders 220 and 222 to act as logic inverter gates with respect to the signal RW(i+1). In other words, in Figure 2D the SCC_cell206D(i,7) and Figure 2E the SCC_cell 208E(i,7), configuring two inputs to receive the signal RW(i+1) has the corresponding effect of causing the state of the signal CL(7) to have no effect on the outputs of decoders 220 and 222. In some embodiments, in view of this effect, the signal CL(7) is described as an "irrelevant" signal with respect to the operation of decoders 220 and 222. Thus, in such embodiments, the signal CL(7) is configured for another purpose, e.g., reducing power consumption or noise, etc.

[0082] The truth table of SCC_cell 206D(i,7) is shown in Table 1 below.

[0083] CL(7) RW(i + 1) AND OR NOR 0 0 0 0 1 0 1 0 1 0 1 0 0 0 1 1 1 1 1 0

[0084] Table 1 (SCC_cell 206D(i,7))

[0085] The truth table of SCC_cell 208E(i,7) is shown in Table 2 below. The inversion of the signal CL(7) is called CL(7)_bar.

[0086] CL(7) CL(7)_bar RW(i + 1) AND OR NOR 0 1 0 0 0 1 0 1 1 1 1 0 1 0 0 0 0 1 1 0 1 0 1 0

[0087] Table 2 (SCC_cell 208E(i,7))

[0088] Figure 3 Table 324 shows partial values of the thermometer code according to some embodiments.

[0089] Figure 3 The table of Figure 2A extends the example of Figure 2A Since the columns col_0 - col_7 of the array 204 represent the corresponding SC_CDACs, Table 324 provides an example of how to individually adjust each SA_CDAC using the thermometer code relative to the other SA_CDACs.

[0090] Table 324 includes: a first column (Column 1), showing the row numbers assigned to the rows in Table 324; a second column (Column 2), showing the count of SCC_cell 206B(i,j), 206D(i,j), 208C(i,j), and 208E(i,j) in the thermometer code ON state; a third column (Column 3), showing the signals RW(0) - RW(7) connected as the corresponding binary digits to form the upper eight bits of an example thermometer code; a fourth column (Column 4) specific to the 'last' ON row of the array 204 (described below), where Column 4 shows the signals CL(0) - CL(7) connected as the corresponding binary digits to form the lower eight bits of an example thermometer code; a fifth column (Column 5) specific to the 'last' ON row of the array 204 (described below), where Column 5 shows which (if any) of the SC_cell 206B(i,j), 206D(i,j), 208C(i,j), or 208E(i,j) in columns col_0 - col_7 are in the thermometer code ON state.

[0091] The complete example code represented by Table 324 is formed by connecting the signals RW(0) - RW(7) and CL(0) - CL(7) as the corresponding binary digits representing Figure 2A the upper eight bits and the lower eight bits of an example thermometer code in an example context. Table 324 is Figure 2A a partial list of the arrangement and combination of the values of an example thermometer code in an example context.

[0092] Each row in the third column of Table 324 is regarded as a whole for the thermometer code ON state. Thus, each row rw_i as a whole is represented by the corresponding single binary digit in the third column of Table 324. If all the SC_cells in row rw_i are in the thermometer code ON state, the binary digit representing row_i in the third column of Table 324 is set to one (logical high). If there are fewer SC_cells in row rw_i in the thermometer code ON state than all, the binary digit representing row_i in the third column of Table 324 is set to zero (logical low).

[0093] In some embodiments, the 'last' ON row of Table 324 is the row (row rw_i) in Table 324 that satisfies the following conditions: (1) row_i has one or more SC_cells in the thermometer code ON state; and (2A) row_i is row_0 or (2B) all SC_cells in the previous row rw_i-1 are in the thermometer code ON state.

[0094] The fifth column of Table 324 is specific to the 'last' ON row, and thus each SC_cell in the 'last' ON row is considered according to its thermometer code ON state. That is, if the SC_cell in column col_i is in the thermometer code ON state, the binary digit representing col_i in the fifth column of Table 324 is set to 1 (logical high). If the SC_cell in row col_i is in the thermometer code OFF state, the binary digit representing col_i in the fifth column of Table 324 is set to 0 (logical low).

[0095] Regarding the 0th row of Table 324, no SCC_cell (206B(i,j), 206D(i,j), 208C(i,j), or 208E(i,j)) is in the thermometer code ON state. For the other rows of Table 324, one or more of the SCC_cell 206B(i,j), 206D(i,j), 208C(i,j), or 208E(i,j) are in the thermometer code ON state.

[0096] For rows 2-9 of Table 324, only the row rw_0 of array 204 has any SCC_cell in the thermometer code ON state. For row 2, therefore, rows 2-9 of Table 324 and column 5 of Table 324 are understood to refer to the row rw_0 of array 204 as the 'last' ON row. For rows 2-9 of Table 324, the values of the high eight bits (the third column) of the example thermometer code are all zero.

[0097] Regarding rows 10-17 of Table 324, column 5 of Table 324 is understood to refer to the row rw_1 of array 204 as the 'last' ON row. For each row in rows 10-17 of Table 324, the value of the high eight bits (the third column) of the example thermometer code is 10000000, with the leftmost binary digit set to 1 (logical high).

[0098] In the fourth column of Table 324, the binary digit representing signal CL(7) is shown as the letter x, rather than being set to 1 (logical high) or 0 (logical low). The use of the letter x in the fourth column of Table 324 is intended to indicate that signal CL(7) is an "irrelevant" signal with respect to the operation of decoders 220 and 222, as described above.

[0099] Figure 4A Schematic diagram of array 404 according to some embodiments.

[0100] Figure 4A The array 404 is similar to Figure 2A the array 204. Thus, in Figure 4A , for the sake of convenience of description, it is also assumed that the number of rows M is M = 9 and the number of columns N is N = 8. Therefore, the array 404 also includes rows rw_0 - rw_8 and columns col_0 - col_8. In some embodiments, M and N have corresponding values other than M = 9 and N = 8. For the sake of brevity, the discussion will focus on the differences rather than the similarities between the array 404 and the array 204.

[0101] In the array 404, the even rows include SCC_cell 406B(i,j) and 406D(i,j). The odd rows include SCC_cell 408C(i,j) and 408E(i,j), where i is odd. For example, the even row rw_0 of the array 404 includes SCC_cell406B(0,0) - 406B(0,6) and 406D(0,7). For example, the odd row rw_1 of the array 404 includes SCC_cell 408C(1,0) - 408C(1,6) and 408E(1,7).

[0102] In the array 404, except for one of SCC_cell 406B(i,j), 406D(i,j), 408C(i,j), and 408E(i,j), the rest are controlled according to the binary coupling scheme (see Figure 2A ), while Figure 2A all SCC_cell 206B(i,j), 206D(i,j), 208C(i,j), and 208E(i,j) in the array 204 of

[0103] The internal configurations of the even - row SCC_cell 406B(i,j) and 406D(i,j) are respectively as shown in Figure 4B and Figure 4D shown. The internal configurations of the odd - row SCC_cell 408C(i,j) and 408E(i,j) are respectively as shown in Figure 4C and Figure 4E shown.

[0104] In Figure 4AAmong them, SCC_cell 406B(i,j), 406D(i,j), 408C(i,j) and 408E(i,j) are addressed and controlled by signals CL(-1), CL(0)-CL(N) and RW(0)-RW(9). The controller (see Figure 1B 112 therein) is configured to generate signals CL(-1), CL(0)-CL(N) and RW(0)-RW(9) based on a digital thermometer coding scheme (see Figure 5 etc.). The signal CL(-1) represents the signal of the virtual column col_-1 located before col_0. The signal CL(8), i.e., CL(N), represents the signal of the virtual column col_8.

[0105] In Figure 4A a digital thermometer code is formed by signals RW(0)-RW(8), CL(-1) and CL(0)-CL(8).

[0106] In Figure 4A the example, the following is assumed: SCC_cell 406B(i,j), 406D(i,j), 408C(i,j) and 408E(i,j) in the first range from SCC_cell 406B(0,0) to SCC_cell 406B(4,0) are in the thermometer code ON state; SCC_cell 406B(i,j), 406D(i,j), 408C(i,j) and 408E(i,j) in the second range from SCC_cell 406B(4,2) (not shown) to SCC_cell 406D(8,7) are assumed to be in the thermometer code OFF state; and SCC_cell 406B(4,1) is in the fractional state. Therefore, SCC_cell 406B(i,j), 406D(i,j), 408C(i,j) and 408E(i,j) in the first range are described as being driven according to a 100% duty cycle. SCC_cell 406B(i,j), 406D(i,j), 408C(i,j) and 408E(i,j) in the second range are described as being driven according to a 0% duty cycle. In some embodiments, by being in the fractional state, SCC cell 406B(4,1) is understood to be driven according to a partial duty cycle DCY within the range of 0% < DCY < 100%.

[0107] Typically, the SC_cell 406B(i,j), 406D(i,j), 408C(i,j), or 408E(i,j) in the fractional state is the first SC_cell 406B(i,j), 406D(i,j), 408C(i,j), or 408E(i,j), which would otherwise be in the thermometer code OFF state if the fractional coupling scheme were not used. In some embodiments, the SC_cell 406B(i,j), 406D(i,j), 408C(i,j), or 408E(i,j) in the fractional state is referred to as the fractionally coupled SC_cell. In some embodiments, herein, the first SC_cell 406B(i,j), 406D(i,j), 408C(i,j), or 408E(i,j) that would otherwise be in the thermometer code OFF state if the fractional coupling scheme were not used is referred to as the original first SC_cell in the thermometer code OFF state.

[0108] When each of the SC_cell 406B(i,j), 406D(i,j), 408C(i,j), and 408E(i,j) is in the thermometer code ON state, each of the SC_cell 406B(i,j), 406D(i,j), 408C(i,j), and 408E(i,j) adds a capacitor cell CPC to the output node out(j) of the corresponding delay stage ds(j). Conversely, when the SC_cell 406B(i,j), 406D(i,j), 408C(i,j), or 408E(i,j) is a fractionally coupled SC_cell, the fractionally coupled SC_cell adds a fraction of a CPC (see Figures 4F - 4G ) to the output node out(j) of the corresponding delay stage ds(j), where the size of the fraction is proportional to the value of DCY multiplied by CPC, such that 0% < DCY * CPC < 100%. For the other first SC_cells in the thermometer code OFF state, a fractional coupling scheme, i.e., a hybrid binary and fractional coupling scheme, is used, which achieves better / finer granularity compared to the pure binary coupling scheme while still maintaining monotonicity.

[0109] With the decoder correspondingly included in the SCC_cell 406B(i,j), 406D(i,j), 408C(i,j), and 408E(i,j) (see Figures 4B - 4DCombined with (etc.), the signals RW(0)-RW(8) and CL(0)-CL(7) are used to form a thermometer code, reducing the total number of control lines required for SA_CDAC corresponding to columns col(0)-col(7) compared to a CDAC-based delay chain according to another method. The reduction in the total number of control lines required for SA_CDAC corresponding to columns col(0)-col(7) compared to a CDAC-based delay chain according to another method results in the corresponding delay chain occupying a smaller area (having a smaller footprint).

[0110] Figure 4B is a schematic diagram of SCC_cell 406B(i,7) according to some embodiments, where i = even and j = {0,…,N-2).

[0111] Figure 4B extends Figure 4A example. SCC_cell 406B(i,j) is used for Figure 4A even rows of the array 404, etc. Recall that Figure 4A in the example N = 8, and SCC_cell 406B(i,j) represents SCC_cell 406B(0,0)-406B(8,6). Figure 4B The SCC_cell 406B(i,7) of Figure 2B is similar to the SCC_cell 206B(i,j) of

[0112] SCC_cell 406B(i,j) has four inputs, while SCC_cell 206B(i,j) has three inputs. Compared to SCC_cell 206B(i,j), the additional fourth input of SCC_cell 406B(i,j) is configured to receive the fractional coupling signal FRCT_ev (see Figure 4F ).

[0113] SCC_cell 406B(i,j) includes a decoder 420, while SCC_cell 206B(i,j) includes a decoder 220. The decoder 420 of SCC_cell 406B(i,j) has four inputs, while the decoder 220 of SCC_cell 206B(i,j) has three inputs. Compared to the decoder 220, the additional fourth input of the decoder 420 is configured to receive the fractional coupling signal FRCT_ev.

[0114] Figure 4CSchematic diagram of SCC_cell 408C(i,j) according to some embodiments, where i = odd and j = {0, …, N-2).

[0115] Figure 4C extends Figure 4A example. SCC_cell 408C(i,j) is used for Figure 4A odd rows of the array 404, etc. Recall that Figure 4A in the example where N = 8, SCC_cell 408C(i,j) represents SCC_cell 408C(1,0)-408C(7,6).

[0116] Figure 4C The SCC_cell 408C(i,j) of Figure 2C is similar to the SCC_cell 208C(i,j) of

[0117] Figure 4C The SCC_cell 408C(i,j) of Figure 2C has four inputs, while the SCC_cell 208C(i,j) of Figure 4G has three inputs. Compared with the SCC_cell 208C(i,j), the additional fourth input of the SCC_cell 408C(i,j) is configured to receive the fractional coupling signal FRCT_od (see

[0118] SCC_cell 408C(i,j) includes a decoder 422, while SCC_cell 208C(i,j) includes a decoder 222. The decoder 422 of SCC_cell 408C(i,j) has four inputs, while the decoder 222 of SCC_cell 208C(i,j) has three inputs. Compared with the decoder 222, the additional fourth input of the decoder 422 is configured to receive the fractional coupling signal FRCT_od.

[0119] Figure 4D Schematic diagram of SCC_cell 406D(i,7) according to some embodiments, where i = even and j = 7.

[0120] Figure 4D extends Figure 4A example. SCC_cell 406D(i,7) is used for the even rows of the last column col_N-1 of the array, i.e., Figure 2A col_7 in the context of the array 404, etc. Figure 4DThe SCC_cell 406D(i,7) is similar to Figure 2D the SCC_cell 206D(i,j). For the sake of brevity, the discussion will focus on Figure 4D the differences between the SCC_cell 406D(i,7) and Figure 2D the SCC_cell 206D(i,j), rather than the similarities.

[0121] Figure 4D The SCC_cell 406D(i,j) has four inputs, while Figure 2D the SCC_cell206D(i,j) has three inputs. Compared with the SCC_cell 206D(i,j), the additional fourth input of the SCC_cell 406D(i,j) is configured to receive the fractional coupling signal FRCT_ev (see Figure 4F ).

[0122] The SCC_cell 406D(i,j) includes a decoder 420, while the SCC_cell 206D(i,j) includes a decoder 220. The decoder 420 of the SCC_cell 406D(i,j) has four inputs, while the decoder 220 of the SCC_cell 206D(i,j) has three inputs. Compared with the decoder 220, the additional fourth input of the decoder 420 is configured to receive the fractional coupling signal FRCT_ev.

[0123] Figure 4E is a schematic diagram of the SCC_cell 408E(i,7) according to some embodiments, where i = odd and j = 7.

[0124] Figure 4E extends Figure 4A the example. The SCC_cell 408E(i,7) is used for the odd rows of the last column col_N - 1 of the array, i.e., Figure 4A col_7 in the context of the array 404, and so on. Figure 4E The SCC_cell 408E(i,7) is similar to Figure 2C the SCC_cell 208C(i,j). For the sake of brevity, the discussion will focus on Figure 4E the differences between the SCC_cell 408E(i,7) and Figure 2C the SCC_cell 208C(i,j), rather than the similarities.

[0125] Figure 4E The SCC_cell 406E(i,j) in Figure 2EThe SCC_cell206E(i,j) therein has three inputs. Compared with the SCC_cell 206E(i,j), the additional fourth input of the SCC_cell 406E(i,j) is configured to receive the fractional coupling signal FRCT_od (see Figure 4G ).

[0126] The SCC_cell 406E(i,j) includes a decoder 422, while the SCC_cell 206E(i,j) includes a decoder 222. The decoder 422 of the SCC_cell 406E(i,j) has four inputs, while the decoder 222 of the SCC_cell 206E(i,j) has three inputs. Compared with the decoder 222, the additional fourth input of the decoder 422 is configured to receive the fractional coupling signal FRCT_od.

[0127] Figure 4F is a schematic diagram of a selector 440 according to some embodiments.

[0128] Figure 4F extends Figure 4A example. The selector 440 is used for Figure 4A the even rows of the array 404, etc. The selector 440 is configured to generate the fractional coupling signal FRCT_ev (see Figure 4B and Figure 4D ), so as to drive the originally first SC_cell in the thermometer code OFF state.

[0129] The selector 440 includes a four-input AND gate 410 and a two-input AND gate 444. The AND gate 410 has two non-inverting inputs and two inverting inputs. The two inverting inputs are represented by inverting bubbles 410 with a prefix, and only one of them is marked with the reference number 410 for the sake of illustration. In some embodiments, the inverting inputs are described as active-low inputs.

[0130] The first of the two non-inverting inputs of the AND gate 442 is configured to receive the row addressing signal RW(i - 1). The second of the two non-inverting inputs of the AND gate 442 is configured to receive the column addressing signal CL(j). The first of the two inverting inputs of the AND gate 442 is configured to receive the row addressing signal RW(i). The second of the two inverting inputs of the AND gate 442 is configured to receive the column addressing signal CL(j - 1). The AND gate 442 is configured to generate an even row fractional selection signal frc_sel_rw_ev (as described below).

[0131] Regarding AND gate 444, the first input of AND gate 444 is configured to receive a duty cycle signal DTY. In some embodiments, the duty cycle signal DTY is a pulse width modulation (PWM) signal having a constant pulse width or a random pulse width. In some embodiments, PWM is described as pulse duration modulation (PDM) or pulse length modulation (PLM). The duty cycle signal DTY is configured to have a waveform representing a partial duty cycle DCY, where 0% < DCY < 100%.

[0132] The second input of AND gate 444 is configured to receive an even row fractional select signal frc_sel_rw_ev from AND gate 442. AND gate 444 is configured to generate a fractional coupling signal FRCT_ev.

[0133] The even row fractional select signal frc_sel_rw_ev is used to select other first SC_cells in the thermometer code OFF state, where the latter will be driven by the duty cycle signal DTY. A partial truth table of the fractional control signal FRCT_ev is shown in Table 3 below.

[0134] In some embodiments, the combinational logic of selector 440 is described as follows. For i = even, when RW(i - 1) = 1, RW(i) = 0, CL(j - 1) = 0, and CL(j) = 1, set frc_sel_rw_ev = 1. More specifically, for i = even, set frc_sel_rw_ev = RW(i - 1)*(~RW(i))*(~CL(j - 1))*CL(j) and set FRCT_ev = DTY*frc_sel_rw_ev, where (~RW(i)) and (~CL(j - 1)) are the inverses of RW(i) and CL(j - 1), respectively.

[0135] Figure 4G is a schematic diagram of selector 446 according to some embodiments.

[0136] Figure 4G extends Figure 4A the example. Selector 446 is used for Figure 4A the odd rows of the array 404, etc. Selector 446 is configured to generate a fractional coupling signal FRCT_odd (see Figure 4C and Figure 4E ), thereby driving the original first SC_cells in the thermometer code OFF state.

[0137] Figure 4G The selector 446 of Figure 4F is similar to selector 440 of Figure 4G For the sake of brevity, the discussion will focus on the selector 446 of Figure 4Fin terms of the differences from selector 440, rather than similarities.

[0138] Regarding selector 446, the second non-inverting input and the second inverting input of the AND gate 442 of selector 446 are configured differently compared to the second non-inverting input and the second inverting input of the AND gate 442 of selector 440.

[0139] The second non-inverting input of the AND gate 442 of selector 446 is configured to receive the column addressing signal CL(j - 1), rather than the signal CL(j) in selector 440. The second inverting input of the AND gate 442 of selector 446 is configured to receive the column addressing signal CL(j), rather than the signal CL(j - 1) in selector 440. A partial truth table of the fractional control signal FRCT_od is shown in Table 3 below.

[0140] In some embodiments, the combinational logic of selector 446 is described as follows. For i = odd, when RW(i - 1) = 1, RW(i) = 0, CL(j - 1) = 1, and CL(j) = 0, set frc_sel_rw_od = 1. More specifically, for i = odd, set frc_sel_rw_od = RW(i - 1)*(~RW(i))*CL(j - 1)*(~CL(j)) and set FRCT_od = DTY*frc_sel_rw_od, where (~CL(j1)) is the inversion of CL(j).

[0141] The truth tables of the fractional control signals FRCT_ev and FRCT_od are shown in Table 3 below.

[0142] Line number parity check CL(j - 1) CL(j) RW(i - 1) RW(i) FRCT_ev FRCT_od Even 1 0 0 1 1 n / a Odd 1 0 1 0 n / a 1

[0143] Table 3 (Signals FRCT_ev and FRCT_od)

[0144] For all permutations and combinations of the signals CL(j - 1), CL(j), RW(i - 1), and RW(i) (except those shown in Table 3), FRCT_ev = 0 and FRCT_od = 0.

[0145] Figure 5 Table 548 shows partial values of the thermometer code according to some embodiments.

[0146] Figure 5 The table of... is extended Figure 4A The example of... Since Figure 4A Columns col_0 - col_7 of the array 404 of... represent the corresponding SC_CDACs. Therefore, Table 548 provides an example of how to individually adjust each SA_CDAC using the thermometer code relative to other SA_CDACs.

[0147] Table 548 includes: a first column (column 1) showing the row numbers assigned to the rows in Table 548; a second column (column 2) showing the signals RW(0)-RW(7) connected as respective binary digits to form the high eight bits of an example thermometer code; a third column (column 3) showing the signal CL(0) as a binary digit, which forms the middle binary digit of the example thermometer code; a fourth column (column 4) showing the signals CL(1)-CL(7) connected as corresponding binary digits to form the low seven bits of the example thermometer code; a fifth column (column 5) showing the signal CL(8) as a binary digit, where the signal CL(8) corresponds to the dummy column col_8; and a sixth column (column 6) showing which of the corresponding columns in col_0-col_7 has an SC_cell 406B(i,j), 406D(i,j), 408C(i,j), or 408E(i,j) in the fractional state. In the sixth column of Table 548, the binary digits in larger font represent the columns having an SC_cell 406B(i,j), 406D(i,j), 408C(i,j), or 408E(i,j) in the fractional state.

[0148] The complete example code represented by Table 548 is formed by connecting the signals RW(0)-RW(7) and CL(0)-CL(7) as the respective binary digits representing Figure 4A the high eight bits and the low eight bits of the example thermometer code in the example context shown. Table 548 is Figure 4A a partial list of the arrangement and combination of the values of the example thermometer code in the example context shown.

[0149] The second column of Table 548 is similar to the third column of Table 324. In summary, the third and fourth columns of Table 548 are similar to the fourth column of Table 324.

[0150] For example, in the 12th row of Table 548, the value of the thermometer code is 1000 0000 0 000 001, which represents the decimal value 11.4375. The binary equivalent of 11.4375 (decimal) includes the binary integer part 0000 1011 and the binary fractional part 0111.

[0151] Figure 6 is a flowchart of method 600 according to some embodiments.

[0152] Method 600 operates on SA_CDACs such as Figure 1A SA_CDAC(0)-SA_CDAC(N-1), SA_DACs corresponding to Figure 2A array 204 corresponding to Figure 4AAn example of a method such as SA_DCAC of the array 404. The method 600 includes blocks 604-616. The process of method 600 starts from block 604.

[0153] At block 604, the delay stages are coupled in series as a delay chain. An example of a delay chain is Figure 1A the delay chain 102 etc. An example of a delay stage is Figure 1A the delay stages ds(0)-ds(N-1) etc. Within block 604, the process continues to block 606.

[0154] At block 606, for each delay stage, the i-th driving device is coupled between the input and output nodes of the i-th delay stage. Examples of the i-th driving device include Figure 1A the driving devices drv(0)-drv(N-1) etc. in. Examples of input nodes include Figure 1A the input nodes in(0)-in(N-1) etc. corresponding to the driving devices drv(0)-drv(N-1) in. Examples of output nodes include Figure 1A the output nodes out(0)-out(N-1) etc. corresponding to the driving devices drv(0)-drv(N-1) in. The process proceeds from block 606 to block 608.

[0155] At block 608, for each delay stage, the i-th SC_CDAC is coupled to the i-th output node of the i-th delay stage. Examples of the i-th SC_CDAC coupled to the i-th output node of the i-th delay stage include the SC_DAC(0)-SC_CDAC(N-1) etc. correspondingly coupled to Figure 1A the output nodes out(0)-out(N-1) of the delay stages ds(0)-ds(N-1). Within block 608, the process continues to block 610.

[0156] At block 610, for each SCC_cell in the i-th SA-CDAC, the corresponding switch and the corresponding capacitor are coupled in series between the output node of the i-th delay stage and the first reference voltage. An example of the first reference voltage is VSS, as Figures 2B - 2E 、 Figures 4B - 4E etc. shown. Examples of output nodes also include Figure 1AThe output nodes out(0)-out(N-1) corresponding to the driving devices drv(0)-drv(N-1) therein, etc. Examples of SCC_cell include SCC_cell 206B(i,j), 206D(i,j), 208C(i,j), 208E(i,j), 406B(i,j), 406D(i,j), 408C(i,j), and 408E(i,j), etc. Examples of the corresponding switches include the switch P(i,j) of SCC_cell 206B(i,j), 208C(i,j), 406B(i,j), and 408C(i,j), the switch P(i,7) of SCC_cell 206D(i,j), 208E(i,j), 406D(i,j), and 408E(i,j), etc. Examples of the corresponding capacitors include each capacitor in SCC_cell 206B(i,j), 206D(i,j), 208C(i,j), 208E(i,j), 406B(i,j), 406D(i,j), 408C(i,j), and 408E(i,j), etc. From block 610, the process proceeds to exit block 608. From block 608, the process proceeds to exit block 604. The process proceeds from block 604 to block 612.

[0157] At block 612, each SA_CDAC is adjusted separately relative to another SA_CDAC. Examples of adjusting each SA_CDAC separately relative to other SA_CDACs include Figure 3 Table 324 of Figure 5 Table 548 of, etc. In some embodiments, at least one but less than all of the SA_CDACs are non-separable adjustable CDAC types. Inside block 612, the process continues to block 614.

[0158] At block 614, for each delay stage, none or some or all of the SCC_cell are selectively coupled to the output node of the i-th delay stage. Examples of none or some or all of the SCC_cell being selectively coupled to the output node of the i-th delay stage include Figure 3 Table 324 of Figure 5 Table 548 of, etc. Inside block 614, the process continues to block 616.

[0159] At block 616, for the capacitors in the SCC_cell of each delay stage, none or some or all of the capacitors in the SCC_cell are selectively coupled to the output node of the i-th delay stage. Examples of none or some or all of the capacitors in the SCC_cell being selectively coupled to the output node of the i-th delay stage include Figure 3 Table 324 of Figure 5 Table 548 of, etc.

[0160] In some embodiments, method 600 further includes controlling the delay chain to act as a controllable delay line, including: receiving a clock signal at an input node of a first delay stage; and serially propagating the clock signal through the delay chain such that a signal on an output node of a last delay stage represents a delayed version of the clock signal. Examples of clock signals are Figure 1D the clock signal CLK, etc. Examples of delayed versions of the clock signal include Figure 1D the signal CLK_dlyd, which represents a delayed version of the signal CLK, etc.

[0161] In some embodiments, method 600 further includes controlling the delay chain to act as a controllable oscillator, including: feedback-coupling an output node of a last delay stage to an input node of a first delay stage. Examples of controllable oscillators are Figure 1C the oscillator 114, etc. Examples of feedback-coupling an output node of a last delay stage to an input node of a first delay stage include Figure 1C the feedback coupling 116, etc.

[0162] Figure 7 is a flowchart (flowchart) of method 700 for a manufacturing system or device according to some embodiments.

[0163] According to some embodiments, method 700 can be implemented, for example, using an EDA system 800 (discussed below Figure 8 ) and an IC manufacturing system 900 (discussed below Figure 9 ). Examples of systems or devices that can be manufactured according to method 700 include the systems or devices disclosed herein, etc.

[0164] In Figure 7 , the method of flowchart 700 includes blocks 702 - 704. At block 702, a layout is generated, which includes, among other things, one or more layouts corresponding to one or more of the systems or devices disclosed herein, etc. According to some embodiments, block 702 can be implemented, for example, using an EDA system 800 ( Figure 8 , discussed below). The flow proceeds from block 702 to block 704.

[0165] At block 704, based on the layout, at least one of the following operations is performed: (A) performing one or more lithographic exposures, or (b) manufacturing one or more lithographic masks, or (C) manufacturing one or more components in a layer of a device (e.g., a device). See the discussion below of Figure 9 the IC manufacturing system 900 in

[0166] Figure 8 is a block diagram of an electronic design automation (EDA) system 800 according to some embodiments.

[0167] In some embodiments, the EDA system 800 includes an automatic placement and routing (APR) system. In some embodiments, the EDA system 800 is a general-purpose computing device that includes a hardware processor 802 and a non-transitory computer-readable storage medium 804. Among other things, the storage medium 804 is encoded, i.e., stores, computer program code 806, i.e., a set of executable instructions. The instructions 806 executed by the hardware processor 802 represent (at least in part) an EDA tool that implements part or all of the method for generating the systems or devices described herein (hereinafter, the process and / or method).

[0168] The storage medium 804 stores, in particular, a layout diagram 811, such as the layout diagrams disclosed herein and the like.

[0169] The processor 802 is electrically coupled to the computer-readable storage medium 804 via a bus 808. The processor 802 is also electrically coupled to an I / O interface 810 via the bus 808. A network interface 812 is also electrically coupled to the processor 802 via the bus 808. The network interface 812 is connected to a network 814 such that the processor 802 and the computer-readable storage medium 804 can be connected to external components via the network 814. The processor 802 is configured to execute the computer program code 806 encoded in the computer-readable storage medium 804 such that the EDA system 800 can be used to perform part or all of the process and / or method. In one or more embodiments, the processor 802 is a central processing unit (CPU), a multi-processor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0170] In one or more embodiments, the computer-readable storage medium 804 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or apparatus or device). For example, the computer-readable storage medium 804 includes semiconductor or solid-state memory, magnetic tape, removable computer floppy disk, random access memory (RAM), read-only memory (ROM), hard disk, and / or optical disk. In one or more embodiments using an optical disk, the computer-readable storage medium 804 includes a compact disc read-only memory (CD-ROM), a compact disc read / write (CD-R / W), and / or a digital video disc (DVD).

[0171] In one or more embodiments, the storage medium 804 stores computer program code 806 that is configured to make the EDA system 800 (where such execution (at least in part) represents an EDA tool) available to perform part or all of the process and / or method. In one or more embodiments, the storage medium 804 also stores information that facilitates the performance of part or all of the process and / or method. In one or more embodiments, the storage medium 804 stores a standard cell library 807, including such standard cells as disclosed herein. In some embodiments, the storage medium 804 stores one or more layout diagrams 811.

[0172] The EDA system 800 includes an I / O interface 810. The I / O interface 810 is coupled to an external circuit. In one or more embodiments, the I / O interface 810 includes a keyboard, a keypad, a mouse, a trackball, a touchpad, a touchscreen, and / or cursor direction keys that convey information and commands to the processor 802.

[0173] The EDA system 800 also includes a network interface 812 coupled to the processor 802. The network interface 812 allows the EDA system 800 to communicate with a network 814 to which one or more other computer systems are connected. The network interface 812 includes a wireless network interface such as BLUETOOTH, WIFI, WIMAX, GPRS, or WCDMA; or a wired network interface such as ETHERNET, USB, or IEEE-1364. In one or more embodiments, part or all of the process and / or method is implemented in two or more EDA systems 800.

[0174] The EDA system 800 is configured to receive information through the I / O interface 810. The information received through the I / O interface 810 includes one or more of instructions, data, design rules, a standard cell library, and / or other parameters for processing by the processor 802. The information is transmitted to the processor 802 through the bus 808. The EPC system 800 is configured to receive information related to a user interface (UI) through the I / O interface 810. This information is stored as the UI 842 in the computer-readable medium 804.

[0175] In some embodiments, part or all of the process and / or method is implemented as a stand-alone software application for execution by a processor. In some embodiments, part or all of the recited process and / or method is implemented as a software application that is part of an additional software application. In some embodiments, part or all of the process and / or method is implemented as a plug-in of a software application. In some embodiments, at least one of the process and / or method is implemented as a software application that is part of an EDA tool. In some embodiments, part or all of the process and / or method is implemented as a software application used by an EDA system 800. In some embodiments, tools such as or other suitable layout generation tools are used to generate a layout including standard cells.

[0176] In some embodiments, the process is implemented as the function of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, one or more of external / removable and / or internal / on-board storage or memory units such as, for example, optical discs (such as DVDs), magnetic disks (such as hard disks), and semiconductor memories (such as ROMs, RAMs, memory cards, etc.).

[0177] Figure 9 is a block diagram of an integrated circuit (IC) manufacturing system 900 and an IC manufacturing process associated therewith.

[0178] In some embodiments, based on the layout diagram generated by Figure 6 block 602, the IC manufacturing system 900 implements Figure 7 block 704, where the manufacturing system 900 is used to fabricate at least one component of (A) one or more semiconductor masks or (B) layers of an early semiconductor integrated circuit. In some embodiments, the IC manufacturing system 900 implements Figure 7 the flowchart of

[0179] In Figure 9In FIG. 900, an IC manufacturing system 900 includes entities that interact with each other in the design, development, and manufacturing cycle and / or services related to manufacturing an IC device 960, such as a design house 920, a mask house 930, and an IC manufacturer / fabrication facility (“fab”) 950. The entities in system 900 are connected by a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to and / or receives services from one or more other entities. In some embodiments, two or more of the design house 920, the mask house 930, and the IC fab 950 are owned by a single larger company. In some embodiments, two or more of the design house 920, the mask house 930, and the IC fab 950 coexist in a common facility and use common resources.

[0180] A design house (or design team) 920 generates an IC design layout 922. The IC design layout 922 includes various geometric patterns designed for the IC device 960. The geometric patterns correspond to patterns of metal, oxide, or semiconductor layers that make up various components of the IC device 960 to be manufactured. The individual layers combine to form various IC functions. For example, a portion of the IC design layout 922 includes various IC components, such as source regions, gate terminals, source and drain electrodes, metal wires or vias for interlayer interconnects, and openings for bonding pads formed in a semiconductor substrate (such as a silicon wafer) and various material layers disposed on the semiconductor substrate. The source / drain regions may refer to the source or the drain individually or collectively, depending on the context. The design house 920 implements an appropriate design process to form the IC design layout 922. The design process includes one or more of logic design, physical design, or placement and routing. The IC design layout 922 is presented in one or more data files having geometric pattern information. For example, the IC design layout 922 is expressed in the GDSII file format or the DFII file format.

[0181] The mask house 930 includes data preparation 932 and mask manufacturing 934. The mask house 930 uses the IC design layout 922 to manufacture one or more masks 935 for use in manufacturing the individual layers of the IC device 960 according to the IC design layout 922. The mask house 930 performs mask data preparation 932, in which the IC design layout 722 is translated into a representative data file (RDF). The mask data preparation 932 provides the RDF to the mask manufacturing 934. The mask manufacturing 934 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (reticle) or a semiconductor wafer. The mask layout data preparation 932 processes the design layout to conform to the specific characteristics of the mask writer and / or the requirements of the IC fab 950. InFigure 9 In this, mask data preparation 932, mask manufacturing 934, and mask 935 are shown as separate elements. In some embodiments, mask data preparation 932 and mask manufacturing 934 are collectively referred to as mask data preparation.

[0182] In some embodiments, mask data preparation 932 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image errors, such as those that may be caused by diffraction, interference, other processing effects, etc. OPC adjusts the IC design layout 922. In some embodiments, mask data preparation 932 includes other resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist features, phase-shift masks, other suitable techniques, etc. or combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, which treats OPC as an inverse imaging problem.

[0183] In some embodiments, mask data preparation 932 includes a mask rule checker (MRC), which uses a set of mask creation rules to check the IC design layout that has already been processed in OPC. The set of mask creation rules contains certain geometric and / or connectivity restrictions to ensure sufficient margins to address variability in semiconductor manufacturing processes, etc. In some embodiments, MRC modifies the IC design layout to compensate for limitations during mask manufacturing 934, which may undo a portion of the modifications performed by OPC to meet the mask creation rules.

[0184] In some embodiments, mask data preparation 932 includes lithography process check (LPC), which simulates the process that will be implemented by IC Fab 950 to fabricate IC device 960. LPC simulates the process based on the IC design layout 922 to fabricate a simulated fabricated device, such as IC device 960. The processing parameters in the LPC simulation may include parameters related to various processes in the IC manufacturing cycle, parameters related to the tools used to manufacture the IC, and / or other aspects of the manufacturing process. LPC takes into account various factors, such as aerial image contrast, depth of focus ("DOF"), mask error enhancement factor ("MEEF"), other suitable factors, etc. or combinations thereof. In some embodiments, after creating a simulated fabricated device through LPC, if the simulated device is not close enough in shape to meet the design rules, OPC and / or MRC are repeated to further refine the IC design layout 922.

[0185] For clarity, the above description of mask data preparation 932 has been simplified. In some embodiments, data preparation 932 includes additional features such as logic operation (LOP) to modify the IC design layout according to manufacturing rules. Additionally, the processes applied to the IC design layout 922 during data preparation 932 can be performed in various different orders.

[0186] After mask data preparation 932 and during mask fabrication 934, a mask 935 or a set of masks 935 is fabricated based on the modified IC design layout 822. In some embodiments, an electron beam (e-beam) or a multi-electron beam mechanism is used to form a pattern on the mask (photomask or reticle) based on the modified IC design layout. The mask can be formed using various techniques. In some embodiments, the mask is formed using a binary technique. In some embodiments, the mask pattern includes opaque regions and transparent regions. A radiation beam, such as an ultraviolet (UV) beam, for exposing an image-sensitive material layer (e.g., photoresist) that has been coated on a wafer is blocked by the opaque regions and passes through the transparent regions. In an embodiment, the binary mask includes a transparent substrate (e.g., quartz glass) and an opaque material (e.g., chromium) coated in the opaque regions. In another example, the mask is formed using a phase-shift technique. In a phase-shift mask (PSM), each component in the pattern formed on the mask is configured to have an appropriate phase difference to improve resolution and imaging quality. In various examples, the phase-shift mask is an attenuated PSM or an alternating PSM. The mask generated by mask fabrication 934 is used in a variety of processes. For example, such a mask is used in an ion implantation process to form various doped regions in a semiconductor wafer, in an etching process to form various etched regions in a semiconductor wafer, and / or in other suitable processes.

[0187] IC fab 950 is an IC manufacturing enterprise that includes one or more manufacturing facilities for manufacturing various different IC products. In some embodiments, IC fab 950 is a semiconductor fabrication plant. For example, there can be a fabrication plant for front-end manufacturing (front-end (FEOL) manufacturing) of multiple IC products, while a second fabrication plant can provide back-end manufacturing (back-end (BEOL) manufacturing) for the interconnect and packaging of IC products, and a third fabrication plant can provide other services for the manufacturing operation.

[0188] IC fab 950 uses the mask 935 fabricated by mask chamber 930 to manufacture IC device 960 using manufacturing tool 952. Thus, IC fab 950 at least indirectly uses IC design layout 922 to manufacture IC device 960. In some embodiments, semiconductor wafer 953 is made into IC device 960 by IC fab 950 using mask 935. Semiconductor wafer 953 includes a silicon substrate or other suitable substrate having material layers formed thereon. The semiconductor wafer also includes one or more of various doped regions, dielectric components, multi-layer interconnections, etc. (formed in subsequent manufacturing steps).

[0189] In some embodiments, the delay chain includes: delay stages coupled in series, each delay stage including a driving device coupled between an input node and an output node of the delay stage, and a capacitor digital-to-analog converter (CDAC) coupled to the output node of the delay stage; at least one CDAC is a separately adjustable (SA) type CDAC (SA_CDAC) that can be adjusted separately relative to at least another CDAC; and a controller configured to adjust at least one CDAC.

[0190] In some embodiments, the delay chain further includes: the delay stages include a first delay stage and a last delay stage; and the delay chain is configured as a controllable delay line such that: the first delay stage is configured to receive a clock signal at its input node; and the last delay stage is configured to generate a delayed version of the clock signal at its output node.

[0191] In some embodiments, the delay stages include a first delay stage and a last delay stage; and the delay chain is configured as a controllable oscillator such that: at the input node of the first delay stage, the first delay stage is configured to receive a signal fed back from the output node of the last delay stage.

[0192] In some embodiments, each CDAC is an SA_CDAC; and the controller is further configured to adjust each SA_CDAC accordingly.

[0193] In some embodiments, at least one SA_CDAC is a one-dimensional array of separately controllable capacitor (SCC) units (SCC_cell), each SCC_cell can be individually controlled to be coupled to the output node of the corresponding delay stage relative to other SCC_cell, the one-dimensional array includes rows and a single column, and each row includes a single SCC_cell; and the controller is further configured to selectively couple zero or some or all of the SCC_cell in at least one SA_CDAC to the output node of the corresponding delay stage.

[0194] In some embodiments, for each of at least one SA_CDAC, each SCC_cell includes: a switch and a capacitor, serially coupled between the output node of the corresponding delay stage and a first reference voltage; and a decoder configured to receive a corresponding addressing signal and generate a switch state control signal to control the switch to be in an open state or a closed state.

[0195] In some embodiments, the decoder has a specific configuration of corresponding row number parity check such that the decoders in odd rows or even rows have a first configuration, and conversely, the decoders in even rows or odd rows have a second configuration different from the first configuration.

[0196] In some embodiments, each CDAC is a SA_CDAC; the number of delay stages is M, where M is an integer and 2 ≤ M, such that the number of one-dimensional arrays is M; the number of rows of each one-dimensional array including SCC_cell is N, where N is an integer and 2 ≤ N; the one-dimensional arrays including SCC_cell together represent an NxM array of SCC_cell; and the controller is further configured to adjust each SA_CDAC accordingly according to a thermometer coding scheme for the NxM array; and for each SA_CDAC, the controller is further configured to generate an addressing signal according to the thermometer coding scheme such that the corresponding resulting switch state control signal controls zero or some or all of the capacitors in the corresponding one-dimensional array to be selectively coupled to the output node of the corresponding delay stage.

[0197] In some embodiments, the delay chain further includes: for each SCC_cell that is in the thermometer code ON state according to the thermometer coding scheme, the controller is further configured to generate an addressing signal such that the corresponding resulting switch state control signal controls the corresponding switch to be in the closed state according to a first duty cycle (DCY_1) of 100%, such that DCY1 = 100%; and for a selected SCC_cell of a first SCC_cell that would otherwise be in the thermometer code OFF state according to the thermometer coding scheme, the controller is further configured to generate an addressing signal such that the corresponding resulting switch state control signal controls the corresponding switch to be in the closed state according to a second duty cycle (DCY_2) in the range of 0% < DCY_2 < 100%.

[0198] In some embodiments, a method (of operating a delay chain) includes: coupling delay stages in series to represent a delay chain, and for each delay stage, coupling the delay stage includes the steps of: coupling a driving device between an input node and an output node of the delay stage; and coupling a capacitor digital-to-analog converter (CDAC) to the output node of the delay stage, where for at least one delay stage, the corresponding CDAC is a separately adjustable (SA) type of CDAC (SA_CDAC) that can be adjusted separately relative to the CDAC of at least another CDAC; and adjusting at least one CDAC separately relative to at least another delay stage; and adjusting at least one CDAC separately relative to at least another CDAC.

[0199] In some embodiments, each CDAC is a SA_CDAC; and the method includes adjusting each SA_CDAC accordingly.

[0200] In some embodiments, at least one SA_CDAC is a one-dimensional array of separate controllable capacitor (SCC) units (SCC_cell), each SCC_cell being separately controllable to couple to an output node of a corresponding delay stage relative to other SCC_cells, the one-dimensional array including rows and a single column, and each row including a single SCC_cell; and the method further includes selectively coupling zero or some or all of the SCC_cells in at least one SA_CDAC to the output node of the corresponding delay stage.

[0201] In some embodiments, for each of at least one SA_CDAC, each SCC_cell includes a switch and a capacitor; and the method further includes, for each SCC_cell, the steps of: coupling the switch and the capacitor in series between the output node of the corresponding delay stage and a first reference voltage; generating a switch state control signal based on a corresponding addressing signal to control the switch to be in an open state or a closed state.

[0202] In some embodiments, generating the switch state control signal includes: performing a specific operation of row number parity check on the corresponding addressing signal before generating the switch state control signal.

[0203] In some embodiments, performing the specific operation of row number parity check includes: in an even row or an odd row, inverting at least one addressing signal before generating the switch state control signal; and, in an odd row or an even row, conversely, not inverting any addressing signal before generating the switch state control signal.

[0204] In some embodiments, generating the switch state control signal includes: performing a logical AND-OR-INVERT (AOI) operation on the corresponding addressing signal.

[0205] In some embodiments, each CDAC is a SA_CDAC; the number of delay stages is M, where M is an integer and 2 ≤ M, such that the number of one-dimensional arrays is M; the number of rows in each one-dimensional array including SCC_cells is N, where N is an integer and 2 ≤ N. The one-dimensional arrays including SCC_cells together represent an NxM array of SCC_cells; and the method further includes adjusting each SA_CDAC accordingly according to the thermometer coding scheme of the NxM array, including: generating addressing signals according to the thermometer coding scheme, so that the generated switch state control signals control zero or part or all of the capacitors in the corresponding one-dimensional array to be selectively coupled to the output node of the corresponding delay stage.

[0206] In some embodiments, for each SCC_cell that is in the thermometer code ON state according to the thermometer coding scheme, generating the addressing signal includes configuring the addressing signal such that the correspondingly generated switch state control signal controls the corresponding switch to be in the closed state according to a first duty cycle (DCY_1) of 100%, such that DCY1 = 100%; and for a selected SCC_cell of a first SCC_cell that would otherwise be in the thermometer code OFF state according to the thermometer coding scheme, generating the addressing signal includes configuring the addressing signal such that the correspondingly generated switch state control signal controls the corresponding switch to be in the closed state according to a second duty cycle (DCY_2) within the range of 0% < DCY_2 < 100%.

[0207] In some embodiments, the delay chain includes: delay stages coupled in series, each delay stage including a drive device coupled between an input node and an output node of the delay stage, and a capacitor digital-to-analog converter (CDAC) coupled to the output node of the delay stage; at least one CDAC is a separately adjustable (SA) type of CDAC (SA_CDAC) that is separately adjustable relative to at least another CDAC; at least one SA_CDAC is a one-dimensional array of separately controllable capacitor (SCC) cells (SCC_cell), each SCC_cell being separately controllable relative to other SCC_cells to be coupled to the output node of the corresponding delay stage, the one-dimensional array including rows and a single column, and each row including a single SCC_cell; and a controller configured to adjust at least one CDAC by selectively coupling zero or some or all of the SCC_cells in at least one SA_CDAC to the output node of the corresponding delay stage.

[0208] In some embodiments, for each of at least one SA_CDAC, each SCC_cell includes: a switch and a capacitor, serially coupled between the output node of the corresponding delay stage and a first reference voltage; and a decoder configured to receive the corresponding addressing signal and generate a switch state control signal to control the switch to be in an open state or a closed state.

[0209] It can be seen that, for those of ordinary skill in the art, one or more of the disclosed embodiments achieve one or more of the advantages set forth above. After reading the foregoing specification, those of ordinary skill in the art will be able to envision various variations, equivalent substitutions, and numerous other embodiments as broadly disclosed herein. Accordingly, it is intended that the protection sought herein be limited only by the limitations contained in the appended claims and their equivalents.

Claims

1. A delay chain comprising: Series coupled delay stages, each delay stage comprising: a driver device coupled between an input node and an output node of the delay stage; and a capacitor digital-to-analog converter CDAC coupled to an output node of the delay stage; at least one CDAC of an individually adjustable (SA) type CDAC (SA_CDAC) that is individually adjustable relative to at least one other CDAC; and A controller is configured to adjust the at least one CDAC.

2. The delay chain of claim 1 , wherein: The delay stages include a first delay stage and a last delay stage; and The delay chain is configured as a controllable delay line such that: The first delay stage is configured to receive a clock signal at an input node thereof; and The last delay stage is configured to generate a delayed version of the clock signal at its output node.

3. The delay chain of claim 1 , wherein: The delay stages include a first delay stage and a last delay stage; and The delay chain is configured as a controllable oscillator such that: The first delay stage is configured to receive, at an input node of the first delay stage, a signal fed back from an output node of the last delay stage.

4. A method of operating a delay chain, the method comprising: The delay stages are coupled in series to represent the delay chain, For each of the delay stages, coupling the delay stage comprises the following steps: coupling a driver device between an input node and an output node of the delay stage; and coupling a capacitor digital-to-analog converter CDAC to an output node of the delay stage, wherein, for at least one of the delay stages, the corresponding CDAC is a CDAC (SA_CDAC) of an individually adjustable (SA) type, which can be adjusted independently relative to the CDAC of at least another delay stage; and At least one CDAC is individually adjusted relative to at least one other CDAC.

5. The method according to claim 4, wherein: Each of the CDACs is a CDAC of an individually adjustable type; and The method further comprises: Each of the individually adjustable types of CDAC is adjusted accordingly.

6. The method according to claim 4, wherein: The at least one individually adjustable type CDAC is a one-dimensional array of individually controllable capacitor (SCC) cells (SCC_cell), Each individually controllable capacitor unit is individually controllable relative to other individually controllable capacitor units to be coupled to an output node of a corresponding delay stage, The one-dimensional array includes rows and a single column, and Each row includes a single capacitive unit that can be controlled individually; as well as The method further comprises: Zero, part, or all of the individually controllable capacitive units in the at least one individually adjustable type CDAC are selectively coupled to an output node of a corresponding delay stage.

7. The method according to claim 6, wherein: For each of the at least one individually adjustable type CDAC, each individually controllable capacitive unit comprises a switch and a capacitor; and For each individually controllable capacitor unit, the method further comprises the following steps: coupling the switch and the capacitor in series between an output node of a corresponding delay stage and a first reference voltage; and A switch state control signal is generated based on the corresponding addressing signal to control the switch to be in an open state or a closed state.

8. The method according to claim 7, wherein: Generating switch state control signals includes: Before generating the switch state control signal, a row number parity check specific operation is performed on the corresponding addressing signal.

9. A delay chain comprising: Series coupled delay stages, each delay stage comprising: a driver device coupled between an input node and an output node of the delay stage; and a capacitor digital-to-analog converter CDAC coupled to an output node of the delay stage; at least one CDAC is an individually adjustable (SA) type CDAC (SA_CDAC) that is individually adjustable relative to at least one other CDAC; The at least one individually adjustable type CDAC is a one-dimensional array of individually controllable capacitor (SCC) cells (SCC_cell), Each individually controllable capacitor unit is individually controllable relative to other individually controllable capacitor units to be coupled to an output node of a corresponding delay stage, The one-dimensional array includes rows and a single column, and Each row includes a single individually controllable capacitive unit; and A controller is configured to adjust the at least one CDAC by selectively coupling zero, some, or all of the individually controllable capacitive units in the at least one individually adjustable type CDAC to an output node of a corresponding delay stage.

10. The delay chain of claim 9, wherein: For each of the at least one individually adjustable type CDAC, each individually controllable capacitive unit comprises: a switch and a capacitor coupled in series between an output node of a corresponding delay stage and a first reference voltage; and The decoder is configured to receive the corresponding addressing signal and generate a switch state control signal to control the switch to be in an open state or a closed state.

Images