Common-mode decoder supporting multi-system LDPC

Abstract

The invention relates to a common-mode decoder supporting multi-system LDPC (Low Density Parity Check), which comprises an LLR input module used for receiving an LLR to be decoded; the front zero padding module is used for padding 0 in front of the LLR to be decoded when the to-be-decoded is the to-be-decoded which is input by the 5G NR; the LLR replacement module is used for replacing the LLR to be decoded when the to-be-decoded is the to-be-decoded input by the DVB; the cyclic shift module is used for performing cyclic shift operation on the LLR to be decoded after zero padding or the LLR to be decoded after replacement; and the variable / verification information updating module is used for aligning the LLRs after the cyclic shift operation by reading the information of the variable information storage and the verification information storage, and carrying out iterative updating. According to the invention, the consumption of resources can be greatly reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of channel coding and decoding, and particularly to a multi-mode LDPC common-mode decoder. Background Art

[0002] Both DVB-S2 / S2X and 5G NR protocol standards adopt LDPC codes as one of the channel coding and decoding schemes. Among them, the construction type of the LDPC code introduced by DVB-S2 / S2X is an extended irregular repeat accumulate code (abbreviated as eIRA-LDPC code), and the construction type of the LDPC code introduced by 5G NR is a Quasi-Cyclic quasi-cyclic code (i.e., Qc-LDPC code). The parity-check matrix structures of the two are very different, so different decoding algorithms and architectures are selected in the mainstream decoding implementation schemes.

[0003] In the prior art, it is proposed to make the parity-check matrix of DVB have quasi-cyclic properties through basic matrix row and column transformations, as follows:

[0004] (1) By transforming the rows of the parity-check matrix in the order of 0, q,..., 359q, 1, q + 1,..., 359q + 1,..., q - 1,..., 359q + q - 1, a q * 45 block is obtained on the left, each block is a 360 * 360 quasi-cyclic matrix, and a new lower triangular bidiagonal matrix under row transformation is obtained on the right.

[0005] (2) Perform elementary column transformations similar to row transformations on the parity-check bit part of the parity-check matrix until a quasi-cyclic matrix with the same stepped lower triangular structure is restored. At the same time, the parity-check bits of the input llr information also need to undergo the same permutation.

[0006] However, for the LDPC code with a parity-check matrix having quasi-cyclic properties after such transformation, there is no relevant public solution on how to design a decoder architecture and a decoding scheduling scheme compatible with the QC-LDPC code in the 5G NR standard. For a communication system receiver with DVB and 5G NR common mode, if LDPC decoders are designed separately for the two modes, it will cause a huge resource overhead and pose great challenges to indicators such as the area, energy consumption, and cost of the communication system. Summary of the Invention

[0007] The technical problem to be solved by the present invention is to provide a multi-mode LDPC common-mode decoder, which can greatly save resource consumption.

[0008] The technical solution adopted by the present invention to solve its technical problem is: to provide a multi-mode LDPC common-mode decoder, including:

[0009] LLR input module, used to receive the LLR to be decoded;

[0010] Leading zero-padding module, used to pad 0 in front of the LLR of the to-be-decoded data when the to-be-decoded data is the to-be-decoded data for 5GNR input;

[0011] LLR permutation module, used to permute the LLR of the to-be-decoded data when the to-be-decoded data is the to-be-decoded data for DVB input;

[0012] Circular shift module, used to perform circular shift operations on the zero-padded LLR of the to-be-decoded data or the permuted LLR of the to-be-decoded data;

[0013] Variable / check information update module, used to align the LLR after the circular shift operation by reading the information in the variable information memory and the check information memory, and perform iterative updates.

[0014] When the leading zero-padding module pads 0 in front of the LLR of the to-be-decoded data, the number of 0s is 2*Zc, where Zc is the extension factor.

[0015] The LLR permutation module uses llr(Info_len+(i-1)*360+j) = llr_in(Info_len+(j-1)*q+i) to permute the LLR of the to-be-decoded data, where llr() is the permuted LLR, llr_in() is the LLR of the to-be-decoded data, Info_len is the information bit length of the LLR of the to-be-decoded data, q represents the number of groups of check bits, i represents the index of the group of check bits, and j represents the index inside a group of check bits.

[0016] The circular shift module includes a set of circular shift networks, and the maximum bit width of the circular shift network is 384; when the circular shift module performs circular shift operations on the zero-padded LLR of the to-be-decoded data, the maximum bit width is 384; when the circular shift module performs circular shift operations on the permuted LLR of the to-be-decoded data, the bit width is 360, and two circular shifts are required for sub-blocks with a row weight of 2.

[0017] The variable / check information update module includes 384 variable / check information update units. When the to-be-decoded data is the to-be-decoded data for 5GNR input, the number of enabled variable / check information update units is Zc, where Zc is the extension factor; when the to-be-decoded data is the to-be-decoded data for DVB input, the number of enabled variable / check information update units is 360.

[0018] The described multi - mode LDPC common - mode decoder further includes: a hard - decision module, which is used to read the latest variable information from the variable - information storage after each generation update is completed, and perform hard - decision to determine whether to perform early termination.

[0019] The described multi - mode LDPC common - mode decoder further includes: a syndrome - checking module, which is used to read the latest variable information from the variable - information storage after each generation update is completed, and perform syndrome - checking to determine whether to perform early termination.

[0020] Beneficial effects

[0021] Due to the adoption of the above - mentioned technical solution, compared with the prior art, the present invention has the following advantages and positive effects: The decoder of the present invention multiplexes the LLR input module, the cyclic - shift module, the variable / check - information update module, the hard - decision module, and the syndrome - checking module. By multiplexing most of the implementation resources, the consumption of resources can be greatly saved. Description of the drawings

[0022] Figure 1 is a block diagram of the multi - mode LDPC common - mode decoder according to the embodiment of the present invention;

[0023] Figure 2 is an implementation structure diagram of the multi - mode LDPC common - mode decoder according to the embodiment of the present invention. Detailed implementation manners

[0024] The following further elaborates the present invention in conjunction with specific embodiments. It should be understood that these embodiments are only used to illustrate the present invention and not to limit the scope of the present invention. In addition, it should be understood that after reading the content taught by the present invention, those skilled in the art can make various changes or modifications to the present invention, and these equivalent forms also fall within the scope defined by the appended claims of this application.

[0025] The embodiment of the present invention relates to a multi - mode LDPC common - mode decoder, as Figure 1 shown, including: an LLR input module, a zero - padding module at the front, an LLR permutation module, a cyclic - shift module, and a variable / check - information update module.

[0026] The LLR input module is used to receive the LLR to be decoded. The LLR input module in this embodiment can receive the LLR to be decoded input by DVB or the LLR to be decoded input by 5GNR.

[0027] The zero - padding module at the front is used to pad 0s in front of the LLR when the LLR to be decoded is the LLR to be decoded input by 5GNR. In this embodiment, when the zero - padding module pads 0s in front of the LLR to be decoded, the number of 0s is 2*Zc, where Zc is the extension factor.

[0028] The LLR permutation module is used to permute the LLR of the to-be-decoded when the to-be-decoded is the input to be decoded for DVB. In this embodiment, the permutation method of the LLR permutation module is the same as the method of elementary column transformation of the parity-check matrix, that is, the LLR of the to-be-decoded is permuted by using llr(Info_len+(i - 1)*360 + j)=llr_in(Info_len+(j - 1)*q + i), where llr() is the permuted LLR, llr_in() is the LLR of the to-be-decoded, Info_len is the information bit length of the LLR of the to-be-decoded, the parity check bits are grouped in groups of 360, q represents the number of groups of parity check bits, i represents the index of the parity check bit group, and j represents the index inside a group of parity check bits.

[0029] The cyclic shift module is used to perform a cyclic shift operation on the LLR of the to-be-decoded after zero-padding or the permuted LLR of the to-be-decoded. In this embodiment, there is a set of cyclic shift networks, and the maximum bit width of the cyclic shift networks is 384; the maximum bit width of the cyclic shift module when performing a cyclic shift operation on the LLR of the to-be-decoded after zero-padding is 384; the bit width of the cyclic shift module when performing a cyclic shift operation on the permuted LLR of the to-be-decoded is 360, and two cyclic shifts are required for sub-blocks with a row weight of 2.

[0030] The variable / check information update module is used to align the LLR after the cyclic shift operation by reading the information in the variable information storage and the check information storage, and perform iterative updates. The variable / check information update module in this embodiment includes 384 variable / check information update units. When the to-be-decoded is the input to be decoded for 5G NR, the number of enabled variable / check information update units is Zc, where Zc is the expansion factor; when the to-be-decoded is the input to be decoded for DVB, the number of enabled variable / check information update units is 360.

[0031] As Figure 1 shown, the multi-mode LDPC common-mode decoder supported by this embodiment further includes a hard decision module and a syndrome check module. Among them, the hard decision module is used to read the latest variable information from the variable information storage after each generation of update, and perform a hard decision to determine whether to perform early stopping; the syndrome check module is used to read the latest variable information from the variable information storage after each generation of update, and perform a syndrome check to determine whether to perform early stopping.

[0032] A specific embodiment is given below to further illustrate the present invention.

[0033] The implementation structure of the multi-mode LDPC common-mode decoder of this embodiment is as Figure 2As shown. When the LLR input module receives the LLR to be decoded from DVB input, the permutation method of the LLR permutation module is as follows:

[0034] for i = 1:q

[0035] for j = 1:360

[0036] llr(Info_len+(i - 1)*360 + j) = llr_in(Info_len+(j - 1)*q + i);

[0037] end

[0038] end

[0039] After the above permutation, the permuted result is stored in the variable information storage.

[0040] When the LLR input module receives the LLR to be decoded from 5G NR input, the zero-padding method of the zero-padding module is as follows: llr = [zeros(2*Zc) llr_in], and the zero-padded result is stored in the variable information storage.

[0041] In the DVB process, assume that the row weight of the first sub-block is 2, corresponding to Zc llrs, Zc = 360. Therefore, two cyclic shift networks with a maximum bit width of 360 need to be arranged. For the first sub-block, the cyclic shifters shift0_0 and shift0_1 read the corresponding variable information from the variable information storage corresponding to the first sub-block and then input it into the CNU / VNU (Check Information Update Module / Variable Information Update Unit) for processing. Because the parity-check matrix corresponding to the parity bits in the DVB process is a bi-diagonal structure, so Figure 2 Taking the last sub-block as an example, the row weight is 2, corresponding to Zc llrs, Zc = 360. The cyclic shifters shiftN_0 and shiftN_1 read the corresponding variable information from the variable information storage corresponding to the last sub-block and then input it into the CNU / VNU for processing.

[0042] In the 5G NR process, the row weight of each sub-block corresponding to each variable node is 1, corresponding to Zc llrs, and Zc is at most 384. Therefore, a cyclic shift network with a maximum bit width of 384 needs to be arranged. For each sub-block corresponding to each variable node, the cyclic shifter shift reads the corresponding variable information from the variable information storage corresponding to the sub-block and then input it into the CNU / VNU for processing.

[0043] In this embodiment, a total of 384 CNU / VNUs are arranged in the multi-mode LDPC common-mode decoder, which constitute the check / variable information update module. In the DVB process, 360 of them are enabled. In the 5G NR process, they are enabled according to the actual number of Zc. The CNU / VNU structure can be reused in both the 5G NR and DVB processing flows. The CNU / VNU aligns the LLR after cyclic shift operation by reading the information from the variable information memory and the check information memory, and performs iterative update.

[0044] After each iteration update, the hard decision module and the syndrome check module both read the latest variable information from the variable information memory, and perform hard decision and syndrome check to determine whether early stopping can be performed. In this embodiment, the same hard decision module and syndrome check module design structure can be reused in both the 5G NR and DVB processing flows.

[0045] It is not difficult to find that the decoder of the present invention reuses the LLR input module, the cyclic shift module, the variable / check information update module, the hard decision module and the syndrome check module. By reusing most of the implementation resources, the resource consumption can be greatly saved.

Claims

1. A multi-standard LDPC common mode decoder, characterized in that: include: LLR input module, used for receiving LLR to be decoded; A leading zero padding module, used for padding 0 in front of the LLR to be decoded when the code to be decoded is a 5GNR input code to be decoded; An LLR replacement module, used for replacing the LLR to be decoded when the code to be decoded is a DVB input code to be decoded; A cyclic shift module, used for performing a cyclic shift operation on the LLR to be decoded after zero padding or the LLR to be decoded after permutation; The variable / check information update module is used to align the LLR after the cyclic shift operation by reading the information in the variable information storage and the check information storage, and perform iterative update.

2. The multi-standard LDPC common mode decoder according to claim 1, characterized in that: When the leading zero-padding module padded the leading zeros of the LLR to be decoded, the number of zeros is 2*Zc, where Zc is an expansion factor.

3. The multi-standard LDPC common mode decoder according to claim 1, characterized in that: The LLR replacement module uses llr(Info_len+(i-1)*360+j)=llr_in(Info_len+(j-1)*q+i) to replace the LLR to be decoded, where llr() is the replaced LLR, llr_in() is the LLR to be decoded, Info_len is the information bit length of the LLR to be decoded, q represents the number of check bit groups, i represents the index of the check bit group, and j represents the internal index of a group of check bits.

4. The multi-standard LDPC common mode decoder according to claim 1, characterized in that: The cyclic shift module includes a set of cyclic shift networks, and the maximum bit width of the cyclic shift network is 384; the maximum bit width of the cyclic shift module when performing a cyclic shift operation on the LLR to be decoded after zero padding is 384; the bit width of the cyclic shift module when performing a cyclic shift operation on the LLR to be decoded after permutation is 360, and two cyclic shifts are required for sub-blocks with a row weight of 2.

5. The multi-standard LDPC common mode decoder according to claim 1, characterized in that: The variable / check information update module includes 384 variable / check information update units. When the code to be decoded is the code to be decoded of 5GNR input, the enabled number of the variable / check information update units is Zc, where Zc is the expansion factor; when the code to be decoded is the code to be decoded of DVB input, the enabled number of the variable / check information update units is 360.

6. The multi-standard LDPC common mode decoder according to claim 1, characterized in that: Also includes: The hard decision module is used to read the latest variable information from the variable information storage after each generation update is completed, and make a hard decision to determine whether to perform early stopping.

7. The multi-standard LDPC common mode decoder according to claim 1, characterized in that: Also includes: The companion check module is used to read the latest variable information from the variable information storage after each generation update is completed, and perform companion check to determine whether to perform early stopping.

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