Otp device and method of manufacturing the same

Abstract

The application provides an OTP device and a preparation method thereof. The OTP device comprises an active region and an X-direction active region extension, and a projection of a first contact hole on a substrate falls into the X-direction active region extension. The first contact hole is arranged at a position without interlayer dielectric layer thickness superposition through active region and first contact hole layout optimization, which is just a gap narrow part formed by an interlayer dielectric layer covering two adjacent floating gates. The position without floating gate covered by the interlayer dielectric layer will not form the gap narrow part. The first contact hole is designed in a Y-direction extension region of the gap space between two X-direction adjacent floating gates, avoiding the gap position of the two Y-direction adjacent floating gates. The first contact hole has the same width up and down, the contact performance is optimized, the bit line contact resistance formed by the metal layer filled in the first contact hole is normal, and the performance of the OTP device is ensured. The first contact hole position is not easy to form a cavity when the interlayer dielectric layer is filled, and the normal first contact hole is ensured.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of integrated circuit manufacturing, and particularly relates to an OTP device and a preparation method thereof. BACKGROUND

[0002] An OTP (one time programmable) device, also known as a one-time programmable device, belongs to a non-volatile memory. In comparison with a multiple-time programmable device (MTP), the programming process of the OTP device is irreversible, and the OTP device is suitable for application occasions with fixed programs. With the continuous reduction of the distance between floating gates (FG) and floating gates of the OTP device, for example, the distance is less than 0.4 um, the contact hole problem of a bit line gradually appears. As shown in FIG. 1, a deposited interlayer dielectric layer (for example, a silicon nitride layer) covers the floating gate and the gap between adjacent floating gates, and the silicon nitride layer includes a first part 01a of the silicon nitride layer covering the gap between adjacent floating gates and a second part 01b of the silicon nitride layer covering the top and sidewall of the floating gate. Under the condition that the distance between the floating gate (FG) and the floating gate is 0.47 um, the lateral distance between adjacent second parts 01b of the silicon nitride layer is only 0.13 um, and the distance between the floating gate and the floating gate will be smaller in the future. The silicon nitride layer is a stop layer of a main etching part in a step of etching a contact hole, and the sum of the thicknesses of the first part 01a of the silicon nitride layer and the second part 01b of the silicon nitride layer, that is, the height in the vertical direction, reaches 1000 angstroms (normally only 400 angstroms). The gap between adjacent second parts 01b of the silicon nitride layer is not etched to the bottom in the step of etching the contact hole, causing poor contact and large contact resistance. If the photoresist exposure overlay of the contact hole is offset, the situation will be worse. Figure 1

[0003] Figure 2 An ideal etching diagram for a contact hole 02 of an OTP device; Figure 3 An actual etching diagram for a contact hole 02 of an OTP device. As shown in FIG. 2, ideal etching of the contact hole 02 is vertical etching from the top to the substrate, and the upper and lower widths are the same. However, actual etching is as shown in FIG. 3. Due to the existence of adjacent second parts 01b of the silicon nitride layer (end of the red circle), and the thickness of the silicon nitride layer in the vertical direction is larger than the pre-designed thickness, the effective contact width of the bottom of the contact hole 02 with a width of 0.16 um is less than or equal to 0.13 um. The bottom of the contact hole 02 is narrow, that is, the upper width of the contact hole 02 is larger than the lower width, the contact area of the bottom of the contact hole 02 is small, leading to large contact resistance of a bit line formed by a metal layer filled in the contact hole 02, and the contact resistance will increase by about 30%, affecting the performance of the OTP device. In addition, due to the small gap between adjacent second parts 01b of the silicon nitride layer, a void (a filling gap) is easily formed at the gap position when an oxide layer covering the silicon nitride layer is formed subsequently, causing abnormality of the first contact hole. Figure 2 Figure 3 Figure 1 SUMMARY ​​​​

[0004] The present application aims to provide an OTP device and a preparation method thereof, a first contact hole is designed in a Y direction extension area of a gap space between two floating gates adjacent in an X direction, avoiding a gap position between two floating gates adjacent in the Y direction, so that the first contact hole has the same width up and down, the contact performance of the first contact hole is optimized, the bit line contact resistance formed by filling a metal layer in the first contact hole is normal, and the performance of the OTP device is ensured. Meanwhile, the first contact hole position is not easy to form a cavity when filling an interlayer dielectric layer, and the normal first contact hole is ensured.

[0005] The present application provides a preparation method of an OTP device, comprising:

[0006] A substrate, defining an X direction and a Y direction perpendicular to each other in a plane parallel to an upper surface of the substrate; a plurality of active regions are formed in the substrate and arranged in parallel along the X direction at intervals; each of the active regions extends along the Y direction to form a Y direction active region extension, and each of the Y direction active region extensions extends along the X direction to form an X direction active region extension;

[0007] A selection gate and a floating gate are located above the substrate, the selection gate extends along the X direction and crosses a plurality of the active regions; a plurality of floating gates are formed along the X direction at intervals; the floating gates are distributed one by one corresponding to the active regions; the projection of the floating gate on the substrate falls within the active region; the X direction active region extension is located on the side of the floating gate away from the selection gate;

[0008] An interlayer dielectric layer covers the floating gate, the selection gate and the substrate;

[0009] A first contact hole exposes the substrate by penetrating the interlayer dielectric layer; a plurality of the first contact holes are formed along the X direction at intervals; the first contact holes are distributed one by one corresponding to the X direction active region extensions; the projection of the first contact hole on the substrate falls within the X direction active region extension, and the first contact hole is located in the Y direction extension area of the gap space between two floating gates adjacent in the X direction.

[0010] Further, a first metal layer is filled in the first contact hole to lead a bit line.

[0011] Further, a common active region extending along the X direction is formed in the substrate on the side of the selection gate away from the floating gate, and the common active region is connected to a plurality of the active regions respectively;

[0012] A second contact hole is formed above the substrate, the projection of the second contact hole on the substrate falls within the common active region, a second metal layer is filled in the second contact hole to lead a source line.

[0013] Further, the X-direction active region extensions are spaced apart along the X direction; and the Y-direction two sides of the X-direction active region extensions are mirror distributed with the active regions, the floating gates and the select gates;

[0014] The Y-direction active region extensions connect the active regions on the Y-direction two sides of the X-direction active region extensions.

[0015] Further, a metal silicide is formed at a position where the first contact hole exposes the substrate, and the first metal layer is electrically connected with the metal silicide.

[0016] Further, one memory cell of the OTP device comprises the floating gate, the select gate, the bit line and the source line; and an oxide layer is formed between the floating gate and the substrate and between the select gate and the substrate.

[0017] Further, the OTP device comprises a plurality of the memory cells, and the memory cells in the same row along the X direction share the select gate and the source line; and the memory cells in the same column along the Y direction share the bit line.

[0018] The application further provides a preparation method of the OTP device, comprising:

[0019] A substrate is provided, and an X direction and a Y direction perpendicular to each other are defined in a plane parallel to the upper surface of the substrate; a plurality of active regions are formed in the substrate and spaced apart and arranged in parallel along the X direction; the active regions extend Y-direction active region extensions along the Y direction, and each Y-direction active region extension extends an X-direction active region extension along the X direction;

[0020] A select gate and a floating gate are formed above the substrate, the select gate extends along the X direction and across the plurality of active regions; a plurality of floating gates are formed and spaced apart along the X direction; the floating gates are distributed one-to-one with the active regions; a projection of the floating gate on the substrate falls within the active region; and the X-direction active region extension is located on a side of the floating gate away from the select gate;

[0021] An interlayer dielectric layer is formed, covering the floating gate, the select gate and the substrate;

[0022] Forming a first contact hole, the first contact hole exposes the substrate through the interlayer dielectric layer; forming a plurality of first contact holes spaced along the X direction; the first contact hole and the X-direction active region extension part are distributed one-to-one; the projection of the first contact hole on the substrate falls within the X-direction active region extension part, and the first contact hole is located in the Y-direction extension area of the gap space between the two adjacent X-direction floating gates.

[0023] Further, the interlayer dielectric layer includes a silicon nitride layer and an oxidation layer from bottom to top.

[0024] Further, the floating gate and the selection gate are formed in the same layer of polysilicon layer.

[0025] Compared with the prior art, the present application has the following beneficial effects:

[0026] The present application provides an OTP device and a preparation method thereof, the OTP device includes an active region and an X-direction active region extension part, the projection of the first contact hole on the substrate falls within the X-direction active region extension part, and the first contact hole is located in the Y-direction extension area of the gap space between the two adjacent X-direction floating gates. The present application optimizes the layout of the active region and the first contact hole to set the first contact hole at a position without the thickness of the interlayer dielectric layer, that is, the narrow position of the adjacent interlayer dielectric layer end, which is exactly at the narrow gap formed by the interlayer dielectric layer covering the adjacent two floating gates. The position covered by the interlayer dielectric layer without the floating gate will not form the narrow gap. The present application designs the first contact hole in the Y-direction extension area of the gap space between the two adjacent X-direction floating gates, avoiding the narrow gap position between the two adjacent Y-direction floating gates, so that the first contact hole has the same width up and down, the contact performance of the first contact hole is optimized, the contact resistance of the bit line formed by the metal layer filled in the first contact hole is normal, and the performance of the OTP device is ensured. At the same time, the position of the first contact hole is not easy to form a cavity when the interlayer dielectric layer is filled, and the normal first contact hole is ensured. BRIEF DESCRIPTION OF DRAWINGS

[0027] Figure 1 It is a sectional view of an OTP device.

[0028] Figure 2 It is an ideal schematic diagram of contact hole etching of an OTP device.

[0029] Figure 3 It is an actual schematic diagram of contact hole etching of an OTP device.

[0030] Figure 4 It is a layout schematic diagram of an OTP device of an embodiment of the present application.

[0031] Figure 5Another schematic view of a layout of an OTP device according to an embodiment of the application.

[0032] Figure 6 For the OTP device according to an embodiment of the application Figure 1 A partial schematic view of a layout of a corresponding prior art OTP device.

[0033] Figure 7 A flowchart of a method of manufacturing an OTP device according to an embodiment of the application.

[0034] In the drawings, the following reference signs apply:

[0035] 01a - first portion of silicon nitride; 01b - second portion of silicon nitride; 02 - contact hole;

[0036] 11 - active region; 12 - Y-direction active region extension; 13 - X-direction active region extension; 14 - common active region; 21 - floating gate; 22 - select gate; 31 - first contact hole; 32 - second contact hole. DETAILED DESCRIPTION

[0037] The application will be further described below in conjunction with the drawings and specific embodiments. The advantages and features of the application will become more apparent from the following description. It should be noted that the drawings are very simplified and use non-precise proportions, only to facilitate, clarify the purpose of assisting the description of the embodiments of the application.

[0038] For the purpose of describing the application, some embodiments can use spatial relative terms, such as "above", "below", "top", "bottom", etc., to describe the relationship between one element or component and another element or component as shown in the drawings of the embodiments. It should be understood that, in addition to the orientation described in the drawings, the spatial relative terms are also intended to include different orientations of the device in use or operation. For example, if the device in the drawings is turned over, the element or component described as "below" or "under" the other element or component will then be positioned "above" or "over" the other element or component. The terms "first", "second", etc. are used in the following description to distinguish between similar elements, and are not necessarily used to describe a particular order or time sequence. It is to be understood that these terms can be replaced as appropriate.

[0039] An OTP device according to an embodiment of the application is provided, such as Figure 4 and Figure 5 as shown, comprising:

[0040] A substrate, defining mutually perpendicular X and Y directions in a plane parallel to an upper surface of the substrate; a plurality of active regions 11 formed in the substrate and spaced apart along the X direction; each active region 11 extending in the Y direction to form a Y-direction active region extension 12, each Y-direction active region extension 12 extending in the X direction to form an X-direction active region extension 13;

[0041] A select gate 22 and a floating gate 21 located above the substrate, the select gate 22 extending along the X direction and across the plurality of active regions 11; a plurality of floating gates 21 formed in the X direction and spaced apart; the floating gates 21 distributed one-to-one with the active regions 11; a projection of the floating gate 21 on the substrate falling within the active region 11; the X-direction active region extension 13 located on a side of the floating gate 21 away from the select gate 22;

[0042] An interlayer dielectric layer, covering the floating gate 21, the select gate 22 and the substrate;

[0043] A first contact hole 31, the first contact hole exposing the substrate through the interlayer dielectric layer; a plurality of first contact holes 31 formed in the X direction and spaced apart; the first contact holes 31 distributed one-to-one with the X-direction active region extensions 13; a projection of the first contact hole 31 on the substrate falling within the X-direction active region extension 13, and the first contact hole 31 located in a Y-direction extension region of a gap between two adjacent floating gates 21 in the X direction.

[0044] Specifically, the substrate includes an OTP region and other regions, and the OTP region is provided with the select gate 22 and the floating gate 21 formed on the semiconductor substrate. The substrate is used to form an OTP device. The substrate can be any suitable substrate material known in the art, for example, at least one of the following materials: silicon (Si), germanium (Ge), silicon-germanium (SiGe), silicon-carbon (SiC), silicon-germanium-carbon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), or other III / V compound semiconductors, including a multilayer structure formed by these semiconductors, etc., or a silicon-on-insulator (SOI), a silicon-on-silicon (SSOI), a silicon-germanium-on-silicon (S-SiGeOI), a silicon-germanium-on-insulator (SiGeOI), and a germanium-on-insulator (GeOI), or a double-polished silicon wafer. For example, the substrate in the embodiment is a silicon wafer. The active region 11 has a predetermined width in the X direction and a predetermined length in the Y direction. In the Y direction, the floating gate 21 is spaced apart from the select gate 22.

[0045] The first contact hole 31 is filled with a first metal layer to lead out a bit line. The first contact hole exposes the substrate, and a metal silicide is formed at the position exposed by the substrate, and the first metal layer is electrically connected with the metal silicide. The substrate away from the floating gate 21 side of the select gate 22 is formed with a common active area 14 extending along the X direction, and the common active area 14 is connected with a plurality of active areas 11 respectively. The substrate is formed with a second contact hole 32 above the substrate, and the projection of the second contact hole 32 on the substrate falls within the common active area 14, and the second contact hole 32 is filled with a second metal layer to lead out a source line.

[0046] The X-direction active area extension 13 is spaced apart along the X direction; the Y-direction two sides of the X-direction active area extension 13 are mirror-imaged with the active area 11, the floating gate 21 and the select gate 22; and the Y-direction active area extension 12 is connected with the active areas 11 on the Y-direction two sides of the X-direction active area extension 13.

[0047] The interlayer dielectric layer covers the floating gate 21, the select gate 22, the substrate and the first metal layer in the first contact hole 31. The interlayer dielectric layer can include a silicon nitride layer and an oxide layer from bottom to top. The OTP device further includes a BPSG (boron phosphorus silicon glass) layer covering the interlayer dielectric layer.

[0048] For example, one memory cell of the OTP device is formed by two standard PMOS transistors in series. One of them is used as a selection transistor, and the other is also a standard PMOS transistor, but the gate is not connected, but is suspended, which is called a floating gate, and is used for data storage. Figure 5 As shown, one memory cell of the OTP device includes a floating gate 21, a select gate 22, a bit line and a source line; the floating gate 21 and the select gate 22 can be formed in the same polysilicon layer, and an oxide layer is formed between the floating gate 21 and the substrate, and between the select gate 22 and the substrate; the bit line is led out by the first metal layer filled in the first contact hole 31; and the source line is led out by the second metal layer filled in the second contact hole 32. The OTP device includes a plurality of memory cells, and the memory cells in the same row along the X direction share the select gate 22 and the source line; and the upper and lower memory cells in the same column along the Y direction share the bit line.

[0049] Figure 6 For example, one memory cell of the OTP device is formed by two standard PMOS transistors in series. One of them is used as a selection transistor, and the other is also a standard PMOS transistor, but the gate is not connected, but is suspended, which is called a floating gate, and is used for data storage. Figure 1 A partial layout diagram of the OTP device before the improvement. Figure 1 And Figure 3 are Figure 6 Cross-sectional views along the Y direction. As shown in Figure 1 , Figure 3 and Figure 6 , the bottom of the contact hole 02 of the OTP device before the improvement is formed at a position where the thickness of the silicon nitride layer is superimposed, that is, at a position where the adjacent silicon nitride layer end is narrow, which is exactly at a narrow gap formed by the silicon nitride layer covering the adjacent two floating gates in the Y direction.

[0050] As shown in Figure 4 and Figure 5 The OTP device of the present application comprises: an active region 11 and an X-direction active region extension 13, the projection of the first contact hole 31 on the substrate falls within the X-direction active region extension 13, and the first contact hole 31 is located in the Y-direction extension region of the gap space between two adjacent floating gates 21 in the X direction. The present application optimizes the layout of the active region 11 and the first contact hole 31 to place the first contact hole 31 at a position without the thickness of the interlayer dielectric layer, that is, the narrow position of the adjacent interlayer dielectric layer end, which is exactly at the narrow gap formed by the interlayer dielectric layer covering the adjacent two floating gates. The position covered by the interlayer dielectric layer without the floating gate 21 will not form the narrow gap. The present application designs the first contact hole 31 in the Y-direction extension region of the gap space between two adjacent floating gates 21 in the X direction, avoiding the gap position between the two adjacent floating gates in the Y direction, so that the first contact hole 31 has the same width up and down, the contact area of the bottom of the first contact hole 31 does not become smaller, the contact performance of the first contact hole 31 is optimized, the contact resistance of the bit line formed by the metal layer filled in the first contact hole 31 is normal, and the performance of the OTP device is ensured. At the same time, the position of the first contact hole 31 is not easy to form a cavity when the interlayer dielectric layer is filled, ensuring the normality of the first contact hole 31.

[0051] The present application also provides a preparation method of an OTP device, as shown in Figure 7 , comprising:

[0052] S1, providing a substrate, defining mutually perpendicular X and Y directions in a plane parallel to the upper surface of the substrate; forming a plurality of active regions in the substrate, which are arranged in parallel along the X direction and are spaced apart; the active regions extend in the Y direction to form Y-direction active region extensions, and each Y-direction active region extension extends in the X direction to form an X-direction active region extension;

[0053] S2, forming a selection gate and a floating gate above the substrate, the selection gate extending in the X direction and crossing a plurality of active regions; a plurality of floating gates are formed in the X direction and are spaced apart; the floating gates are distributed one-to-one with the active regions; the projection of the floating gate on the substrate falls within the active region; the X-direction active region extension is located on the side of the floating gate away from the selection gate;

[0054] S3, forming an interlayer dielectric layer, the interlayer dielectric layer covering the floating gate, the selection gate and the substrate;

[0055] S4, forming a first contact hole, the first contact hole exposing the substrate through the interlayer dielectric layer; a plurality of first contact holes are formed in the X direction and are spaced apart; the first contact holes are distributed one-to-one with the X-direction active region extensions; the projection of the first contact hole on the substrate falls within the X-direction active region extension, and the first contact hole is located in the Y-direction extension region of the gap space between two adjacent floating gates in the X direction.

[0056] The interlayer dielectric layer includes a silicon nitride layer and an oxide layer from bottom to top. The floating gate and the select gate are formed in the same polysilicon layer.

[0057] In summary, the OTP device and the manufacturing method thereof are provided. The OTP device includes an active region and an X-direction active region extension. A projection of the first contact hole on the substrate falls into the X-direction active region extension. The first contact hole is located in a Y-direction extension region of a gap space between two adjacent floating gates in the X direction. The first contact hole is located at a position without thickness superposition of the interlayer dielectric layer by optimizing the layout of the active region and the first contact hole. The position is a narrow position of an adjacent end of the interlayer dielectric layer. The position is exactly a narrow gap formed by the interlayer dielectric layer covering the two adjacent floating gates in the Y direction. The position without the floating gate covered by the interlayer dielectric layer will not form the narrow gap. The first contact hole is designed in the Y-direction extension region of the gap space between the two adjacent floating gates in the X direction. The first contact hole avoids the gap position between the two adjacent floating gates in the Y direction. Therefore, the first contact hole has the same width in the up and down directions. The contact performance of the first contact hole is optimized. The contact resistance of the bit line formed by the metal layer filled in the first contact hole is normal. The performance of the OTP device is ensured. At the same time, the first contact hole position is not easy to form a void when the interlayer dielectric layer is filled. The first contact hole is normal.

[0058] The embodiments in the specification are described in a progressive manner. Each embodiment focuses on the difference from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the method disclosed by the embodiments, the description is relatively simple because the method corresponds to the device disclosed by the embodiments. The relevant part can be referred to the method part.

[0059] The above description is only a description of the preferred embodiments of the present application, and is not any limitation on the scope of the present application. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present application without departing from the spirit and scope of the present application by using the disclosed methods and technical contents. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application, without departing from the technical solutions of the present application, are within the protection scope of the present application.

Claims

1. An OTP device, characterized by Comprising: a substrate, defining mutually perpendicular X and Y directions in a plane parallel to an upper surface of the substrate; a plurality of active regions are formed in the substrate and are spaced apart and arranged in parallel along the X direction; each of the active regions extends along the Y direction to form a Y-direction active region extension, and each of the Y-direction active region extensions extends along the X direction to form an X-direction active region extension; a select gate and a floating gate above the substrate, the select gate extends along the X direction and spans a plurality of the active regions; a plurality of the floating gates are formed in the substrate and are spaced apart along the X direction; the floating gates are distributed one-to-one with the active regions; a projection of the floating gate on the substrate falls within the active region; the X-direction active region extension is located on a side of the floating gate away from the select gate; an interlayer dielectric layer covering the floating gate, the select gate, and the substrate; a first contact hole exposing the substrate through the interlayer dielectric layer; a plurality of the first contact holes are formed in the substrate and are spaced apart along the X direction; the first contact holes are distributed one-to-one with the X-direction active region extensions; a projection of the first contact hole on the substrate falls within the X-direction active region extension, and the first contact hole is located in a Y-direction extension region of a gap between two adjacent floating gates in the X direction.

2. The OTP device of claim 1, wherein: the first contact hole is filled with a first metal layer to lead a bit line.

3. The OTP device of claim 2, wherein: a common active region extending along the X direction is formed in the substrate on a side of the select gate away from the floating gate, and the common active region is connected with a plurality of the active regions respectively; a second contact hole is formed above the substrate, a projection of the second contact hole on the substrate falls within the common active region, and the second contact hole is filled with a second metal layer to lead a source line.

4. The OTP device of claim 1, wherein: the X-direction active region extensions are spaced apart along the X direction; the active regions, the floating gates, and the select gates are mirror distributed on both sides of the Y direction of the X-direction active region extensions; the Y-direction active region extension connects the active regions on both sides of the Y direction of the X-direction active region extension.

5. The OTP device of claim 2, wherein: a metal silicide is formed at a position where the first contact hole exposes the substrate, and the first metal layer is electrically connected with the metal silicide.

6. The OTP device of claim 3, wherein: one memory cell of the OTP device includes the floating gate, the select gate, the bit line, and the source line; an oxide layer is formed between the floating gate and the substrate, and between the select gate and the substrate.

7. The OTP device of claim 6, wherein: the OTP device includes a plurality of the memory cells; the select gate and the source line are shared by the memory cells in the same row in the X direction; and the bit line is shared by the memory cells in the same column in the Y direction.

8. A method of manufacturing an OTP device, characterized by, Comprising: A substrate is provided, and an X direction and a Y direction perpendicular to each other are defined in a plane parallel to an upper surface of the substrate; A plurality of active regions are formed in the substrate, spaced apart and arranged in parallel along the X direction; each of the active regions extends along the Y direction to form a Y-direction active region extension, and each of the Y-direction active region extensions extends along the X direction to form an X-direction active region extension; A select gate and a floating gate are formed above the substrate, the select gate extending along the X direction and across a plurality of the active regions; a plurality of the floating gates are formed spaced apart along the X direction; the floating gates are distributed one-to-one corresponding to the active regions; a projection of the floating gate on the substrate falls within the active region; and the X-direction active region extension is located on a side of the floating gate away from the select gate; An interlayer dielectric layer is formed, covering the floating gate, the select gate, and the substrate; A first contact hole is formed, exposing the substrate through the interlayer dielectric layer; a plurality of the first contact holes are formed spaced apart along the X direction; the first contact holes are distributed one-to-one corresponding to the X-direction active region extensions; a projection of the first contact hole on the substrate falls within the X-direction active region extension, and the first contact hole is located in a Y-direction extension region of a gap space between two adjacent floating gates along the X direction.

9. The method of claim 8, wherein: The interlayer dielectric layer comprises, from bottom to top, a silicon nitride layer and an oxide layer.

10. The method of claim 8, wherein: The floating gate and the select gate are formed in the same polycrystalline silicon layer.

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