A novel semiconductor non-volatile memory and its preparation method and application

Abstract

The present invention belongs to the technical field of semiconductor devices, and discloses a novel semiconductor non-volatile memory, its preparation method and application. The memory includes a substrate, a bottom electrode, an amorphous oxide interface layer, a ferroelectric dielectric layer, and a top electrode which are sequentially arranged from bottom to top. The preparation method includes: (1) substrate cleaning; (2) bottom electrode deposition; (3) forming an amorphous oxide interface layer; (4) ferroelectric dielectric layer deposition, forming a ultrathin ferroelectric dielectric layer with uniform composition and good ferroelectricity on the amorphous MoO3 interface layer; (5) top electrode patterning and deposition; (6) rapid thermal annealing treatment. The above-mentioned memory is applied to a three-dimensional stacked non-volatile memory array or to construct a back-gate ferroelectric transistor structure. The present invention effectively inhibits the formation of non-ferroelectric phases, promotes the preferred orientation arrangement of ferroelectric phases, enhances the polarization intensity, and improves the ferroelectric performance of the device. It has both a low thermal budget, high process compatibility and excellent ferroelectric performance.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor devices, and particularly relates to a novel semiconductor non-volatile memory and its preparation method and application, which are applicable to application scenarios such as non-volatile memories, high-density three-dimensional integrated systems, and brain-like computing chips. Background Art

[0002] With the advent of the era of big data and artificial intelligence, the electronic information industry has put forward more stringent technical requirements for non-volatile storage devices in terms of high density, low power consumption, and high reliability. As an important candidate for the new generation of non-volatile storage technology, hafnium oxide (HfO2)-based ferroelectric devices have received extensive attention and in-depth research in recent years due to their excellent thickness scaling potential, stable nano-scale ferroelectricity, and good compatibility with complementary metal oxide semiconductor (CMOS) processes.

[0003] However, at present, hafnium oxide (HfO2)-based ferroelectric memories generally have the technical bottleneck of relatively high operating voltage (usually about 3V), with relatively large power consumption, which limits their further application in low-power integrated systems. Promoting the thickness scaling of ferroelectric films is considered a feasible path that combines economy and efficiency. On the one hand, the thickness scaling of the film can effectively increase the electric field strength of the device and reduce the operating voltage; on the other hand, it can reduce power consumption and optimize the thermal management performance of the device in high-density packaging scenarios, improving the integration stability. In addition, reducing the thickness of the ferroelectric film can also shorten the atomic layer deposition (ALD) process time, improve the production line efficiency, and enhance the thickness uniformity and device process consistency. At the same time, the current heat treatment temperature of hafnium oxide (HfO2)-based ferroelectric films is generally high (usually ≥400°C), which severely limits their compatibility with advanced three-dimensional integration and back-end interconnect (BEOL) processes. Therefore, there is an urgent need to develop a new ferroelectric performance regulation strategy with simple process, low thermal budget, and back-end process compatibility.

[0004] Existing research shows that the ferroelectricity of hafnium oxide (HfO2)-based films mainly stems from the stable formation of the orthorhombic phase and its preferred orientation. Although there have been methods to attempt to increase the proportion of the ferroelectric phase through electrode engineering or introducing intermediate layers (such as β-W, WS2, etc.), these techniques are mostly applicable to relatively thick film layers and have problems such as complex processes and high integration difficulties, making it difficult to meet the dual requirements of performance and process coordination for ultra-thin devices. Summary of the Invention

[0005] Aiming at the deficiencies of the existing technologies, the present invention aims to solve the compatibility problem of reducing the thermal budget and thickness scaling of HfO2-based ferroelectric thin films, especially the technical bottlenecks in aspects such as insufficient polarization intensity, increasing proportion of non-ferroelectric phase, and reliability degradation. For this purpose, a new type of semiconductor non-volatile memory with a low thermal budget and backend process compatibility is proposed. This memory is based on an amorphous interface layer to improve the ferroelectric performance of the device and enhance its stability and reliability. At the same time, a preparation method for this memory is provided. On the basis of ensuring the simplicity of the process and the compatibility of BEOL integration, this method realizes effective regulation of the stability of the ferroelectric phase and the out-of-plane ferroelectric domain orientation.

[0006] The new type of semiconductor non-volatile memory of the present invention includes a substrate, a bottom electrode, an amorphous oxide interface layer, a ferroelectric dielectric layer, and a top electrode sequentially arranged from bottom to top.

[0007] The material of the substrate is Si and SiO2; the material of the bottom electrode is Mo, the amorphous oxide interface layer is an amorphous MoO3 interface layer (amorphous molybdenum oxide (a-MoO3)), and the ferroelectric dielectric layer is a hafnium-based ferroelectric material (such as Si:HfO2, La:HfO2, Zr:HfO2, etc.); the material of the top electrode includes but is not limited to Mo, TiN, W, and Pt.

[0008] The thickness of the bottom electrode is 20-100 nm, the thickness of the ferroelectric dielectric layer is 5-10 nm, the thickness of the top electrode is 20-100 nm, and the thickness of the amorphous oxide interface layer is 1-2 nm.

[0009] The ferroelectric dielectric layer is a HZO ferroelectric dielectric layer, and HfO2 and ZrO2 are sequentially deposited from bottom to top in a layer-by-layer stacking (alternate deposition) manner to regulate the crystal phase evolution process; the single-layer thickness of HfO2 and ZrO2 is 0.5-1 nm, and the molar ratio of HfO2 to ZrO2 is 1:1.

[0010] The present invention introduces an amorphous MoO3 interface layer between the Mo bottom electrode and the HZO ferroelectric dielectric layer by precisely regulating the oxidation reaction on the surface of the Mo bottom electrode in the atomic layer deposition (ALD) process. This amorphous interface layer effectively inhibits the formation of paraelectric and antiferroelectric phases by regulating the interface energy and crystal phase growth mechanism, significantly promotes the preferential orientation and spontaneous stability of the ferroelectric orthorhombic phase in the out-of-plane direction, thereby enhancing the remanent polarization intensity and improving the overall ferroelectric performance of the thin film.

[0011] The preparation method of the above-mentioned new type of semiconductor non-volatile memory includes the following steps:

[0012] (1) Substrate cleaning;

[0013] Ultrasonic cleaning was performed using acetone, absolute ethanol, and deionized water to remove organic matter and particulate contamination, followed by drying in a nitrogen environment.

[0014] (2)Bottom electrode deposition;

[0015] On the cleaned substrate, metal Mo was deposited as the bottom electrode using physical vapor deposition (PVD) method, and the thickness was controlled within 20 - 100 nm to ensure good conductivity and stable crystal structure.

[0016] The deposition by the physical vapor deposition (PVD) method was carried out using a magnetron sputtering process. The set sputtering power was 55 W, the working atmosphere was Ar, the flow rate was 3 sccm, and the deposition rate was 1 Å / s.

[0017] (3)Formation of amorphous oxide interface layer;

[0018] After the deposition of the Mo bottom electrode was completed, atomic layer deposition (ALD) process was used to perform interface oxidation treatment by introducing an oxidizing gas (oxidants include but are not limited to H2O, O3, and H2O2); by controlling the oxidation time, temperature, and oxidant flow rate (such as treating for 60 seconds at 300 °C), an amorphous MoO3 interface layer with a thickness of 1 - 2 nm was induced to form on the Mo surface.

[0019] (4)Ferroelectric dielectric layer deposition;

[0020] On the amorphous MoO3 interface layer, HfO2 layer and ZrO2 layer were alternately deposited by atomic layer deposition (ALD) process in a 1:1 molar ratio. The oxygen source was a water source or an ozone source, and the thickness of each layer was controlled within 0.5 - 1 nm, and the total thickness was controlled within 5 - 10 nm (to meet the requirements of low power consumption and high-density integration), forming an ultrathin HZO ferroelectric dielectric layer with uniform composition and good ferroelectricity.

[0021] (5)Top electrode patterning and deposition;

[0022] Photoresist was spin-coated on the HZO ferroelectric dielectric layer, and standard photolithography process was used to complete pattern exposure and development. Then, metal Mo was deposited as the top electrode using physical vapor deposition (PVD) method, and the thickness was controlled within 20 - 100 nm. Finally, the electrode patterning was completed by the Lift-off process.

[0023] (6)Rapid thermal annealing (RTA) treatment;

[0024] The above structure was subjected to rapid thermal annealing treatment in an inert nitrogen atmosphere to promote the crystallization of the HZO thin film to form a stable ferroelectric orthorhombic phase and stimulate its ferroelectricity. The rapid thermal annealing treatment was carried out by rapid thermal annealing at 300 - 400 °C for 250 - 350 seconds in a nitrogen atmosphere.

[0025] The above method regulates the oxidation state on the surface of the molybdenum (Mo) bottom electrode through an atomic layer deposition process, and a stable amorphous MoO3 (a-MoO3) interface layer can be formed. This amorphous interface layer can effectively inhibit the growth of the non-ferroelectric paraelectric phase, promote the spontaneous and stable alignment of the ferroelectric phase in the out-of-plane direction, and significantly improve the ferroelectric properties of the thin film. Experiments have proved that compared with the devices without introducing the a-MoO3 interface layer or using a crystalline MoO3 (c-MoO3) interface layer, the back-end compatible ultra-thin HfO2-based ferroelectric device prepared by the present invention exhibits higher polarization intensity and more excellent reliability, and is suitable for the practical application of the next-generation low-power high-density integrated memory.

[0026] The novel semiconductor non-volatile memory of the present invention is applied to a three-dimensional stacked non-volatile memory array. The architecture adopts a 2TnC cell array, that is, each column is vertically integrated by two transistors and n (2 - 100) novel semiconductor non-volatile memories proposed by the present invention to achieve high-density vertical stacked storage.

[0027] The novel semiconductor non-volatile memory of the present invention can also be applied to construct a back-gate ferroelectric transistor structure. This structure uses Mo as the back-gate metal, and optimizes the performance of the ferroelectric layer through the amorphous (a-MoO3) interface engineering process proposed by the present invention, thereby effectively improving the switching characteristics, threshold voltage regulation ability and data retention characteristics of the device.

[0028] By introducing an amorphous interface layer between the bottom electrode and the ferroelectric dielectric layer, the present invention effectively inhibits the formation of the non-ferroelectric phase, promotes the preferred orientation arrangement of the ferroelectric phase, enhances the polarization intensity, and improves the ferroelectric properties of the device without introducing additional doping elements, without sacrificing the thickness of the functional layer, and while keeping the process simple. It has low thermal budget, high process compatibility and excellent ferroelectric properties, and can be widely applied to the preparation of key devices in next-generation HfO2-based ferroelectric capacitors, ferroelectric transistors, three-dimensional flash architectures, three-dimensional DRAM architectures, neuromorphic computing units and other non-volatile memories and brain-like chips. Description of the Drawings

[0029] Figure 1 is a schematic structural diagram of the novel semiconductor non-volatile memory of the present invention.

[0030] Figure 2 is a preparation flow chart of the novel semiconductor non-volatile memory of the present invention.

[0031] Figure 3 is a schematic structural diagram of the HZO ferroelectric capacitor (MoO3-free group) without the MoO3 interface layer in Comparative Example 1.

[0032] Figure 4 is a schematic structural diagram of the HZO ferroelectric capacitor (c-MoO3 group) with a crystalline MoO3 interface layer in Comparative Example 2.

[0033] Figure 5 It is a graph of the remanent polarization intensity and operating voltage of the novel semiconductor non-volatile memory prepared in Example 1 (a-MoO3 group) and the ferroelectric capacitors in Comparative Example 1 and Comparative Example 2 (MoO3-free group and c-MoO3 group).

[0034] Figure 6 It is a hysteresis loop graph of the novel semiconductor non-volatile memory prepared in Example 1 (a-MoO3 group) and the ferroelectric capacitors in Comparative Example 1 and Comparative Example 2 (MoO3-free group and c-MoO3 group) (MoO3-free group and c-MoO3 group).

[0035] Figure 7 It is a retention characteristic graph of the novel semiconductor non-volatile memory prepared in Example 1 (a-MoO3 group) and the ferroelectric capacitors in Comparative Example 1 and Comparative Example 2 (MoO3-free group and c-MoO3 group).

[0036] Figure 8 It is a graph of the electric field cycling life of the novel semiconductor non-volatile memory prepared in Example 1 (a-MoO3 group) and the ferroelectric capacitors in Comparative Example 1 and Comparative Example 2 (MoO3-free group and c-MoO3 group).

[0037] Figure 9 It is a graph of the constant voltage operating life of the novel semiconductor non-volatile memory prepared in Example 1 (a-MoO3 group) and the ferroelectric capacitors in Comparative Example 1 and Comparative Example 2 (MoO3-free group and c-MoO3 group).

[0038] Figure 10 It is a schematic structural diagram of a three-dimensional stacked non-volatile memory array.

[0039] Figure 11 It is a schematic circuit diagram of a three-dimensional stacked non-volatile memory array.

[0040] Figure 12 It is a schematic structural diagram of a back-gate ferroelectric transistor.

[0041] In the figure: 1. Substrate, 2. Bottom electrode, 3. Amorphous oxide interface layer, 4. Ferroelectric dielectric layer, 5. Top electrode, 6. Substrate. Detailed implementation manners

[0042] The novel semiconductor non-volatile memory provided by the present invention introduces an amorphous MoO3 interfacial layer between the Mo bottom electrode and the HZO ferroelectric dielectric layer by precisely controlling the oxidation reaction on the surface of the Mo bottom electrode during the atomic layer deposition (ALD) process. This amorphous interfacial layer effectively inhibits the formation of the paraelectric phase and the antiferroelectric phase by regulating the interfacial energy and the crystal phase growth mechanism, significantly promotes the out-of-plane preferred orientation and spontaneous stability of the ferroelectric orthorhombic phase, thereby enhancing the remanent polarization intensity and improving the overall ferroelectric performance of the thin film.

[0043] The novel semiconductor non-volatile memory of the present invention has a structure as Figure 1 shown, which sequentially includes a substrate: 1, a bottom electrode 2, an amorphous oxide interfacial layer 3, a ferroelectric dielectric 4, and a top electrode 5 from bottom to top. The material of the substrate 1 is Si or SiO2, and the thickness is 300 nm. The materials of the bottom electrode 2 and the top electrode 5 are Mo, and the thickness is 20 - 100 nm. The material of the amorphous oxide interfacial layer 3 is MoO3, and the thickness is 1 - 2 nm. The material of the ferroelectric dielectric layer 4 is HZO, and the thickness is 5 - 10 nm. HfO2 and ZrO2 are sequentially deposited from bottom to top in a layer-by-layer stacking manner, the single-layer thickness of HfO2 and ZrO2 is 0.5 - 1 nm, and the molar ratio of HfO2 to ZrO2 is 1:1.

[0044] Figure 2 The specific preparation process of the novel semiconductor non-volatile memory of the present invention is given.

[0045] The novel semiconductor non-volatile memory of the present invention and its preparation process are described in detail below in combination with embodiments, and the performance of the ultra-thin ferroelectric capacitor of the present invention is described in combination with comparative examples.

[0046] Example 1

[0047] In this example, a novel semiconductor non-volatile memory based on an amorphous MoO3 interfacial layer is prepared, and its structure is referred to Figure 1 , the material of the substrate 1 is SiO2, and the thickness is 300 nm. The thicknesses of the bottom electrode 2 and the top electrode 5 are both 100 nm. The thickness of the amorphous oxide interfacial layer 3 is 2 nm. The thickness of the ferroelectric dielectric layer 4 is 5 nm.

[0048] Referring to Figure 2 , the specific process of this example includes the following steps.

[0049] Step S1: Clean the substrate 1;

[0050] Select a SiO2 silicon substrate with a thickness of 300 nm, ultrasonically clean it with acetone and absolute ethanol for 5 minutes in sequence, rinse it with deionized water, and dry it with nitrogen for standby.

[0051] Step S2: Deposit the Mo bottom electrode 2;

[0052] Prepare the Mo bottom electrode 2 using a sputtering process, which includes but is not limited to magnetron sputtering, ion beam sputtering, reactive sputtering, etc. In this embodiment, the magnetron sputtering process is used to deposit the Mo electrode with a deposition thickness of 100 nm. The target material is high-purity Mo (99.99%). Set the sputtering power to 55 W, the working atmosphere is Ar (flow rate 3 sccm), and the deposition rate is approximately 1 Å / s.

[0053] Step S3: Form the amorphous oxide interface layer 3;

[0054] In-situ oxidize the Mo bottom electrode through atomic layer deposition. The oxidizing agent includes but is not limited to H2O, O3, H2O2, etc. In this embodiment, O3 is used as the oxygen source and treated at 300 °C for 60 s to form an amorphous MoO3 layer with a thickness of approximately 2 nm on the Mo surface.

[0055] Step S4: Deposit the ferroelectric dielectric layer 4;

[0056] Continue to deposit a 5-nm-thick HZO ferroelectric thin film (ferroelectric dielectric layer 4) using atomic layer deposition. First deposit a 0.5-nm-thick HfO2 layer, then deposit a 0.5-nm-thick ZrO2 layer, and cycle and stack in sequence until the target thickness of 5 nm is reached. The precursors are Hf[N(C2H5)CH3]4 and Zr[N(C2H5)CH3]4 respectively, the oxygen source is H2O, and the deposition temperature is set at 300 °C.

[0057] Step S5: Pattern the top electrode region;

[0058] Spin-coat a photoresist (positive photoresist) on the surface of the HZO thin film, pre-bake at 100 °C, and then perform exposure and development after 60 s. The development time is 30 s, and the developer is a conventional alkaline developer. Then rinse with deionized water and dry with nitrogen.

[0059] Step S6: Deposit the Mo top electrode 5;

[0060] Deposit a 100-nm Mo top electrode using the magnetron sputtering process. The sputtering parameters are the same as those for depositing the Mo bottom electrode 2 in Step S2.

[0061] Step S7: Photoresist stripping;

[0062] Place the sample in acetone and ultrasonicate for 30 s to perform Lift-off to remove the photoresist, and then clean and dry with ethanol and deionized water.

[0063] Step S8: Rapid thermal annealing treatment (RTA);

[0064] The sample was rapidly thermally annealed for 300 seconds (adjustable between 250 - 350 seconds) at 350 °C (adjustable between 300 - 400 °C) under a nitrogen atmosphere to promote the crystallization of HZO, stabilize the ferroelectric phase, and stimulate ferroelectricity.

[0065] Example 2

[0066] In this example, a novel semiconductor non-volatile memory based on an amorphous MoO3 interfacial layer was fabricated. The substrate 1 was made of Si with a thickness of 300 nm. The bottom electrode 2 and the top electrode 5 both had a thickness of 20 nm. The amorphous oxide interfacial layer 3 had a thickness of 1 nm. The ferroelectric dielectric layer 4 had a thickness of 7 nm.

[0067] The steps of its preparation process were the same as those in the example, except that the corresponding thicknesses of each layer were adjusted according to the above specific thicknesses, and the thicknesses of the deposited HfO2 layer and ZrO2 layer in step S4 were also adjusted.

[0068] Example 3

[0069] In this example, a novel semiconductor non-volatile memory based on an amorphous MoO3 interfacial layer was fabricated. The substrate 1 was made of SiO2 with a thickness of 300 nm. The bottom electrode 2 and the top electrode 5 both had a thickness of 60 nm. The amorphous oxide interfacial layer 3 had a thickness of 1.5 nm. The ferroelectric dielectric layer 4 had a thickness of 10 nm.

[0070] The steps of its preparation process were the same as those in the example, except that the corresponding thicknesses of each layer were adjusted according to the above specific thicknesses, and the thicknesses of the deposited HfO2 layer and ZrO2 layer in step S4 were also adjusted.

[0071] Comparative Example 1

[0072] This Comparative Example 1 was an ultra-thin HZO ferroelectric capacitor without an introduced MoO3 interfacial layer. Different from the novel semiconductor non-volatile memory in Example 1, it did not contain a MoO3 interfacial layer. As Figure 3 shown, its structure from bottom to top successively included a substrate 1, a bottom electrode 2, a ferroelectric dielectric 4, and a top electrode 5.

[0073] The difference in the preparation process of this Comparative Example 1 from that of Example 1 was that step S3 (oxidation of the bottom electrode) was omitted, that is, the surface oxidation treatment of the bottom electrode was not performed before depositing the HZO dielectric layer, and the HZO layer was directly grown on the Mo electrode surface. The remaining steps such as substrate cleaning, Mo electrode deposition, HZO layer deposition, patterning, top electrode deposition, photoresist stripping, and thermal annealing were the same.

[0074] Comparative Example 2

[0075] In Comparative Example 2, it is an ultra-thin HZO ferroelectric capacitor based on a crystalline MoO3 interface layer, where the crystalline MoO3 interface layer replaces the amorphous MoO3 interface layer of the novel semiconductor non-volatile memory in Example 1. As Figure 4 shown, the capacitor structure of Comparative Example 2 includes a substrate 1, a bottom electrode 2, a crystalline oxide interface layer 6, a ferroelectric dielectric 4, and a top electrode 5 in sequence from bottom to top.

[0076] The main difference between the preparation process of Comparative Example 2 and that of Example 1 lies in that step S3 (oxidizing the bottom electrode) adopts a long-time oxidation method to form a crystalline phase MoO3 interface layer. Specifically, through the atomic layer deposition process with O3 as the oxygen source, the Mo bottom electrode is in-situ oxidized for 20 minutes to form a MoO3 layer with a definite crystal structure on its surface, and then the HZO layer is deposited.

[0077] The following gives the specific performance evaluation and comparison between the examples and the comparative examples.

[0078] A probe station (Cascade Summit 12000) and a semiconductor device parameter analyzer (Keysight B1500A) are used to perform high-precision electrical tests on the device to systematically evaluate its electrical performance.

[0079] 1. Polarization intensity characteristic test;

[0080] Evaluate the influence of the amorphous MoO3 interface layer (a-MoO3 group) on the remanent polarization intensity (Pr) of the device.

[0081] A scanning voltage test is performed on the novel semiconductor non-volatile memory with an amorphous MoO3 interface layer in Example 1 (a-MoO3 group), the ferroelectric capacitor without a MoO3 interface layer in Comparative Example 1 (no-MoO3 group), and the ferroelectric capacitor with a crystalline MoO3 interface layer in Comparative Example 2 (c-MoO3 group). During the test, the top electrode is pressurized and the bottom electrode is grounded. The PUND method is used to extract the polarization current with a 2 kHz triangular pulse scan, and the polarization amount is calculated by integration. The scanning voltage ranges from ±0.5 V to ±3 V with a step of 0.25 V. The results are as Figure 5 shown. In this voltage range, the a-MoO3 group in Example 1 exhibits the highest remanent polarization intensity.

[0082] As Figure 6 shown, under the application of a ±1.5 V electric field, the polarization hysteresis loop of the novel semiconductor non-volatile memory with an amorphous MoO3 interface layer (a-MoO3 group) in Example 1 shows that 2Pr is 44.5 μC / cm 2 , which is significantly higher than that of Comparative Example 1 (28.7 μC / cm 2 ) and Comparative Example 2 (11.5 μC / cm 2 ).

[0083] 2. Retention characteristic test;

[0084] Evaluate the effect of the amorphous MoO3 interfacial layer (a-MoO3 group) on the polarization retention characteristics of the device.

[0085] Test the novel semiconductor non-volatile memory with an amorphous MoO3 interfacial layer in Example 1 (a-MoO3 group), the ferroelectric capacitor without a MoO3 interfacial layer in Comparative Example 1 (no MoO3 group), and the ferroelectric capacitor with a crystalline MoO3 interfacial layer in Comparative Example 2 (c-MoO3 group). Use a ±1.5V, 2kHz triangular wave PUND read pulse to extract the polarization current and integrate to obtain the polarization intensity. As Figure 7 The results shown indicate that when extended to a retention time of 10 years, the positive and negative polarization states of the a-MoO3 group in Example 1 retained 98% and 94% of the polarization values respectively, significantly superior to the comparative example samples.

[0086] 3. Electric field cycling life test;

[0087] Use a ±1.5V, 1MHz square wave as the cycling pulse and the PUND scheme (±1.5V, 2kHz triangular wave) as the read pulse during the test. As Figure 8 The results shown display that after applying 10 12 cycles, the a-MoO3 group in Example 1 still retained approximately 90% of the window width, significantly superior to Comparative Example 1 (58%) and Comparative Example 2 (10%).

[0088] 4. Constant voltage operating life test;

[0089] The test evaluates the time-dependent dielectric breakdown characteristics of the device at different voltages by applying a constant voltage to the top electrode. According to the Weibull distribution fitting, extract the characteristic breakdown time T 63 when 63.2% of the devices fail, and extrapolate its long-term life using a power-law model.

[0090] As Figure 9 The results shown indicate that if aiming for a 10-year operating life, the a-MoO3 group in Example 1 can withstand an operating voltage of 2.44V, superior to Comparative Example 1 (2.13V) and Comparative Example 2 (2.25V).

[0091] In summary, the novel semiconductor non-volatile memory based on the amorphous MoO3 interface proposed by the present invention not only exhibits excellent ferroelectric properties but also has significantly improved long-term operating stability and reliability, providing strong technical support for practical applications.

[0092] In addition, the present invention can also be extended to the following application scenarios.

[0093] 1. Three-dimensional stacked non-volatile memory array.

[0094] Figure 10 shows Figure 1 the extended application structure of the novel semiconductor non-volatile memory of the present invention shown in []. The architecture uses a 2TnC cell array, that is, each column is vertically integrated by two transistors and n (2 - 100) novel semiconductor non-volatile memories proposed by the present invention to achieve high-density vertical stacked storage.

[0095] Figure 11 is the circuit principle corresponding to the three-dimensional stacked non-volatile memory array, showing its control and read mechanisms.

[0096] 2. Back-gate ferroelectric transistor.

[0097] Figure 12 gives a Figure 1 back-gate ferroelectric transistor structure constructed by the novel semiconductor non-volatile memory of the present invention shown in []. This structure uses Mo as the back-gate metal and optimizes the performance of the ferroelectric layer through the amorphous (a-MoO3) interface engineering process proposed by the present invention, thereby effectively improving the switching characteristics, threshold voltage regulation ability, and data retention characteristics of the device, providing a new solution for high-performance and low-power non-volatile devices.

Claims

1. A novel semiconductor non-volatile memory, characterized in that, It includes a substrate, a bottom electrode, an amorphous oxide interface layer, a ferroelectric dielectric layer, and a top electrode which are arranged successively from bottom to top; The material of the substrate is Si and SiO2; the material of the bottom electrode is Mo, the amorphous oxide interface layer is an amorphous MoO3 interface layer, and the ferroelectric dielectric layer is a hafnium-based ferroelectric material; the material of the top electrode includes but is not limited to Mo, TiN, W, and Pt; The ferroelectric dielectric layer is an HZO ferroelectric dielectric layer, and HfO2 and ZrO2 are deposited in a layer-by-layer stacking manner.

2. The novel semiconductor non-volatile memory according to claim 1, characterized in that, The thickness of the bottom electrode is 20 - 100 nm, the thickness of the ferroelectric dielectric layer is 5 - 10 nm, the thickness of the top electrode is 20 - 100 nm, and the thickness of the amorphous oxide interface layer is 1 - 2 nm.

3. The novel semiconductor non-volatile memory according to claim 1, characterized in that, The single-layer thickness of HfO2 and ZrO2 is 0.5 - 1 nm, and the molar ratio of HfO2 to ZrO2 is 1:

1.

4. A method for preparing the novel semiconductor non-volatile memory according to any one of claims 1-3, characterized in that, It includes the following steps: (1) Substrate cleaning; (2) Bottom electrode deposition; Deposit metal Mo as the bottom electrode on the substrate by physical vapor deposition, and control the thickness within 20 - 100 nm; (3) Forming an amorphous oxide interface layer; After the deposition of the Mo bottom electrode is completed, use atomic layer deposition technology to introduce an oxidizing gas for interface oxidation treatment; by controlling the oxidation time, temperature, and oxidant flow rate, induce the formation of an amorphous MoO3 interface layer with a thickness of 1 - 2 nm on the Mo surface; (4) Ferroelectric dielectric layer deposition; On the amorphous MoO3 interface layer, alternately deposit HfO2 layers and ZrO2 layers by atomic layer deposition technology according to a molar ratio of 1:1, with the thickness of each layer controlled within 0.5 - 1 nm and the total thickness controlled within 5 - 10 nm; (5) Top electrode patterning and deposition; Spin coat photoresist on the ferroelectric dielectric layer, complete pattern exposure and development by photolithography, then deposit the top electrode by physical vapor deposition, control the thickness within 20 - 100 nm, and finally complete electrode patterning by the Lift-off process; (6) Rapid thermal annealing treatment.

5. The manufacturing method of the novel semiconductor non-volatile memory according to claim 4, characterized in that, In the physical vapor deposition method deposition in step (2), it is deposited by magnetron sputtering technology, with the set sputtering power of 55 W, the working atmosphere of Ar, the flow rate of 3 sccm, and the deposition rate of 1 Å / s.

6. The manufacturing method of the novel semiconductor non-volatile memory according to claim 4, characterized in that, The rapid thermal annealing treatment in step (6) is carried out in a nitrogen atmosphere at 300 - 400 °C for 250 - 350 seconds.

7. Application of the novel semiconductor non-volatile memory according to any one of claims 1-3, characterized in that, It is used for three-dimensional stacked non-volatile memory arrays, and each column is vertically integrated by two transistors and n novel semiconductor non-volatile memories to achieve high-density vertical stacked storage.

8. The application of the novel semiconductor non-volatile memory according to any one of claims 1-3, characterized in that, It is used to construct a back-gate ferroelectric transistor structure.

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