A dual-gate structure and optimization method for high-performance MOSFET

Abstract

The present invention relates to the field of MOS semiconductor technology and discloses a dual-gate structure and optimization method for high-performance MOSFETs. The structure comprises a plurality of MOS cells, each of which includes a drain, a source, a gate, a gate oxide layer, and a semiconductor epitaxial layer; the semiconductor epitaxial layer includes an N substrate layer, an N diffusion layer, a P-layer, a P-well layer, and an N-well layer; a single MOS cell has two gates, which are located on the left and right sides of the gate oxide layer, respectively, and the cross-sectional profile of the gate oxide layer is semicircular; polysilicon is provided within the gate oxide layer and between the two gates, and the polysilicon is in ohmic contact with the source. Through the dual-gate structure, geometric shape optimization, doping layer design, and process innovation, the present invention significantly improves the switching speed, voltage resistance, thermal stability, and integration of the MOSFET, while reducing leakage current and on-resistance, making it suitable for high-performance power devices and high-frequency applications.

Description

Technical Field

[0001] The present invention relates to the technical field of MOS semiconductors, and in particular to a dual-gate structure for high-performance MOSFET and an optimization method thereof. Background Art

[0002] As semiconductor devices rapidly develop towards high performance and high integration, traditional single-gate MOSFETs are gradually exposing significant technical bottlenecks at the nanoscale. First, the short channel effect weakens the gate's ability to control the channel, causing increased leakage current and threshold voltage drift, which seriously restricts the miniaturization process of the device. Secondly, the electric field concentration phenomenon at the gate edge is significant under the single-gate structure, which can easily cause local breakdown, limiting the device's voltage resistance and reliability. In the prior art, although there have been attempts at multi-gate structures or doping optimization, they are often accompanied by problems such as high process complexity, increased manufacturing costs, and insufficient thermal stability. For example, complex multi-gate designs are difficult to be compatible with existing photolithography processes, and the optimization of the doping layer has limited effect on improving the electric field distribution. Therefore, there is an urgent need for a new MOSFET structure that is both high performance, high reliability, and process-friendly to break through the bottleneck of existing technologies.

[0003] An existing patent discloses a high-performance trench-gate SiC MOSFET device (publication number CN117766587A). The device comprises a semiconductor substrate, a buffer layer, a voltage-resistant layer, and a current-spreading layer, arranged sequentially on an ohmic drain contact electrode. Two trenches are provided within the voltage-resistant layer, each filled with a polysilicon gate. Electric field shielding regions are located at the bottom of each trench, and P-type interconnecting regions connected to the electric field shielding regions are alternately located between the trenches. Channels are located within the P-type interconnecting regions. The technology disclosed in this patent suffers from a narrow conductive path, high on-resistance, and insufficient current driving capability, making it difficult to meet the requirements of high-frequency and high-power applications. Summary of the Invention

[0004] In order to solve the existing technical problems, the present invention provides a dual-gate structure and an optimization method for high-performance MOSFET, which solves the problems in the above-mentioned background technology.

[0005] To solve the above technical problems, according to one aspect of the present invention, more specifically, a dual-gate structure for high-performance MOSFET is provided, comprising a plurality of MOS cells, wherein a single MOS cell includes a drain, a source, a gate, a gate oxide layer, and a semiconductor epitaxial layer; the semiconductor epitaxial layer includes an N substrate layer, an N diffusion layer, a P-layer, a P-well layer, and an N-well layer; a single MOS cell has two gates, which are respectively located on the left and right sides of the gate oxide layer.

[0006] Furthermore, the cross-sectional profile of the gate oxide layer is semicircular; polysilicon is provided inside the gate oxide layer and between the two gates, and the polysilicon is in ohmic contact with the source electrode;

[0007] The cross-sectional depth of the polysilicon is twice the cross-sectional depth of the gate. times.

[0008] Furthermore, the polysilicon further includes a side silicon layer, and the cross-sectional profile of the side silicon layer is thick at the bottom and narrow at the top.

[0009] Furthermore, the middle of the side silicon layer is filled with a high-resistance doped layer, wherein the high-resistance doped layer divides the side silicon layer into two parts, a left part and a right part.

[0010] Furthermore, the cross-sectional profile of the gate oxide layer is rectangular; the two gates further comprise rectangular gates;

[0011] Rectangular silicon is provided inside the gate oxide layer and between the two rectangular gates. The cross-sectional depth of the rectangular silicon is the same as that of the rectangular gates.

[0012] Furthermore, the N diffusion layer further includes a low-doped N-layer, wherein the low-doped N-layer is located between the N substrate layer and the gate oxide layer.

[0013] An optimization method for a high-performance MOSFET dual-gate structure, specifically comprising:

[0014] S1. Using an N-type substrate layer as a base, an N-diffusion layer and a low-doped N-layer are formed by epitaxial growth;

[0015] S2, sequentially depositing a P-layer, a P-well layer, and an N-well layer on the N-diffusion layer to form a multi-layer doping structure;

[0016] S3, forming a gate oxide layer on the surface of the semiconductor epitaxial layer by chemical vapor deposition;

[0017] S4. Deposit polysilicon on both sides of the gate oxide layer to form two gates on the left and right. Fill the space between the two gates with polysilicon and adjust its doping concentration by ion implantation to ensure that the depth of the polysilicon is 1 / 4 of the gate depth. times;

[0018] S5. forming side silicon layers on both sides of the polysilicon, and using tilted ion implantation to achieve a profile shape in which the side silicon layers are thick at the bottom and narrow at the top;

[0019] S6, implanting a high-resistance doped layer into the middle region of the side silicon layer to divide the side silicon layer into two parts, left and right;

[0020] S7. Forming source and drain electrode contacts through a metallization process.

[0021] Furthermore, in step S5, by optimizing the tilted ion implantation angle, , thereby controlling the ratio of the bottom width to the top narrow area of the side silicon layer.

[0022] Furthermore, in step S6, a low-doped N-layer may be introduced between the N diffusion layer and the gate oxide layer, wherein the doping concentration of the low-doped N-layer is lower than that of the N diffusion layer. orders of magnitude.

[0023] The present invention provides a dual-gate structure and optimization method for high-performance MOSFETs. Compared with the prior art, this method achieves the following results:

[0024] 1. This invention significantly improves the switching speed, voltage resistance, thermal stability and integration of MOSFET through dual-gate structure, geometry optimization, doping layer design and process innovation, while reducing leakage current and on-resistance, making it suitable for high-performance power devices and high-frequency application scenarios.

[0025] 2. The present invention jointly regulates the channel through the left and right gates to enhance the control over carriers. This can shorten the channel opening / closing time through the synergistic effect of the dual gates, and the superposition of the dual gate electric fields suppresses subthreshold leakage. The more uniform electric field distribution reduces the impact of the short channel effect.

[0026] 3. The present invention uses this semicircular structure to disperse the electric field to increase the breakdown voltage, reduce the electric field concentration at the gate edge, and enhance the current driving capability. In addition, the ohmic contact between the polysilicon and the source can reduce the contact resistance heating.

[0027] 4. Since the rectangular structure of the present invention matches the existing photolithography process, it can simplify the manufacturing process of the rectangular gate and silicon filling, and the rectangular silicon and the gate have the same depth, ensuring the uniformity of the electric field and the stability of the threshold voltage.

[0028] 5. The present invention introduces a low-doped N-layer between the N substrate and the gate oxide layer, thereby allowing the low-doped N-layer to form a buffer and reduce leakage between the N substrate layer and the gate oxide layer. The structure also optimizes the electric field gradient, enhances the breakdown voltage of the device, and reduces parasitic capacitance to improve the high-frequency response speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 This is a schematic structural diagram of Example 1 of the present invention;

[0030] Figure 2 This is a schematic structural diagram of Example 2 of the present invention;

[0031] Figure 3 This is a schematic structural diagram of Example 3 of the present invention;

[0032] Figure 4 This is a schematic structural diagram of Embodiment 4 of the present invention;

[0033] Figure 5 This is a schematic structural diagram of Embodiment 5 of the present invention;

[0034] Figure 6 This is a comparison diagram of the current density of the dual-gate structure in the present invention and the traditional single-gate structure.

[0035] In the figure: 1. Drain; 2. Source; 3. Gate; 4. Gate oxide layer; 5. N substrate layer; 6. N diffusion layer; 7. P-layer; 8. P well layer; 9. N well layer; 10. Polysilicon; 11. High-resistance doped layer; 101. Side silicon layer; 102. Rectangular silicon; 31. Rectangular gate; 61. Low-doped N-layer. DETAILED DESCRIPTION

[0036] In order to make the technical solution of the present invention clearer, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0037] like Figure 1-5 As shown, an optimization method for a high-performance MOSFET dual-gate structure specifically includes:

[0038] Step 1: Using the N-type substrate layer 5 as the base, an N diffusion layer 6 and a low-doped N-layer 61 are formed by epitaxial growth. This step precisely controls the doping concentration gradient through epitaxial growth to form a low-defect semiconductor layer, providing an electrical performance foundation for subsequent structures.

[0039] Step 2: depositing a P-layer 7, a P-well layer 8 and an N-well layer 9 in sequence on the N-diffusion layer to form a multi-layer doping structure.

[0040] Step 3: forming a gate oxide layer 4 on the surface of the semiconductor epitaxial layer by chemical vapor deposition.

[0041] Step 4: Deposit polysilicon on both sides of the gate oxide layer 4 to form two left and right gates 3, fill polysilicon 10 between the two gates 3, and adjust its doping concentration through ion implantation to ensure that the depth of the polysilicon 10 is 1.2-1.7 times the depth of the gate. This method of adjusting the polysilicon doping concentration through ion implantation to ensure that the depth is 1.2-1.7 times the depth of the gate 3 can optimize the conductive path, reduce the on-resistance, and avoid short circuits between the gates 3.

[0042] Step 5: Form side silicon layers 101 on both sides of the polysilicon 10, and use tilted ion implantation to achieve a profile shape of the side silicon layer 101 that is thick at the bottom and narrow at the top. In this step, the tilted ion implantation angle is optimized to be between 30° and 60°, thereby controlling the ratio of the bottom width and the top narrow area of the side silicon layer 101. The tilted angle controls the implantation depth and distribution, forming a profile that is thick at the bottom and narrow at the top, thereby enhancing the uniformity of current distribution and reducing the risk of local overheating.

[0043] Step 6: A high-resistance doped layer 11 is implanted in the middle region of the side silicon layer 101 to divide the side silicon layer 101 into left and right parts. In this step, a low-doped N-layer 61 can also be introduced between the N-diffusion layer 6 and the gate oxide layer 4. The doping concentration of the low-doped N-layer 61 is 1-2 orders of magnitude lower than that of the N-diffusion layer 6. The high-resistance region is formed through selective ion implantation, isolating the left and right current paths, suppressing crosstalk and parasitic capacitance, and improving high-frequency performance.

[0044] Step 7: Form electrode contacts between source 2 and drain 1 through a metallization process. The metallization process forms low-resistance metal electrodes through evaporation, reducing contact resistance and improving overall device efficiency and power handling capabilities.

[0045] Example 1

[0046] like Figure 1 As shown, according to one aspect of the present invention, a dual-gate structure for a high-performance MOSFET is provided, comprising a plurality of MOS cells. A single MOS cell includes a drain 1, a source 2, a gate 3, a gate oxide layer 4, and a semiconductor epitaxial layer. The semiconductor epitaxial layer includes an N substrate layer 5, an N diffusion layer 6, a P-layer 7, a P well layer 8, and an N well layer 9. A single MOS cell has two gates 3, located on the left and right sides of the gate oxide layer 4. The left and right gates 3 jointly regulate the channel, enhancing the ability to control carriers. This allows the synergistic effect of the dual gates to shorten the channel turn-on / off time, and the dual-gate electric field superposition suppresses subthreshold leakage. The more uniform electric field distribution reduces the impact of the short channel effect.

[0047] Example 2

[0048] like Figure 2 、 6As shown, the cross-sectional profile of the gate oxide layer 4 is semicircular; polysilicon 10 is provided inside the gate oxide layer 4 and between the two gates 3, and the polysilicon 10 is in ohmic contact with the source 2; the cross-sectional depth of the polysilicon 10 is 1.2-1.7 times the cross-sectional depth of the two gates 3. In this embodiment, the electric field distribution is optimized by the semicircular gate oxide layer 4, and the conductivity is enhanced by controlling the depth of the polysilicon 10. This semicircular structure disperses the electric field, increases the breakdown voltage, and reduces the electric field concentration at the gate edge; and the depth of the polysilicon 10 (1.2-1.7 times the depth of the gate 3) expands the conductive path (such as Figure 6 As shown), the current driving capability is improved, and the 2-ohm contact between the polysilicon 10 and the source can reduce the contact resistance heat.

[0049] Example 3

[0050] like Figure 3 As shown, the polysilicon 10 also includes a side silicon layer 101, and the cross-sectional profile of the side silicon layer 101 is thick at the bottom and narrow at the top. The middle of the side silicon layer 101 is filled with a high-resistance doped layer 11, wherein the high-resistance doped layer 11 divides the side silicon layer 101 into two parts, left and right. The thick bottom and narrow top profile of the side silicon layer 101 is combined with the high-resistance doped layer 11 to adjust the current path, and the shape of the side silicon layer 101 can reduce the local current density and reduce the hot spot effect; the side silicon layer 101 is divided by the high-resistance doped layer 11, thereby suppressing parasitic capacitance and leakage.

[0051] Example 4

[0052] like Figure 4 As shown, the cross-sectional profile of the gate oxide layer 4 is rectangular; the two gates 3 also include a rectangular gate 31; a rectangular silicon 102 is provided inside the gate oxide layer 4 and between the two rectangular gates 31. The cross-sectional depth of the rectangular silicon 102 is the same as that of the rectangular gate 31. The rectangular gate 31 and the silicon filling simplify the manufacturing process because the rectangular structure matches the existing photolithography process, reducing manufacturing costs. The rectangular silicon 102 is the same depth as the gate 3, ensuring electric field uniformity and threshold voltage stability. In addition, this regular structure facilitates the arrangement of cell arrays and improves device density.

[0053] Example 5

[0054] like Figure 5 As shown, the N-diffusion layer 6 also includes a low-doped N-layer 61, which is located between the N substrate layer 5 and the gate oxide layer 4. The low-doped N-layer 61 is introduced between the N substrate 5 and the gate oxide layer 4 to form a buffer, reducing leakage between the N substrate layer 5 and the gate oxide layer 4. This structure also optimizes the electric field gradient, enhances the device's breakdown voltage, reduces parasitic capacitance, and improves high-frequency response speed.

[0055] The above-described embodiments merely illustrate several implementations of the present invention, and while their descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A dual-gate structure for MOSFET, comprising a plurality of MOS cells, wherein each MOS cell comprises a drain (1), a source (2), a gate (3), a gate oxide layer (4), and a semiconductor epitaxial layer; the semiconductor epitaxial layer comprises an N substrate layer (5), an N diffusion layer (6), a P-layer (7), a P well layer (8), and an N well layer (9), characterized in that: There are two gates (3) in a single MOS cell, and they are located on the left and right sides of the gate oxide layer (4) respectively; The cross-sectional profile of the gate oxide layer (4) is semicircular; polysilicon (10) is provided inside the gate oxide layer (4) and between the two gate electrodes (3); the polysilicon (10) is in ohmic contact with the source electrode (2); The cross-sectional depth of the polysilicon (10) is 1.2-1.7 times the cross-sectional depth of the two gate electrodes (3); The polysilicon (10) further comprises a side silicon layer (101), and the cross-sectional profile of the side silicon layer (101) is in a shape of being thick at the bottom and narrow at the top; The middle of the side silicon layer (101) is filled with a high-resistance doping layer (11), wherein the high-resistance doping layer (11) divides the side silicon layer (101) into two parts, a left part and a right part.

2. The dual-gate structure for MOSFET according to claim 1, wherein: The cross-sectional profile of the gate oxide layer (4) is rectangular; the two gate electrodes (3) further include rectangular gate electrodes (31); A rectangular silicon (102) is provided inside the gate oxide layer (4) and between the two rectangular gates (31); the cross-sectional depth of the rectangular silicon (102) is the same as the cross-sectional depth of the rectangular gates (31).

3. The dual-gate structure for MOSFET according to claim 2, wherein: The N diffusion layer (6) further includes a low-doped N-layer (61), wherein the low-doped N-layer (61) is located between the N substrate layer (5) and the gate oxide layer (4).

4. A method for manufacturing a MOSFET dual-gate structure, characterized in that: Applied to the dual-gate structure according to any one of claims 1 to 3, the manufacturing method specifically comprises: S1, using an N substrate layer (5) as a base, forming an N diffusion layer (6) and a low-doped N-layer (61) by epitaxial growth; S2, sequentially depositing a P-layer (7), a P-well layer (8) and an N-well layer (9) on the N-diffusion layer to form a multi-layer doping structure; S3, forming a gate oxide layer (4) on the surface of the semiconductor epitaxial layer by chemical vapor deposition; S4, depositing polysilicon on both sides of the gate oxide layer (4) to form two left and right gates (3), filling polysilicon (10) between the two gates (3), and adjusting the doping concentration thereof by ion implantation to ensure that the depth of the polysilicon (10) is 1.2-1.7 times the depth of the gate; S5, forming side silicon layers (101) on both sides of the polysilicon (10), and using inclined ion implantation to achieve a profile shape of the side silicon layers (101) with a thick bottom and a narrow top; S6, implanting a high-resistance doped layer (11) into the middle region of the side silicon layer (101) to divide the side silicon layer (101) into two parts, left and right; S7. Forming electrode contacts of the source (2) and the drain (1) through a metallization process.

5. The method for manufacturing a MOSFET dual-gate structure according to claim 4, wherein: In the step S5, the ratio of the bottom width to the top narrow area of the side silicon layer (101) is controlled by optimizing the tilted ion implantation angle to be between 30° and 60°.

6. The method for manufacturing a MOSFET dual-gate structure according to claim 4, wherein: In step S6, a low-doped N-layer (61) may be introduced between the N diffusion layer (6) and the gate oxide layer (4), wherein the doping concentration of the low-doped N-layer (61) is 1-2 orders of magnitude lower than that of the N diffusion layer (6).

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