Array substrate, manufacturing method thereof and display panel

Abstract

The invention belongs to the field of display, and particularly relates to an array substrate and a manufacturing method thereof and a display panel, the manufacturing method of the array substrate comprises the steps that a pixel electrode, a grid electrode, a grid electrode insulating layer, an active layer, a source-drain electrode and a passivation layer are formed on one side of a substrate, the source-drain electrode comprises a source electrode and a drain electrode which are arranged at intervals, the passivation layer and the grid electrode insulating layer are patterned, and the active layer is formed on the other side of the substrate; a via hole communicating the drain electrode and the pixel electrode is formed, a liquid coating agent is poured into the via hole, the liquid coating agent at least covers the lower surface, close to the substrate, of the drain electrode, the liquid coating agent comprises a film forming material and a carrier material, and the carrier material is evaporated to form a conductive layer connecting the drain electrode and the pixel electrode. Due to the fact that the area, below the drain electrode, in the via hole can be filled with the liquid coating agent with fluidity, after the carrier material is evaporated, the film forming material can be evenly attached to the inner surface of the via hole to form the conducting layer regardless of the shape of the via hole, and therefore poor contact between the drain electrode and the pixel electrode is avoided, and the yield of the array substrate is improved.

Description

Technical Field

[0001] This application belongs to the field of display, and particularly relates to an array substrate, a manufacturing method thereof, and a display panel. Background Art

[0002] With the development of display technology, thin film transistor liquid crystal display panels (TFT-LCDs) have been widely used in various consumer electronic products such as mobile phones, TVs, computer monitors, and laptop computers due to their advantages of high picture quality, power saving, thin body, and mature and stable manufacturing processes, and have become the mainstream in display panels.

[0003] A display panel includes an array substrate, and the array substrate includes a substrate and a pixel electrode, a gate insulating layer, and a thin film transistor formed on the substrate. The thin film transistor includes a gate, an active layer, and source / drain electrodes. The pixel electrode and the gate are located on one side of the gate insulating layer close to the substrate, and the source / drain electrodes are located on one side of the gate insulating layer far from the substrate. The source / drain electrodes are connected to the pixel electrode.

[0004] In the prior art, when etching a via hole connecting the source / drain electrodes and the pixel electrode, lateral etching is likely to occur, that is, a part of the gate insulating layer under the source / drain electrodes is undesirably etched, and a taper is formed under the source / drain electrodes. When depositing a conductive material in the via hole to connect the source / drain electrodes and the pixel electrode, poor contact or even disconnection is likely to occur, resulting in a decrease in the yield of the display panel. Summary of the Invention

[0005] The purpose of this application is to provide an array substrate, a manufacturing method thereof, and a display panel to improve the reliability of the connection between the source / drain electrodes and the pixel electrode, and thus improve the yield of the display panel.

[0006] To achieve the above purpose, this application provides an array substrate, including a substrate, and the array substrate further includes:

[0007] A pixel electrode formed on one side of the substrate;

[0008] A gate formed on one side of the substrate, and the pixel electrode and the gate are arranged at intervals;

[0009] A gate insulating layer formed on one side of the substrate and covering the pixel electrode and the gate;

[0010] An active layer formed on one side of the gate insulating layer far from the substrate, and an orthographic projection of the active layer on the substrate overlaps with an orthographic projection of the gate on the substrate;

[0011] A source-drain electrode is formed on a side of the active layer away from the substrate, and the source-drain electrode includes a source electrode and a drain electrode that are spaced apart.

[0012] A passivation layer is formed on a side of the gate insulating layer away from the substrate and covers the active layer and the source-drain electrode. A via hole is formed in the passivation layer and extends to the pixel electrode, and at least a part of the drain electrode is located in the via hole.

[0013] A conductive layer is at least formed on a part of the inner surface of the via hole and connects the drain electrode and the pixel electrode.

[0014] Optionally, a chamfer is formed between a part of the gate insulating layer on a side of the drain electrode close to the substrate and the drain electrode.

[0015] Optionally, the inner wall of the via hole is divided into a hole bottom surface, a first hole side wall, and a second hole side wall along the thickness direction of the passivation layer and the gate insulating layer. The distance between one end of the first hole side wall away from the substrate and the substrate is H1, and the distance between the upper surface of the drain electrode away from the substrate and the substrate is H2, where H1 > H2, and the conductive layer covers the hole bottom surface and the first hole side wall of the via hole.

[0016] Optionally, the manufacturing material of the conductive layer includes gold, silver, copper, aluminum, and their alloys.

[0017] Optionally, the array substrate further includes a planarization layer and a common electrode. The planarization layer is formed on a side of the passivation layer away from the substrate, and a part of the planarization layer fills the via hole to form a filling body. The conductive layer is located between the filling body and the inner wall of the via hole, and the common electrode is located on a side of the planarization layer away from the substrate.

[0018] The present application also provides a manufacturing method of an array substrate, including:

[0019] Forming a pixel electrode, a gate electrode, a gate insulating layer, an active layer, a source-drain electrode, and a passivation layer on one side of a substrate. The pixel electrode and the gate electrode are spaced apart. The gate insulating layer is located on one side of the substrate and covers the pixel electrode and the gate electrode. The active layer is located on a side of the gate insulating layer away from the substrate. The orthographic projection of the active layer on the substrate overlaps with the orthographic projection of the gate electrode on the substrate. The source-drain electrode is located on a side of the active layer away from the substrate, and the source-drain electrode includes a source electrode and a drain electrode that are spaced apart. The passivation layer is located on a side of the gate insulating layer away from the substrate and covers the active layer and the source-drain electrode.

[0020] Pattern the passivation layer and the gate insulating layer to form a via hole connecting the drain and the pixel electrode;

[0021] Infuse a liquid coating agent into the via hole, where the liquid coating agent covers at least the lower surface of the drain close to the substrate, and the liquid coating agent includes a film-forming material and a carrier material, and the evaporation temperature of the carrier material is less than the evaporation temperature of the film-forming material;

[0022] Heat the liquid coating agent to evaporate the carrier material, so that the film-forming material adheres to the inner surface of the via hole to form a conductive layer, and the conductive layer connects the drain and the pixel electrode.

[0023] Optionally, the carrier material includes mercury, and the film-forming material includes gold, silver, copper, aluminum and their alloys.

[0024] Optionally, before infusing the liquid coating agent, the manufacturing method of the array substrate further includes:

[0025] Etch the inner wall of the via hole to make the inner wall of the via hole uneven; or

[0026] Form a contact layer on the inner wall of the via hole, and the contact layer is used to improve the adhesion between the conductive layer and the drain, the pixel electrode, the passivation layer, the active layer and the gate insulating layer.

[0027] Optionally, the infusion amount of the liquid coating agent is less than the volume of the via hole, and the liquid coating agent covers the upper surface of the drain away from the substrate.

[0028] This application also provides a display panel, including:

[0029] The array substrate;

[0030] A counter substrate, which is arranged opposite to the array substrate;

[0031] A liquid crystal layer, which is arranged between the array substrate and the counter substrate.

[0032] The array substrate, its manufacturing method, and the display panel disclosed in this application have the following beneficial effects:

[0033] In this application, a pixel electrode, a gate electrode, a gate insulating layer, an active layer, source-drain electrodes, and a passivation layer are formed on one side of a substrate. The source-drain electrodes include a source electrode and a drain electrode arranged at intervals. The passivation layer and the gate insulating layer are patterned to form a via connecting the drain electrode and the pixel electrode. A liquid coating agent is poured into the via. The liquid coating agent covers at least the lower surface of the drain electrode close to the substrate. The liquid coating agent includes a film-forming material and a carrier material, and the evaporation temperature of the carrier material is lower than that of the film-forming material. The liquid coating agent is heated to evaporate the carrier material, so that the film-forming material adheres to the inner surface of the via to form a conductive layer, and the conductive layer connects the drain electrode and the pixel electrode. Since the liquid coating agent with fluidity can fill the area under the drain electrode in the via, after evaporating the carrier material, the film-forming material can uniformly adhere to the inner surface of the via regardless of the shape of the via to form a conductive layer, thereby avoiding poor contact between the drain electrode and the pixel electrode and improving the yield of the array substrate.

[0034] Other features and advantages of the present application will become apparent from the following detailed description, or will be learned in part from the practice of the present application.

[0035] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, showing embodiments consistent with the present application, and are used together with the specification to explain the principles of the present application. Obviously, the accompanying drawings in the following description are only some embodiments of the present application, and those of ordinary skill in the art can obtain other drawings based on these drawings without creative efforts.

[0037] Figure 1 is a flowchart of a method for manufacturing an array substrate in Embodiment 1 of the present application.

[0038] Figure 2 is a schematic structural diagram of an array substrate in Embodiment 1 of the present application.

[0039] Figure 3 is a schematic diagram of forming a via on a passivation layer and a gate insulating layer in Embodiment 1 of the present application.

[0040] Figure 4 is a schematic diagram of pouring a liquid coating agent into a via in Embodiment 1 of the present application.

[0041] Figure 5 is a schematic diagram of evaporating a carrier material to form a conductive layer in Embodiment 1 of the present application.

[0042] Figure 6 is a schematic structural diagram of an array substrate in Embodiment 2 of the present application.

[0043] Figure 7 It is a schematic structural diagram of a display panel in Embodiment 3 of the present application.

[0044] Explanation of reference numerals:

[0045] 100, array substrate; 101, via hole; 1011, bottom surface of the hole; 1012, first sidewall of the hole; 1013, second sidewall of the hole; 110, substrate; 120, pixel electrode; 130, gate; 140, gate insulating layer; 150, active layer; 160, source-drain electrode; 161, source; 162, drain; 170, passivation layer; 180, conductive layer; 190, planarization layer; 191, filling body

[0046] 200, counter substrate; 300, liquid crystal layer. Detailed implementation manners

[0047] Now, example embodiments will be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this application will be more thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art.

[0048] In addition, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of the embodiments of the present application. However, those skilled in the art will realize that the technical solutions of the present application can be practiced without one or more of the specific details, or other methods, components, devices, steps, etc. can be adopted. In other cases, well-known methods, devices, implementations, or operations are not shown or described in detail to avoid obscuring aspects of the present application.

[0049] The present application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted here that the technical features involved in the various embodiments of the present application described below can be combined with each other as long as they do not conflict with each other. The embodiments described below by referring to the accompanying drawings are exemplary and are intended to explain the present application and should not be construed as limiting the present application.

[0050] Embodiment 1

[0051] See Figures 1 to 5 As shown, the manufacturing method of the array substrate 100 in this embodiment includes steps S100 to S400.

[0052] S100: On one side of the substrate 110, a pixel electrode 120, a gate 130, a gate insulating layer 140, an active layer 150, source-drain electrodes 160, and a passivation layer 170 are formed. The pixel electrode 120 and the gate 130 are arranged at intervals. The gate insulating layer 140 is located on one side of the substrate 110 and covers the pixel electrode 120 and the gate 130. The active layer 150 is located on the side of the gate insulating layer 140 away from the substrate 110. The orthographic projection of the active layer 150 on the substrate 110 overlaps with the orthographic projection of the gate 130 on the substrate 110. The source-drain electrodes 160 are located on the side of the active layer 150 away from the substrate 110. The source-drain electrodes 160 include a source electrode 161 and a drain electrode 162 arranged at intervals. The passivation layer 170 is located on the side of the gate insulating layer 140 away from the substrate 110 and covers the active layer 150 and the source-drain electrodes 160.

[0053] The substrate 110 can be a glass substrate or a transparent flexible substrate. The pixel electrode 120 can be made of a transparent conductive material, such as indium tin oxide (ITO). The gate 130 can be made of a metal material. The pixel electrode 120 and the gate 130 can be formed using the same photomask. For example, a transparent conductive material layer and a first metal material layer are sequentially formed on the substrate 110, and the patterned transparent conductive material layer and the first metal material layer are formed using the same photomask to form the pixel electrode 120 and the gate 130. There is a transparent conductive material between the gate 130 and the substrate 110.

[0054] The material for making the gate insulating layer 140 includes silicon dioxide (SiO 2 ), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), and hafnium oxide (HfO), etc.; the material for making the passivation layer 170 includes silicon dioxide, silicon nitride, and silicon oxynitride, etc. The active layer 150 can be made of a semiconductor material, and the source-drain electrodes 160 can be made of a metal material. The active layer 150 and the source-drain electrodes 160 can be formed using the same photomask. For example, a semiconductor material layer and a second metal material layer are sequentially formed on the gate insulating layer 140, and the patterned semiconductor material layer and the second metal material layer are formed using the same photomask to form the active layer 150 and the source-drain electrodes 160.

[0055] S200: Pattern the passivation layer 170 and the gate insulating layer 140 to form a via 101 connecting the drain electrode 162 and the pixel electrode 120.

[0056] The via 101 can be formed by dry etching. Inside the via 101, the area of the drain 162 and the area of the pixel electrode 120 each approximately account for half. That is, the overlapping area of the orthographic projection of the drain 162 on the substrate 110 and the orthographic projection of the via 101 on the substrate 110 approximately accounts for half of the area of the orthographic projection of the via 101 on the substrate 110, and the overlapping area of the orthographic projection of the pixel electrode 120 on the substrate 110 and the orthographic projection of the via 101 on the substrate 110 approximately accounts for half of the area of the orthographic projection of the via 101 on the substrate 110. Therefore, the via 101 is also called a half via.

[0057] S300: Pour the liquid coating agent 400 into the via 101. The liquid coating agent 400 at least covers the lower surface of the drain 162 close to the substrate 110. The liquid coating agent 400 includes a film-forming material and a carrier material, and the evaporation temperature of the carrier material is less than the evaporation temperature of the film-forming material.

[0058] The process of pouring the liquid coating agent 400 can adopt processes such as dropping and inkjet printing. The film-forming material is solid at room temperature, and the film-forming material is a conductor material. The carrier material is solid at room temperature, and the liquid coating agent 400 is a mixture of the carrier material and the film-forming material.

[0059] S400: Heat the liquid coating agent 400 to evaporate the carrier material, so that the film-forming material adheres to the inner surface of the via 101 to form a conductive layer 180, and the conductive layer 180 connects the drain 162 and the pixel electrode 120.

[0060] Since the evaporation temperature of the carrier material is less than the evaporation temperature of the film-forming material, by heating the liquid coating agent 400, the carrier material can be evaporated, and the film-forming material adheres to the inner surface of the via 101 to form a conductive layer 180. The conductive layer 180 conducts electricity to connect the drain 162 and the pixel electrode 120. It should be understood that the carrier material is selected as a material that is easy to evaporate, and the evaporation temperature of the carrier material should be at least lower than the temperature that the array substrate 100 can withstand.

[0061] It should be noted that the array substrate 100 may further include film layers such as a planarization layer 190 and a common electrode. The manufacturing method of the array substrate 100 may further include steps of forming the planarization layer 190 on the side of the passivation layer 170 away from the substrate 110, and forming the common electrode on the side of the planarization layer 190 away from the substrate 110.

[0062] The via 101 is formed by dry etching. Due to the limitations of the via 101 formation process, when etching the via 101 connecting the source-drain electrode 160 and the pixel electrode 120, lateral etching is likely to occur, that is, a part of the gate insulating layer 140 under the source-drain electrode 160 is undesirably etched, forming an inverted slope angle under the source-drain electrode 160. Due to the shielding of the source-drain electrode 160, when depositing a conductive material in the via 101 to connect the source-drain electrode 160 and the pixel electrode 120, it is difficult for the conductive material to be deposited in the inverted slope angle area, and poor contact or even disconnection is likely to occur, resulting in a decrease in the yield of the display panel.

[0063] In this embodiment, a pixel electrode 120, a gate 130, a gate insulating layer 140, an active layer 150, a source-drain electrode 160, and a passivation layer 170 are formed on one side of the substrate 110. The source-drain electrode 160 includes a source electrode 161 and a drain electrode 162 arranged at intervals. The passivation layer 170 and the gate insulating layer 140 are patterned to form a via 101 connecting the drain electrode 162 and the pixel electrode 120. A liquid coating agent 400 is poured into the via 101. The liquid coating agent 400 at least covers the lower surface of the drain electrode 162 close to the substrate 110. The liquid coating agent 400 includes a film-forming material and a carrier material. The evaporation temperature of the carrier material is lower than that of the film-forming material. The liquid coating agent 400 is heated to evaporate the carrier material, and the film-forming material adheres to the inner surface of the via 101 to form a conductive layer 180. The conductive layer 180 connects the drain electrode 162 and the pixel electrode 120. Since the liquid coating agent 400 with fluidity can fill the area under the drain electrode 162 in the via 101, after evaporating the carrier material, the film-forming material can uniformly adhere to the inner surface of the via 101 regardless of the shape of the via 101 to form the conductive layer 180, thereby avoiding poor contact between the drain electrode 162 and the pixel electrode 120 and improving the yield of the array substrate 100.

[0064] In some embodiments, the carrier material includes mercury, and the film-forming material includes gold, silver, copper, aluminum, and their alloys. Mercury has a low boiling point (about 357 °C) and is easy to volatilize. Using mercury as the carrier material, rapid evaporation of mercury can be achieved without heating to the boiling point. The film-forming material includes gold, silver, copper, aluminum, and their alloys. Gold, silver, copper, aluminum, and their alloys have excellent ductility and conductivity. The conductive layer 180 formed by gold, silver, copper, aluminum, and their alloys has low impedance, which is beneficial to improving the performance of the array substrate 100. In addition, the mixture formed by dissolving gold, silver, copper, aluminum, and their alloys in mercury is liquid and has strong fluidity.

[0065] It should be noted that the carrier material is not limited to mercury, and the film-forming material is not limited to gold, silver, copper, aluminum, and their alloys. The liquid coating agent 400 can also use other carrier materials and film-forming materials that are liquid after mixing.

[0066] The carrier material is mercury. The carrier material is cheap and easy to obtain, which is beneficial to reducing the manufacturing cost of the array substrate 100.

[0067] In some embodiments, the filling amount of the liquid coating agent 400 is less than the volume of the via 101, and the liquid coating agent 400 covers the upper surface of the drain 162 away from the substrate 110. After the carrier material is evaporated to form the conductive layer 180, the distance between the upper surface of the conductive layer 180 and the substrate 110 is H1, and the distance between the upper surface of the drain 162 away from the substrate 110 and the substrate 110 is H2, and H1 > H2.

[0068] The filling amount of the liquid coating agent 400 is less than the volume of the via 101, which can prevent the conductive liquid coating agent 400 from flowing out of the via 101 and causing short circuits in other areas of the array substrate 100. The liquid coating agent 400 covers the upper surface of the drain 162 away from the substrate 110, and the distance between the upper surface of the conductive layer 180 and the substrate 110 is greater than the distance between the upper surface of the drain 162 and the substrate 110, which can prevent poor contact between the drain 162 and the pixel electrode 120.

[0069] In some embodiments, before filling the liquid coating agent 400, the manufacturing method of the array substrate 100 further includes:

[0070] Etching the inner wall of the via 101 to make the inner wall of the via 101 uneven.

[0071] The inner wall of the via 101 is surrounded by the passivation layer 170, the gate insulating layer 140, the drain 162, the active layer 150 and the pixel electrode 120. The material used to etch the inner wall of the via 101 can simultaneously etch the passivation layer 170, the gate insulating layer 140, the drain 162, the active layer 150 and the pixel electrode 120.

[0072] Etching the inner wall of the via 101 can increase the roughness of the inner wall of the via 101, improve the adhesion between the conductive layer 180 and the inner wall of the via 101, and prevent poor contact between the drain 162 and the pixel electrode 120 caused by the peeling of the conductive layer 180.

[0073] In some embodiments, before filling the liquid coating agent 400, the manufacturing method of the array substrate 100 further includes:

[0074] Forming a contact layer on the inner wall of the via 101, and the contact layer is used to improve the adhesion between the conductive layer 180 and the drain 162, the pixel electrode 120, the passivation layer 170, the active layer 150 and the gate insulating layer 140.

[0075] A contact layer is formed on the inner wall of the via 101 to improve the adhesion between the conductive layer 180 and the inner wall of the via 101, which can prevent poor contact between the drain electrode 162 and the pixel electrode 120 caused by the peeling of the conductive layer 180.

[0076] It should be noted that to improve the adhesion between the conductive layer 180 and the inner wall of the via 101, the method of etching the inner wall of the via 101 can be used, or the method of forming a contact layer on the inner wall of the via 101 can be used, or both methods can be used simultaneously, depending on the specific situation. Before etching the via 101 or forming a contact layer on the inner wall of the via 101, the inner surface of the via 101 can be cleaned, and after etching the via 101 or forming a contact layer on the inner wall of the via 101, the inner surface of the via 101 can be cleaned again.

[0077] Embodiment 2

[0078] In this embodiment, the array substrate 100 is fabricated by using the fabrication method of the array substrate 100 disclosed in Embodiment 1. Refer to Figure 5 and Figure 6 As shown, the array substrate 100 includes a substrate 110, a pixel electrode 120, a gate 130, a gate insulating layer 140, an active layer 150, source-drain electrodes 160, a passivation layer 170, and a conductive layer 180.

[0079] The pixel electrode 120 is formed on one side of the substrate 110, the gate 130 is formed on one side of the substrate 110, and the pixel electrode 120 and the gate 130 are arranged at intervals. The gate insulating layer 140 is formed on one side of the substrate 110 and covers the pixel electrode 120 and the gate 130. The active layer 150 is formed on the side of the gate insulating layer 140 away from the substrate 110, and the orthographic projection of the active layer 150 on the substrate 110 overlaps with the orthographic projection of the gate 130 on the substrate 110. The source-drain electrodes 160 are formed on the side of the active layer 150 away from the substrate 110, and the source-drain electrodes 160 include a source electrode 161 and a drain electrode 162 arranged at intervals. The gate 130, the active layer 150, the source electrode 161, and the drain electrode 162 form a thin film transistor.

[0080] The passivation layer 170 is formed on the side of the gate insulating layer 140 away from the substrate 110 and covers the active layer 150 and the source-drain electrodes 160. A via 101 is formed in the passivation layer 170 and extends through the passivation layer 170 to the pixel electrode 120, and at least a part of the drain electrode 162 is located in the via 101. The conductive layer 180 is at least formed on a part of the inner surface of the via 101 and connects the drain electrode 162 and the pixel electrode 120.

[0081] The conductive layer 180 is formed on a part of the inner surface of the via 101 and connects the drain electrode 162 and the pixel electrode 120, which avoids poor contact between the drain electrode 162 and the pixel electrode 120 and improves the yield of the array substrate 100.

[0082] In some embodiments, an inverse slope angle is formed between a portion of the gate insulating layer 140 on the side of the drain 162 close to the substrate 110 and the drain 162.

[0083] The via 101 is formed by dry etching. Due to the limitations of the via 101 formation process, when etching the via 101 connecting the source-drain electrode 160 and the pixel electrode 120, lateral etching is likely to occur, that is, a portion of the gate insulating layer 140 under the source-drain electrode 160 is undesirably etched, and an inverse slope angle is formed under the source-drain electrode 160. The conductive layer 180 is formed on a partial inner surface of the via 101. Without being affected by the inverse slope angle, the process requirements for forming the via 101 in the etching passivation layer 170 and the gate insulating layer 140 can be reduced. That is to say, even if relatively severe lateral etching occurs when forming the via 101, the conductive connection between the drain 162 and the pixel electrode 120 is not affected.

[0084] In some embodiments, the inner wall of the via 101 is divided into a hole bottom surface 1011, a first hole side wall 1012, and a second hole side wall 1013 along the thickness direction of the passivation layer 170 and the gate insulating layer 140. The distance between one end of the first hole side wall 1012 far from the substrate 110 and the substrate 110 is H1, and the distance between the upper surface of the drain 162 far from the substrate 110 and the substrate 110 is H2, where H1 > H2. The conductive layer 180 covers the hole bottom surface 1011 and the first hole side wall 1012 of the via 101.

[0085] The conductive layer 180 is formed by the film-forming material after the carrier material of the liquid coating agent 400 evaporates. It is defined that the distance between the upper surface of the conductive layer 180 and the substrate 110 is greater than the distance between the upper surface of the drain 162 and the substrate 110, avoiding poor contact between the drain 162 and the pixel electrode 120. At the same time, it is avoided that the height of the conductive layer 180 is too large, resulting in an excessive perfusion amount of the conductive liquid coating agent 400 when forming the conductive layer 180, and causing a short circuit in other areas of the array substrate 100.

[0086] In some embodiments, the manufacturing material of the conductive layer 180 includes gold, silver, copper, aluminum, and their alloys.

[0087] Gold, silver, copper, aluminum, and their alloys have excellent ductility and conductivity. The conductive layer 180 formed by gold, silver, copper, aluminum, and their alloys has low impedance, which is beneficial to improving the performance of the array substrate 100. Gold, silver, copper, aluminum, and their alloys dissolve in mercury to form a liquid coating agent 400 with strong fluidity.

[0088] In some embodiments, the array substrate 100 further includes a planarization layer 190 and a common electrode (not shown). The planarization layer 190 is formed on the side of the passivation layer 170 away from the substrate 110. Part of the planarization layer 190 fills the via 101 to form a filling body 191. The conductive layer 180 is located between the filling body 191 and the inner wall of the via 101. The common electrode is located on the side of the planarization layer 190 away from the substrate 110.

[0089] On the one hand, the planarization layer 190 planarizes the upper surface of the array substrate 100, improving the uniformity of the subsequent formed film layers such as the common electrode. On the other hand, the planarization layer 190 fills the via 101, making the conductive layer 180 closely attached to the inner wall of the via 101, which can prevent the conductive layer 180 from peeling off and causing poor contact between the drain 162 and the pixel electrode 120.

[0090] Embodiment III

[0091] Refer to Figure 7 As shown, in this embodiment, the display panel includes an array substrate 100, a counter substrate 200, and a liquid crystal layer 300. The counter substrate 200 is disposed opposite to the array substrate 100. The counter substrate 200 includes a color filter substrate. The liquid crystal layer 300 is disposed between the array substrate 100 and the counter substrate 200. The array substrate 100 is fabricated by using the fabrication method of the array substrate 100 disclosed in Embodiment I.

[0092] In this embodiment, the display panel includes an array substrate 100. When fabricating the array substrate 100, a pixel electrode 120, a gate 130, a gate insulating layer 140, an active layer 150, a source-drain electrode 160, and a passivation layer 170 are formed on one side of the substrate 110. The source-drain electrode 160 includes a source 161 and a drain 162 which are spaced apart. The passivation layer 170 and the gate insulating layer 140 are patterned to form a via 101 communicating the drain 162 and the pixel electrode 120. A liquid coating agent 400 is poured into the via 101. The liquid coating agent 400 at least covers the lower surface of the drain 162 close to the substrate 110. The liquid coating agent 400 includes a film-forming material and a carrier material. The evaporation temperature of the carrier material is less than that of the film-forming material. The liquid coating agent 400 is heated to evaporate the carrier material, and the film-forming material adheres to the inner surface of the via 101 to form a conductive layer 180. The conductive layer 180 connects the drain 162 and the pixel electrode 120. Since the liquid coating agent 400 with fluidity can fill the area under the drain 162 in the via 101, after evaporating the carrier material, the film-forming material can uniformly adhere to the inner surface of the via 101 regardless of the shape of the via 101 to form the conductive layer 180, thereby avoiding poor contact between the drain 162 and the pixel electrode 120 and improving the yield of the array substrate 100 and the display panel.

[0093] The terms "first", "second", etc. are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first", "second", etc. may explicitly or implicitly include one or more of such features. In the description of this application, "a plurality of" means two or more, unless otherwise specifically defined.

[0094] In this application, unless otherwise clearly defined and limited, the terms "assemble", "connect", etc. should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or integrated; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium, and it may be the communication inside two components or the interaction relationship between two components. For those of ordinary skill in the art, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0095] In the description of this specification, the description with reference to terms such as "some embodiments", "exemplarily", etc. means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of this application. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0096] Although the embodiments of this application have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting this application. Those of ordinary skill in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application. Therefore, any changes or modifications made in accordance with the claims and the description of this application shall fall within the scope covered by the patent of this application.

Claims

1. An array substrate, comprising a base substrate, characterized in that: The array substrate further includes: A pixel electrode is formed on one side of the base substrate; A gate is formed on one side of the base substrate, and the pixel electrode and the gate are spaced apart; A gate insulating layer, formed on one side of the base substrate and covering the pixel electrode and the gate; An active layer is formed on a side of the gate insulating layer away from the base substrate, and an orthographic projection of the active layer on the base substrate overlaps with an orthographic projection of the gate on the base substrate; Source-drain electrodes are formed on a side of the active layer away from the substrate, and the source-drain electrodes include a source electrode and a drain electrode that are spaced apart; a passivation layer, formed on a side of the gate insulating layer away from the base substrate and covering the active layer and the source and drain electrodes, the passivation layer being provided with a via hole penetrating the passivation layer and extending to the pixel electrode, and at least a portion of the drain electrode being located in the via hole; A conductive layer is formed at least on a portion of the inner surface of the via hole and connects the drain electrode and the pixel electrode.

2. The array substrate according to claim 1, characterized in that: A reverse slope angle is formed between a portion of the gate insulating layer on a side of the drain electrode close to the substrate and the drain electrode.

3. The array substrate according to claim 1 or 2, characterized in that: The inner wall of the via hole is divided into a hole bottom surface, a first hole side wall and a second hole side wall along the thickness direction of the passivation layer and the gate insulation layer. The distance between the first hole side wall away from one end of the substrate and the substrate is H1, and the distance between the drain electrode away from the upper surface of the substrate and the substrate is H2, H1>H2, and the conductive layer covers the hole bottom surface and the first hole side wall of the via hole.

4. The array substrate according to claim 1, characterized in that: The conductive layer is made of materials including gold, silver, copper, aluminum and alloys thereof.

5. The array substrate according to claim 1, characterized in that: The array substrate also includes a flat layer and a common electrode, the flat layer is formed on the side of the passivation layer away from the base substrate, a portion of the flat layer is filled in the via hole to form a filling body, the conductive layer is located between the filling body and the inner wall of the via hole, and the common electrode is located on the side of the flat layer away from the base substrate.

6. A method for manufacturing an array substrate, characterized in that: include: A pixel electrode, a gate, a gate insulating layer, an active layer, a source-drain electrode and a passivation layer are formed on one side of the base substrate, wherein the pixel electrode and the gate are spaced apart, the gate insulating layer is located on one side of the base substrate and covers the pixel electrode and the gate, the active layer is located on a side of the gate insulating layer away from the base substrate, the orthographic projection of the active layer on the base substrate overlaps with the orthographic projection of the gate on the base substrate, the source-drain electrode is located on a side of the active layer away from the base substrate, the source-drain electrode includes a source electrode and a drain electrode spaced apart, and the passivation layer is located on a side of the gate insulating layer away from the base substrate and covers the active layer and the source-drain electrode; Patterning the passivation layer and the gate insulating layer to form a via hole connecting the drain electrode and the pixel electrode; Filling the via hole with a liquid coating agent, the liquid coating agent at least covers the lower surface of the drain electrode close to the base substrate, the liquid coating agent comprises a film-forming material and a carrier material, and the evaporation temperature of the carrier material is lower than the evaporation temperature of the film-forming material; The liquid coating agent is heated to evaporate the carrier material, so that the film-forming material adheres to the inner surface of the via hole to form a conductive layer, and the conductive layer connects the drain electrode and the pixel electrode.

7. The method for manufacturing an array substrate according to claim 6, characterized in that: The carrier material includes mercury, and the film-forming material includes gold, silver, copper, aluminum and alloys thereof.

8. The method for manufacturing an array substrate according to claim 6, characterized in that: Before pouring the liquid coating agent, the method for manufacturing the array substrate further includes: Corroding the inner wall of the via hole to make the inner wall of the via hole uneven; or A contact layer is formed on the inner wall of the via hole, and the contact layer is used to improve the adhesion between the conductive layer and the drain electrode, the pixel electrode, the passivation layer, the active layer and the gate insulating layer.

9. The method for manufacturing an array substrate according to claim 6, characterized in that: The injection volume of the liquid coating agent is smaller than the volume of the via hole, and the liquid coating agent covers the upper surface of the drain electrode away from the base substrate.

10. A display panel, characterized in that: include: The array substrate according to any one of claims 1 to 5; An opposing substrate, arranged in a box with the array substrate; The liquid crystal layer is arranged between the array substrate and the counter substrate.

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