Surface roughening method for near-infrared LED chip GaP layer dry etching
The formation of a high aspect ratio nanostructure on the GaP layer through dry etching technology solves the problems of poor wet corrosion selectivity and preparation of microstructures, improves the light extraction efficiency of LEDs, and is compatible with MicroLED, suitable for small-size applications.
Patent Information
- Application Number
- CN202510210722.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-25
- Publication Date
- 2025-06-03
AI Technical Summary
Existing LED surface roughening technologies such as poor wet corrosion selectivity, difficult to accurately control, and the prepared microstructure is incompatible with MicroLED, which affects the light extraction efficiency and luminous performance of LEDs.
The nanoscale microstructure is formed on the GaP layer by dry etching technology. Through wafer pretreatment, thin film deposition, hard mask patterning and GaP layer nanostructure etching steps, the diameter to depth ratio of the nanostructure is accurately controlled.
The light extraction efficiency of LEDs has been improved. Experiments show that the photoluminescence intensity of LEDs after surface nanocoarseness is twice as high as that of planar LEDs, and the nanostructure is compatible with MicroLED, and is suitable for small-size applications.
Smart Images
Figure CN120091669A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of surface treatment of GaP materials, and in particular to a surface roughening method for dry etching of the GaP layer of a near-infrared LED chip. Background Art
[0002] An important index for judging the quality of an LED is the luminous efficiency. Generally, the luminous efficiency can be measured by the external quantum efficiency. The external quantum efficiency is the product of the internal quantum efficiency and the light extraction efficiency. The internal quantum efficiency depends on the structure and crystal quality of the epitaxial wafer, and this part of the technology tends to be stable and it is difficult to upgrade and improve. However, there is still a relatively large room for improvement in the light extraction efficiency of LEDs. Among the various factors affecting the light extraction efficiency, total internal reflection is the main factor. Total internal reflection will form a light escape cone, and only the light falling into the light escape cone may contribute to the light extraction efficiency. The surface roughening technology is to roughen the surface or side of the device, so that the light propagation path is changed, so that more photons enter the escape cone and are emitted into the air.
[0003] The semiconductor surface roughening technology commonly used in the current industry is wet etching. By immersing the sample in the prepared chemical etching solution, the etching solution will gradually etch and dissolve the contacted material through chemical reaction, so as to leave a microstructure in the etched area of the sample.
[0004] The most commonly used surface roughening technology for current LEDs is wet etching. However, wet etching has poor selectivity and may not be able to precisely control the etching degree of different materials under specific conditions; the anisotropy is low, it is not easy to control, and it is difficult to perform fine processing; the feature size is large, usually micron structures. When wet etching is applied to the surface of LED materials, its technical defects will cause problems such as uneven luminous intensity between regions or uncontrollable luminous angle in the device, and electrode contact problems will also occur, affecting current injection. Since the structures prepared by wet etching are usually micron structures, they are not compatible with the currently popular MicroLEDs. The application size of MicroLEDs in some fields is only a few microns.
[0005] Therefore, the present application proposes a surface roughening method for dry etching of the GaP layer of a near-infrared LED chip. Summary of the Invention
[0006] The object of the present invention is to propose a surface roughening method for dry etching of the GaP layer of a near-infrared LED chip in view of the problem of poor selectivity of the most commonly used surface roughening technology for current LEDs in the background art.
[0007] The technical solution of the present invention: A surface roughening method for dry etching of the GaP layer of a near-infrared LED chip, comprising the following steps:
[0008] Wafer pretreatment to remove impurities on the wafer surface;
[0009] Film deposition on the wafer surface to build the structural basis for subsequent etching, and utilize films with different characteristics to assist in forming fine patterns;
[0010] Hard mask patterning, by precisely controlling the reaction of plasma with the film, to create a specific patterned mask and guide the etching direction of the GaP layer;
[0011] Etching steps for the nanostructure of the GaP layer: Relying on the previous mask, directly acting on the GaP layer to create a nanoscale microstructure.
[0012] Optionally, the wafer pretreatment specifically includes ultrasonic cleaning the wafer with acetone, ethanol, and ultrapure water for five minutes respectively, and then drying it with a nitrogen gun.
[0013] Optionally, in the film deposition on the wafer surface, the following steps are specifically included:
[0014] It is carried out at room temperature using an electron beam evaporation system, and two layers of film materials are deposited on the surface of the target wafer. One layer is silicon dioxide with a thickness between 100 - 400 nm, and the other layer is a metal with a thickness between 60 - 150 nm.
[0015] Optionally, the metal is used to react with fluorine-based plasma to form metal bumps later, and the metal is any one of gold, silver, nickel, titanium, aluminum, and platinum.
[0016] Optionally, in the hard mask patterning, the following steps are specifically included:
[0017] Use the plasma generated by a reactive ion etching equipment to etch the two layers of hard mask. First, make the plasma react with the metal film to generate metal bumps, and then, under the protection of the metal bumps, make the plasma react with the SiO 2 film to generate a patterned structure.
[0018] Optionally, the etching parameters of the reactive ion etching equipment are set as follows: time 10 - 25 min, pressure 2 - 20 mtorr, power 50 - 300 W, and the gas composition is CHF 3 、CF 4 、Ar 2 、O 2 in a combination of two or more of them.
[0019] Optionally, in the etching of the GaP layer nanostructure, the following steps are specifically included:
[0020] Under the protection of a graphical hard mask, an inductively coupled plasma etching equipment is used to etch the GaP layer. By reasonably controlling the etching selectivity ratio between the mask and the GaP material, nanostructures with a high aspect ratio are left on the GaP layer.
[0021] Optionally, the etching parameters of the inductively coupled plasma etching equipment are set as follows: time 0.5 - 10 min, pressure 2 - 20 mtorr, two radio frequency powers are 50 - 300 W and 100 - 3000 W respectively, and the gas composition is Cl 2 , BCl 3 , CH 4 , H 2 , Ar 2 , O 2 or a combination of three or more of them.
[0022] Compared with the prior art, the present application includes at least one of the following beneficial technical effects:
[0023] The nanostructures formed in the GaP layer of the present invention can change the light propagation path, enabling more photons to enter the light escape cone. Experiments show that the photoluminescence intensity of the LED after surface nano-roughening is twice that of the planar LED. The nanostructures can make the light scatter on the inclined side and vertically exit after being generated in the active layer, improving the light emission efficiency.
[0024] Dry etching can precisely control the diameter-to-depth ratio of the nanostructures, overcome the problem of difficult fine processing in wet etching, and leave nanostructures with a high aspect ratio on the GaP layer. When etching the nanostructures in the GaP layer, reasonably selecting the gas and setting the radio frequency source power can ensure etching anisotropy, solving the problem of low anisotropy and difficult control in wet etching.
[0025] An electron beam evaporation system is used for coating at room temperature to avoid the influence of temperature on the performance and quality of the epitaxial wafer. The parameters of the hard mask patterning process and the GaP layer nanostructure etching are determined through experiments to ensure etching uniformity and stability.
[0026] Overcoming the limitation that wet etching can only prepare micron-scale structures, it can prepare nanostructures, is compatible with Micro-LED technology, and is conducive to expanding the development of LEDs in small-size application fields; when depositing a thin film on the wafer surface, various factors are comprehensively considered to select the metal material, providing a scientific basis for material selection and optimizing the process effect.
[0027] The present invention realizes the improvement of the light extraction efficiency of the LED. The random and aperiodic roughened structure does not require additional lithography processes, has a low cost, and is easy to industrialize. The dense nanostructures indicate a higher degree of surface roughening, making it easier for light to enter the roughened structure and increasing the probability of exiting into the air. Description of the Drawings
[0028] Figure 1 Provide a flowchart of a surface roughening method for dry etching of the GaP layer of a near-infrared LED chip;
[0029] Figure 2 Scanning electron microscope image of the conical nanostructure on the surface of the GaP material processed by the method of the present invention;
[0030] Figure 3 Characterization diagram of the light emission efficiency of the LED processed by the method of the present invention;
[0031] Figure 4 It is a diagram for regulating reactive ion etching parameters (confirm whether the description of the following figure is accurate). Detailed implementation mode
[0032] The technical solution of the present invention will be further described below in conjunction with the accompanying drawings and specific embodiments.
[0033] As Figure 1 shown, a surface roughening method for dry etching of the GaP layer of a near-infrared LED chip proposed by the present invention includes wafer pretreatment, thin film deposition on the wafer surface, hard mask patterning, and GaP layer nanostructure etching. By the above steps, nanostructures are formed on the GaP layer, and the diameter-to-depth ratio of the nanostructures is controllable, which can improve the light extraction efficiency of the LED. Each step will be described in detail below.
[0034] I. Wafer pretreatment - Cleaning of the LED wafer
[0035] The wafer is ultrasonically cleaned with acetone, ethanol, and ultrapure water for five minutes respectively, and then blown dry with a nitrogen gun (N 2) ).
[0036] II. Thin film deposition on the wafer surface - Deposition of thin films on the surface of the LED wafer
[0037] The electron beam evaporation system (E-Beam) can perform the coating process at room temperature without affecting the performance and quality of the epitaxial wafer due to temperature. Use E-Beam to deposit two thin film materials on the surface of the target wafer, namely silicon dioxide (SiO 2) with a thickness between 100 - 400 nm and a metal with a thickness between 60 - 150 nm. Among them, the metal needs to react with fluorine-based plasma to form metal bumps in the subsequent process. After repeated experiments and comparisons of various metals, including gold, silver, nickel, titanium, aluminum, and platinum, etc., considering the uniformity of the bumps formed by the metal and the residual factors of the reaction by-products generated, one of gold, silver, aluminum, and nickel is selected.
[0038] III. Hard mask patterning - Hard mask patterning etching
[0039] Etch two layers of hard masks using the plasma generated by a reactive ion etching equipment. First, the plasma reacts with the metal thin film to generate metal bumps with a certain structure. Then, protected by the metal bumps, the plasma reacts with the SiO 2 thin film to generate a patterned structure. The quality of the mask patterning plays a decisive role in the etched nanostructures. As can be seen from Figure 4 , through repeated experiments by regulating the reactive ion etching parameters, it is known that the process gas pressure has a greater impact on the etching uniformity within a certain range. A higher etching power combined with a larger main etching gas flow rate can achieve a faster etching rate and a reasonable gas selection to prepare a smooth sidewall of the silicon oxide structure. Finally, the etching parameters are determined as follows: time 10 - 25 min, pressure 2 - 20 mtorr, power 50 - 300 W, and the gas composition is CHF 3 , CF 4 , Ar 2 , O 2 , with a combination of two or more of them.
[0040] IV. Etching of GaP Layer Nanostructures
[0041] Under the protection of the patterned hard mask, use an inductively coupled plasma etching equipment to etch the GaP layer. By reasonably controlling the etching selectivity ratio between the mask and the GaP material, nanostructures with a high aspect ratio can be left on the GaP layer. In addition, the process gas pressure will affect the etching rate and uniformity. The settings of the two radio frequency source power values will affect the plasma concentration and the etching rate, and a reasonable gas selection can better ensure the etching anisotropy. Finally, the etching parameters are determined as follows: time 0.5 - 10 min, pressure 2 - 20 mtorr, the two radio frequency powers are 50 - 300 W and 100 - 3000 W respectively, and the gas composition is Cl 2 , BCl 3 , CH 4 , H 2 , Ar 2 , O 2 , with a combination of three or more of them.
[0042] To verify the technical effects of the present invention, the materials processed in this embodiment are subjected to
[0043] 1. Nanostructure Morphology
[0044] As Figure 2As shown, random and aperiodic cone nanostructures were fabricated on the surface of GaP material. The height of the structures is in the range of 300 - 400 nm, and the size is in the range of 100 - 200 nm. Overall, the nanostructures are densely arranged with consistent uniformity. Such cone nanostructures contribute to improving the light extraction efficiency of LEDs. This is mainly because most of the light generated in the active layer will undergo relatively strong scattering on the inclined sides, allowing more light to vertically exit and escape from the semiconductor material.
[0045] 2. Luminescence Efficiency Characterization
[0046] As Figure 3 shown, photoluminescence (PL) is a phenomenon in which light emission occurs when the light-emitting layer of an LED is excited by short-wavelength light, which can show whether the surface roughening structure has an enhancing effect on the light extraction efficiency. As shown in the following figure, the PL intensity of the LED after surface nanoroughening is twice that of the planar LED. It can be concluded that constructing nanostructures on the GaP layer of the near-infrared LED chip using the light extraction technology of this patent can improve the light-emitting efficiency of the LED.
[0047] In the present invention, by forming controllable nanostructures in the GaP layer, the light propagation path is changed, enabling more photons to enter the light escape cone and exit into the air, thereby improving the light extraction efficiency of the LED. For example, experiments show that the photoluminescence (PL) intensity of the LED after surface nanoroughening is twice that of the planar LED. The fabricated cone nanostructures contribute to strong scattering of light on the inclined sides after being generated in the active layer, and then allowing more light to vertically exit and escape from the semiconductor material, which plays a key role in improving the light-emitting efficiency of the LED.
[0048] It is worth noting that dry etching can precisely control the diameter-to-depth ratio of the nanostructures, overcoming the problem that wet etching is difficult for fine processing. For example, nanostructures with a high aspect ratio can be left in the GaP layer, which helps to achieve precise control of light propagation.
[0049] Among them, during the etching process of the nanostructures in the GaP layer, by reasonably selecting gases and setting parameters such as the radio frequency source power, better etching anisotropy can be ensured, solving the problem of low anisotropy and difficult control in wet etching.
[0050] In addition, in the thin film deposition step on the wafer surface, an electron beam evaporation system (E-Beam) is used for coating at room temperature, avoiding the influence of temperature on the performance and quality of the epitaxial wafer, and ensuring the performance stability of the wafer during the processing.
[0051] Furthermore, during the hard mask patterning and GaP layer nanostructure etching processes, the etching parameters, such as process gas pressure, etching power, gas flow rate, etc., affecting the etching uniformity were determined through repeated experiments, and a reasonable parameter range was given to ensure the uniformity and stability of the etching process. Since this method can fabricate nanostructures, it overcomes the limitation that wet etching can only fabricate microstructures, making it compatible with the currently popular Micro-LED technology and facilitating the development of LEDs in smaller-size application fields.
[0052] The present invention elaborates in detail on four steps including wafer pretreatment, thin film deposition on the wafer surface, hard mask patterning, and GaP layer nanostructure etching and their specific operation methods, providing clear process guidance for actual production and reducing the operation difficulty. In the step of thin film deposition on the wafer surface, for the selection of metal materials, factors such as the morphology of the formed bump structure, side effects of reaction compounds, and adhesion to silicon dioxide were comprehensively considered, providing a scientific basis for material selection and helping to optimize the process effect.
[0053] The above specific embodiments are merely several alternative embodiments of the present invention. Based on the technical solution of the present invention and the relevant inspirations of the above embodiments, those skilled in the art can make various alternative improvements and combinations to the above specific embodiments.
Claims
1. A surface roughening method for dry etching of GaP layer of near-infrared LED chip, characterized in that: The following steps are involved: Wafer pretreatment to remove impurities on the wafer surface; Thin film deposition on the wafer surface builds the structural foundation required for subsequent etching, and uses thin films with different characteristics to assist in forming fine patterns; Hard mask patterning processing, through precise control of plasma and film reaction, shapes a specific patterned mask to guide the etching direction of the GaP layer; GaP layer nanostructure etching: Relying on the previous mask, it directly acts on the GaP layer to create a nanoscale microstructure.
2. The surface roughening method of the GaP layer of a near-infrared LED chip by dry etching according to claim 1, characterized in that: The wafer pretreatment specifically includes ultrasonically cleaning the wafer using acetone, ethanol and ultrapure water for five minutes respectively, and then drying it using a nitrogen gun.
3. The surface roughening method of the GaP layer of a near-infrared LED chip by dry etching according to claim 1, characterized in that: The wafer surface thin film deposition specifically includes the following steps: An electron beam evaporation system is used at room temperature to deposit two layers of thin film materials on the surface of the target wafer, one layer of which is silicon dioxide with a thickness of between 100-400nm, and the other layer is metal with a thickness of between 60-150nm.
4. The surface roughening method of the GaP layer of a near-infrared LED chip by dry etching according to claim 3, characterized in that: The metal is used for subsequent reaction with fluorine-based plasma to form metal bumps, and the metal is any one of gold, silver, nickel, titanium, aluminum and platinum.
5. The surface roughening method of the GaP layer of a near-infrared LED chip by dry etching according to claim 1, characterized in that: The hard mask patterning process specifically includes the following steps: The two layers of hard masks are etched using plasma generated by a reactive ion etching device. The plasma is first reacted with the metal film to form metal bumps, and then the plasma is reacted with the SiO2 film under the protection of the metal bumps to form a graphic structure.
6. A surface roughening method for dry etching of GaP layer of near-infrared LED chip according to claim 5, characterized in that: The etching parameters of the reactive ion etching equipment are set as follows: time 10-25 min, pressure 2-20 mtorr, power 50-300 W, and gas composition is a combination of two or more of CHF3, CF4, Ar2, and O2.
7. The surface roughening method of the GaP layer of a near-infrared LED chip by dry etching according to claim 1, characterized in that: The etching of the GaP layer nanostructure specifically includes the following steps: Under the protection of the patterned hard mask, the GaP layer is etched using an inductively coupled plasma etching device. By properly controlling the etching selectivity of the mask and the GaP material, a nanostructure with a high aspect ratio is left in the GaP layer.
8. The surface roughening method of the GaP layer of a near-infrared LED chip by dry etching according to claim 7, characterized in that: The etching parameters of the inductively coupled plasma etching equipment are set as follows: time 0.5-10 min, pressure 2-20 mtorr, two RF powers of 50-300 W and 100-3000 W respectively, and the gas composition is a combination of three or more of Cl2, BCl3, CH4, H2, Ar2, and O2.