Display method and display device

Abstract

The invention provides a display method and a display device, and belongs to the technical field of display. According to the display method disclosed by the invention, the physical resolution of the display panel is M1 * N1; the display method comprises the steps that a mainboard converts first original image data sent by a display card into first image data and sends the first image data to a time schedule controller; the resolution of the first image data is M2 * N2; n2: N1 = a: b < = 1; the time schedule controller provides P clock signals for a gate drive circuit in the display panel and provides a data control signal for a source drive circuit; p = i * b; the gate drive circuit gates each row of sub-pixels of the display panel according to P clock signals, and the source drive circuit writes N2 rows of display data in first image data row by row for each row of sub-pixels except the (j * b) th row according to a data control signal and a scanning sequence; writing the sub-pixels in the (j * b) th row into display data of the sub-pixels in the (b * j-1) th row and the (b * j + 1) th row; j is a positive integer greater than or equal to 1, and b * j + 1 < = N1.

Description

Technical Field

[0001] The present disclosure belongs to the technical field of display, and particularly relates to a display method and a display device. Background Art

[0002] Currently, the performance improvement of e-sports displays mainly focuses on the synchronous improvement of resolution and refresh rate to achieve a better user experience. However, inevitably, the simultaneous increase in resolution and refresh rate will cause the pixel charging time to become shorter rapidly. Although the panel process can be adjusted, the design materials can be replaced (A-SI → Oxide), and an IC with stronger driving ability can be adopted, there will still be a problem of insufficient charging. At the same time, with the synchronous increase in refresh rate and resolution, in order to support such high display specifications, it is also required that the graphics card and Scaler board be improved synchronously to show excellent display performance. In this case, it often leads to an increase in user consumption and affects the market sales volume. Summary of the Invention

[0003] The present invention aims to at least solve one of the technical problems existing in the prior art, and provides a display method and a display device.

[0004] An embodiment of the present disclosure provides a display method, which is applied to a display device. The display device includes a graphics card, a main board, a timing controller, and a display panel. The physical resolution of the display panel is M1×N1. The display method includes:

[0005] The main board converts the first original image data sent by the graphics card into first image data, and sends it to the timing controller. The resolution of the first image data is M2×N2, and N2:N1 = a:b ≤ 1.

[0006] The timing controller provides P clock signals to the gate driving circuit in the display panel, and provides data control signals to the source driving circuit. P = i×b, where i is a positive integer greater than or equal to 1. The gate driving circuit selects each row of sub-pixels in the display panel according to the P clock signals. The source driving circuit, according to the data control signals, for each row of sub-pixels except the j×b-th row, writes the N2 rows of display data in the first image data row by row in the scanning order. The display data of the j×b-th row of sub-pixels is written into the display data of the (b×j - 1)-th row and the (b×j + 1)-th row of sub-pixels. j is a positive integer greater than or equal to 1, and b×j + 1 ≤ N1.

[0007] Wherein, the start time of the effective level of the (k + 1)-th clock signal is earlier than the end time of the effective level of the k-th clock signal, where k takes values from 1 to P - 1.

[0008] Among the P clock signals, except for the b×j-th clock signal, the phase difference between the starting times of the active levels of adjacent clock signals is 1H1. The phase difference between the starting times of the active levels of the b×j-th and the b×j - 1-th clock signals is A, and the phase difference between the starting times of the active levels of the b×j + 1-th and the b×j-th clock signals is B; A + B = H1; where H1 is the phase difference between the starting times of two adjacent active levels of the data control signal.

[0009] Among them, the phase difference between the starting times of the active levels of the b×j-th and the b×j - 1-th clock signals is H1 / 2, and the phase difference between the starting times of the active levels of the b×j + 1-th and the b×j-th clock signals is H1 / 2.

[0010] Among them, the clock signals provided by the timing controller to the gate driving circuit and the data control signals provided to the source driving circuit satisfy:

[0011] For sub-pixels other than those in the j×b-th row, the termination time of the data signal written by the source driving circuit to the sub-pixels is earlier than the termination time of the active level of the gate driving signal loaded by the sub-pixels.

[0012] Among them, the clock signals provided by the timing controller to the gate driving circuit and the data control signals provided to the source driving circuit satisfy:

[0013] For sub-pixels other than those in the j×b-th row, the phase difference between the termination time of the data signal written by the source driving circuit to the sub-pixels and the termination time of the active level of the gate driving signal loaded by the sub-pixels is H1 / 2, where H1 is the phase difference between the starting times of two adjacent active levels of the data control signal.

[0014] Among them, the clock signals provided by the timing controller to the gate driving circuit satisfy: the time when the gate driving signals loaded by the sub-pixels in adjacent rows are simultaneously in the active level is not less than 2H1, where H1 is the phase difference between the starting times of two adjacent active levels of the data control signal.

[0015] Among them, when a:b = 3:4 and P = 4i; except for the 4e-th clock signal, the phase differences between the starting times of the active levels of the remaining clock signals differ by 1H1 in sequence; e takes positive integers from 1 to i; H1 is the phase difference between the starting times of two adjacent active levels of the data control signal; the phase difference between the starting times of the active levels of the 4e-th and the 4e - 1-th clock signals is H1 / 2.

[0016] Among them, when a:b = 2:3 and P = 3i; except for the 3e-th clock signal, the phase differences of the starting moments of the active levels of the remaining clock signals differ by 1H1 in sequence; e takes positive integers from 1 to i; H1 is the phase difference of the starting times of two adjacent active levels of the data control signal; the phase difference between the starting moments of the active levels of the 3e-th and 3e - 1-th clock signals is H1 / 2.

[0017] Among them, the duty cycle of the active level of the clock signal is 50%, and the duration of the active level of the clock signal is 3H1; H1 is the phase difference of the starting times of two adjacent active levels of the data control signal.

[0018] Among them, M1 is equal to M2.

[0019] Among them, the display method further includes:

[0020] Receiving a display mode selection instruction, and when the display mode selection instruction is the first display mode, the graphics card sends the received first original image data to the main board; the resolution of the first original image data is M3×N3; M3 < M2;

[0021] The main board converts the first original image data sent by the graphics card into first image data, including:

[0022] The main board performs horizontal interpolation processing on the first original image data to obtain first image data.

[0023] Among them, the display method further includes: receiving a display mode selection instruction, and when the display mode selection instruction is the second display mode, the graphics card sends the received second original image data to the main board;

[0024] The main board converts the second original image data into second image data; the resolution of the second image data is M4×N4; N4:N1 = 1:2; the refresh frequency of the second image data is greater than the refresh frequency of the first image data;

[0025] The timing controller provides a plurality of clock signals to the gate driving circuit in the display panel, and provides a data control signal to the source driving circuit;

[0026] The gate driving circuit gates each row of sub-pixels in the display panel according to the plurality of clock signals, and the source driving circuit, according to the data control signal, writes the second image data into the sub-pixels in the even rows row by row, and writes the display data of two adjacent sub-pixels in the even rows into the sub-pixels in the odd rows; or,

[0027] The gate driving circuit gates each row of sub-pixels of the display panel according to the multiple clock signals, and the source driving circuit writes the second image data row by row into the sub-pixels located in the odd rows according to the data control signal, and writes the display data of two adjacent sub-pixels located in the odd rows into the sub-pixels of the even rows.

[0028] Wherein, in the second display mode, the starting times of the active levels of the multiple clock signals differ from each other by 1H2 in sequence, and H2 is half of the phase difference of the starting times of two adjacent active levels of the data control signal.

[0029] Wherein, in the second display mode, the duration of the active level of the clock signal is 4H2, and the duty cycle of the active level of the clock signal is 50%; the multiple clock signals satisfy that the duration for which adjacent row sub-pixels are simultaneously on is 3H2.

[0030] The present disclosure example provides a display device, which includes a graphics card, a main board, a gate driving circuit, a source driving circuit and a display panel; the physical resolution of the display panel is M1×N1;

[0031] The main board is configured to convert the first original image data sent by the graphics card into first image data and send it to the timing controller; the resolution of the first image data is M2×N2; N2:N1 = a:b < 1;

[0032] The timing controller is configured to provide P clock signals to the gate driving circuit in the display panel and provide a data control signal to the source driving circuit; P = i×b; i is a positive integer greater than or equal to 1; the gate driving circuit gates each row of sub-pixels of the display panel according to the P clock signals, and the source driving circuit, according to the data control signal, for each row of sub-pixels except the j×b-th row, writes the N2 rows of display data in the first image data row by row in the scanning order; writes the display data of the j×b-th row of sub-pixels into the display data of the (b×j - 1)-th row and the (b×j + 1)-th row of sub-pixels; j is a positive integer greater than or equal to 1, and b×j + 1 ≤ N1. Description of the Drawings

[0033] Figure 1 It is a schematic diagram of the display device provided by the embodiment of the present disclosure.

[0034] Figure 2A and Figure 2B It is an example structural diagram of the gate driving circuit provided by the embodiment of the present disclosure.

[0035] Figure 3 It is a signal timing diagram of a display method provided by the embodiment of the present disclosure.

[0036] Figure 4Flow chart of the display method according to an embodiment of the present disclosure.

[0037] Figure 5 Timing diagram of the display method according to an embodiment of the present disclosure.

[0038] Figure 6 Flow chart of the display method according to an embodiment of the present disclosure.

[0039] Figure 7 A timing diagram of the display method according to an embodiment of the present disclosure in the second display mode.

[0040] Figure 8 Another timing diagram of the display method according to an embodiment of the present disclosure in the second display mode. Detailed implementation manners

[0041] To enable those skilled in the art to better understand the technical solutions of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific implementation manners.

[0042] Unless otherwise defined, the technical terms or scientific terms used in this disclosure should have the ordinary meanings understood by those of ordinary skill in the art to which this disclosure belongs. The "first", "second" and similar terms used in this disclosure do not denote any order, quantity or importance, but are only used to distinguish different components. Similarly, the terms such as "a", "an" or "the" do not denote a quantity limitation, but mean that there is at least one. The terms such as "include" or "comprise" mean that the elements or items appearing before this term cover the elements or items listed after this term and their equivalents, without excluding other elements or items. The terms such as "connect" or "couple" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The terms such as "upper", "lower", "left" and "right" are only used to represent relative positional relationships, and when the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0043] Figure 1 Schematic diagram of the display device provided by an embodiment of the present disclosure; as Figure 1 shown, the display device 100 includes a display panel, and the display panel includes a plurality of sub-pixels arranged in an M1×N1 array, where both N1 and M1 are integers greater than 1.

[0044] The display device 100 may further include a gate driving circuit 10, and the gate driving circuit 10 is connected to the plurality of sub-pixels. The gate driving circuit 10 may be along a first direction ( Figure 1A plurality of gate signal lines extending in the x - direction (the middle is the x - direction) are respectively connected to N1 rows of sub - pixels. For example, the first row of sub - pixels is connected through the first gate signal line to provide the first gate driving signal G1 to the first row of sub - pixels, the second row of sub - pixels is connected through the second gate signal line to provide the second gate driving signal G2 to the second row of sub - pixels, and so on. The first row of sub - pixels is turned on in response to receiving the first gate driving signal G1, the second row of sub - pixels is turned on in response to receiving the second gate driving signal G2, and so on.

[0045] In some embodiments, the gate driving circuit 10 can scan the N1 rows of sub - pixels row by row or multiple rows at a time. For example, the gate driving circuit 10 can scan one row of sub - pixels each time, for example, sequentially generate N1 gate driving signals G1, G2, … GN to sequentially turn on the first row of sub - pixels, the second row of sub - pixels P … the N1th row of sub - pixels P. The gate driving circuit 10 can also scan two or more rows of sub - pixels P each time. For example, the gate driving circuit 10 can simultaneously generate the first gate driving signal G1 and the second gate driving signal G2 to turn on the first row of sub - pixels and the second row of sub - pixels simultaneously. Next, the gate driving circuit 10 can simultaneously generate the third gate driving signal G3 and the fourth gate driving signal G4 to turn on the third row of sub - pixels and the fourth row of sub - pixels simultaneously, and so on. In some embodiments, the gate driving circuit 10 can scan the N1 rows of sub - pixels with at least one row interval in between to sequentially turn on some rows of sub - pixels. For example, the gate driving circuit 10 can sequentially turn on the odd - numbered rows of sub - pixels (for example, sequentially turn on the first row of sub - pixels, the third row of sub - pixels, the fifth row of sub - pixels, and so on), or sequentially turn on the even - numbered rows of sub - pixels (for example, sequentially turn on the second row of sub - pixels, the fourth row of sub - pixels, the sixth row of sub - pixels, and so on).

[0046] The display device 100 may further include a source driving circuit 20, and the source driving circuit 20 is connected to a plurality of sub - pixels. For example, the source driving circuit 20 can be respectively connected to M1 columns of sub - pixels P through a plurality of data lines extending in the second direction ( Figure 1 the middle is the y - direction). For example, the source driving circuit 20 can be connected to the first column of sub - pixels through the first data line to provide the first data signal D1 to the first column of sub - pixels, and connected to the second column of sub - pixels through the second data line to provide the second data signal D2 to the second column of sub - pixels, and so on.

[0047] For example, when the first row of sub-pixels is turned on, the source driver circuit 20 can provide M1 data signals D11, D12, …, D1M for the M1 sub-pixels in the first row through M1 data lines respectively; when the second row of sub-pixels is turned on, the source driver circuit 20 can provide M1 data signals D21, D22, …, D2M1 for the M1 sub-pixels in the second row through multiple data lines respectively, and so on. Of course, the embodiments of the present disclosure are not limited thereto, and will be further described in detail below.

[0048] In some embodiments, the display device 100 may further include a graphics card 50, a main board 40, and a timing controller 30. The main board 40 may specifically be a Scalar main board 40. The graphics card 50 is used for image formation, and the main board 40 is used for data transmission. For example, the graphics card 50 transmits image data to the main board 40, and the main board 40 sends the image data to the timing controller 30.

[0049] The timing controller 30 is connected to the gate driver circuit 10 and the source driver circuit 20, and can provide relevant control signals to the gate driver circuit 10 and the source driver circuit 20. For example, the timing controller 30 can provide a data control signal TP to the source driver circuit 20, and the source driver circuit 20 can output data signals for each row under the control of the data control signal TP. The timing controller 30 can also provide other control signals to the source driver circuit 20, including but not limited to a row data start signal, a data synchronization signal, a data inversion signal, etc. The timing controller 30 can also provide various control signals to the gate driver circuit 10, including but not limited to a frame start signal, a clock signal, etc. required by the gate driver circuit 10. In the present disclosure, it is taken as an example that the effective level of each signal is a high level, and the corresponding invalid level is a low level.

[0050] Figure 2A and Figure 2B shows an exemplary structure diagram of the gate driver circuit according to an embodiment of the present disclosure. As Figure 2A and Figure 2B shown, the gate driver circuit includes multiple cascaded shift registers GOA1, GOA2, …, GOAN. For example, for a super high definition (QHD: resolution 2560×1440) display panel, the number of horizontal pixels is 2560, and the number of vertical pixels is 1440. If multiple sub-pixels included in each pixel are arranged horizontally, the display panel includes 1440 rows of sub-pixels. In the case where the display panel includes 1440 rows of sub-pixels and each shift register corresponds to one row of sub-pixels, the number of shift registers included in the gate driver circuit can be 1440.

[0051] Figure 2A shows the first-stage to ninth-stage shift register units GOA1 to GOA9. AsFigure 2A As shown, STV1 is a frame start signal. When the gate driving circuit is connected to 8 CLKs, the input ends Input of the first-stage to fourth-stage shift register units GOA1 to GOA4 can be connected to the frame start signal end STV1. After the fourth-stage shift register unit GOA4, the input end Input of the nth-stage shift register unit GOAn is connected to the output end of the (n - 4)th-stage shift register unit GOA(n - 4), where 5 ≤ n ≤ N. For example, the output of GOA1 is connected to the input of GOA5, the output of GOA2 is connected to the input of GOA6, the output of GOA3 is connected to the input of GOA7, the output of G4 is connected to the input of GOA8, the output of G5 is connected to the input of GOA9, and so on. The reset end RST of the nth-stage shift register unit GOAn is connected to the output end OUT of the (n + 4)th-stage shift register unit GOA(n + 4), where 1 ≤ n ≤ N - 4. Figure 2B The last-stage shift register unit GOA1440 and the dummy shift register unit (DummyGOA) are shown in Figure 2B As shown, the last 4 rows of GOA can be reset by 4 rows of Dummy GOA. For example, Dummy GOA1 (Dum1) resets GOA1437, Dummy GOA2 (Dum2) resets GOA1438, etc., in sequence. Each Dummy GOA can be reset by STV1.

[0052] It should be noted that in the above example, only the case where the reset end RST of the nth-stage shift register unit GOAn is connected to the output end OUT of the (n + 4)th-stage shift register unit GOA(n + 4) is taken as an example. In some examples, it can also be that the reset end RST of the nth-stage shift register unit GOAn is connected to the output end OUT of the (n + 4)th-stage shift register unit GOA(n + 5), where 1 ≤ n ≤ N - 5. Correspondingly, the gate driving circuit includes 5 Dummy GOAs, and the last 5 rows of GOA can be reset by 5 rows of Dummy GOAs. For example, Dummy GOA1 (Dum1) resets GOA1436, Dummy GOA2 (Dum2) resets GOA1437, etc., in sequence. That is to say, for the setting of Dummy GOA, it can be flexibly set according to the reset relationship between GOAs. Figure 2A and 2BThe shown gate driving circuit adopts eight clock signals CLK1 to CLK8. The clock signal terminal CLK of the first-stage shift register unit GOA1 is connected to receive the first clock signal CLK1, the clock signal terminal CLK of the second-stage shift register unit GOA2 is connected to receive the second clock signal CLK2, and so on. The clock signal terminal CLK of the eighth-stage shift register unit GOA8 is connected to receive the eighth clock signal CLK8. In a similar manner, the ninth-stage to sixteenth-stage shift register units GOA9 to GOA16 are respectively connected to receive the first to eighth clock signals CLK1 to CLK8.

[0053] Each stage of the shift register units GOA1, GOA2, …, GOAN can generate an output signal at its output terminal OUT as a gate driving signal (or gate scanning signal) under the control of the signals at its clock signal terminal CLK and input terminal. For example, the first-stage shift register unit GOA1 generates the first gate driving signal G1, the second-stage shift register unit GOA2 generates the second gate driving signal G2, and so on. Through the cascading method, the gate driving signal generated by one stage of the shift register unit can be shifted relative to the gate driving signal generated by another stage of the shift register unit.

[0054] The above is only an example description of the display device of the embodiments of the present disclosure. The structure of the display device of the embodiments of the present disclosure is not limited thereto and may have other structures according to needs. For example, the display device may be a display device based on liquid crystal display (LCD) technology or a display device based on organic light-emitting diode (OLED) display technology. The gate driving circuit of the display device may adopt a cascading method different from Figure 2A and 2B the shown one. For example, 10 or 12 clock signals may be adopted for cascading in different ways.

[0055] Figure 3 is the signal timing diagram of a display method of the embodiments of the present disclosure; hereinafter, taking the display device of Figure 1 、 Figure 2A and Figure 2B as an example to illustrate the signal timing of Figure 3 . As Figure 3 shown, when each frame of image is displayed, under the control of the clock signals CLK1 to CLK8, the gate driving circuit 10 sequentially generates the first gate driving signal G1, the second gate driving signal G2, the third gate driving signal G3, the fourth gate driving signal G4, and so on at a preset time interval. The phase difference between the starting moments when two adjacent rows of sub-pixels are written with data signals is H. In Figure 3 , the effective level duration of each gate driving signal is, for example, 4H.

[0056] For the first row of sub-pixels, in the time period T1 to T4, the first gate drive signal G1 is at a high level, so that the first row of sub-pixels is in an on state, wherein the length of the time period T1 to T4 is H, that is, the first sub-pixel is turned on for 4H. In the time period T4, the first high-level pulse of the data control signal TP arrives, thereby controlling the source drive circuit 20 to apply the data signal (also referred to as the first row data signal) DATA1 for the first row of sub-pixels to the first row of sub-pixels in an on state. The first row data signal DATA1 may include M1 data signals D11, D12, ..., D1M for M1 sub-pixels in the first row, respectively, wherein the data signal D11 is provided to the first row and first column sub-pixels, the data signal D12 is provided to the first row and second column sub-pixels, ..., the data signal D1M is provided to the M1st column sub-pixel in the first row.

[0057] Similarly, for the second row of sub-pixels, in the time period T2 to T5, the second gate drive signal G2 is at a high level, so that the second row of sub-pixels is in an on state, wherein in the time period T5, the second high level pulse of the data control signal TP arrives, thereby controlling the source drive circuit 20 to apply the data signal (also referred to as the second row data signal) DATA2 for the second row of sub-pixels to the second row of sub-pixels in an on state. The second row data signal DATA2 may include M1 data signals D21, D22, ..., D2M for M1 sub-pixels in the second row, respectively, wherein the data signal D21 is provided to the first column sub-pixel of the second row, the data signal D22 is provided to the second column sub-pixel of the second row, ..., the data signal D2M1 is provided to the M1th column sub-pixel of the second row. The same can be applied to the other rows of sub-pixels.

[0058] According to the display of the above frame of image, the refresh frequency of the QHD display panel is 180Hz. If the refresh frequency of the QHD display panel is increased from 180Hz to 240Hz, the refresh frequency is increased by 4 / 3 times. Specifically, when the graphics card 50 receives the original image data 2560*1440*180Hz and adjusts it to 1920*1080*240Hz, and outputs 2560*1080*240Hz after being processed by the motherboard 40Scalar, from the perspective of the timing controller 30 receiving the image data, since 2560*1440*180=2560*1080*240, its receiving bandwidth remains unchanged. In this way, the refresh frequency is increased from 180Hz to 240Hz; however, since the timing controller 30 actually receives 1080 rows of display data, and the number of physical sub-pixel rows of the display panel is 1440 rows, the display data on the display panel will be missing. In response to this problem, the present disclosure provides the following technical solutions.

[0059] An embodiment of the present disclosure provides a display method, which can also be applied to Figure 1 the display device described above. The physical resolution of the display panel is M1×N1. As Figure 4 shown, the display method includes:

[0060] S10. The main board 40 converts the first original image data sent by the graphics card 50 into first image data and sends it to the timing controller 30; the resolution of the first image data is M2×N2; N2:N1 = a:b ≤ 1.

[0061] Specifically, in the display method of the embodiment of the present disclosure, the refresh frequency of the first image data is higher than the normal refresh frequency of the display device. For example, the normal refresh frequency of the display panel is 180Hz, the refresh frequency of the first image data is 240Hz, the physical resolution of the display panel is M1×N1 = 2560×1440; the resolution of the first image data is M2×N2 = 2560×1080. Accordingly, N2:N1 = 3:4, that is, a = 3 and b = 4.

[0062] S20. The timing controller 30 provides P clock signals to the gate driving circuit 10 in the display panel and provides a data control signal to the source driving circuit 20; P = i×b; i is a positive integer greater than or equal to 1. The gate driving circuit 10 selects each row of sub-pixels of the display panel according to the P clock signals, and the source driving circuit 20, according to the data control signal, writes the N2 rows of display data in the first image data row by row in the scanning order for each row of sub-pixels except the j×b-th row; writes the display data of the j×b-th row of sub-pixels into the display data of the (b×j - 1)-th row and the (b×j + 1)-th row of sub-pixels; j is a positive integer greater than or equal to 1, and j×b + 1 ≤ N1.

[0063] That is to say, the data written to each row of sub-pixels except the j×b-th row in the display panel is the real display data in the first image data, while for the j×b-th row of sub-pixels, the written display data is the interpolation of the display data of the upper and lower two adjacent rows of sub-pixels. In this way, each sub-pixel on the display panel has display data written, and the interpolation of the display data of the upper and lower two adjacent rows of sub-pixels is written to the j×b-th row of sub-pixels, avoiding the problem that the display of the interpolated row of sub-pixels is too different from that of the adjacent row of sub-pixels, resulting in abnormal display.

[0064] Specifically, taking a = 3 and b = 4 in step S10 as an example, if i is taken as 2, then P = 8, that is, the timing controller 30 generates 8 clock signals, namely CLK1 to CLK8. At this time, the 8 clock signals generated by the timing controller 30, as well as the data control signal, can control that the sub-pixels of each row except the sub-pixels in the (3j + 1)-th row (for example: the 4th, 8th, 12th,...) are written with real display data. For the sub-pixels in the (3j + 1)-th row, the interpolation of the display data of the upper and lower two rows of sub-pixels adjacent to it is used for display. For example: the sub-pixels in the 4th row are mixedly charged with the display data written by the sub-pixels in the 3rd row and the 5th row.

[0065] It should be noted that in the case of the above example, the number of clock signals is not limited to 8 either. Specifically, it can be an integer multiple of 4. For example, the number of clock signals can be 4, 8, 12, etc. In addition, for the above example, only taking the resolution of the first image data M2×N2 = 2560×1080 and filling 2560×1080 data into the display panel with a physical resolution of M1×N1 = 2560×1440 as an example, if the resolution of the first image data M2×N2 = 2560×1440 and 2560×1440 data are filled into the display panel with a physical resolution of M1×N1 = 3840×2160, at this time, N2:N1 = 2:3, that is, a = 2 and b = 3. At this time, the display data of the display panel needs to be filled every two rows, that is, the sub-pixels in the 3rd, 6th, 9th,... rows need to be mixedly charged with the display data of the upper and lower sub-pixels adjacent to them. This requires that the number of clock signals generated by the timing controller 30 at this time is a multiple of 3, such as 6, 9, 12 clock signals, and so on. By analogy, they are not listed one by one here.

[0066] In some examples, the start time of the high level of the (k + 1)-th clock signal is earlier than the end time of the high level of the k-th clock signal; k takes values from 1 to P - 1; among the P clock signals, except for the (b×j)-th clock signal, the phase difference between the start times of the valid levels of adjacent clock signals is 1H1, the phase difference between the start times of the valid levels of the (b×j)-th and the (b×j - 1)-th clock signals is A, and the phase difference between the start times of the valid levels of the (b×j + 1)-th and the (b×j)-th clock signals is B; A + B = H1; H1 is the phase difference between the start times of two adjacent valid levels of the data control signal. For example: the phase difference between the start times of the high levels of the (b×j)-th and the (b×j - 1)-th clock signals is H1 / 2, and the phase difference between the start times of the high levels of the (b×j + 1)-th and the (b×j)-th clock signals is H1 / 2. Specifically, taking a = 3, b = 4, i taking 2, and P = 8 as an example; except for the 4e-th clock signal, the phase differences between the start times of the valid levels of the remaining clock signals differ by 1H1 in sequence; e takes positive integers of 1 and 2; H1 is the phase difference between the start times of two adjacent valid levels of the data control signal; the phase difference between the start times of the valid levels of the 4e-th and the 4e - 1-th clock signals is H1 / 2. Of course, in the embodiments of the present disclosure, it may also be that the phase difference between the start times of the high levels of the (b×j)-th and the (b×j - 1)-th clock signals is H1 / 3, and the phase difference between the start times of the high levels of the (b×j + 1)-th and the (b×j)-th clock signals is 2H1 / 3, etc., which will not be listed one by one here.

[0067] Since the output of the gate driving circuit 10 is determined by the clock signal, during the output stage of the gate driving circuit 10, when the clock signal is at a high level, the gate driving signal output by the gate driving circuit 10 is also at a high level. Therefore, the starting time of the high level of the (k + 1)-th clock signal is earlier than the ending time of the high level of the k-th clock signal. That is to say, two adjacent rows of sub-pixels have a period of simultaneous turn-on, and pre-charging can be performed before the sub-pixel data is written to improve the charging efficiency of the sub-pixels. In the embodiments of the present disclosure, except for the 4th and 8th clock signals, the phase difference between the starting times of the high levels of adjacent clock signals is 1H1, the phase difference between the starting times of the high levels of the 4th and 3rd clock signals is H1 / 2, and the phase difference between the starting times of the high levels of the 4th and 5th clock signals is H1 / 2; that is to say, the starting times of the high level signals of the first clock signal CLK1, the second clock signal CLK2, the third clock signal CLK3, the fifth clock signal CLK5, the sixth clock signal CLK6, and the seventh clock signal CLK7 differ by 1H1 in sequence. The phase difference between the starting time of the high level of the fourth clock signal CLK4 and the third clock signal CLK3 is H1 / 2, and the phase difference between the starting time of the high level of the fifth clock signal CLK5 and the fourth clock signal CLK4 is H1 / 2. In this way, it is ensured that the sub-pixels in the (3j + 1)-th row are charged by mixing the display data of the upper and lower two adjacent rows of sub-pixels.

[0068] In some examples, the clock signal provided by the timing controller 30 to the gate driving circuit 10 and the data control signal provided to the source driving circuit 20 satisfy: for sub-pixels other than those in the (j×b)-th row, the ending time of the source driving circuit 20 writing the data signal to the sub-pixels is earlier than the ending time of the high level of the gate driving signal loaded by the sub-pixels. In this way, it is ensured that the sub-pixels in the (j×b)-th row are charged by the display data of the adjacent sub-pixels.

[0069] In one example, the clock signal provided by the timing controller 30 to the gate driving circuit 10 and the data control signal provided to the source driving circuit 20 satisfy: for sub-pixels other than those in the (j×b)-th row, the phase difference between the ending time of the source driving circuit 20 writing the data signal to the sub-pixels and the ending time of the high level of the gate driving signal loaded by the sub-pixels is H1 / 2, where H1 is the phase difference between the starting times of two adjacent high levels of the data control signal.

[0070] In some examples, the clock signal provided by the timing controller 30 to the gate driving circuit 10 satisfies that the time when the gate driving signals loaded by the sub-pixels of adjacent rows are simultaneously at a high level is not less than 2H1, where H1 is the phase difference between the starting times of two adjacent high levels of the data control signal. For example: the duty cycle of the high-level signal of each clock signal is 50%, the high-level clock can be 3H1, and the corresponding low-level duration is also 3H1. At this time, the time when the gate driving signals loaded by the sub-pixels of adjacent rows are simultaneously at a high level is not less than 2H1.

[0071] To more clearly illustrate the display of the first image data received by the display panel in the embodiments of the present disclosure, taking the example that the gate driving circuit 10 of the display panel is controlled by 8 clock signals, the display method of the embodiments of the present disclosure will be described.

[0072] Refer to Figure 5 , the 8 clock signals, CLK1~CLK8, provided by the timing controller 30 to the gate driving circuit 10, the duty cycle of the high-level signal of each clock signal is 50%, the high-level clock can be 3H1, and the corresponding low-level duration is also 3H1. The starting times of the high-level signals of the first clock signal CLK1, the second clock signal CLK2, the third clock signal CLK3, the fifth clock signal CLK5, the sixth clock signal CLK6, and the seventh clock signal CLK7 differ by 1H1 in sequence. The phase difference between the starting time of the high level of the fourth clock signal CLK4 and the third clock signal CLK3 is H1 / 2, and the phase difference between the starting time of the high level of the fifth clock signal CLK5 and the fourth clock signal CLK4 is H1 / 2. The phase difference between the starting time of each data row of the data control signal written by the timing controller 30 to the source driving circuit 20 and the termination time of the high level of the gate driving signal of the corresponding sub-pixel row is 3H1 / 4, and the phase difference between the termination time of each data row of the data control signal written by the timing controller 30 to the source driving circuit 20 and the termination time of the high level of the gate driving signal of the corresponding sub-pixel row is H1 / 2. In this case, sub-pixel row 1 is charged by data row 1, sub-pixel row 2 is charged by data row 2, sub-pixel row 3 is charged by data row 3, sub-pixel 4 is charged by data rows 3 and 4, sub-pixel row 5 is charged by data row 4, sub-pixel row 6 is charged by data row 5, sub-pixel row 7 is charged by data row 6, sub-pixel row 8 is charged by data rows 6 and 7, and so on.

[0073] In some examples, refer to Figure 6, before the display method of the present embodiment executes the above steps, it further includes receiving a display mode selection instruction, and when the display mode selection instruction is the first display mode, the graphics card 50 sends the received first original image data to the main board 40; the resolution of the first original image data is M3×N3; M3 < M2. The main board 40 converts the first original image data sent by the graphics card 50 into first image data, including: the main board 40 performs horizontal interpolation processing on the first original image data to obtain the first image data.

[0074] It should be noted that the display device in the embodiments of the present disclosure supports multiple display modes. For example: the display device includes a normal display mode, that is, the resolution of the image data is the same as the resolution of the display panel. At this time, the data of each sub-pixel row and data row correspond one by one, and the display data written to each sub-pixel is real data. The display device includes a first display mode. When receiving a display mode selection instruction for the first display mode selected by the user, the graphics card 50 sends the received first original image data to the main board 40; the resolution of the first original image data is M3×N3; M3 < M2; the main board 40 performs horizontal interpolation processing on the first original image data to obtain the first image data. For example: the resolution of the first original image data in the first display mode is M3×N3 = 1920×1080, and the refresh rate is 240Hz. The main board 40 performs horizontal interpolation processing on the first original image data to obtain the first image data, M2×N2 = 2560×1080, and the refresh rate is 240Hz.

[0075] In some examples, referring to Figure 6 , the display method of the embodiments of the present disclosure not only includes the above steps, but also may include: receiving a display mode selection instruction, and when the display mode selection instruction is the second display mode, the graphics card 50 sends the received second original image data to the main board 40.

[0076] The main board 40 converts the second original image data into second image data; the resolution of the second image data is M4×N4; N4:N1 = 1:2; the refresh rate of the second image data is greater than the refresh rate of the first image data. For example: the resolution of the second image data is M4×N4 = 2560×720, and the refresh rate is 360Hz.

[0077] Among them, the steps for the main board 40 to convert the second original image data into the second image data specifically include the main board 40 performing horizontal interpolation processing on the second original image data to obtain the second image data. For example, the resolution of the second original image data is 1280*720, and the refresh frequency is 360Hz. The main board 40 performs horizontal interpolation processing on the second original image data to obtain the second image data, and the resolution of the second image data is 2560*720, and the refresh frequency is 360Hz.

[0078] The timing controller 30 provides a plurality of clock signals to the gate driving circuit 10 in the display panel, and provides a data control signal to the source driving circuit 20.

[0079] The gate driving circuit 10 selects each row of sub-pixels in the display panel according to the plurality of clock signals. The source driving circuit 20 writes the second image data row by row into the sub-pixels located in the even rows, and writes the display data of two adjacent sub-pixels located in the even rows into the sub-pixels located in the odd rows; or, the gate driving circuit 10 selects each row of sub-pixels in the display panel according to the plurality of clock signals, and the source driving circuit 20 writes the second image data row by row into the sub-pixels located in the odd rows, and writes the display data of two adjacent sub-pixels located in the odd rows into the sub-pixels located in the even rows.

[0080] In the second display mode, its refresh frequency is higher than that of the first display mode and is twice the refresh frequency in the normal display mode, while the number of data lines of the second image data in the second display mode is half of the number of sub-pixel rows of the display panel. At this time, by controlling the data control signal generated by the timing controller 30, the source driving circuit 20 writes real data into the sub-pixels located in the odd rows, and the sub-pixels located in the even rows are mixedly charged by the upper and lower two rows of sub-pixels, or the source driving circuit 20 writes real data into the sub-pixels located in the even rows, and the sub-pixels located in the odd rows are mixedly charged by the upper and lower two rows of sub-pixels. In this way, the image quality loss can be reduced.

[0081] In some examples, in the second display mode, the starting times of the effective levels of the plurality of clock signals differ from each other by 1H2 in sequence, where H2 is half of the phase difference between the starting times of two adjacent effective levels of the data control signal. The duration of the effective level of the clock signal is 4H2, and the duty cycle of the effective level of the clock signal is 50%; the duration of the adjacent row of sub-pixels being simultaneously turned on for the plurality of clock signals is 3H2.

[0082] To make the display method in the second display mode of the present disclosure clearer, the following is a specific description in conjunction with Figure 7 the timing diagram shown.

[0083] The eight clock signals, CLK1 to CLK8, provided by the timing controller 30 to the gate driving circuit 10 each have a duty cycle of 50% for the high-level signal, and the high-level clock can be 4H2, and the corresponding low-level duration is also 4H2. The start times of the high-level signals of the first clock signal CLK1, the second clock signal CLK2, the third clock signal CLK3, the fourth clock signal CLK4, the fifth clock signal CLK5, the sixth clock signal CLK6, the seventh clock signal CLK7, and the eighth clock signal CLK8 differ by 1H2 in sequence. The phase difference between the start time of each data row of the data control signal written by the timing controller 30 to the source driving circuit 20 and the end time of the high level of the gate driving signal of the corresponding sub-pixel row (odd row) is 5H2 / 3, and the phase difference between the end time of each data row of the data control signal written by the timing controller 30 to the source driving circuit 20 and the end time of the high level of the gate driving signal of the corresponding sub-pixel row is 4H2 / 3. In this case, sub-pixel row 1 is charged by data row 1, sub-pixel row 2 is charged by data row 1 and data row 2, sub-pixel row 3 is charged by data row 2, sub-pixel row 4 is charged by data row 2 and data row 3, sub-pixel row 5 is charged by data row 3, sub-pixel row 6 is charged by data row 3 and data row 4, sub-pixel row 7 is charged by data row 4, sub-pixel row 8 is charged by data row 4 and data row 5, and so on. That is to say, for odd-row sub-pixels, the real display data is written, and for even-row sub-pixels, the display data of the upper and lower adjacent sub-pixel rows is used for mixed charging. Similarly, referring to Figure 8 , sub-pixel row 1 is charged by data row 1, sub-pixel row 2 is charged by data row 1, sub-pixel row 3 is charged by data row 1 and data row 2, sub-pixel row 4 is charged by data row 2, sub-pixel row 5 is charged by data row 2 and data row 3, sub-pixel row 6 is charged by data row 3, sub-pixel row 7 is charged by data row 3 and data row 4, sub-pixel row 8 is charged by data row 4, and so on. In this case, except for the first row of sub-pixels, for even-row sub-pixels, the real display data is written, and for odd-row sub-pixels, the display data of the upper and lower adjacent sub-pixel rows is used for mixed charging.

[0084] Continue to refer to Figure 1, embodiments of the present disclosure further provide a graphics card 50, a motherboard 40, a gate driving circuit 10, a source driving circuit 20, and a display panel; the physical resolution of the display panel is M1×N1. Among them, the motherboard 40 is configured to convert the first original image data sent by the graphics card 50 into first image data and send it to the timing controller 30; the resolution of the first image data is M2×N2; N2:N1 = a:b < 1. The timing controller 30 is configured to provide P clock signals to the gate driving circuit 10 in the display panel and provide data control signals to the source driving circuit 20; P = i×b; i is a positive integer greater than or equal to 1; the gate driving circuit 10 selects each row of sub-pixels of the display panel according to the P clock signals, and the source driving circuit 20, according to the data control signals, for each row of sub-pixels except the j×b-th row, writes the N2 rows of display data in the first image data row by row in the scanning order; writes the display data of the j×b-th row of sub-pixels into the display data of the (b×j - 1)-th row and the (b×j + 1)-th row of sub-pixels; j is a positive integer greater than or equal to 1, and b×j + 1 ≤ N1.

[0085] The display device according to the embodiments of the present disclosure can be any device such as a mobile phone, a tablet computer, a laptop computer, an e-book, a game console, a television, a digital photo frame, a navigator, etc., or any combination of a display device and hardware. The embodiments of the present disclosure do not limit this.

[0086] It should be noted that, for the sake of clarity and conciseness, embodiments of the present disclosure do not show all the constituent units of the electronic device 1. To achieve the necessary functions of the electronic device, those skilled in the art can provide and set other constituent units not shown according to specific needs. The embodiments of the present disclosure do not limit this.

[0087] For the relevant description and technical effects of the electronic device 1, reference can be made to the relevant description and technical effects of the frequency divider provided in the embodiments of the present disclosure, which will not be elaborated here.

[0088] It can be understood that the above embodiments are merely exemplary embodiments adopted to illustrate the principle of the present invention. However, the present invention is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also regarded as the protection scope of the present invention.

Claims

1. A display method, applied to a display device, wherein the display device comprises a graphics card, a mainboard, a timing controller and a display panel; The physical resolution of the display panel is M1×N1; the display method includes: The mainboard converts the first original image data sent by the graphics card into first image data, and sends the first image data to the timing controller; the resolution of the first image data is M2×N2; N2:N1=a:b≤1; The timing controller provides P clock signals to the gate driving circuit in the display panel, and provides a data control signal to the source driving circuit; P=i×b; i is a positive integer greater than or 1; the gate driving circuit selects each row of sub-pixels of the display panel according to the P clock signals, and the source driving circuit writes N2 rows of display data in the first image data row by row in a scanning order for each row of sub-pixels except the j×b row according to the data control signal; writes the display data of the b×j-1th row and the b×j+1th row of sub-pixels into the j×bth row of sub-pixels; j is a positive integer greater than or 1, and b×j+1≤N1.

2. The display method according to claim 1, wherein: The starting time of the effective level of the k+1th clock signal is earlier than the ending time of the effective level of the kth clock signal; K is 1 to P-1; The phase difference between the start times of the effective levels of adjacent clock signals among the P clock signals, except for the b×j-th clock signal, is 1H1, the phase difference between the start times of the effective levels of the b×j-th and b×j-1-th clock signals is A, and the phase difference between the start times of the effective levels of the b×j+1-th and b×j-th clock signals is B; A+B=H1; The H1 is the phase difference between the start times of two adjacent effective levels of the data control signal.

3. The display method according to claim 1, wherein: The phase difference between the start times of the valid levels of the b×j-th and b×j-1-th clock signals is H1 / 2, and the phase difference between the start times of the valid levels of the b×j+1-th and b×j-th clock signals is H1 / 2.

4. The display method according to claim 1, wherein: The clock signal provided by the timing controller to the gate driving circuit and the data control signal provided to the source driving circuit meet the following requirements: For the sub-pixels except the j×bth row, the termination time of the source driving circuit writing the data signal to the sub-pixels is earlier than the termination time of the effective level of the gate driving signal loaded on the sub-pixels.

5. The display method according to claim 4, wherein: The clock signal provided by the timing controller to the gate driving circuit and the data control signal provided to the source driving circuit meet the following requirements: For sub-pixels except the j×bth row, the phase difference between the termination time of the source driving circuit writing the data signal to the sub-pixel and the termination time of the effective level of the gate driving signal loaded by the sub-pixel is H1 / 2, and H1 is the phase difference between the start times of two adjacent effective levels of the data control signal.

6. The display method according to claim 1, wherein: The clock signal provided by the timing controller to the gate driving circuit satisfies: the time during which the gate driving signals loaded by the sub-pixels of adjacent rows are simultaneously at the effective level is not less than 2H1, where H1 is the phase difference between the start times of two adjacent effective levels of the data control signal.

7. The display method according to claim 1, wherein: When a:b=3:4, P=4i; except for the 4e-th clock signal, the phase differences of the starting times of the effective levels of the remaining clock signals differ by 1H1 respectively; e is a positive integer from 1 to i; H1 is the phase difference between the starting times of two adjacent effective levels of the data control signal; the phase difference between the starting times of the effective levels of the 4e-th and 4e-1-th clock signals is H1 / 2.

8. The display method according to claim 1, wherein: When a:b=2:3, P=3i; except for the 3e-th clock signal, the phase differences of the starting times of the effective levels of the remaining clock signals differ by 1H1 respectively; e is a positive integer from 1 to i; H1 is the phase difference between the starting times of two adjacent effective levels of the data control signal; the phase difference between the starting times of the effective levels of the 3e-th and 3e-1-th clock signals is H1 / 2.

9. The display method according to claim 1, wherein: The duty cycle of the effective level of the clock signal is 50%, and the duration of the effective level of the clock signal is 3H1; H1 is the phase difference between the start times of two adjacent effective levels of the data control signal.

10. The display method according to any one of claims 1 to 9, wherein: The M1 is equal to the M2.

11. The display method according to any one of claims 1 to 9, wherein: Also includes: receiving a display mode selection instruction, and when the display mode selection instruction is a first display mode, the graphics card sends the received first original image data to the mainboard; the resolution of the first original image data is M3×N3; M3<M2; The mainboard converts the first original image data sent by the graphics card into first image data, including: The main board performs horizontal interpolation processing on the first original image data to obtain first image data.

12. The display method according to claim 11, wherein: Also includes: receiving a display mode selection instruction, and when the display mode selection instruction is a second display mode, the graphics card sends the received second original image data to the mainboard; The mainboard converts the second original image data into second image data; the resolution of the second image data is M4×N4; N4:N1=1:2; the refresh frequency of the second image data is greater than the refresh frequency of the first image data; The timing controller provides a plurality of clock signals to the gate driving circuit in the display panel, and provides a data control signal to the source driving circuit; The gate driving circuit selects the sub-pixels of each row of the display panel according to the multiple clock signals, and the source driving circuit writes the second image data into the sub-pixels located in the even-numbered rows row by row according to the data control signal, and writes the display data of the two adjacent sub-pixels located in the even-numbered rows into the sub-pixels in the odd-numbered rows; or, The gate driving circuit selects sub-pixels in each row of the display panel according to the multiple clock signals, and the source driving circuit writes the second image data into the sub-pixels located in odd rows row by row according to the data control signal, and writes the display data of the two adjacent sub-pixels located in odd rows into the sub-pixels in even rows.

13. The display method according to claim 12, wherein: In the second display mode, the start times of the effective levels of the plurality of clock signals are sequentially different by 1H2, where H2 is half of the phase difference between the start times of two adjacent effective levels of the data control signal.

14. The display method according to claim 13, wherein: In the second display mode, the duration of the effective level of the clock signal is 4H2, and the duty cycle of the effective level of the clock signal is 50%; the duration of the multiple clock signals satisfying that adjacent rows of sub-pixels are turned on at the same time is 3H2.

15. A display device comprising a graphics card, a mainboard, a gate driving circuit, a source driving circuit and a display panel; the physical resolution of the display panel is M1×N1; The mainboard is configured to convert the first original image data sent by the graphics card into first image data and send the first image data to the timing controller; the resolution of the first image data is M2×N2; N2:N1=a:b<1; The timing controller is configured to provide P clock signals to the gate driving circuit in the display panel, and provide data control signals to the source driving circuit; P=i×b; i is a positive integer greater than or equal to 1; the gate driving circuit selects each row of sub-pixels of the display panel according to the P clock signals, and the source driving circuit writes N2 rows of display data in the first image data row by row into each row of sub-pixels except the j×bth row according to the data control signal in a scanning order; The display data of the sub-pixels in the j×bth row are written into the sub-pixels in the b×j-1th row and the b×j+1th row; j is a positive integer greater than or 1, and b×j+1≤N1.

Images