Memory BIST circuit for testing memory based on user data

Abstract

An electronic circuit includes: a memory (102) including a data input, an address input, a command input, and a data output; a register (112) having a data input coupled to the data output of the memory; a comparator circuit (115) having a first data input coupled to the data output of the memory and a second data input coupled to the data output of the register; an inverter circuit (114) having a data input coupled to the data output of the register and a data output coupled to the data input of the memory; and a controller (101) having a command output coupled to the command input of the memory, an address output coupled to the address input of the memory, and a fault input coupled to a data output of the comparator circuit, wherein the controller is configured to determine whether the memory has a fault based on the fault input of the controller.

Description

[0001] The present disclosure generally relates to an electronic system and method, and in particular embodiments, to a memory built-in self-test (BIST) circuit and method. BACKGROUND OF THE INVENTION

[0002] BIST circuits are commonly used to automatically test target circuits during product manufacturing and / or during circuit operation. Many BIST circuits include a controller that generates test conditions for one or more target circuits and receives responses from the one or more target circuits to identify faults in those target circuits.

[0003] BIST circuits can be used to help comply with certain safety requirements in certain industries. For example, the ISO 26262 Road Vehicle Functional Safety Standard defines four automotive safety integrity levels (ASILs) that specify the integrity requirements of a product, where ASIL-D is associated with the highest safety standard among the four safety standards. As an example, to comply with ASIL-D, the latent failure metric of a device (which measures the robustness of the design against potential failures) should have a test coverage of at least 90%.

[0004] A memory BIST (MBIST or MEMBIST) circuit is an example of a BIST circuit used to test a memory. The MBIST circuit can test the memory (also referred to as performing an MBIST test) to check for stuck-at faults, transition delay faults, coupling faults, neighborhood pattern sensitive faults, etc. For example, the MBIST circuit can write a set of data to a first memory address of the memory, read the set of data from the first memory address of the memory, and compare the written set of data with the read set of data. If the read data is different from the written data, the MBIST circuit determines that there is a fault associated with the memory cells of the first memory.

[0005] In automotive applications, a memory test can be performed when power is on (during vehicle startup), when power is off (during vehicle power-down), and / or during operation. When performing a memory test during operation, the system software running in the vehicle processor first saves the state of the target memory, then the system software allows the MBIST circuit to test the target memory, and after the MBIST circuit finishes testing the target memory (which erases the original data stored in the target memory), the system software restores the target memory to the saved memory state to continue operation. SUMMARY OF THE INVENTION

[0006] According to an embodiment, an electronic circuit includes: a memory including a data input, an address input, a command input, and a data output; a register having a data input coupled to the data output of the memory; a comparator circuit having a first data input coupled to the data output of the memory and a second data input coupled to the data output of the register; an inverter circuit having a data input coupled to the data output of the register and a data output coupled to the data input of the memory; and a controller having a command output coupled to the command input of the memory, an address output coupled to the address input of the memory, and a fault input coupled to the data output of the comparator circuit, wherein the controller is configured to determine whether the memory has a fault based on the fault input of the controller.

[0007] According to an embodiment, a device includes: a memory including a data input, an address input, a command input, and a data output; a register having a data input coupled to the data output of the memory; a comparator circuit having a first data input coupled to the data output of the memory and a second data input coupled to the data output of the register; an inverter circuit having a data input coupled to the data output of the register and a data output coupled to the data input of the memory; a controller having a command output coupled to the command input of the memory, an address output coupled to the address input of the memory, and a fault input coupled to the data output of the comparator circuit; a first multiplexer having a first data input coupled to the data output of the inverter circuit and a data output coupled to the data input of the memory; a second multiplexer having a first address input coupled to the address output of the controller and an address output coupled to the address input of the memory; and a third multiplexer having a first command input coupled to the command output of the controller and a command output coupled to the command input of the memory; and a processor including: a data output coupled to the second data input of the first multiplexer; an address output coupled to the second address input of the second multiplexer; a command output coupled to the second command input of the third multiplexer; and a data input coupled to the data output of the memory.

[0008] According to an embodiment, a method includes: asserting a test mode signal; after the test mode signal is asserted, transmitting a first memory address and a first read command to a first memory to cause the first memory to output first read data at a data output of the first memory; after transmitting the first read command to the first memory, storing the first read data in a first register; after storing the first read data in the first register, transmitting a first write command to the first memory to cause first input data at a data input of the first memory to be stored at the first memory address of the first memory, wherein the data input of the first memory is coupled to a data output of the first register via a first inverter circuit, and wherein the first input data corresponds to the inverted first read data; after transmitting the first write command to the first memory, transmitting a second read command to the first memory to cause the first memory to output second read data at the data output of the first memory, wherein the second read data corresponds to the inverted first read data; and after transmitting the second read command to the first memory, comparing the first read data with the second read data using a first comparator circuit, and determining whether the first memory has a fault based on a data output of the first comparator circuit, the first comparator circuit including a first data input coupled to the data output of the first memory, a second data input coupled to the data output of the first register, and a data output. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] To more fully understand the present invention and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 and 2 schematically illustrate a BIST circuit and associated waveforms in accordance with an embodiment of the present invention;

[0011] Figure 3 and 4 schematically illustrate a BIST circuit and associated waveforms in accordance with an embodiment of the present invention;

[0012] Figure 5 and 6 illustrate a schematic diagram of a BIST data path for Figure 3 in accordance with an embodiment of the present invention;

[0013] Figure 7 and 8 illustrate a schematic diagram of a BIST data path for Figure 1 in accordance with an embodiment of the present invention;

[0014] Figures 9 to 11 illustrates a flowchart of an exemplary method for testing a memory in accordance with an embodiment of the present invention;

[0015] Figure 12 An automobile according to an embodiment of the present invention is described;

[0016] Figures 13 to 15 A schematic diagram of a BIST circuit according to an embodiment of the present invention is shown.

[0017] Unless otherwise specified, corresponding reference numerals and symbols in different figures generally refer to corresponding parts. The figures are drawn to clearly illustrate relevant aspects of the preferred embodiments and are not necessarily drawn to scale. Detailed Description

[0018] The making and using of the disclosed embodiments are discussed in detail below. However, it should be understood that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed merely illustrate specific ways of making and using the present invention and do not limit the scope of the present invention.

[0019] The following description sets forth various specific details to provide an in - depth understanding of several example embodiments according to the description. Embodiments may be obtained without one or more of the specific details or with other methods, components, materials, etc. In some cases, well - known structures, materials, or operations are not shown or described in detail so as not to obscure different aspects of the embodiments. References to "an embodiment" in this specification indicate that a particular configuration, structure, or feature described relative to the embodiment is included in at least one embodiment. Thus, phrases such as "in one embodiment" that may appear in different places in this specification do not necessarily all refer to the same embodiment. Additionally, a particular form, structure, or feature may be combined in any suitable manner in one or more embodiments.

[0020] Embodiments of the present invention will be described in a particular context, namely, in a non - destructive memory BIST circuit and method for a system - on - chip (SoC) (such as a microcontroller or a processor) for automotive applications (e.g., during vehicle operation). Embodiments of the present invention can be used in other types of circuits, such as other circuits including memories such as volatile or non - volatile memory devices. Instead of or in addition to during vehicle operation, some embodiments may also perform memory tests during other times, such as when powering on or off. Some embodiments can be used in circuits and devices in applications different from automotive (such as industrial or consumer applications).

[0021] In an embodiment of the present invention, the BIST controller is capable of performing a non-destructive memory test on a memory, which advantageously allows a processor to cause the BIST controller to perform a memory test without the need to save the state of the memory before performing the memory test and without the need to restore the state of the memory after performing the memory test. In some embodiments, during the memory test, a write command to the memory flips (inverts) the content of the memory without the intervention of the BIST controller or the processor. In some such embodiments, by sending an even number of write commands to a specific address of the memory, the original data of the specific address is advantageously restored without the intervention of the BIST controller or the processor. In some embodiments, a memory fault is detected by comparing the content of the memory after an odd number of write commands with the content of the memory after an even number of write commands.

[0022] In some embodiments, the same write and read commands can be transmitted to multiple memories in parallel, which advantageously allows a processor to cause the BIST controller to perform a memory test to test multiple memories in parallel without the need to save the state of the memories before performing the memory test and without the need to restore the state of the memories after performing the memory test.

[0023] Figure 1 A schematic diagram of a BIST circuit 100 according to an embodiment of the present invention is shown. The BIST circuit 100 can be used to test a memory 102. The BIST circuit 100 includes a BIST controller 101, a BIST data path 118, multiplexers (MUXs) 104, 106, 108, and 110, a temporary register 112, an inverter 114, and a comparator circuit 115. The comparator circuit 115 can include an XOR gate 116. The circuits that are part of the BIST circuit 100, i.e., the circuits that do not include the BIST controller 101, can be collectively referred to as the BIST auxiliary circuit 103.

[0024] During normal operation (when the test mode signal S test is de-asserted, e.g., at Figure 1When the value in the illustrated embodiment is low, the processor 150 sends commands (e.g., read, write), a memory address, and write data to the memory 102, and receives read data from the memory 102 (depending on the command). For example, when the processor 150 sends a read command (via MUX 104) and a memory address (via MUX 106) to the memory 102, the memory 102 provides the read data associated with the memory address to the processor 150 in response to the read command (via MUX 110). As another example, when the processor 150 sends a write command (via MUX 104), a memory address (via MUX 106), and write data (via MUX 108) to the memory 102, the memory 102 stores the write data into the memory location associated with the memory address in response to the write command.

[0025] In some embodiments, the word lengths associated with the read data and the write data are 32 bits. Word lengths different from 32 bits (e.g., 16 bits or less, or 64 bits, 128 bits, 256 bits, 512 bits or more) may also be used.

[0026] In some embodiments, the temporary register 112 is capable of storing one data word. For example, if the data word Dout 102 has 32 bits, then the temporary register 112 has 32 bits (or more). The temporary register 112 can be implemented in any manner known in the art.

[0027] In some embodiments, the XOR gate 116 represents a plurality of XOR gates for performing a bitwise XOR operation between the content of the temporary register 112 and the content of the data Dout 102 The XOR gate 116 can be implemented in any manner known in the art.

[0028] In some embodiments, the inverter gate 114 represents a plurality of inverter gates for performing a bitwise inversion operation on the content of the temporary register 112. The inverter gate 114 can be implemented in any manner known in the art.

[0029] In some embodiments, the MUX 110 is configured to select between the data Dout 102 and the error data D 116perform a multiplexing operation therebetween; MUX 104 is configured to perform a multiplexing operation between command data received from processor 150 and command data received from BIST controller 101; MUX 106 is configured to perform a multiplexing operation between memory addresses received from processor 150 and memory addresses received from BIST controller 101; and MUX 108 is configured to perform a multiplexing operation between read data received from processor 150 and received data received from inverter gate 114. MUX 104, 106, 108, and 110 may be implemented in any manner known in the art.

[0030] During the memory test mode (when the test mode signal S test is asserted, e.g., high as in the embodiment shown in Figure 1 ), BIST controller 101 may send commands and memory addresses to memory 102 via MUX 104 and 106, respectively. As shown in Figure 1 , during the memory test mode, write data Din is provided by temporary register 112 (via inverter gate 114). 102 . In some embodiments, after the capture signal S capture is asserted, temporary register 112 latches data Dout 102 .

[0031] In some embodiments, BIST controller 101 may be implemented as a general-purpose or custom processor or controller, e.g., coupled to a memory (e.g., external and / or internal to BIST controller 101) and configured to execute instructions stored in such memory. For example, in some embodiments, BIST controller 101 may include one or more general-purpose or custom components such as a field-programmable gate array (FPGA), a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor (DSP) that can instantiate instructions. In some embodiments, BIST controller 101 may include a finite state machine (FSM). Other implementations are possible.

[0032] In some embodiments, processor 150 may be implemented as a general-purpose or custom processor. In some embodiments, processor 150 is configured to execute instructions stored in memory 102. In some embodiments, processor 150 is configured to process data stored in memory 102.

[0033] In some embodiments, memory 102 may be implemented as a volatile or non-volatile memory. For example, in some embodiments, memory 102 may be implemented as a synchronous dynamic random access memory (SDRAM), a dynamic random access memory (DRAM), Dynamic Random Access Memory and / or any other type of RAM memory, flash memory (e.g., NAND-based flash memory or NOR-based flash memory), Phase Change Memory (PCM), Resistive Random Access Memory (RRAM), Magnetoresistive Random Access Memory (MRAM), etc.

[0034] In some embodiments, the MBIST circuit 100 can be used for non-destructive memory testing. For example, Figure 2 illustrates waveforms associated with memory cells of a memory word located at address Addr in memory 102 being tested in a non-destructive manner according to an embodiment of the present invention i in view of Figure 1 to understand Figure 2 .

[0035] As Figure 2 shown, when the MBIST circuit 100 enters the memory test mode at time t 0 (when signal S test is asserted), the data stored at location Addr in memory 102 is P. After the first read command (which makes data P available for data Dout i ) and the first capture pulse (which causes the temporary register 112 to latch data Dout 102 ), data P is stored in the temporary register 112 at time t 102 . After the first write command, at time t 1 the inverted data ~P (received from the inverter gate 114 via the MUX 108 at data Din 2 ) is stored at location Addr in memory 102 102 . After the second read command and the second capture pulse, at time t i data ~P is stored in the temporary register 112. After the second write command, at time t 4 the original data P is stored again at location Addr in memory 102 5 i .

[0036] Figure 2 ​​As shown, if the number of write commands to a specific address of the memory 102 during the memory test mode is even, the memory cells associated with the specific memory address are utilized in a non-destructive manner (restoring the original data after each pair of write commands). Thus, in some embodiments, different command patterns (e.g., write, read, write, read; write, read, read, write, read, etc.) associated with a specific memory address can be executed to utilize the memory cells associated with such specific memory address to perform various memory tests (e.g., stuck-at-1 test, stuck-at-0 test, read disturb test, etc.) in a non-destructive manner.

[0037] Figure 2 The behavior of the output of the XOR gate 116 when there is no fault is also illustrated in the error data D 116 As Figure 2 shown, between time t 1 and t 3 , the output of the XOR 116 is 0 (this is because Dout 102 is equal to the data stored in the temporary register 112, which is equal to the original data P). Between time t 3 and t 4 , the outputs of the XOR 116 are all 1 (this is because Dout 102 is equal to the inverted data stored in the temporary register 112). After time t 4 , the output of the XOR 116 is 0 (this is because Dout 102 is equal to the data stored in the temporary register 112, which is equal to the inverted data ~P). The output of the XOR 116 is ignored before time t 1 .

[0038] The output of the XOR gate 116 deviating from the expected result (e.g., Figure 2 shown) indicates the presence of a fault associated with the address Addr i . Thus, in some embodiments, the BIST controller 101 sends a series of read and write commands to the memory 102, receives the output (or a compressed version of the output) from the XOR gate 116 via the BIST data path 118 (shown as the signal S result ), and compares the signal S result with the expected value (e.g., in a bit-by-bit manner). If the value of the signal S result is different from the expected value, a fault is detected, and the BIST controller 101 can report the presence of the fault to the processor 150 (and / or a conventional fault management circuit) via the signal S fault , for example.

[0039] In some embodiments, during a memory test mode, the BIST data path 118 is configured to deliver error data D 116 (or error data D 116 in a compressed form) to the BIST controller 101. In some embodiments, the BIST data path 118 may be implemented using logic circuits such as buffers and / or other logic gates.

[0040] As Figure 1 and 2 shown, the error data D 116 can be generated by the XOR gate 116. In some embodiments, different polarities and logic circuits (e.g., replacing the XOR gate 116 with an XNOR gate) may be used to generate the error data D 116 . When there is no fault, the polarity of the expected value of the error data D 116 may also change.

[0041] In some embodiments, a capture operation (e.g., asserting the capture signal S capture ) may be performed in conjunction with a read operation (e.g., each time a read command is executed). In some embodiments, the capture operation may be performed at other times, such as in conjunction with a write operation (e.g., each time a write command is executed).

[0042] Figure 3 FIG. shows a schematic diagram of a BIST circuit 300 according to an embodiment of the present invention. The BIST circuit 300 can be used to test the memory 102. The BIST circuit 300 operates in a similar manner to the BIST circuit 100. However, the BIST circuit 300 includes an inverter gate 312 as part of the comparator circuit 115.

[0043] Figure 4 illustrates waveforms associated with testing a memory cell having a memory word located at address Addr i in the memory 102 in a non-destructive manner. It can be understood in view of Figure 3 . Figure 4 .

[0044] As shown, Figure 4 the waveforms shown are very similar to Figure 2 the waveforms shown. However, Figure 4 the waveform of 312 illustrates the output of the inverter gate 312 (labeled D 116 ), and the expected value of the error data D Figure 2 is different from that in

[0045] due to the presence of the inverter gate 312. Figures 1 - 4 In some embodiments, asresult When deviating from the expected value, the BIST controller can detect a fault. For example, in Figure 1 and 2 In the illustrated embodiment, if a value other than all 0s is detected for S between time t 1 and t 3 and between time t 4 and t 6 or if a value other than all 1s is detected for S between time t result and t 3 and t 4 a fault is detected. As another example, in result the embodiment of Figure 3 and 4 if a value other than all 1s is detected for S between time t 11 and t 13 and between time t 14 and t 16 or if a value other than all 0s is detected for S between time t result and t 13 and t 14 a fault is detected. result

[0046] In some embodiments, the BIST controller 101 is configured to read the signal S result and compare the signal S result with a predetermined value during a specific time period (e.g., in a bit-by-bit manner), where the specific time is, for example, when the signal S result is expected to have a fixed predetermined value (e.g., 0) in the absence of a fault. For example, in Figure 3 and 4 In the illustrated embodiment, the BIST controller 101 can: when the expected value of the error data D 116 is 0 (e.g., between time t 13 and t 14 ), process the signal S result to determine whether there is a fault in the memory 102; and when the expected value of the signal S result is 1 (e.g., between time t 11 and t 13 and between time t 14 and t 16 ) or is indeterminate (e.g., between time t 10 and t 11 ), ignore the signal S result . By comparing the signal S result only when the expected data is equal to a fixed predetermined value (e.g., all 0s in the embodiment shown in Figure 4 ​As a result, some embodiments may simplify the determination of whether a fault exists and the implementation of signal compression in the BIST data path 118. For example, Figure 5 FIG. shows a schematic diagram illustrating a BIST data path 500 according to an embodiment of the present invention. In some embodiments, the BIST data path 118 may be implemented as the BIST data path 500. It can be understood in view of Figure 3 and 4 to understand Figure 5 .

[0047] As Figure 5 shown, the BIST data path 500 includes an OR gate 502 that performs an OR operation on M bits of data Dout MEM , where M is the word length associated with the memory 102. Thus, in some embodiments, the output bus Dout MEM can be compressed into a single-bit signal S result , and the BIST controller 101 can use the single-bit signal S result to determine (e.g., at a predetermined time, such as between time t 13 and t 14 ) whether a fault is detected.

[0048] In some embodiments, the OR gate 502 may be implemented at other circuit locations, such as between the output of the XOR gate 116 and the input of the MUX 110.

[0049] In some embodiments, the BIST controller 101 determines when to monitor and when to ignore the signal S result via software. In some embodiments, the BIST circuit (e.g., 100 or 300) may include circuitry for ignoring error data D 116 during a specific time period. For example, Figure 6 FIG. shows a schematic diagram illustrating a BIST data path 600 according to an embodiment of the present invention. In some embodiments, the BIST data path 118 may be implemented as the BIST data path 600. It can be understood in view of Figure 3 and 4 to understand Figure 6 .

[0050] The BIST data path 600 may operate in a manner similar to the BIST data path 500. However, the BIST data path 600 includes an AND gate 602 that serves as a masking circuit for masking the output of the OR gate 502 based on the signal S mask (e.g., when the signal S mask is asserted, such as being low). In some embodiments, the signal S mask is generated by the BIST controller 101, and when the BIST controller 101 monitors the signal Sresult during a period of time (e.g., at time t 13 and t 14 ), it is asserted (e.g., high), and during a time period when signal S result is ignored (e.g., between time t 10 and t 13 and between time t 14 and t 16 ), it is de-asserted (e.g., high). In some such embodiments, when signal S result is asserted (e.g., in the embodiment shown in Figure 6 , when signal S result changes from low to high), the BIST controller 101 can detect whether there is a fault in an asynchronous manner.

[0051] As Figure 5 and 6 shown, some embodiments can be used to detect whether there is a fault when the output of the comparator circuit 115 changes to a predetermined state (e.g., high), which can advantageously allow for compressing the output of the comparator circuit 115. Some embodiments can be implemented using different polarities. For example, Figure 7 and 8 show schematic diagrams illustrating BIST data paths 700 and 800 according to embodiments of the present invention. The BIST data path 118 can be implemented as the BIST data path 700 or 800. It can be understood in view of Figure 1 and 2 to understand Figure 7 and 8 .

[0052] As Figure 7 shown, when the expected value of the error data D 116 is all 1s, if any bit of the data Dout MEM becomes 0, then the signal S result becomes 0. Therefore, in some such embodiments, if the signal S result becomes 0, the BIST controller 101 can determine whether there is a fault.

[0053] As Figure 8 shown, the BIST controller 101 can assert the signal S result (e.g., high) during a period of time when the BIST controller 101 monitors the signal S 3 and t 4 and de-assert the signal S mask during a time period when the signal S result is ignored (e.g., between time t 0 and t 3 and between time t 4 and t6 de-assert the assertion signal S within mask (e.g., being low) to mask the output of the AND gate 702.

[0054] Figure 9 FIG. 9 shows a flow chart of an exemplary method 900 for testing the memory 102 according to an embodiment of the present invention. The method 900 may be executed by the BIST controller 101. It can be understood in view of Figure 3 to understand Figure 9 .

[0055] As Figure 9 shown, each of steps 904, 906, 908, and 910 includes various operations (read, capture, write, compare). For ease of understanding, Figure 9 the expected value of each operation when the comparator circuit 115 includes the inverter gate 312 (as Figure 3 shown) is shown in parentheses. It should be understood that Figure 9 the expected values shown are merely exemplary and different expected values may be used according to a particular implementation.

[0056] As Figure 9 shown, the method 900 is an example of a possible test sequence for testing the memory. It should be understood that different combinations of commands (read, write, capture, compare) may be used to test the memory. In some embodiments, the method 900 is non-destructive (preserving the original content of the memory) as long as an even (or zero) number of write operations are performed on each memory address of the memory.

[0057] During step 902, enter the memory test mode, for example, by asserting the test mode signal S test (e.g., being high). In some embodiments, the test mode signal S is asserted by the BIST controller 101 test . In some embodiments, the test mode signal S is asserted by the processor 150 test (where the signal S test is also received by the BIST controller 101 and triggers the BIST controller 101 to perform the memory test).

[0058] During step 904, the BIST controller 101 performs the following operations for each memory address of the memory 102:

[0059] - Transmit a read command to the memory 102 (via the MUX 104) such that the original data (labeled P) associated with the current address becomes available in the data Dout 102 ;

[0060] - Assert the capture signal S capture , such that from the data Dout102 The data (P) is stored in the temporary register 112;

[0061] - Transmit a write command to the memory 102 (via the MUX 104) such that the data Din 102 (~P) is stored at the current address;

[0062] - Transmit a read command to the memory 102 (via the MUX 104) such that the inverted data (~P) becomes available in the data Dout 102 ; and

[0063] - Read the output of S result (shown as the comparison command in Figure 9 ), at which time if there is no fault, the output of S result should be all 0s (this is because the data at the temporary register 112 is P, D 312 is ~P, and the data at Dout 102 is ~P).

[0064] In some embodiments, the operations performed for each memory address during step 904 are performed in ascending sequential order for each memory address.

[0065] After performing step 904 and before performing step 906, the content of each memory address of the memory 102 is the inverted data (~P) of the original data (P) of a specific memory address (this is because an odd number of write operations (only a single write operation) have been performed for each memory address at this time).

[0066] During step 906, the BIST controller 101 performs the following operations for each memory address of the memory 102:

[0067] - Transmit a read command to the memory 102 (via the MUX 104) such that the current data associated with the current address (which is the inverted original data ~P at this time) becomes available in the data Dout 102 ;

[0068] - Assert the capture signal S capture , such that the data (~P) from the data Dout 102 is stored in the temporary register 112;

[0069] - Transmit a write command to the memory 102 (via the MUX 104) such that the data Din 102 (P) is stored at the current address;

[0070] - Transmit a read command to the memory 102 (via the MUX 104) such that the data (P) becomes available in the data Dout102 becomes available in;

[0071] - Read S result 's output. At this time, if there is no fault, the output of S result should be all 0s (this is because the data at the temporary register 112 is ~P, D 312 is P, and the data at Dout 102 is P);

[0072] - Assert the capture signal S capture such that the data (P) from the data Dout 102 is stored in the temporary register 112;

[0073] - Transmit a write command to the memory 102 (via the MUX 104) such that the data Din 102 (~P) is stored at the current address;

[0074] - Transmit a read command to the memory 102 (via the MUX 104) such that the data (~P) becomes available in the data Dout 102 ; and

[0075] - Read S result 's output. At this time, if there is no fault, the output of S result should be all 0s (this is because the data at the temporary register 112 is P, D 312 is ~P, and the data at Dout 102 is ~P).

[0076] In some embodiments, the operations performed for each memory address during step 906 are performed in ascending order for each memory address in sequence.

[0077] After performing step 906 and before performing step 908, the content of each memory address of the memory 102 is the inverted data (~P) of the original data (P) of a specific memory address (this is because an odd number of write operations (3 write operations) have been performed for each memory address at this time).

[0078] During step 908, the BIST controller 101 performs the following operations for each memory address of the memory 102:

[0079] - Transmit a read command to the memory 102 (via the MUX 104) such that the inverted data (~P) becomes available in the data Dout 102 ;

[0080] - Assert the capture signal S capture such that the data from the data Dout102 The data (~P) is stored in the temporary register 112;

[0081] - Transmit a write command to the memory 102 (via the MUX 104) such that the data Din 102 (P) is stored at the current address;

[0082] - Transmit a read command to the memory 102 (via the MUX 104) such that the data (P) becomes available in the data Dout 102 ; and

[0083] - Read the output of S result (shown as the comparison command in Figure 9 ), at which time if there is no fault, the output of S result should be all 0s (this is because the data at the temporary register 112 is ~P, D 312 is P, and the data at Dout 102 is P).

[0084] In some embodiments, the operations performed during step 908 for each memory address are executed in descending sequential order for each memory address.

[0085] After executing step 908 and before executing step 910, the content of each memory address of the memory 102 is the original data (P) of a specific memory address (this is because an even number of write operations (4 write operations) have been performed for each memory address at this time).

[0086] During step 910, the BIST controller 101 performs the following operations for each memory address of the memory 102:

[0087] - Transmit a read command to the memory 102 (via the MUX 104) such that the current data associated with the current address (which is the original data P at this time) becomes available in the data Dout 102 ;

[0088] - Assert the capture signal S capture , such that the data (P) from the data Dout 102 is stored in the temporary register 112;

[0089] - Transmit a write command to the memory 102 (via the MUX 104) such that the data Din 102 (~P) is stored at the current address;

[0090] - Transmit a read command to the memory 102 (via the MUX 104) such that the data (~P) becomes available in the data Dout 102 ;

[0091] - Read the output of S result At this time, if there is no fault, the output of S result should be all 0s (this is because the data at the temporary register 112 is P, D 312 is ~P, and the data at Dout 102 is ~P);

[0092] - Assert the capture signal S capture such that the data from Dout 102 (~P) is stored in the temporary register 112;

[0093] - Transmit a write command to the memory 102 (via MUX 104) such that the data Din 102 (P) is stored at the current address;

[0094] - Transmit a read command to the memory 102 (via MUX 104) such that the data (P) becomes available in the data Dout 102 ; and

[0095] - Read the output of S result At this time, if there is no fault, the output of S result should be all 0s (this is because the data at the temporary register 112 is ~P, D 312 is P, and the data at Dout 102 is P).

[0096] In some embodiments, the operations performed for each memory address during step 910 are performed in a sequentially descending order for each memory address.

[0097] After performing step 910, the content of each memory address of the memory 102 is the original data of the specific memory address (this is because an even number of write operations (6 write operations) have been performed for each memory address at this time).

[0098] During step 912, if the signal S result is different from the expected value (e.g., 0) during any of steps 904, 906, 908, and 910, then the signal S fault is asserted (e.g., made high) to indicate that a fault has been detected (e.g., to the processor 150).

[0099] In some embodiments, step 912 is performed after step 910 (as Figure 9as shown). In some embodiments, step 912 is performed during the execution of steps 904, 906, 908, and 910 (e.g., in some embodiments, reporting a fault when a fault is detected).

[0100] In some embodiments, steps 904 and 906 may be performed in ascending order for each memory address, and steps 908 and 910 may be performed in descending order for each memory address. In some embodiments, the operations may be performed in a different order.

[0101] As Figure 9 shown, in some embodiments, the BIST controller 101 may perform a capture operation (e.g., asserting the capture signal S capture )(also referred to as an early write-back operation) before transmitting each write command. For example, in some embodiments, the write instruction executed by the BIST controller 101 includes asserting the capture signal S capture , and after asserting the capture signal S capture , transmitting a write command to the memory 102.

[0102] In some embodiments, the BIST controller 101 is capable of performing two types of read operations: a read-compare operation and a read-ignore operation. In some embodiments, the read-compare instruction executed by the BIST controller 101 includes transmitting a read command to the memory 102, and after transmitting the read command, performing a comparison operation to read the signal S result . In some embodiments, the read-ignore instruction executed by the BIST controller 101 includes transmitting a read command to the memory 102, but not performing a comparison operation after transmitting the read command.

[0103] As an illustrative example, in some embodiments implementing write instructions, read-compare instructions, and read-ignore instructions that include early write-back, the operation sequence shown in step 904 may be obtained by the BIST controller 101 executing the following instructions for each memory address:

[0104] Read-ignore instruction;

[0105] Write instruction;

[0106] Read-compare instruction.

[0107] Figure 10 shows a flowchart of an exemplary method 1000 for testing a memory 102 according to an embodiment of the present invention. The method 1000 may be executed by the BIST controller 101. It can be understood in view of Figure 1 to Figure 10 .

[0108] Method 10 includes steps 902, 1004, 1006, 1008, 1010, and 912. Method 1000 is very similar to Method 900. However, since the inverter gate 312 is not present in the BIST circuit 100, Method 1000 illustrates different expected values (1) during the comparison operations of steps 1004, 1006, 1008, and 1010.

[0109] Figure 11 A flowchart illustrating an example method 1100 for performing a memory test in accordance with an embodiment of the present invention is shown. Method 1100 may be implemented, for example, by a processor 150.

[0110] During step 1102, the processor (e.g., 150) causes a BIST circuit (e.g., 100 or 300) to perform a memory test (e.g., 900 or 1000) on a memory (e.g., 102). In some embodiments, the processor causes the BIST circuit to perform the memory test by asserting a test mode signal S test to perform the memory test. In some embodiments, the processor triggers the BIST controller 101 to perform the memory test, for example, using one or more (e.g., digital) signals, such as using a conventional digital communication interface coupled to the BIST circuit 101.

[0111] During step 1104, the processor receives an indication of whether a fault has been detected in the memory 102 from the BIST circuit (e.g., via signal S fault ). In some embodiments, the processor receives the fault indication via a conventional digital communication interface coupled to the BIST controller 101.

[0112] If a fault is detected during step 1106 based on the result received from the BIST circuit (output “yes”), the processor takes action, such as entering a safe mode, reporting an error to an external user (e.g., an external processor or controller), storing the fault in a log, etc.

[0113] As Figure 11 shown, steps 1102, 1104, and 1106 may be performed multiple times, such as during power-on (e.g., when turning on a vehicle application), during power-off (e.g., when turning off a vehicle application), performed as needed (e.g., by an external user), and / or at a predetermined (e.g., fixed) time interval.

[0114] As Figure 11 shown, the processor 150 may cause a memory test to be performed on the memory 102 without incurring the overhead of saving the state of the memory 102 before performing the memory test or restoring the state of the memory 102 after performing the memory test.

[0115] Figure 12 Illustrates a vehicle 1200 according to an embodiment of the present invention. The vehicle 1200 includes a processor 150, a memory 1204, and a BIST circuit 1202. In some embodiments, the BIST circuit 1202 may be implemented as the BIST circuit 100 or 300. In some embodiments, the processor 150 may execute the method 1100, for example, using a trigger signal MBIST trig Trigger the execution of a memory test (e.g., 900, 1000) to cause the BIST circuit 1202 to test the memory 1204.

[0116] In some embodiments, the memory 1204 may be implemented as the memory 102.

[0117] In some embodiments, the trigger signal MBIST trig Corresponds to a test mode signal S test . In some embodiments, the trigger signal MBIST trig Corresponds to (e.g., a digital) communication protocol.

[0118] In some embodiments, provide a signal S fault As a single digital signal asserted (e.g., asynchronously or synchronously) in response to a fault detection. In some embodiments, the signal S fault Corresponds to (e.g., a digital) communication protocol.

[0119] In some embodiments, the processor 150 may execute the method 1100 during vehicle operation (e.g., while driving) (e.g., periodically).

[0120] In some embodiments, the vehicle 1200 complies with the requirements of ASIL-D.

[0121] In some embodiments, the BIST circuit 1202 and the memory 1204 may be implemented as an integrated circuit, for example, in a single monolithic subtraction or in a multi-die integrated circuit. In some embodiments, such an integrated circuit may additionally include the processor 150. In some embodiments, the memory 1204 may be implemented external to the integrated circuit that includes the BIST circuit 1202. Other implementations are also possible.

[0122] Advantages of some embodiments include performing non-destructive memory tests (e.g., during vehicle operation) without the involvement of system software (e.g., running in a vehicle's processor) in the memory test process and without any time overhead associated with the system software saving and restoring the state of the target memory. Additional advantages of some embodiments include implementing potential fault metrics associated with the memory circuit, which complies with the requirements of ASIL-D defined by ISO 26262, having a small impact on silicon area, and having little or no time overhead.

[0123] In some embodiments, a BIST circuit (e.g., 100, 300, 1202) can be used to test multiple memories in parallel. For example, Figure 13 FIG. 4 shows a schematic diagram of a BIST circuit 1300 according to an embodiment of the present invention. The BIST circuit 1300 includes a BIST controller 101 and L BIST auxiliary circuits 103 (e.g., as Figure 1 implemented in FIG. 2 or 3), where L is greater than 1.

[0124] In some embodiments, the BIST circuit 1202 can be implemented as the BIST circuit 1300, and the memory 1204 can include L memories 102.

[0125] During normal operation, the processor 150 can access any one of the L memories 102, for example, via the corresponding MUXes 104, 106, and 110 ( Figure 13 not shown in FIG. 4).

[0126] During the memory test mode (when the test mode signal S test is asserted), the BIST controller 101 can test two or more (or all) of the L memories 102 in parallel. For example, as Figure 13 shown, in some embodiments, the same operation sequence (e.g., read, write, capture) and memory addresses are provided to the L memories 102. Each of the memories 102 provides a corresponding signal S result , and the signal S result can be independently analyzed by the BIST controller 101, for example, to determine whether a fault has been detected. For example, in some embodiments, the BIST controller 101 can execute method 900 or 1000 while independently analyzing the corresponding signal S result (e.g., during a comparison operation).

[0127] Since the memory tests performed by some embodiments are non-destructive (the original data is automatically restored after the memory test without the intervention of the BIST controller 101 or the processor 150), some embodiments are advantageously able to test multiple memories in parallel without the overhead of saving and restoring the memory state. By performing non-destructive memory tests on multiple memories in parallel, some embodiments are advantageously able to test the memories in (e.g., substantially) less time, which may help meet some safety requirements, such as some timing requirements associated with ASIL-D.

[0128] In some embodiments, the signals S from the L BIST auxiliary circuits 103 can be compressed result, and this compressed signal can be delivered to the BIST circuit 101. For example, Figure 14 and 15 FIGS. Figure 14 and 15 illustrate schematic diagrams of BIST circuits 1400 and 1500 according to embodiments of the present invention. In some embodiments, the BIST circuit 1202 can be implemented as the BIST circuit 1400 or 1500.

[0129] In some embodiments, the BIST circuits 1400 and 1500 operate in a manner similar to the BIST circuit 1300. However, the BIST circuit 1400 includes an OR gate 1402 that compresses L signals S from L BIST auxiliary circuits L into a signal S result compressed as signal S result (e.g., in embodiments where S result equal to 1 indicates a fault); and the BIST circuit 1500 includes an AND gate 1502 that compresses L signals S from L BIST auxiliary circuits L into a signal S result compressed as signal S result (e.g., in embodiments where S result equal to 0 indicates a fault).

[0130] In some embodiments where S result equal to 1 indicates a fault, each of the L BIST auxiliary circuits 103 can implement its corresponding BIST data path 118 as the BIST data path 500 or 600, and the corresponding output of the BIST data path 118 can be coupled to the OR gate 1402 (e.g., as Figure 14 shown), so that the BIST controller 101 can use a single comparison operation (based on a single signal S result ) to determine whether there is a fault in any of the L memories 102.

[0131] In some embodiments where S result equal to 0 indicates a fault, each of the L BIST auxiliary circuits 103 can implement its corresponding BIST data path 118 as the BIST data path 700 or 800, and the corresponding output of the BIST data path 118 can be coupled to the AND gate 1502 (e.g., as Figure 15 shown), so that the BIST controller 101 can use a single comparison operation (based on a single signal S result ) to determine whether there is a fault in any of the L memories 102.

[0132] In some embodiments, for example, in the BIST circuits 1300, 1400, or 1500, each of the L memories 102 can be the same as each other (e.g., having the same memory type, the same size, etc.).

[0133] In some embodiments, one or more (or all) of the L memories 102 may be different from each other (e.g., having different sizes, 1 port vs. 2 ports, etc.). For example, in some embodiments, each of the BIST assist circuits 103 may include a converter circuit (not shown) that may perform a conversion operation between the received command and memory address and the command and memory address provided to the associated memory 102, and may optionally deactivate or otherwise not test the associated memory 102 based on the received command and memory address. For example, in some embodiments, if the memory address is outside the acceptable memory range of the associated memory 102, the BIST assist circuit 103 may not forward the command to the associated memory 102 and may mask the associated signal S result and perform masking. Thus, in some embodiments, the BIST controller 101 may broadcast the same command and memory address in parallel to all L memories 102 (e.g., in sequence to cover the largest memory 102 among the L memories 102) to test all memories 102. In some such embodiments, when the memory address is within the memory range of the memory 102, each memory performs an operation (read, write, capture), and when the memory address is outside the memory range of the memory 102, each memory does not perform an operation.

[0134] For example, in an embodiment where L equals 2, the first memory 102 has a size of 1 kB while the second memory 102 has a size of 2 kB, the BIST controller 101 may perform a memory test (e.g., 900, 1000) by broadcasting an operation sequence on the memory addresses to be tested in ascending sequential order to the first and second memories 102. During the first 1 kB memory addresses, the first and second memories 102 are tested in parallel. During the last 1 kB memory address, only the first memory 102 is tested and the second memory 102 is not tested.

[0135] Example embodiments of the present invention are summarized herein. Other embodiments can also be understood from the entire specification and claims submitted herein.

[0136] Example 1. An electronic circuit, comprising: a memory including a data input, an address input, a command input, and a data output; a register having a data input coupled to the data output of the memory; a comparator circuit having a first data input coupled to the data output of the memory and a second data input coupled to the data output of the register; an inverter circuit having a data input coupled to the data output of the register and a data output coupled to the data input of the memory; and a controller having a command output coupled to the command input of the memory, an address output coupled to the address input of the memory, and a fault input coupled to the data output of the comparator circuit, wherein the controller is configured to determine whether the memory has a fault based on the fault input of the controller.

[0137] Example 2. The electronic circuit according to Example 1, wherein the controller is configured to test the memory by transmitting an even number of write commands to the command input of the memory.

[0138] Example 3. The electronic circuit according to any one of Examples 1 or 2, wherein the comparator circuit includes an XOR circuit having a first data input coupled to the data output of the memory, a second data input coupled to the data output of the register, and a data output coupled to the fault input of the controller.

[0139] Example 4. The electronic circuit according to any one of Examples 1 to 3, wherein the comparator circuit includes another inverter circuit having a data input coupled to the data output of the register and a data output coupled to the second data input of the XOR circuit.

[0140] Example 5. The electronic circuit according to any one of Examples 1 to 4, further comprising: a first multiplexer having a first data input coupled to the data output of the inverter circuit and a data output coupled to the data input of the memory; a second multiplexer having a first address input coupled to the address output of the controller and an address output coupled to the address input of the memory; and a third multiplexer having a first command input coupled to the command output of the controller and a command output coupled to the command input of the memory.

[0141] Example 6. The electronic circuit according to any one of Examples 1 to 5 further includes a fourth multiplexer having a first data input coupled to the data output of the memory, a second data input coupled to the data output of the comparator circuit, and a data output coupled to the fault input of the controller.

[0142] Example 7. The electronic circuit according to any one of Examples 1 to 6, wherein each of the first multiplexer, the second multiplexer, the third multiplexer, and the fourth multiplexer has a selection input configured to receive a test mode signal.

[0143] Example 8. The electronic circuit according to any one of Examples 1 to 7, wherein the controller is configured to provide the test mode signal to the first multiplexer, the second multiplexer, the third multiplexer, and the fourth multiplexer.

[0144] Example 9. The electronic circuit according to any one of Examples 1 to 8 further includes a processor, the processor including: a data output coupled to the second data input of the first multiplexer; an address output coupled to the second address input of the second multiplexer; a command output coupled to the second command input of the third multiplexer; and a data input coupled to the data output of the memory.

[0145] Example 10. The electronic circuit according to any one of Examples 1 to 9, wherein the controller is configured to provide a capture signal to the register, and wherein the register is configured to store data from the data output of the memory into the register when the capture signal is asserted.

[0146] Example 11. The electronic circuit according to any one of Examples 1 to 10, wherein the controller is configured to assert the capture signal before transmitting a write command to the memory whenever the controller transmits a write command to the memory.

[0147] Example 12. The electronic circuit according to any one of Examples 1 to 11, wherein the fault input of the controller is a single-bit input.

[0148] Example 13. The electronic circuit according to any one of Examples 1 to 12 includes an OR gate coupled between the data output of the comparator circuit and the fault input of the controller.

[0149] Example 14. The electronic circuit according to any one of Examples 1 to 13 includes an AND gate coupled between the data output of the comparator circuit and the fault input of the controller.

[0150] Example 15. The electronic circuit according to any one of Examples 1 to 14 includes a masking circuit coupled between the data output of the comparator circuit and the fault input of the controller, where the masking circuit is configured to mask the data output of the comparator circuit based on a masking signal.

[0151] Example 16. The electronic circuit according to any one of Examples 1 to 15, where the controller is configured to provide the masking signal to the masking circuit.

[0152] Example 17. The electronic circuit according to any one of Examples 1 to 16, where the electronic circuit is integrated in an integrated circuit.

[0153] Example 18. A device includes: a memory including a data input, an address input, a command input, and a data output; a register having a data input coupled to the data output of the memory; a comparator circuit having a first data input coupled to the data output of the memory and a second data input coupled to the data output of the register; an inverter circuit having a data input coupled to the data output of the register and a data output coupled to the data input of the memory; a controller having a command output coupled to the command input of the memory, an address output coupled to the address input of the memory, and a fault input coupled to the data output of the comparator circuit; a first multiplexer having a first data input coupled to the data output of the inverter circuit and a data output coupled to the data input of the memory; a second multiplexer having a first address input coupled to the address output of the controller and an address output coupled to the address input of the memory; and a third multiplexer having a first command input coupled to the command output of the controller and a command output coupled to the command input of the memory; and a processor including: a data output coupled to the second data input of the first multiplexer; an address output coupled to the second address input of the second multiplexer; a command output coupled to the second command input of the third multiplexer; and a data input coupled to the data output of the memory.

[0154] Example 19. The device according to Example 18, where the processor is configured to execute instructions stored in the memory.

[0155] Example 20. The apparatus according to any one of Examples 18 or 19, wherein the apparatus is an automobile.

[0156] Example 21. A method, comprising: asserting a test mode signal; after the test mode signal is asserted, transmitting a first memory address and a first read command to a first memory to cause the first memory to output first read data at a data output of the first memory; after transmitting the first read command to the first memory, storing the first read data in a first register; after storing the first read data in the first register, transmitting a first write command to the first memory to cause first input data at a data input of the first memory to be stored at the first memory address of the first memory, wherein the data input of the first memory is coupled to a data output of the first register via a first inverter circuit, and wherein the first input data corresponds to inverted first read data; after transmitting the first write command to the first memory, transmitting a second read command to the first memory to cause the first memory to output second read data at the data output of the first memory, wherein the second read data corresponds to the inverted first read data; and after transmitting the second read command to the first memory, comparing the first read data with the second read data using a first comparator circuit, and determining whether the first memory has a fault based on a data output of the first comparator circuit, the first comparator circuit comprising a first data input coupled to the data output of the first memory, a second data input coupled to the data output of the first register, and a data output.

[0157] Example 22. The method according to Example 21, wherein: transmitting the first memory address and the first read command to the first memory further comprises transmitting the first memory address and the first read command to a second memory to cause the second memory to output additional first read data at a data output of the second memory; transmitting the first write command to the first memory further comprises transmitting the first write command to the second memory to cause additional first input data at a data input of the second memory to be stored at the first memory address of the second memory, wherein the data input of the second memory is coupled to a data output of a second register via a second inverter circuit, and wherein the additional first input data corresponds to inverted additional first read data; and transmitting the second read command to the first memory further comprises transmitting the second read command to the second memory to cause the second memory to output additional second read data at the data output of the second memory, wherein the additional second read data corresponds to the inverted additional first read data, the method further comprising: after transmitting the second read command to the first memory and the second memory, comparing the additional first read data with the additional second read data using a second comparator circuit, and determining whether the second memory has a fault based on a data output of the second comparator circuit, the second comparator circuit comprising a first data input coupled to the data output of the second memory, a second data input coupled to the data output of the second register, and a data output.

[0158] Example 23. The method according to any one of Examples 21 or 22, wherein the data path circuit comprises a first input coupled to the data output of the first comparator circuit and a second input coupled to the data output of the second comparator circuit, the method further comprising determining that a fault exists in the first memory or the second memory in response to an output of the data path circuit being asserted.

[0159] Example 24. The method according to any one of Examples 21 to 23, wherein the first memory is a first type of memory, and the second memory is a second type of memory different from the first type.

[0160] Example 25. The method according to any one of Examples 0 to 24, wherein the first type comprises a first size, and the second type comprises a second size different from the first size.

[0161] In this specification, the term "coupled" may encompass a connection, communication, or signal path that implements a functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first instance, device A is coupled to device B by a direct connection; or (b) in a second instance, device A is coupled to device B through an intermediate component C, provided that the intermediate component C does not change the functional relationship between device A and device B, such that device B is controlled by device A via the control signal generated by device A.

[0162] A device "configured to" perform a task or function may be configured (e.g., programmed and / or hardwired) by a manufacturer to perform the function at the time of manufacture, and / or may be configured (or reconfigured) by a user after manufacture to perform the function and / or other additional or alternative functions. The configuration may be achieved through firmware and / or software programming of the device, through the construction and / or layout of the hardware components and interconnections of the device, or a combination thereof.

[0163] Although the present invention has been described with reference to illustrative embodiments, this specification is not limiting. This specification encompasses various modifications and combinations of the illustrative embodiments, as well as other embodiments of the present invention. The appended claims cover any such modifications or embodiments.

Claims

1. An electronic circuit, which comprises: a memory, which includes a data input, an address input, a command input, and a data output; a register, which includes a data input coupled to the data output of the memory; a comparator circuit, which includes a first data input coupled to the data output of the memory and a second data input coupled to the data output of the register; an inverter circuit, which includes a data input coupled to the data output of the register and a data output coupled to the data input of the memory; and a controller, which includes a command output coupled to the command input of the memory, an address output coupled to the address input of the memory, and a fault input coupled to the data output of the comparator circuit, wherein the controller is configured to determine whether the memory has a fault based on the fault input of the controller.

2. The electronic circuit according to claim 1, wherein the controller is configured to test the memory by transmitting an even number of write commands to the command input of the memory.

3. The electronic circuit according to claim 1, wherein the comparator circuit includes an XOR circuit, the XOR circuit having a first data input coupled to the data output of the memory, a second data input coupled to the data output of the register, and a data output coupled to the fault input of the controller.

4. The electronic circuit according to claim 3, wherein the comparator circuit includes another inverter circuit, the another inverter circuit having a data input coupled to the data output of the register and a data output coupled to the second data input of the XOR circuit.

5. The electronic circuit according to claim 1, which further comprises: a first multiplexer, which includes a first data input coupled to the data output of the inverter circuit and a data output coupled to the data input of the memory; a second multiplexer, which includes a first address input coupled to the address output of the controller and an address output coupled to the address input of the memory; and a third multiplexer, which includes a first command input coupled to the command output of the controller and a command output coupled to the command input of the memory.

6. The electronic circuit according to claim 5, which further includes a fourth multiplexer, the fourth multiplexer having a first data input coupled to the data output of the memory, a second data input coupled to the data output of the comparator circuit, and a data output coupled to the fault input of the controller.

7. The electronic circuit according to claim 6, wherein the first multiplexer, the second multiplexer, the third multiplexer, and the fourth multiplexer each have a selection input configured to receive a test mode signal.

8. The electronic circuit according to claim 7, wherein the controller is configured to provide the test mode signal to the first multiplexer, the second multiplexer, the third multiplexer, and the fourth multiplexer.

9. The electronic circuit according to claim 5, further comprising a processor, the processor comprising: a data output coupled to a second data input of the first multiplexer; an address output coupled to a second address input of the second multiplexer; a command output coupled to a second command input of the third multiplexer; and a data input coupled to the data output of the memory.

10. The electronic circuit according to claim 1, wherein the controller is configured to provide a capture signal to the register, and wherein the register is configured to store data output from the memory into the register when the capture signal is asserted.

11. The electronic circuit according to claim 10, wherein the controller is configured to assert the capture signal before transmitting the write command whenever the controller transmits a write command to the memory.

12. The electronic circuit according to claim 1, wherein the fault input of the controller is a single-bit input.

13. The electronic circuit according to claim 12, comprising an OR gate coupled between the data output of the comparator circuit and the fault input of the controller.

14. The electronic circuit according to claim 12, comprising an AND gate coupled between the data output of the comparator circuit and the fault input of the controller.

15. The electronic circuit according to claim 1, comprising a masking circuit coupled between the data output of the comparator circuit and the fault input of the controller, wherein the masking circuit is configured to mask the data output of the comparator circuit based on a mask signal.

16. The electronic circuit according to claim 15, wherein the controller is configured to provide the mask signal to the masking circuit.

17. The electronic circuit according to claim 1, wherein the electronic circuit is integrated in an integrated circuit.

18. A device, which comprises: a memory comprising a data input, an address input, a command input, and a data output; a register comprising a data input coupled to the data output of the memory; a comparator circuit comprising a first data input coupled to the data output of the memory, and a second data input coupled to the data output of the register; an inverter circuit comprising a data input coupled to the data output of the register, and a data output coupled to the data input of the memory; a controller comprising a command output coupled to the command input of the memory, an address output coupled to the address input of the memory, and a fault input coupled to the data output of the comparator circuit; A first multiplexer including a first data input coupled to the data output of the inverter circuit, a second data input, and a data output coupled to the data input of the memory; A second multiplexer including a first address input coupled to the address output of the controller, a second address input, and an address output coupled to the address input of the memory; And A third multiplexer including a first command input coupled to the command output of the controller, a second command input, and a command output coupled to the command input of the memory; And A processor including: A data output coupled to the second data input of the first multiplexer; An address output coupled to the second address input of the second multiplexer; A command output coupled to the second command input of the third multiplexer; and A data input coupled to the data output of the memory.

19. The apparatus according to claim 18, wherein the processor is configured to execute instructions stored in the memory.

20. The apparatus according to claim 18, wherein the apparatus is an automobile.

21. A method that includes: Asserting a test mode signal; After the test mode signal is asserted, transmitting a first memory address and a first read command to a first memory to cause the first memory to output first read data at the data output of the first memory; After transmitting the first read command to the first memory, storing the first read data in a first register; After storing the first read data in the first register, transmitting a first write command to the first memory to cause first input data at the data input of the first memory to be stored at the first memory address of the first memory, wherein the data input of the first memory is coupled to the data output of the first register via a first inverter circuit, and wherein the first input data corresponds to the inverted first read data; After transmitting the first write command to the first memory, transmitting a second read command to the first memory to cause the first memory to output second read data at the data output of the first memory, wherein the second read data corresponds to the inverted first read data; And After transmitting the second read command to the first memory, comparing the first read data with the second read data using a first comparator circuit, and determining whether the first memory has a fault based on the data output of the first comparator circuit, the first comparator circuit including a first data input coupled to the data output of the first memory, a second data input coupled to the data output of the first register, and a data output.

22. The method according to claim 21, wherein: Transmitting the first memory address and the first read command to the first memory further includes transmitting the first memory address and the first read command to a second memory to cause the second memory to output additional first read data at a data output of the second memory; Transmitting the first write command to the first memory further includes transmitting the first write command to the second memory to cause additional first input data at a data input of the second memory to be stored at the first memory address of the second memory, wherein the data input of the second memory is coupled to a data output of a second register via a second inverter circuit, and wherein the additional first input data corresponds to inverted additional first read data; and Transmitting the second read command to the first memory further includes transmitting the second read command to the second memory to cause the second memory to output additional second read data at the data output of the second memory, wherein the additional second read data corresponds to the inverted additional first read data, the method further comprising: after transmitting the second read command to the first memory and the second memory, comparing the additional first read data with the additional second read data using a second comparator circuit, and determining whether the second memory has a fault based on a data output of the second comparator circuit, the second comparator circuit including a first data input coupled to the data output of the second memory, a second data input coupled to the data output of the second register, and a data output.

23. The method according to claim 22, wherein the data path circuit includes a first input coupled to the data output of the first comparator circuit and a second input coupled to the data output of the second comparator circuit, the method further comprising determining that a fault exists in the first memory or the second memory in response to an output of the data path circuit being asserted.

24. The method according to claim 22, wherein the first memory is a first type of memory, and the second memory is a second type of memory different from the first type.

25. The method according to claim 24, wherein the first type includes a first size, and the second type includes a second size different from the first size.

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