Method for manufacturing semiconductor device, and semiconductor device

Abstract

A method of manufacturing a semiconductor device includes: preparing a semiconductor package having a package substrate and a plurality of solder balls located on one surface of the package substrate, and a mother board having a plurality of metal pads and a plurality of solder pastes disposed on a portion of the metal pads, a step for disposing the semiconductor package and the mother board such that the plurality of solder balls face the plurality of metal pads; and a step of heating the semiconductor package and the mother board and electrically bonding the plurality of solder balls and the plurality of metal pads, in the disposing step, the mother board in which the solder paste is not disposed on the metal pads disposed on at least a portion of the peripheral end portion side is prepared, and the semiconductor package and the mother board are disposed with a spacer therebetween.

Description

Technical Field

[0001] The present disclosure relates to a method for manufacturing a semiconductor device and a semiconductor device. Background Art

[0002] In recent years, in electronic devices such as computers, the signals used have become faster and larger in capacity, leading to an increase in size. The high integration and high functionality of semiconductor packages used in these electronic devices are also developing.

[0003] A semiconductor package is formed by mounting a semiconductor chip made of an inorganic compound such as silicon on an organic substrate containing resin or the like. The semiconductor package is electrically connected to a motherboard or the like via solder or the like.

[0004] In a semiconductor package, warpage may occur due to stress caused by the difference in the coefficient of linear expansion between the semiconductor chip and the organic substrate. The warpage of the semiconductor package increases as the package becomes larger, becoming a major cause of failure to connect smoothly when mounting on a motherboard or the like.

[0005] As a method for mounting a semiconductor package with warpage on a motherboard, a method of previously providing a spacer between the semiconductor package and the motherboard is cited (for example, refer to Non-Patent Document 1).

[0006] Furthermore, there is a method of changing the amount of solder paste applied to the motherboard side corresponding to the warpage shape of the semiconductor package (for example, refer to Patent Document 1). Specifically, in Patent Document 1, it is described that in a printed wiring board such as a motherboard, a welding material is printed on a plurality of pads connected to solder balls of an electronic component in such a manner that the amount of the welding material decreases from the center toward the outside.

[0007] Prior Art Documents

[0008] Patent Documents

[0009] Patent Document 1: Japanese Unexamined Patent Application Publication No. 2009-76812

[0010] Non-Patent Documents

[0011] Non-Patent Document 1: Fletcher (Cheng Piao) Tung et al., Challenges of Large Body FCBGA on Board Level Assembly and Reliability, 2018 IEEE 68th Electronic Components and Technology Conference Summary of the Invention

[0012] Technical Problem to be Solved by the Invention

[0013] In recent years, semiconductors used in computers, servers, etc. have been becoming multifunctional, and along with this, the package substrates and semiconductor packages on which semiconductor chips are mounted have been increasing in size. Further, along with the increase in size of the semiconductor package, the warpage amount and mass of the entire semiconductor package formed by connecting the semiconductor chip and the package substrate have been continuously increasing.

[0014] Furthermore, according to the research by the present inventors, when spacers are provided at the ends of the semiconductor package as described in Non-Patent Document 1 to suppress the contact between solder balls, sometimes the connection between the semiconductor package and the motherboard becomes difficult. The reason is that in the central portion of the semiconductor package in a top view, the gap between the semiconductor package and the motherboard at the melting temperature of the solder balls becomes wide, and poor connection between the two is likely to occur.

[0015] On the other hand, it is known that if solder paste is added to the connection portion on the motherboard side and the motherboard and the semiconductor package are connected by reflow soldering, the phenomenon that the solder balls at the ends of the semiconductor package come into contact with adjacent solder balls (also referred to as bridging) is likely to cause a short circuit.

[0016] It is easy to cause poor connection at the ends and central portions of the semiconductor package and the motherboard as described above, resulting in a reduction in the yield rate, which is the main cause of increasing the manufacturing cost of the semiconductor device. In addition, in the case where solder paste is added to the connection portion on the motherboard side in such a manner that the amount of solder paste decreases from the center of the motherboard toward the outside as in Patent Document 1, it is necessary to change the addition amount of solder paste according to the position of the motherboard. Therefore, the process of applying the solder paste becomes complicated, and there is a problem of low manufacturing efficiency of the semiconductor device.

[0017] The present disclosure has been completed in view of the above-described conventional situation, and an object thereof is to provide a method for manufacturing a semiconductor device that can reduce poor connection at the ends and central portions of the semiconductor package and the motherboard and has excellent manufacturing efficiency of the semiconductor device.

[0018] An object of the present disclosure is to provide a semiconductor device in which poor connection at the ends and central portions of the semiconductor package and the motherboard is reduced.

[0019] [Means for Solving Technical Problems]

[0020] Specific means for solving the above technical problems are as follows.

[0021] <1> A method for manufacturing a semiconductor device, including the following steps:

[0022] Prepare a semiconductor package and a mother board. The semiconductor package has a package substrate and a plurality of solder balls located on one surface of the package substrate. The mother board has a plurality of metal pads and a plurality of solder pastes disposed on a part of the plurality of metal pads. A process of disposing the semiconductor package and the mother board such that the plurality of solder balls face the plurality of metal pads; and

[0023] A process of heating the semiconductor package and the mother board to electrically connect the plurality of solder balls and the plurality of metal pads,

[0024] In the disposing process, prepare the mother board on which the solder paste is not disposed on at least a part of the metal pads on the peripheral end side, and dispose the semiconductor package and the mother board with a spacer therebetween.

[0025] <2>The manufacturing method of the semiconductor device according to <1>, regarding the plurality of solder pastes, the volume of the solder paste for each metal pad is independently 0.01 mm 3 to 0.03 mm 3 .

[0026] <3>The manufacturing method of the semiconductor device according to <1> or <2>, regarding the plurality of solder pastes, the volume of the solder paste for each metal pad is 80% or more with respect to the maximum volume of the solder paste for each metal pad, respectively and independently.

[0027] <4>The manufacturing method of the semiconductor device according to any one of <1> to <3>, form the plurality of solder pastes on a part of the plurality of metal pads by screen printing.

[0028] <5>The manufacturing method of the semiconductor device according to any one of <1> to <4>, the height of the spacer in a cross-sectional view is 0.2 mm to 0.3 mm.

[0029] <6>The manufacturing method of the semiconductor device according to any one of <1> to <5>, the area of the semiconductor package in a top view is 2500 mm 2 or more.

[0030] <7>The manufacturing method of the semiconductor device according to any one of <1> to <6>, the package substrate is rectangular in a top view, and the lengths of the four sides of the package substrate in a top view are 50 mm or more, respectively and independently.

[0031] <8>The manufacturing method of the semiconductor device according to any one of <1> to <7>, the mass of the semiconductor package is 100 g or more.

[0032] <9>The manufacturing method of the semiconductor device according to any one of <1> to <8>, wherein the package substrate includes a core layer including a copper-clad laminate.

[0033] <10>The manufacturing method of the semiconductor device according to any one of <1> to <9>, wherein the semiconductor package includes a silicon interposer or a plurality of semiconductor chips, and when the semiconductor package includes a silicon interposer, the silicon interposer is mounted on the package substrate in electrical connection with the plurality of semiconductor chips.

[0034] <11>A semiconductor device

[0035] A semiconductor package having a package substrate and a plurality of solder balls on one surface of the package substrate is electrically joined to a mother board having a plurality of metal pads via the plurality of solder balls and the plurality of metal pads.

[0036] In the plurality of connection portions formed by electrically joining the plurality of solder balls and the plurality of metal pads, the ratio of the minimum value of the solder volume of each connection portion to the maximum value of the solder volume of each connection portion is 0.6 to 0.95.

[0037] <12>The semiconductor device according to <11>, wherein the ratio of the solder volume of each connection portion in at least one connection portion located at the peripheral end portion of the semiconductor package to the solder volume of each connection portion in at least one connection portion located at the central portion of the semiconductor package is 0.6 to 0.95.

[0038] <13>The semiconductor device according to <11>, wherein the package substrate is rectangular in plan view, and the solder volume of each connection portion at the corner of the rectangle is smaller than the solder volume of each connection portion at a position other than the corner.

[0039] <14>The semiconductor device according to any one of <11> to <13>, wherein the package substrate includes a core layer including a copper-clad laminate.

[0040] <15>The semiconductor device according to any one of <11> to <14>, wherein the semiconductor package includes a silicon interposer or a plurality of semiconductor chips, and when the semiconductor package includes a silicon interposer, the silicon interposer is mounted on the package substrate in electrical connection with the plurality of semiconductor chips.

[0041] [Advantages of the Invention]

[0042] According to the present disclosure, it is possible to provide a manufacturing method of a semiconductor device that can reduce connection failures at the ends and the center of a semiconductor package and a mother board and has excellent manufacturing efficiency of the semiconductor device.

[0043] The present disclosure can provide a semiconductor device that reduces connection failures at the ends and the central portion of a semiconductor package and a mother board. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 FIG. is a cross-sectional view showing the structure of a semiconductor device manufactured by the manufacturing method of the present disclosure.

[0045] Figure 2 FIG. is a cross-sectional view showing the structure of a sample imitating the semiconductor device.

[0046] Figure 3 FIG. is a top view showing the mother board used in the production of the sample. DETAILED DESCRIPTION

[0047] Hereinafter, embodiments of the present disclosure will be described in detail. However, the present disclosure is not limited to the following embodiments. In the following embodiments, unless otherwise specifically stated, its constituent elements (including element steps, etc.) are not essential. The numerical values and their ranges also do not limit the present disclosure.

[0048] In the present disclosure, the term "process" includes not only a process independent of other processes, but also a process that cannot be clearly distinguished from other processes, provided that the purpose of the process is achieved.

[0049] In the numerical range represented by "~" in the present disclosure, the numerical values described before and after "~" are included as the minimum value and the maximum value, respectively.

[0050] In the numerical ranges described stepwise in the present disclosure, the upper limit value or the lower limit value described in one numerical range can also be replaced with the upper limit value or the lower limit value of other stepwise described numerical ranges. In addition, in the numerical ranges described in the present disclosure, the upper limit value or the lower limit value of the numerical range can also be replaced with the value shown in the examples.

[0051] <Method for Manufacturing a Semiconductor Device>

[0052] The manufacturing method of the semiconductor device of the present disclosure is as follows, including the following steps: preparing a semiconductor package and a mother board, the semiconductor package having a package substrate and a plurality of solder balls on one surface of the package substrate, the mother board having a plurality of metal pads and a plurality of solder pastes disposed on a part of the metal pads among the plurality of metal pads, and arranging the semiconductor package and the mother board such that the plurality of solder balls face the plurality of metal pads (hereinafter, also referred to as "arrangement step"); and

[0053] A step of heating the semiconductor package and the mother board to electrically connect the plurality of solder balls and the plurality of metal pads (hereinafter, also referred to as "connection step").

[0054] In the placement step, a mother board on which the solder paste is not disposed on at least a part of the peripheral end side is prepared, and the semiconductor package and the mother board are placed with a spacer therebetween.

[0055] In the manufacturing method of the present disclosure, the semiconductor package and the mother board are placed with a spacer therebetween in a state where the solder paste is not disposed on the metal pads disposed on at least a part of the peripheral end side of the mother board. Then, the semiconductor package and the mother board are heated to electrically connect the plurality of solder balls and the plurality of metal pads, thereby manufacturing a semiconductor device. Thereby, it is possible to reduce connection failures at the ends and the central portion of the semiconductor package and the mother board, and the manufacturing efficiency of the semiconductor device is excellent. The reason is presumed as follows. In addition, the present disclosure is not limited to the following presumption.

[0056] By placing the semiconductor package and the mother board with a spacer therebetween, there is a tendency that it is possible to reduce the generation of bridging in which the solders adjacent to the ends of the semiconductor package and the mother board come into contact with each other in the connection step. On the other hand, even when a spacer is used, the gap between the semiconductor package and the mother board at the melting temperature of the solder balls becomes wider at the central portion of the semiconductor package, and connection failures between the two are likely to occur. When the amount of the solder paste applied to the metal pads is increased, the above-mentioned connection failures at the central portion can be reduced, but there is a problem that bridging is likely to occur at the above-mentioned ends.

[0057] In the present disclosure, the plurality of solder balls and the plurality of metal pads are electrically connected in a state where the solder paste is not disposed on the metal pads disposed on at least a part of the peripheral end side of the mother board. Thereby, by the metal pads on which the solder paste is disposed at the central portion and the like, the amount of the solder paste is increased, and the connection failures at the above-mentioned central portion can be reduced. And, on the above-mentioned peripheral end side, since the solder paste is not disposed on a part of the metal pads, the generation of bridging in which adjacent solders come into contact with each other can also be reduced.

[0058] In addition, by using a printing technique such as screen printing, the solder paste can be selectively disposed on the plurality of metal pads. Therefore, by a simple process, a mother board in which the solder paste is not disposed on a part of the metal pads and the solder paste is disposed on the other metal pads can be obtained. Therefore, compared with the case where the solder paste is disposed on the plurality of metal pads in such a manner that the amount of the solder paste decreases from the center to the outside of the mother board, the process of disposing the solder paste is simple, and the manufacturing efficiency of the semiconductor device is excellent.

[0059] [Placement Step]

[0060] The manufacturing method of the present disclosure includes: a step (configuration step) of preparing the aforementioned semiconductor package and the aforementioned mother board so that a plurality of solder balls face a plurality of metal pads.

[0061] (Semiconductor package)

[0062] The semiconductor package used in the manufacturing of a semiconductor device has a package substrate and a plurality of solder balls located on one surface of the package substrate.

[0063] The package substrate has a plurality of solder balls. The plurality of solder balls are electrically connected to the metal pads provided on the mother board. The plurality of solder balls are respectively located at positions corresponding to the connection parts, which are the connection parts with the metal pads provided on the mother board.

[0064] The package substrate can, for example, include a build-up layer, a core layer, a solder mask layer, etc., and these layers can also be laminated. For example, when observing the package substrate from the side of the surface where a plurality of solder balls are provided, a build-up layer, a core layer, and a build-up layer can be laminated in sequence, or a solder mask layer, a build-up layer, a core layer, a build-up layer, and a solder mask layer can be laminated in sequence. The package substrate can also have through holes, via holes, etc.

[0065] The package substrate can also have a core layer including a copper-clad laminate. The copper-clad laminate is, for example, a component in which copper foils are laminated on both sides of an insulating layer including a glass cloth impregnated with resin.

[0066] From the viewpoint of heat resistance, the glass transition temperature Tg of the insulating layer measured by the tensile method of dynamic viscoelasticity measurement (DMA) can be 200 °C or higher, can be 250 °C to 400 °C, can be 280 °C to 350 °C, or can be 300 °C to 350 °C.

[0067] The linear expansion coefficient α1 of the insulating layer measured by the compression method of thermomechanical analysis (TMA) can be 3.0 ppm / °C to 15.0 ppm / °C, can also be 4.0 ppm / °C to 11.0 ppm / °C, can further be 5.0 ppm / °C to 8.0 ppm / °C, or can further be 5.5 ppm / °C to 8.0 ppm / °C. By setting the linear expansion coefficient α1 of the insulating layer to 5.0 ppm / °C or higher, there is a tendency to be able to produce a semiconductor device with a high yield that can simultaneously reduce solder bridging and reduce connection failures.

[0068] The linear expansion coefficient α1 of the insulating layer refers to the linear expansion coefficient smaller than the glass transition temperature of the insulating layer.

[0069] The linear expansion coefficient α2 of the insulating layer measured by the compression method through thermomechanical analysis (TMA) can be 0.1 ppm / °C to 3.0 ppm / °C, can also be 0.3 ppm / °C to 2.0 ppm / °C, and can further be 0.5 ppm / °C to 1.5 ppm / °C.

[0070] The linear expansion coefficient α2 of the insulating layer refers to the linear expansion coefficient above the glass transition temperature of the insulating layer.

[0071] The storage modulus of the insulating layer measured by the tensile method through dynamic viscoelasticity measurement (DMA) at 30°C can be 15 GPa to 40 GPa, can also be 20 GPa to 35 GPa, and can further be 20 GPa to 30 GPa.

[0072] The storage modulus of the insulating layer measured by the tensile method through dynamic viscoelasticity measurement (DMA) at 260°C can be 10 GPa to 30 GPa, can also be 12 GPa to 25 GPa, and can further be 15 GPa to 25 GPa.

[0073] The semiconductor package may also have components other than the package substrate and a plurality of solder balls. For example, the semiconductor package may include an interposer, a semiconductor chip, a stiffener, a lid, etc.

[0074] The interposer is a component for electrically connecting between a plurality of semiconductor chips and the package substrate, and is disposed on the package substrate. Examples of the interposer include a silicon interposer and an organic interposer.

[0075] When the semiconductor package has an interposer, from the viewpoint of fine connection between semiconductor chips, the semiconductor package preferably has a silicon interposer on the package substrate. Compared with organic materials, silicon can perform electrical connection through fine wiring. By using a silicon interposer with a linear expansion coefficient similar to that of the semiconductor chip, the reliability between the electrically connected semiconductor chips is good. Furthermore, when using a silicon interposer, a plurality of semiconductor chips are mounted on the silicon interposer, and after performing processes such as sealing, the silicon interposer is mounted on the package substrate. Therefore, compared with the case where an organic interposer is mounted on the package substrate side and semiconductor chips are individually mounted on the organic interposer, it is easier to improve the yield, and there is a tendency that the manufacturing efficiency of qualified products is excellent.

[0076] The semiconductor chip includes processors such as a CPU (Central Processing Unit) and a GPU (Graphics Processing Unit), memories such as a DRAM (Dynamic Random Access Memory) and a NAND, a power circuit, a sensor, etc.

[0077] The semiconductor chip can also be a processor or a system-on-chip (SoC) with a processor, a memory such as a high-bandwidth memory (HBM) in which multiple DRAMs (dynamic random access memories) are stacked, etc., and the semiconductor chips are three-dimensionally assembled (3D assembled) by stacking them vertically. Alternatively, the semiconductor chip can also be a semiconductor chip in which a processor or an SoC, a memory such as an HBM, etc. are respectively mounted on an interposer such as a silicon interposer in a planar direction (for example, a semiconductor chip assembled in 2.5D).

[0078] The semiconductor chip is mounted on a package substrate, an interposer, etc., and the semiconductor chip is connected to wirings formed on the package substrate, the interposer, etc. by solder bumps or wire bonding. Further, the space between the semiconductor chip and the package substrate, the interposer, etc. can be sealed with a sealing material such as underfill material.

[0079] One semiconductor chip can be disposed on the package substrate, or multiple semiconductor chips can be disposed. The semiconductor chip disposed on the package substrate can also be sealed with a sealing material such as liquid molding compound (LMC). Further, in the case where multiple semiconductor chips are disposed, the entire multiple semiconductor chips can also be sealed with a sealing material.

[0080] The reinforcing member is a member for reducing the warpage of the semiconductor package. For example, in a plan view, the reinforcing member can be disposed on the outer peripheral portion of the package substrate, or can be disposed on a part or the entire outer peripheral portion. The shape of the reinforcing member is not particularly limited and can be a frame shape, a rod shape, etc. The material, width, etc. of the reinforcing member can also be adjusted according to the linear expansion coefficient of the material constituting the package substrate, the area ratio of the semiconductor chip in the semiconductor package in a plan view, etc. The width of the reinforcing member can be, for example, 10 mm to 30 mm, or can be 15 mm to 25 mm.

[0081] The material of the reinforcing member is not particularly limited, and examples include copper alloys such as copper, Cu-Mo alloy, and Cu-W alloy, and SUS such as SUS304 and SUS430. The reinforcing member can also be bonded to the package substrate using an adhesive, etc. A plating treatment can also be performed on the surface of the reinforcing member to improve the bonding strength.

[0082] The lid is a member that covers the semiconductor chip and can function as a member for dissipating heat generated by the semiconductor chip. The material of the lid is not particularly limited, and from the viewpoint of heat dissipation, a metal with a small thermal resistance such as copper is preferred.

[0083] The area of the semiconductor package in a plan view can be 2500 mm 2 The above can be 4000 mm2 Above, it can also be 5000 mm 2 Above, it can also be 5625 mm 2 Above (for example, 75 mm × 75 mm or more), it can also be 6400 mm 2 ~22500 mm 2 . Generally, when mounting a large semiconductor package on a mother board, connection failures are likely to occur. In the manufacturing method of the present disclosure, even when using a relatively large semiconductor package with the above-mentioned area of 2500 mm 2 or more, it is possible to appropriately reduce connection failures at the ends and the central part.

[0084] When the package substrate is rectangular in a top view, the lengths of the four sides of the package substrate in the top view can be independently 50 mm or more, or can be 60 mm or more, or can be 75 mm or more, or can also be 80 mm or more, or can also be 80 mm to 150 mm. In the manufacturing method of the present disclosure, even when using a relatively large semiconductor package with the above-mentioned length of 50 mm or more, it is possible to appropriately reduce connection failures at the ends and the central part.

[0085] The mass of the semiconductor package can be 100 g or more, or can be 100 g to 300 g, or can also be 120 g to 200 g. Generally, when mounting a semiconductor package with a large mass on a mother board, bridging is likely to occur due to the self-weight of the semiconductor package. In the manufacturing method of the present disclosure, even when using a relatively heavy semiconductor package with the above-mentioned mass of 100 g or more, it is possible to appropriately reduce the occurrence of bridging.

[0086] (Mother board)

[0087] The mother board used in the manufacturing of the semiconductor device is a component electrically connected to the semiconductor package, and includes a plurality of metal pads electrically connected to a plurality of solder balls provided on the semiconductor package. Solder paste is respectively disposed on a part of the metal pads (two or more metal pads) among the plurality of metal pads.

[0088] The mother board can also be a conventionally known electronic circuit board used in semiconductor mounting.

[0089] In the mother board used in the manufacturing of the semiconductor device, solder paste is not disposed on the metal pads disposed at least partially on the peripheral end side among the plurality of metal pads. As a method of selectively disposing solder paste on the plurality of metal pads, there is no particular limitation, and screen printing, inkjet printing, spray printing, etc. can be cited. Among them, from the viewpoint of productivity, screen printing or inkjet printing is preferred.

[0090] Solder paste can also be separately formed on a part of the plurality of metal pads (more than 2 metal pads) by screen printing. For example, an opening member (such as a stencil) having a plurality of openings is arranged to face the plurality of metal pads, solder paste is applied to the opening member, and the solder paste is printed on the metal pads facing the openings using a squeegee. At this time, by performing screen printing in a state where the metal pads where solder paste is not arranged, for example, at least a part of the metal pads arranged on the peripheral end side, are shielded, a mother board without solder paste arranged on at least a part of the metal pads arranged on the peripheral end side can be easily obtained. Or, from the viewpoints of improving productivity, reducing foreign matter mixing, etc., screen printing can also be performed using an opening member that does not have an opening at a position facing the metal pads where solder paste is not arranged, for example, an opening member that does not have an opening at a position facing the metal pads arranged on at least a part of the peripheral end side.

[0091] Solder paste can also be separately formed on a part of the plurality of metal pads (more than 2 metal pads) by inkjet printing. By the settings, programs, etc. of inkjet printing, it is easy to adjust the part where the solder paste is formed and the amount of the solder paste.

[0092] The metal pads where solder paste is not arranged only need to be the metal pads arranged on at least a part of the peripheral end side. For example, it can also be that no solder paste is arranged on all the metal pads arranged on the peripheral end side.

[0093] For example, when the package substrate is rectangular in plan view, it is preferable that a plurality of solder balls are arranged along the outer periphery of the rectangle, and it is more preferable that a plurality of metal pads are also arranged in a manner facing the plurality of solder balls (Structure 1). At this time, it is preferable that no solder paste is arranged on the metal pads located at the corners in the rectangular area of the mother board where a plurality of metal pads are arranged. In this area, for the metal pads arranged on the peripheral end side other than the corners, solder paste can be arranged or not arranged.

[0094] In the rectangular area where a plurality of metal pads are arranged in the above Structure 1, the length Y ( Figure 3 Y in Figure 3 X in Figure 3 The dot in

[0095] means the arrangement of the metal pads) of the part where no solder paste is arranged on the metal pads in the direction of this one side starting from the corner relative to the length X of this one side (Figure 3 The ratio (Z / X) of Z) in

[0096] In addition, the configuration, size, distance between metal pads, density, etc. of the metal pads are not limited to Figure 3 the structure of

[0097] The numerical range of the above-mentioned length X is the same as the numerical range of the lengths of the four sides of the package substrate when viewed from above, and can be 50 mm or more, can be 60 mm or more, can be 75 mm or more, can be 80 mm or more, and can also be 80 mm to 150 mm.

[0098] The above-mentioned length Y can be 5 mm to 50 mm, can be 10 mm to 40 mm, can be 15 mm to 25 mm, and can also be 20 mm to 25 mm.

[0099] The above-mentioned length Z can be 0.5 mm to 25 mm, can be 1 mm to 20 mm, can be 2 mm to 15 mm, and can also be 4 mm to 10 mm.

[0100] The proportion of the metal pads without solder paste among the multiple metal pads arranged on the mother board can be 35% or less by number, or can be 9% to 25% by number.

[0101] Regarding the solder paste arranged on two or more metal pads respectively, the volume of the solder paste on each metal pad can be independently 0.01 mm 3 to 0.03 mm 3 also can be 0.015 mm 3 to 0.03 mm 3 also can be 0.02 mm 3 to 0.028 mm 3 .

[0102] Regarding the solder paste arranged on two or more metal pads respectively, the volume of the solder paste is preferably almost unchanged. For example, regarding multiple solder pastes, the volume of the solder paste on each metal pad is preferably 80% or more independently with respect to the maximum volume of the solder paste on each metal pad, and more preferably 90% to 100% respectively.

[0103] The maximum volume of the solder paste on each metal pad refers to the volume of the solder paste with the largest volume among the multiple solder pastes. For example, in the case where the above maximum volume is 0.03 mm 3 , the volume of the solder paste on each metal pad is preferably 0.024 mm 3 (0.03 mm 3×0.8) or more.

[0104] Regarding the solder paste respectively disposed on two or more metal pads, the height of the solder paste can be 0.05 mm to 0.25 mm, or can be 0.1 mm to 0.2 mm.

[0105] The area of the solder paste in a top view can be the same as the area of the metal pad having the solder paste disposed thereon in a top view, or can be larger or smaller than the area of the metal pad in a top view.

[0106] In the above-described placement process, the semiconductor package and the mother board are placed with a spacer therebetween. The spacer is preferably placed between the semiconductor package and the mother board in a state of being located at the end portion of the package substrate in a top view. When the package substrate is rectangular in a top view, the spacer is preferably placed between the semiconductor package and the mother board in a state of being located at the corner portion of the semiconductor package.

[0107] The height of the spacer in a cross-sectional view can be 0.1 mm to 0.5 mm. From the viewpoint of appropriately reducing the bridging where adjacent solders come into contact with each other and the connection failure between the semiconductor package and the mother board at the central portion, it is preferably 0.2 mm to 0.35 mm, and more preferably 0.2 mm to 0.3 mm.

[0108] [Bonding Process]

[0109] The manufacturing method of the present disclosure includes a process (bonding process) of heating the semiconductor package and the mother board after the placement process and electrically bonding a plurality of solder balls to a plurality of metal pads.

[0110] In the bonding process, the semiconductor package and the mother board are heated, and the plurality of solder balls and the solder paste are subjected to reflow soldering to electrically bond the plurality of solder balls to the plurality of metal pads. In the metal pads having the solder paste disposed thereon, the solder balls and the solder paste are bonded by reflow soldering. On the other hand, in the metal pads without the solder paste disposed thereon, the solder balls and the metal pads are bonded by reflow soldering. After bonding, the spacer is removed, and thus a semiconductor device can be obtained.

[0111] During reflow soldering, it becomes a shape in which the peripheral end portion of the semiconductor package descends in the vertical direction and the central portion of the semiconductor package floats in the vertical direction in a top view. That is, due to reflow soldering, the semiconductor package warps. Therefore, bridging is likely to occur near the peripheral end portion, and connection failure is likely to occur near the central portion.

[0112] On the other hand, in the manufacturing method of the present disclosure, as described above, a spacer is used and metal pads without solder paste are provided on the peripheral end portion side of the mother board, so that connection failures at the end portion and the central portion of the semiconductor package and the mother board can be reduced.

[0113] A cross-sectional view showing the structure of a semiconductor device manufactured by the manufacturing method of the present disclosure is shown in Figure 1 . Figure 1 The semiconductor device 100 shown includes a mother board 1 and a semiconductor package 10. Through reflow soldering, a plurality of metal pads 14 provided on the mother board 1 and a plurality of solder balls provided on the semiconductor package 10 are directly connected or connected via solder paste, thereby forming a connection portion 15.

[0114] The semiconductor package 10 includes a package substrate 2 having a plurality of solder balls provided on one surface, a semiconductor chip 3, a reinforcement 4, a silicon interposer 8, etc.

[0115] When viewed from the side where the solder balls are provided, the package substrate 2 is laminated in the order of a solder resist layer 13, a build-up layer 12, a core layer 11, a build-up layer 12, and a solder resist layer 13. On the side of the package substrate 2 opposite to the side where the solder balls are provided, a frame-shaped reinforcement 4 is bonded via an adhesive at the peripheral end portion in a plan view, and is electrically connected to the silicon interposer 8 via solder bumps. In addition, the space between the silicon interposer 8 and the solder resist layer 13 is sealed with an underfill material 9.

[0116] The semiconductor chip 3 includes a processor 5 such as a CPU or a GPU and a memory 6 such as an HBM, and is sealed with a sealing material 7 such as an LMC around it. Moreover, the semiconductor chip 3 is electrically connected to the silicon interposer 8 via solder bumps, and the space between the semiconductor chip 3 and the silicon interposer 8 is sealed with an underfill material.

[0117] <Semiconductor Device>

[0118] In the semiconductor device of the present disclosure, a semiconductor package having a package substrate and a plurality of solder balls on one surface of the package substrate is electrically joined to a mother board having a plurality of metal pads via the plurality of solder balls and the plurality of metal pads. Among the plurality of connection portions formed by electrically joining the plurality of solder balls and the plurality of metal pads, the ratio of the minimum value of the solder volume of each connection portion to the maximum value of the solder volume of each connection portion satisfies 0.6 to 0.95.

[0119] The semiconductor device of the present disclosure includes a plurality of connection portions formed by electrically joining a plurality of solder balls and a plurality of metal pads. The ratio (minimum value of solder volume / maximum value of solder volume) of the minimum value of the solder volume of each connection portion to the maximum value of the solder volume of each connection portion satisfies 0.6 to 0.95. That is, the aforementioned semiconductor device includes both connection portions with more solder volume and connection portions with less solder volume. As a result, connection failures at the ends and the center of the semiconductor package and the mother board can be reduced.

[0120] The preferable modes of the respective structures in the semiconductor device of the present disclosure are the same as those of the respective structures in the manufacturing method of the semiconductor device of the present disclosure described above.

[0121] The semiconductor device of the present disclosure can be manufactured by applying the manufacturing method of the semiconductor device of the present disclosure described above. For example, for a connection portion with a larger solder volume, the solder ball and the metal pad can be electrically connected in a state where solder paste is disposed on the metal pad. In addition, for a connection portion with a smaller solder volume, the solder ball and the metal pad can be electrically connected in a state where no solder paste is disposed on the metal pad. By adjusting the amount of solder paste disposed on the metal pad, the minimum value of the solder volume / the maximum value of the solder volume can be adjusted.

[0122] From the viewpoint of appropriately reducing connection failures at the ends and the central portion of the semiconductor package and the mother board, it is preferable that the solder volume of each connection portion in the connection portions located in the central portion is larger than the solder volume of each connection portion in the connection portions located in the peripheral end portion.

[0123] The solder volume (hereinafter also referred to as solder volume A) of each connection portion in at least one connection portion located in the central portion of the semiconductor package can be larger than the solder volume (hereinafter also referred to as solder volume B) of each connection portion in at least one connection portion located in the peripheral end portion of the semiconductor package. For example, the ratio of solder volume B to solder volume A (solder volume B / solder volume A) can satisfy 0.6 to 0.95, can also satisfy 0.7 to 0.95, and can further satisfy 0.7 to 0.9.

[0124] The package substrate can be rectangular in plan view. In this case, it is preferable that a plurality of connection portions electrically connecting the solder balls and the metal pads are disposed along the outer periphery of the rectangle. Moreover, it is preferable that the solder volume (hereinafter also referred to as solder volume C) of each connection portion located at the corner of the rectangle is smaller than the solder volume (hereinafter also referred to as solder volume D) of each connection portion located at a position other than the corner. The ratio of solder volume C to solder volume D (solder volume C / solder volume D) can satisfy 0.6 to 0.95, can also satisfy 0.7 to 0.95, and can further satisfy 0.7 to 0.9.

[0125] In the present disclosure, the solder volume of each connection part can be obtained by the following method. When the connection part can be cut, the pad area on the package substrate side, the pad area on the mother board side, the projected area of the solder (since it is not a perfect sphere but a shape flattened in the plane direction), etc. can also be measured by X-ray, and the solder volume can be obtained based on these measurement results and the height of the connection part obtained from the cut surface. When the connection part cannot be cut, three-dimensional image data of the connection part can also be obtained in a non-destructive manner by X-ray CT (for example, high-resolution X-ray CT) scanning, and the solder volume can be obtained based on the three-dimensional image data.

[0126] [Embodiment]

[0127] Hereinafter, the present disclosure will be specifically described by way of embodiments, but the scope of the present disclosure is not limited to these embodiments.

[0128] In the following experimental examples, a sample 100A imitating the Figure 2 shown semiconductor device was fabricated. In the fabrication of the sample 100A, a mother board 1A having a plurality of metal pads 14, a stacked substrate 2A having a core layer 11, build-up layers 12, and a solder resist layer 13, and further having a plurality of solder balls (substantially spherical with a radius of 300 μm), a reinforcement 4, an adhesive, and a component 3A imitating a semiconductor chip were used. The component 3A was connected to the stacked substrate 2A with solder bumps, and the space therebetween was sealed with underfill 9. The metal pads 14 and the solder balls were connected directly or via solder paste (not shown) by reflow soldering, thereby forming a connection part 15.

[0129] Details of each component are as follows.

[0130] Mother board: A rectangular mother board with a side length of 160 mm and having a plurality of metal pads in a rectangular area

[0131] Build-up layer: A laminated structure of Ajinomoto Fine-Techno Co., Ltd.'s Ajinomoto Build-up Film (ABF) GX-92 (thickness 30 μm) and a copper layer (thickness 18 μm)

[0132] Core layer: A copper-clad laminate in which copper foils (thickness 12 μm) are laminated on both sides of an insulating layer

[0133] Solder resist layer: Photosensitive solder resist (SR) manufactured by Showa Denko Materials Co., Ltd.

[0134] The configurations of the solder resist layer, build-up layer, and core layer are as described below.

[0135] SR (15μm) / Copper Foil (18μm) / ABF (30μm) / ABF (30μm) / Copper Foil (18μm) / ABF (30μm) / ABF (30μm) / Copper Foil (18μm) / ABF (30μm) / ABF (30μm) / Copper Foil (18μm) / ABF (30μm) / ABF (30μm) / Copper Foil (12μm) / Core Layer (1400 - 1500μm) / Copper Foil (12μm) / ABF (30μm) / ABF (30μm) / Copper Foil (18μm) / ABF (30μm) / ABF (30μm) / Copper Foil (18μm) / ABF (30μm) / ABF (30μm) / Copper Foil (18μm) / ABF (30μm) / ABF (30μm) / Copper Foil (18μm) / SR (15μm)

[0136] Reinforcement: Made of copper, with a width of 16 mm and a thickness of 2.5 mm

[0137] Adhesive: Silicone-based adhesive KE - 1867 manufactured by Shin-Etsu Chemical Co., Ltd.

[0138] Component simulating a semiconductor chip: Manufactured by WALTS Co., Ltd., WALTS - TEG FBW200A - 0000 JY (one side is 50 mm, solder bumps are Cu30μm + SnAg30μm)

[0139] As the insulating layers included in the copper - clad laminate, insulating layers 1 - 5 having the physical properties shown in Table 1 below are used.

[0140] [Table 1]

[0141] Physical property Unit Insulating layer 1 Insulating layer 2 Insulating layer 3 Insulating layer 4 Insulating layer 5 Tg(DMA) Tensile method ℃ 300 300 330 330 220 a1(TMA) Compression method ppm / °C 9.5 7.2 8.0 5.6 7.8 a2(TMA) Compression method ppm / °C 1.1 1.0 1.0 1.0 1.0 Storage modulus at 30°C (DMA) Tensile method GPa 24 29 27 32 21 Storage modulus at 260°C (DMA) Tensile method GPa 16 20 22 25 14

[0142] [Fabrication of Samples]

[0143] Solder paste is dispensed on multiple metal pads provided on a mother board. Specifically, a stencil having multiple openings is placed on the mother board such that the openings face the metal pads of the mother board, and solder paste is printed on the metal pads by screen printing. The opening height of the stencil is 130μm, and the opening diameter of the stencil is 350μm or 450μm. The height of the formed solder paste is 130μm (0.13 mm). For the printing of the solder paste, a mother board with metal pads in a rectangular area where the four corner portions of the peripheral ends are masked and no solder paste is printed and a mother board with solder paste printed without the said mask in the rectangular area where the metal pads are provided are prepared respectively.

[0144] Prepare to bond a reinforcement member using an adhesive on a stacked substrate (a substrate in a rectangular shape with one side being 100 mm) having a plurality of solder balls, and a packaged component in which a WALTS-TEG is connected via solder bumps. In the packaged component, the space between the WALTS-TEG and the stacked substrate is sealed with underfill material.

[0145] Arrange the packaged component and the motherboard with spacers in between. Two spacers are arranged at each corner of the packaged component, for a total of eight spacers. The heights of the spacers are 200 μm, 250 μm, 300 μm, and 350 μm.

[0146] Then, heat the packaged component and the motherboard with spacers arranged thereon, so that the solder balls are electrically connected to the metal pads by reflow soldering.

[0147] Thus, a sample imitating Figure 2 the semiconductor device shown was fabricated.

[0148] The volume of the solder paste for each metal pad is 450×450×130 (μm 3 ) or 350×350×130 (μm 3 ), and the volume of the solder ball is 4 / 3×π×(300) 3 (μm 3 ). Based on these volume values, calculate the volume ratio of the connection part with less solder volume (only solder balls) to the connection part with more solder volume (solder balls + solder paste), which is 0.81 or 0.88.

[0149] <Evaluation of solder bridging>

[0150] By observing the fabricated sample with X-rays, confirm whether there is solder bridging where adjacent solders are in contact with each other. In particular, confirm whether there is solder bridging near the corners and the central part of the packaged component when viewed from above.

[0151] <Evaluation of connection>

[0152] For the fabricated sample, use a tester to measure the resistance value of the connection part. Specifically, when viewed from above, measure the resistance values of the connection parts in three horizontal and vertical rows along the four sides of the packaged component, and the resistance values of the connection parts in three horizontal and vertical rows inside the four sides of the WALTS-TEG. And evaluate the connection parts with a significant increase in resistance value as poor connections.

[0153] [Experimental Example 1]

[0154] As the core layer, a copper-clad laminate in which copper foils are laminated on both sides of the insulating layer 1 in Table 1 was used. Furthermore, in the above-mentioned <Fabrication of Samples>, a template with a template opening diameter of 350 μm and a spacer with a spacer height of 300 μm were used to prepare a mother board having metal pads printed with solder paste without masking, and samples were fabricated.

[0155] [Experimental Examples 2 - 5]

[0156] Samples were fabricated in the same manner as in Experimental Example 1, except that the template opening diameter and the spacer height were changed to the values shown in Table 2. In Experimental Example 5, the insulating layer 2 was used instead of the insulating layer 1 in Table 1.

[0157] The samples fabricated in Experimental Examples 1 - 5 were used to evaluate solder bridging and connection. The results are shown in Table 2.

[0158] [Table 2]

[0159]

[0160] From the results of Experimental Examples 1 - 5, it was found that it was difficult to simultaneously reduce solder bridging and reduce connection failures.

[0161] [Experimental Example 6]

[0162] As the core layer, a copper-clad laminate in which copper foils are laminated on both sides of the insulating layer 2 in Table 1 was used. Furthermore, in the above-mentioned <Fabrication of Samples>, a template with a template opening diameter of 450 μm and a spacer with a spacer height of 250 μm were used to prepare a mother board having metal pads with the four corners of the peripheral end masked and not printed with solder paste, and samples were fabricated. In Experimental Example 6, 15 columns at the four corners of the peripheral end were masked ( Figure 3 Y in Figure 3 and the ratio to the length of one piece is 0.15) × 4 columns (

[0163] [Experimental Example 7]

[0164] In Experimental Example 7, as the core layer, a copper-clad laminate in which copper foils are laminated on both sides of the insulating layer 4 in Table 1 was used. Furthermore, except for masking 20 columns at the four corners of the peripheral end ( Figure 3 Y in Figure 3 and the ratio to the length of one piece is 0.2) × 4 columns (

[0165] Samples were fabricated in the same manner as in Experimental Example 6.

[0166] [Table 3]

[0167]

[0168] In Experimental Example 6, solder bridging near the central portion of the package component was not confirmed, and a part of solder bridging was confirmed near the corner portion. However, compared with Experimental Examples 2 to 5, the number of solder bridges was significantly reduced. In Experimental Example 7, solder bridging near the corner portion and the central portion of the package component was not confirmed. In addition, in Experimental Examples 6 and 7, unconnected portions were not confirmed by the tester.

[0169] In Experimental Examples 6 and 7 (especially Experimental Example 7), it was possible to simultaneously reduce solder bridging and reduce connection failures.

[0170] [Experimental Examples 8 to 12]

[0171] Furthermore, in Experimental Examples 8 to 12, a plurality of samples were produced using copper-clad laminates in which copper foils were laminated on both sides of Insulation Layers 1 to 5 in Table 1, and the yield of good products capable of simultaneously reducing solder bridging and reducing connection failures was evaluated. The results are shown in Table 4.

[0172] "The first to third weeks from the outside on the outside" in Table 4 means: in the top view of the mother board of Figure 3 , in the rectangular area where the metal pads are arranged, the ratio of the samples in which no connection failure occurred at the connection portion corresponding to the metal pads arranged in a frame shape from the first to the third ( Figure 3 A in

[0173] "The first to third weeks from the outside on the inside" in Table 4 means: in the inside of the rectangular area where the metal pads are arranged in the top view of the mother board of Figure 3 , the ratio of the samples in which no connection failure occurred at the connection portion corresponding to the metal pads arranged in a frame shape from the first to the third ( Figure 3 B in

[0174] [Table 4]

[0175]

[0176] In Experimental Examples 8 to 12, samples capable of simultaneously reducing solder bridging and reducing connection failures could be obtained with a high yield (for example, 75% or more).

[0177] All documents, patent applications, and technical standards described in this specification are incorporated by reference to the same extent as if each document, patent application, and technical standard were specifically and separately described as being incorporated by reference.

Claims

1. A method for manufacturing a semiconductor device, comprising the following steps: Preparing a semiconductor package and a mother board, the semiconductor package having a package substrate and a plurality of solder balls located on one surface of the package substrate, the mother board having a plurality of metal pads and a plurality of solder pastes disposed on a part of the plurality of metal pads, and disposing the semiconductor package and the mother board such that the plurality of solder balls face the plurality of metal pads; and Heating the semiconductor package and the mother board to electrically connect the plurality of solder balls and the plurality of metal pads. In the disposing step, prepare the mother board on which the solder paste is not disposed on at least a part of the metal pads on the peripheral end side, and dispose the semiconductor package and the mother board with a spacer therebetween.

2. The method for manufacturing a semiconductor device according to claim 1. Regarding the plurality of solder pastes, the volume of the solder paste for each metal pad is independently 0.01 mm 3 to 0.03 mm 3 .

3. The method for manufacturing a semiconductor device according to claim 1 or 2. Regarding the plurality of solder pastes, the volume of the solder paste for each metal pad is independently 80% or more with respect to the maximum volume of the solder paste for each metal pad.

4. The method for manufacturing a semiconductor device according to any one of claims 1 to 3. Form the plurality of solder pastes on a part of the plurality of metal pads by screen printing.

5. The method for manufacturing a semiconductor device according to any one of claims 1 to 4. The height of the spacer in cross-section is 0.2 mm to 0.3 mm.

6. The method for manufacturing a semiconductor device according to any one of claims 1 to 5. The area of the semiconductor package when viewed from above is 2500 mm 2 or more.

7. The method for manufacturing a semiconductor device according to any one of claims 1 to 6. The package substrate is rectangular in plan view, and the lengths of the four sides of the package substrate in plan view are independently 50 mm or more.

8. The method for manufacturing a semiconductor device according to any one of claims 1 to 7. The mass of the semiconductor package is 100 g or more.

9. The method for manufacturing a semiconductor device according to any one of claims 1 to 8. The package substrate includes a core layer including a copper-clad laminate.

10. The method for manufacturing a semiconductor device according to any one of claims 1 to 9. The semiconductor package includes a silicon interposer or includes a plurality of semiconductor chips. When the semiconductor package includes a silicon interposer, the silicon interposer is mounted on the package substrate in electrical connection with the plurality of semiconductor chips.

11. A semiconductor device A semiconductor package having a package substrate and a plurality of solder balls located on one surface of the package substrate is electrically connected to a mother board having a plurality of metal pads via the plurality of solder balls and the plurality of metal pads. In the plurality of connection portions formed by electrically connecting the plurality of solder balls and the plurality of metal pads, the ratio of the minimum value of the solder volume of each connection portion to the maximum value of the solder volume of each connection portion is 0.6 to 0.

95.

12. The semiconductor device according to claim 11. The ratio of the solder volume of each connection part in at least one connection part located at the peripheral end part of the semiconductor package to the solder volume of each connection part in at least one connection part located at the central part of the semiconductor package is 0.6 to 0.

95.

13. The semiconductor device according to claim 11, The package substrate is rectangular in plan view, and the solder volume of each connection part located at the corner of the rectangle is smaller than the solder volume of each connection part located at a position other than the corner.

14. The semiconductor device according to any one of claims 11 to 13, The package substrate includes a core layer including a copper-clad laminate.

15. The semiconductor device according to any one of claims 11 to 14, The semiconductor package includes a silicon interposer or includes a plurality of semiconductor chips. When the semiconductor package includes a silicon interposer, the silicon interposer is mounted on the package substrate in electrical connection with the plurality of semiconductor chips.

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