Inertial navigation information real-time processing and sending method based on data interaction between DSP and FPGA RAM

Abstract

The invention relates to an inertial navigation information real-time processing and sending method based on data interaction between a DSP (Digital Signal Processor) and an FPGA (Field Programmable Gate Array) RAM (Random Access Memory), which comprises the following steps of: constructing a DSP + FPGA dual-core heterogeneous information processing architecture with the characteristics of high performance and low power consumption, finishing high-order filter operation and a high-frequency strapdown inertial navigation attitude updating algorithm by adopting the DSP, transmitting information obtained by operation to an RAM IP (Internet Protocol) core of the FPGA through an EMIF (External Memory Interface) of the DSP, in addition, time sequence carding and strict planning are carried out on inertial element collection time and DSP operation time, the time occupied by information collection, calculation and transmission is compressed to the minimum, and it is ensured that after an FPGA receives an external timing system trigger pulse, latest attitude information is rapidly sent to user equipment in real time. According to the invention, the FPGA RAM is innovatively adopted to carry out data transfer and transmission, and an information acquisition, processing and transmission time sequence control method is designed, so that the transmission waiting time after the external trigger pulse is received is shortened, and the user equipment is ensured to obtain the latest resolving information within the required time range.

Description

Technical Field

[0001] The invention belongs to the technical field of navigation systems, and in particular to a method for real-time processing and sending of inertial navigation information based on data interaction between DSP and FPGA_RAM. Background Art

[0002] In recent years, the strapdown fiber optic gyro inertial navigation system has gradually become one of the mainstream equipment types for ship attitude reference due to its advantages of high precision, high reliability, low power consumption, and high cost performance. In the application of ship attitude reference equipment, not only does the inertial navigation equipment need to synchronize and transmit information with the external time system, but also because the antenna, tower and other equipment need to use the inertial navigation attitude information for real-time control, this requires the inertial navigation equipment to quickly and timely send the corresponding information after receiving the external time system input signal to ensure that the user equipment meets the real-time use requirements of attitude and other information.

[0003] To meet the above requirements, traditional inertial navigation equipment usually uses an X86 architecture processor + an operating system (such as a PC104 board + a VxWorks operating system), runs an attitude update algorithm at the same time, and uses the advantage of its operating system's ability to process multiple tasks in parallel to send attitude information in real time.

[0004] However, on the one hand, as users of attitude information such as ship antennas and towers have set limits on the power consumption and volume of inertial navigation equipment, the traditional information processing architecture can no longer meet the current new demands. For example, after the traditional X86 architecture processor is combined with the commonly used interface, the power consumption of a single board is generally not less than 10W, and the size is generally not less than 10*10*4mm, while the power consumption of the whole machine of the medium-sized fiber-optic strapdown inertial navigation is usually limited to within 15W. Except for the power consumption of the necessary inertial components, it is impossible to use an information processing architecture solution with high power consumption; on the other hand, the overall accuracy index of the fiber-optic strapdown inertial navigation mainly depends on the accuracy of the fiber-optic gyroscope, and the accuracy of the fiber-optic gyroscope is greatly affected by temperature fluctuations. In addition, the size of the inertial navigation equipment is small (the medium-precision attitude reference equipment generally does not exceed 20*20*20mm). If a high-power information processor is used, the heat generated will accumulate inside the equipment, which will cause the temperature of the fiber-optic gyroscope to rise and the temperature difference between the temperature fields at different positions to be large, thereby resulting in a decrease in the overall attitude accuracy of the equipment.

[0005] Using DSP for inertial navigation data processing and transmission is also a common method for current low-power inertial navigation devices. However, when the user device requests high-real-time attitude information at irregular intervals, the DSP needs to use interrupts to output and send processing. Since the navigation solution inside the DSP requires strict timing control, this indefinite external transmission interruption will interrupt the navigation solution algorithm and cause the navigation information update to fail.

[0006] Therefore, it is necessary to design a low-power, small-volume, and high-real-time inertial navigation information processing and sending method to meet the application needs of ship attitude reference equipment. Summary of the invention

[0007] The purpose of the present invention is to overcome the shortcomings of the prior art, and propose a real-time processing and sending method for inertial navigation information based on DSP and FPGA_RAM data interaction. Aiming at the high real-time demand of user equipment for strapdown fiber optic gyroscope attitude reference equipment information, a DSP+FPGA dual-core heterogeneous information processing architecture with high performance and low power consumption is built, and DSP is used to complete high-order filter calculation and high-frequency strapdown inertial navigation attitude update algorithm, and the information obtained by calculation is transmitted to the RAM IP core of FPGA through the EMIF of DSP. In addition, by performing timing combing and strict planning on the inertial element acquisition time and DSP operation time, the time occupied by information acquisition, calculation and transmission is compressed to the minimum, so as to ensure that after the FPGA receives the external timing trigger pulse, the latest attitude information is quickly and real-timely sent to the user equipment.

[0008] The present invention solves the technical problem by adopting the following technical solutions:

[0009] A method for real-time processing and sending of inertial navigation information based on DSP and FPGA_RAM data interaction, comprising the following steps:

[0010] Step 1: Build a DSP+FPGA dual-core heterogeneous information processing architecture;

[0011] Step 2: Use DSP to complete high-order filter calculation and high-frequency strapdown inertial navigation attitude update algorithm, and transmit the calculated information to the RAM IP core of FPGA through DSP's EMIF;

[0012] Step 3: By sorting out and strictly planning the inertial element acquisition time and DSP operation time, the time occupied by information acquisition, calculation and transmission is compressed to a minimum. After the FPGA receives the external timing trigger pulse, it quickly and in real time sends the latest attitude information to the user device.

[0013] Moreover, the DSP+FPGA dual-core heterogeneous information processing architecture built in the step 1 includes: a fiber optic gyroscope, an accelerometer component, an FPGA, a DSP and an attitude information user device, wherein the fiber optic gyroscope and the accelerometer component are respectively connected to the FPGA, the FPGA and the DSP are connected to each other, and the FPGA and the attitude information user device are connected to receive the timing signal and send the attitude information; the fiber optic gyroscope is used to measure the angular velocity, the accelerometer component is used to measure the linear velocity, the FPGA is used for data acquisition, data preprocessing and data transmission, and the DSP is used for processing the inertial element data, running the high-order filter and calculating the attitude update solution algorithm.

[0014] Moreover, there are three fiber optic gyroscopes in total, which are installed in an orthogonal manner to measure the angular velocity of the reference device in three axes in space respectively.

[0015] Moreover, the accelerometer assembly includes three quartz accelerometers and a VF module, and the three quartz accelerometers and the VF module respectively measure the linear acceleration of the reference device in three directions in space.

[0016] Moreover, the FPGA uses EG4X20BG256I. The FPGA is responsible for signal acquisition and timing control in the system solution board, including internal acquisition of the device and timing control of the interface, fiber optic gyroscope signal and temperature acquisition, accelerometer signal and temperature acquisition, user equipment external timing pulse reception, DSP solution interrupt triggering, serial port function expansion and GPS / BD_1PPS signal reception.

[0017] Moreover, the DSP uses FT-C6713 as a signal processing unit, and the FPGA is connected to the emif interface of the DSP as an asynchronous memory peripheral for data transmission.

[0018] Moreover, the specific implementation method of step 2 is: connecting the parallel data, address and control buses of the DSP to the general IO pins of the FPGA at the same time, adaptively conditioning the control bus and the address bus in the FPGA, and connecting them together with the data bus to the BRAM32K module inside the FPGA;

[0019] The specific configuration of the BRAM32K module inside the FPGA is: clock frequency 48MHz, data bus 8 bits, address bus 15 bits, single-port RAM mode; at the same time, by performing a logical AND operation on the DSP enable signal and the high bit of the address, the address of this module is mapped to the CE2 space of the FT-C6713, with a base address of 0xB0000000 and an offset address of 0x00. On the FT-C6713, the addressing space of the storage unit is 0xB0000000-0xB0007FFF, a total of 32K bytes, which meets the storage space requirements of the reference device posture information;

[0020] After the DSP chip FTC6713 completes the inertia solution of each cycle, it writes the latest calculated posture information into the address space through the EMIF bus according to the address protocol specified in advance; at the same time, the external timing signal acquisition module of the FPGA is in real-time monitoring state. Once the timing signal sent by the user equipment is detected, the corresponding posture data is read from the BRAM32K module, transferred to the serial port sending module, and the latest posture information is sent out according to the protocol agreed with the user.

[0021] The advantages and positive effects of the present invention are:

[0022] 1. The present invention constructs a DSP+FPGA dual-core heterogeneous information processing architecture with high performance and low power consumption, uses DSP to complete high-order filter operations and high-frequency strapdown inertial navigation attitude update algorithms, transmits the information obtained from the operations to the RAM IP core of the FPGA through the EMIF of the DSP, and in addition, by timing combing and strictly planning the inertial element acquisition time and DSP operation time, the time occupied by information acquisition, calculation and transmission is compressed to a minimum, ensuring that after the FPGA receives the external timing trigger pulse, the latest attitude information is quickly and in real time sent to the user device. The present invention innovatively uses FPGA_RAM for data transfer and transmission, and designs a method for information acquisition, processing and transmission timing control, which reduces the transmission waiting time after receiving the external trigger pulse, ensuring that the user device can obtain the latest solution information within the required time range.

[0023] 2. The present invention adopts a low-power hardware architecture, avoids dependence on a high-power operating system computing platform, and greatly reduces the power consumption and size of the device while meeting the computing performance. At the same time, it takes advantage of the FPGA multi-task logic parallel processing to transfer the real-time external information sending function from the traditional DSP to the FPGA, while ensuring the real-time information sending and avoiding the solution failure problem that may be caused by the DSP interrupt sending method. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 The internal structure diagram of the fiber optic gyro strapdown attitude reference of the present invention is shown in FIG.

[0025] Figure 2 It is a block diagram of the information flow of DSP and FPGA of the present invention;

[0026] Figure 3 This is a timing diagram of the internal data processing and external transmission of the attitude reference of the present invention. DETAILED DESCRIPTION

[0027] The present invention is further described in detail below with reference to the accompanying drawings.

[0028] A method for real-time processing and sending of inertial navigation information based on DSP and FPGA_RAM data interaction comprises the following steps:

[0029] Step 1: Build a DSP+FPGA dual-core heterogeneous information processing architecture.

[0030] like Figure 1As shown, building a DSP+FPGA dual-core heterogeneous information processing architecture includes: a fiber optic gyro strapdown attitude reference device and an attitude information user device, wherein the fiber optic gyro strapdown attitude reference device includes a fiber optic gyroscope, an accelerometer component, an FPGA and a DSP, the fiber optic gyroscope and the accelerometer component are connected to the FPGA respectively, the FPGA and the DSP are connected to each other, and the FPGA and the attitude information user device are connected to receive timing signals and send attitude information; the fiber optic gyroscope is used to measure angular velocity, the accelerometer component is used to measure linear velocity, the FPGA is used for data acquisition, data preprocessing and data transmission, and the DSP is used for processing inertial element data, running high-order filters and calculating attitude update solution algorithms.

[0031] There are three fiber optic gyroscopes in total. The three fiber optic gyroscopes are installed in an orthogonal manner to measure the angular velocity of the reference device in three axes in space respectively.

[0032] The accelerometer assembly includes three quartz accelerometers and a VF module, and the three quartz accelerometers and the VF module respectively measure the linear acceleration of the reference device in three directions in space.

[0033] The FPGA in the fiber optic gyro strapdown attitude reference device is used for data acquisition, preprocessing and transmission. The FPGA chip is Anlu Technology's EG4X20BG256I, which has rich logic resources and has an embedded true dual-port memory module BRAM32K with a capacity of 32Kb, which creates conditions for the storage and transmission of large amounts of information. The FPGA is responsible for signal acquisition and timing control in the system solution board, mainly including internal equipment acquisition and timing control of interfaces, fiber optic gyro signal and temperature acquisition, accelerometer signal and temperature acquisition, user equipment external timing pulse reception, DSP solution interrupt triggering, serial port function expansion, GPS / BD_1PPS signal reception, etc.

[0034] The DSP in the fiber optic gyro strapdown attitude reference device is the core computing unit, which is used for inertial element data processing, high-order filter operation, attitude update solution algorithm calculation and other functions. The 32-bit floating-point DSP chip FT-C6713 of Great Wall Galaxy is selected as the signal processing unit. The chip has a maximum main frequency of 300MHz and has the advantages of low power consumption and small size. The DSP chip has an EMIF parallel bus interface and supports multiple peripherals including SRAM, SDRAM, asynchronous memory, etc. The FPGA is connected to the emif interface of the DSP as an asynchronous memory peripheral to realize data transmission.

[0035] The attitude information user device sends a timing signal instruction to the fiber optic gyro strapdown attitude reference device, requiring the reference device to send back attitude information via the serial port within a specified short time (generally about 3m) after receiving the pulse edge signal. In the present invention, in order not to affect the algorithm operation in the DSP and to ensure the rapidity of sending information to the outside, FPGA is used to receive the external timing signal and send the real-time attitude information required by the user to the outside.

[0036] Step 2: Use DSP to complete high-order filter calculations and high-frequency strapdown inertial navigation attitude update algorithms, and transmit the calculated information to the RAM IP core of FPGA through the EMIF of DSP.

[0037] like Figure 2 As shown in the figure, the DSP chip FT-C6713 selected for the fiber optic gyro strapdown attitude reference device has a fully functional bus interface, in which the EMIF module can realize a variety of external memory interfaces, including SBSRAM, SDRAM, asynchronous memory, etc.; the parallel data, address and control buses of the DSP are connected to the FPGA general IO pins at the same time, and the control bus and address bus are adaptively adjusted in the FPGA, and connected to the BRAM32K module inside the FPGA together with the data bus.

[0038] The specific configuration of the BRAM32K module inside the FPGA is: clock frequency 48MHz, data bus 8 bits, address bus 15 bits, single-port RAM mode. At the same time, by performing a logical AND operation on the DSP enable signal and the high bit of the address, the address of this module is mapped to the CE2 space of the FT-C6713, with a base address of 0xB0000000 and an offset address of 0x00. Therefore, on the FT-C6713, the addressing space of this storage unit is 0xB0000000-0xB0007FFF, a total of 32K bytes, which meets the storage space requirements of the reference device posture information.

[0039] After the DSP chip FTC6713 completes the inertia solution of each cycle, it writes the latest calculated posture information into the address space through the EMIF bus according to the address protocol specified in advance. On the other hand, the external time signal acquisition module of the FPGA is in real-time monitoring state. Once the user device sends a time signal, it immediately reads the corresponding posture data from the BRAM32K module, transfers it to the serial port sending module, and sends the latest posture information according to the protocol agreed with the user.

[0040] Step 3: By sorting out and strictly planning the inertial element acquisition time and DSP operation time, the time occupied by information acquisition, calculation and transmission is compressed to a minimum. After the FPGA receives the external timing trigger pulse, it quickly and in real time sends the latest attitude information to the user device.

[0041] The internal sampling clock of the fiber optic gyro strapdown attitude reference device is a 1KHz square wave generated by the FPGA. This signal is sent to the fiber optic gyro and accelerometer components, triggering them to send their own angular velocity and acceleration information. At the same time, the 1KHz square wave signal is transmitted to the DSP, which uses this signal to trigger the external interrupt program as the main interrupt for data calculation. The above actions are all effective at the falling edge of the 1KHz clock, such as Figure 3 t, t+1··· shown.

[0042] like Figure 3 As shown, the FPGA of the fiber optic gyro strapdown attitude reference device receives the timing signal sent by the user equipment at time T0, and the FPGA forwards the timing signal flag and offset time n us to the DSP. The DSP obtains these two information at time t+2, and simultaneously performs calculation on the gyro and accelerometer information G / A2 in the time period from t+1 to t+2. The DSP calculation time is Figure 3 As shown in T_Calc, after DSP completes the operation of the current t+2 cycle and calculates the posture information Calc2 of this cycle, it combines the posture information Calc1 of the previous cycle and interpolates to calculate the posture value corresponding to the external timing signal at time T0. DSP writes this value into FPGA_RAM and issues a posture information serial port sending command to FPGA. FPGA starts sending posture information through the internal serial port module at time T1 and completes sending at time T2.

[0043] From the moment the fiber optic gyro strapdown attitude reference device receives the external timing signal T0 to the moment the serial port data is sent T2, the information delay is:

[0044] ΔT=T2-T0=(1ms-n us)+T_Calc+T_TxPro

[0045] Among them, n is between 0-1000; using the high-performance computing platform built by the patent of this invention, T_Calc is less than 0.5ms; T_TxPro is the serial port data transmission time, taking 50 bytes and baud rate 460800 as an example, the transmission time is about 1.1ms. Therefore, the maximum transmission delay is about 1ms+0.5ms+1.1ms=2.6ms, which meets the user equipment's requirement that the posture information delay does not exceed 3ms.

[0046] The present invention constructs a DSP+FPGA dual-core heterogeneous information processing architecture with high performance and low power consumption, uses DSP to complete high-order filter operations and high-frequency strapdown inertial navigation attitude update algorithms, transmits the information obtained from the operations to the RAM IP core of the FPGA through the EMIF of the DSP, and in addition, by performing timing combing and strict planning on the inertial element acquisition time and DSP operation time, the time occupied by information acquisition, calculation and transmission is compressed to a minimum, ensuring that after the FPGA receives an external timing trigger pulse, the latest attitude information is quickly and in real time sent to the user device. The present invention innovatively uses FPGA_RAM for data transfer and transmission, and designs a method for information acquisition, processing and transmission timing control, which reduces the transmission waiting time after receiving an external trigger pulse, ensuring that the user device can obtain the latest solution information within the required time range.

[0047] The present invention adopts a low-power hardware architecture, avoids dependence on a high-power operating system computing platform, and greatly reduces the power consumption and size of the device while meeting the computing performance. At the same time, it takes advantage of the FPGA multi-task logic parallel processing to transfer the real-time external information sending function from the traditional DSP to the FPGA, while ensuring the real-time information sending and avoiding the solution failure problem that may be caused by the DSP interrupt sending method.

[0048] It should be emphasized that the embodiments described in the present invention are illustrative rather than restrictive. Therefore, the present invention includes but is not limited to the embodiments described in the specific implementation manner. Any other implementation manners derived by those skilled in the art based on the technical solution of the present invention also fall within the scope of protection of the present invention.

Claims

1. A method for real-time processing and sending of inertial navigation information based on DSP and FPGA_RAM data interaction, characterized in that: The following steps are involved: Step 1: Build a DSP+FPGA dual-core heterogeneous information processing architecture; Step 2: Use DSP to complete high-order filter calculation and high-frequency strapdown inertial navigation attitude update algorithm, and transmit the calculated information to the RAM IP core of FPGA through DSP's EMIF; Step 3: By sorting out and strictly planning the inertial element acquisition time and DSP operation time, the time occupied by information acquisition, calculation and transmission is compressed to a minimum. After the FPGA receives the external timing trigger pulse, it quickly and in real time sends the latest attitude information to the user device.

2. The method for real-time processing and sending of inertial navigation information based on DSP and FPGA-RAM data interaction according to claim 1, characterized in that: The DSP+FPGA dual-core heterogeneous information processing architecture built in the step 1 includes: a fiber optic gyroscope, an accelerometer component, an FPGA, a DSP and an attitude information user device, wherein the fiber optic gyroscope and the accelerometer component are respectively connected to the FPGA, the FPGA and the DSP are connected to each other, and the FPGA and the attitude information user device are connected to receive a timing signal and send attitude information; the fiber optic gyroscope is used to measure angular velocity, the accelerometer component is used to measure linear velocity, the FPGA is used for data acquisition, data preprocessing and data transmission, and the DSP is used for processing inertial element data, running high-order filters and calculating attitude update solution algorithms.

3. The method for real-time processing and sending of inertial navigation information based on DSP and FPGA-RAM data interaction according to claim 2, characterized in that: There are three fiber optic gyroscopes in total, which are installed in an orthogonal manner to measure the angular velocity of the reference device in three axes in space respectively.

4. The method for real-time processing and sending of inertial navigation information based on data interaction between DSP and FPGA_RAM according to claim 2, characterized in that: The accelerometer assembly includes three quartz accelerometers and a VF module, and the three quartz accelerometers and the VF module respectively measure the linear acceleration of the reference device in three directions of space.

5. The method for real-time processing and sending of inertial navigation information based on DSP and FPGA-RAM data interaction according to claim 2, characterized in that: The FPGA uses EG4X20BG256I. The FPGA is responsible for signal acquisition and timing control in the system solution board, including internal acquisition of the equipment and timing control of the interface, fiber optic gyroscope signal and temperature acquisition, accelerometer signal and temperature acquisition, user equipment external timing pulse reception, DSP solution interrupt triggering, serial port function expansion and GPS / BD_1PPS signal reception.

6. The method for real-time processing and sending of inertial navigation information based on data interaction between DSP and FPGA_RAM according to claim 2, characterized in that: The DSP uses FT-C6713 as a signal processing unit, and the FPGA is connected to the emif interface of the DSP as an asynchronous memory peripheral for data transmission.

7. The method for real-time processing and sending of inertial navigation information based on data interaction between DSP and FPGA_RAM according to claim 1, characterized in that: The specific implementation method of step 2 is: connecting the parallel data, address and control buses of the DSP to the general IO pins of the FPGA at the same time, adaptively conditioning the control bus and the address bus in the FPGA, and connecting them together with the data bus to the BRAM32K module inside the FPGA; The specific configuration of the BRAM32K module inside the FPGA is: clock frequency 48MHz, data bus 8 bits, address bus 15 bits, single-port RAM mode; at the same time, by performing a logical AND operation on the DSP enable signal and the high bit of the address, the address of this module is mapped to the CE2 space of the FT-C6713, with a base address of 0xB0000000 and an offset address of 0x00. On the FT-C6713, the addressing space of the storage unit is 0xB0000000-0xB0007FFF, a total of 32K bytes, which meets the storage space requirements of the reference device posture information; After the DSP chip FTC6713 completes the inertia solution of each cycle, it writes the latest calculated posture information into the address space through the EMIF bus according to the address protocol specified in advance; at the same time, the external timing signal acquisition module of the FPGA is in real-time monitoring state. Once the timing signal sent by the user equipment is detected, the corresponding posture data is read from the BRAM32K module, transferred to the serial port sending module, and the latest posture information is sent out according to the agreement agreed with the user.

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