Novel wide-range high-precision temperature sensor circuit based on BJT architecture

Abstract

The invention discloses a novel wide-range high-precision temperature sensor circuit based on a BJT architecture. The novel wide-range high-precision temperature sensor circuit comprises a temperature sensing core circuit, a bias current generating circuit, a chopping amplifier, a starting circuit and an SAR ADC reading circuit. A cascode current mirror is adopted in the bias current generating circuit, and the DEM technology is adopted in the temperature sensing front-end circuit to reduce mismatch. In order to reduce the influence caused by the offset voltage and 1 / f noise of the operational amplifier, compared with the traditional chopping operational amplifier, the novel chopping technology is used for the operational amplifier to further reduce the offset voltage and noise. Meanwhile, limited current gain compensation, second-order curvature compensation and circuit gain detection are innovatively introduced to reduce errors. Compared with the prior art, the structure design of the temperature sensor with higher precision can be better realized while the noise is low, the range is large, and the stability is high. In addition, the temperature sensor based on the BJT architecture can be applied to the fields of aerospace, smart agriculture, wearable electronics, smart home and the like, and the application range is wide.

Description

Technical Field

[0001] The present invention belongs to the field of fully integrated temperature sensor chips, and in particular relates to a novel wide-range and high-precision temperature sensor circuit based on a BJT architecture. Background Art

[0002] At present, temperature sensors have generally gone through three stages of development: traditional discrete temperature sensors, analog integrated temperature sensors and digital intelligent temperature sensors. Commonly used temperature sensors in modern industry include semiconductor integrated circuit sensors, thermistors, resistance temperature detectors and thermocouple temperature sensors. Compared with traditional temperature sensors, semiconductor integrated circuit temperature sensors based on CMOS technology have fast temperature measurement speed, wide temperature measurement range, low circuit power consumption and small footprint. In addition, the integrated temperature sensor includes a bandgap circuit and an analog-to-digital conversion circuit. Not only is the area small, but its peripheral circuit is also simple and can directly output digital codes.

[0003] The research on analog temperature sensors mainly has the following directions: The first is the research on temperature sensing devices for temperature sensing circuits. In addition to traditional platinum metals, different devices can now be used, such as BJT or MOS tubes in the subthreshold region. The other is to use different ADCs to design circuits. Using different ADCs will show different advantages for the design of temperature sensors. For example, a temperature sensor using SAR ADC has lower power consumption, and a temperature sensor using Σ-Δ ADC has higher accuracy. The last is the design of the error elimination circuit and correction circuit of the temperature sensor. For temperature sensors designed using CMOS technology, due to the drift of its process and the mechanical stress during the packaging process, certain errors often occur, which greatly reduces the accuracy of the temperature sensor. CMOS temperature sensor products on the market now often use some correction methods or compensation circuits to correct the output error of the temperature sensor and improve its accuracy.

[0004] However, in the design of temperature sensors, performance is often limited by amplifier offset voltage and noise. Solving these problems is the key to improving the accuracy of temperature sensors, and corresponding technologies are needed to eliminate or reduce DC offset and 1 / f noise. In addition, analog circuits such as current mirrors are usually required in the design of CMOS temperature sensors. There is a problem of current mirror mismatch caused by process manufacturing deviations. Since the output impedance of the PMOS tube is limited, when the PMOS tube is used as a current mirror tube, there is a problem of non-constant output current. The limited current gain β of the current source often causes V BE Error, ΔV caused by Δβ BE There are many problems such as errors. The bias resistor and saturation current introduce a PTAT temperature error, and the curvature of the final temperature-voltage relationship is also affected by the temperature dependence of the bias resistor. Summary of the invention

[0005] In order to solve the above problems existing in the prior art, the present invention provides a novel wide-range high-precision temperature sensor circuit using CMOS technology. The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0006] The present invention provides a novel wide-range high-precision temperature sensor circuit using CMOS technology, comprising: a temperature sensing front-end circuit and a SAR ADC readout circuit; wherein:

[0007] The temperature sensing front end includes a temperature sensing core circuit, a bias current generating circuit, a chopper amplifier circuit, a common mode feedback, a proportional amplifier circuit and a startup circuit. The high-precision bias circuit provides bias current for the two substrate PNPs of the temperature sensing device. The output of the temperature sensing core is V BE1 and V BE2 The bias current generation circuit and the temperature sensing core circuit both use common source and common gate current mirrors, and the DEM technology is used in the circuit to reduce the mismatch, and the chopper amplifier is used to reduce the impact of the operational amplifier offset voltage in the bias circuit. Due to the limited number of bits in the ADC readout circuit, it is necessary to BE Amplify to a certain multiple, so the V output of the temperature sensing core BE1 and V BE2 Connect to the differential input of the proportional amplifier circuit with common-mode feedback and amplify to the set multiple. The startup circuit makes the circuit leave the zero current degenerate point and injects current into the tube when powered on.

[0008] The SAR ADC readout circuit includes a sampling and holding circuit, a comparator circuit, a DAC capacitor array circuit and a SAR logic circuit. The input signal of the SAR ADC circuit is the differential output signal OUTP and OUTN provided by the temperature sensing circuit, and the output signal is a 12-bit digital signal D11-D0. The SAR ADC circuit is used to complete the analog-to-digital conversion function.

[0009] In one embodiment of the present invention, the temperature sensing core circuit uses a PNP transistor as a temperature sensing device, and two 1:1 PMOS common source and common gate current mirrors are biased to the two 1:p PNP transistors respectively to obtain the CTAT voltage and the PTAT voltage, which are input to the back end for temperature reading. In order to reduce the impact of the current mirror mismatch, the DEM technology is used for the current mirror, so that the two current mirrors take turns as separate current sources, and a cycle is formed after two cycles, at which time the current mirror provides two completely identical currents.

[0010] The bias current generating circuit described above converts the PNP tube Q 1 and Q 2 The voltage difference ΔV caused by the op amp clampingBE,b Through a bias resistor (R 1 ) to generate a bias current (I bias =ΔV BE,b / R 1 ), the bias current has a positive temperature coefficient and can compensate for V BE The influence of nonlinearity. The size ratio of the common source and common gate current mirror and the PNP tube of the bias current generating circuit is consistent with that described in claim 2. At the same time, the DEM technology consistent with that described in claim 2 is adopted.

[0011] The starting circuit is characterized in that current is injected into the tube when power is turned on to prevent the circuit from entering the zero current degenerate point. N1 The saturation current should be much larger than M P14 , you need to take M N1 The width-to-length ratio is much larger than M P14 , so M P14 Need to take the inverted ratio tube, M N1 Take the normal tube.

[0012] The proportional amplifier circuit is composed of a high-gain folding operational amplifier, a proportional capacitor and a continuous-time common-mode feedback loop. The common-mode level detection circuit is used to detect V outn and V outp The output DC level and the reference voltage V ref (V ref Yes V outn and V outp The error is amplified and added to M in the form of negative feedback. 11 and M 12 The gate (also serves as the bias voltage V cmfb ) to adjust the bias current in the common gate branch, thereby adjusting V outn and V outp The output DC level is adjusted to the desired value V ref .

[0013] In one embodiment of the present invention, the chopper operational amplifier modulates the offset to a high frequency, while the useful signal is located at a low frequency after a modulation and demodulation, and the high frequency noise is filtered out by a low-pass filter, thereby eliminating the offset and suppressing the 1 / f noise of the operational amplifier. in First, the clock signal The controlled "chopper switch" periodically reverses the polarity of the input signal, which is equivalent to switching the input signal through a period of T = 1 / f ch The modulated signal is modulated by a square wave. os The differential amplifier at the output of the op amp, the amplified Vin exist The second “chopping switch” will amplify the V in Demodulate back to DC, and at the same time convert the offset V os Modulate to The harmonics are then filtered out by the LPF, leaving only the amplified input signal without the offset component. In this process, V os Modulate only once, modulate to f ch At the frequency, it can be filtered out by LPF, while the input signal is modulated and demodulated and amplified normally.

[0014] In one embodiment of the present invention, a limited current gain compensation part is added to the bias current generating circuit, and a β (limited current gain of BJT) compensation resistor is added to correct the V caused by β. BE In the bias circuit structure, the transistor V BE There is an error amount Adding this error, the transistor V BE The expression can be written as: To reduce the gain on V BE The influence of current gain compensation technology is adopted. The transistor Q 2 A compensation resistor R is connected in series with the base β . R β The size is R 1 / p, in this design, p = 5, and the following derivation is performed using the virtual short characteristic of the operational amplifier: At this time, the new bias current can be expressed as: If the bias current is used to bias the transistor Q 3 , V BE The β in the expression is cancelled, becoming: In this formula, ΔV BE The influence of β is relatively small. The application of current gain compensation technology can effectively suppress the effect of limited current gain β on V BE The influence of the system is very good.

[0015] In one embodiment of the present invention, the bias current generating circuit, taking into account that the temperature-sensitive characteristic of the bias resistor will ultimately affect the curvature of the temperature-voltage relationship, performs second-order curvature compensation, characterized in that a resistor with a negative first-order temperature coefficient reduces the curvature, while a resistor with a positive temperature coefficient may increase the curvature. It can be proved that when the second-order curvature is zero, the theoretical optimal value of the bias resistor temperature coefficient is as follows: For typical values, η = 4, m = 1 and T r =300K, the optimal first-order temperature coefficient of resistance is -0.0033K-1 and 0.01K -1 In this design, after a lot of simulation tests in the early stage, we chose a temperature coefficient of -0.001K -1 The bias resistor has a temperature coefficient that can minimize the curvature of the final voltage-temperature curve. On the other hand, the temperature coefficient can be achieved by using a polysilicon resistor.

[0016] In one embodiment of the present invention, the sampling and holding circuit effectively reduces the attenuation that the input voltage signal may experience when passing through the sampling and holding circuit by setting the gate-source voltage of the switch tube to a constant voltage value. The sampling and holding circuit is controlled by a clock signal and includes a MIM capacitor.

[0017] In one embodiment of the present invention, the comparator circuit adopts a pre-amplifier + latch structure to improve the accuracy of the comparator and achieve the ability to distinguish small voltage differences.

[0018] The pre-amplifier uses a cross-coupled MOS tube pair and a diode load pair as the load of the amplifier. Since the cross-coupled MOS tube introduces positive feedback in the circuit, it shows a negative resistance characteristic externally.

[0019] The inputs VIN+ and VIN- of the latch are connected to VO+ and VO- of the preamplifier respectively. The preamplifier amplifies the input differential small signal into a larger differential voltage signal and serves as the input voltage signal of the latch.

[0020] In one embodiment of the present invention, the DAC capacitor array circuit adopts V cm -based strategy, in the initial stage, the bottom plates of the capacitors are reset to Vcm. When the comparator starts to compare under the control of the timing signal, the output signal of the comparator is fed back to the DAC array through the SAR logic module. According to the charge scaling principle, when V+ is greater than V- at this time, the lower plate of the capacitor on the V+ side will be connected to GND, so that the potential at V+ will drop, and the lower plate of the capacitor on the V- side will be connected to Vref, so that the potential at V- will rise; when V- is greater than V+ at this time, the lower plate of the capacitor on the V- side will be connected to GND, so that the potential at V- will drop, and the lower plate of the capacitor on the V+ side will be connected to Vref, so that the potential at V+ will rise.

[0021] In one embodiment of the present invention, the SAR logic circuit, the overall circuit structure is composed of a D flip-flop, including a sample-hold switch control signal Clks, a comparator control signal Clkc, and a DAC capacitor array switch control signal CLK1-CLK12. Clks is used to sample the input signal, using two clock cycles as the sampling phase to ensure that the sampling bandwidth is greater than the Nyquist frequency. The SAR ADC circuit requires 14 clock cycles for one conversion. At a sampling rate of 1MS / s, this design uses a global clock of 14MHz. Clkc is a comparator control signal that controls the comparator to compare the input signal according to a preset timing and generate a complementary output signal.

[0022] Compared with the prior art, the present invention has the following beneficial effects:

[0023] The present invention provides a novel wide-range and high-precision temperature sensor circuit based on a BJT architecture, including: a temperature sensing core circuit, a bias current generating circuit, a chopper amplifier, a startup circuit and a SAR ADC readout circuit. A common source and common gate current mirror is adopted, and the DEM technology is adopted in the circuit to reduce the mismatch. In order to reduce the impact of the operational amplifier offset voltage and 1 / f noise, compared with the traditional chopper operational amplifier, the present invention uses a new chopper technology for the operational amplifier to further reduce the offset voltage and noise. At the same time, the innovative introduction of limited current gain compensation, second-order curvature compensation and circuit gain detection is used to reduce the error. Compared with the existing technology, it can better realize the design of a higher-precision temperature sensor structure while having low noise, wide range and strong stability.

[0024] In addition, the BJT architecture-based temperature sensor proposed in the present invention can be used in aerospace, smart agriculture, wearable electronics, smart home and other fields, and has a wide range of applications.

[0025] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 This is a structural diagram of a novel wide-range and high-precision temperature sensor circuit based on a BJT architecture provided by an embodiment of the present invention;

[0027] Figure 2 It is a circuit diagram of a temperature sensing front-end circuit in a novel wide-range and high-precision temperature sensor circuit based on a BJT architecture provided by an embodiment of the present invention;

[0028] Figure 3 This is a structural diagram of a SAR ADC in a novel wide-range and high-precision temperature sensor circuit based on a BJT architecture provided by an embodiment of the present invention;

[0029] Figure 4It is a circuit diagram of a chopper amplifier circuit in a novel wide-range and high-precision temperature sensor circuit based on a BJT architecture provided by an embodiment of the present invention;

[0030] Figure 5 It is a circuit diagram of a SAR logic circuit in a novel wide-range and high-precision temperature sensor circuit based on a BJT architecture provided by an embodiment of the present invention;

[0031] Figure 6 It is a circuit diagram of a DAC capacitor array circuit in a novel wide-range and high-precision temperature sensor circuit based on a BJT architecture provided by an embodiment of the present invention;

[0032] Figure 7 It is a result schematic diagram of a novel wide-range and high-precision temperature sensor based on a BJT architecture provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0033] The present invention is further described below in conjunction with specific embodiments, but the embodiments of the present invention are not limited thereto.

[0034] Figure 1 1 is a structural diagram of a novel wide-range, high-precision temperature sensor circuit based on a BJT architecture provided by an embodiment of the present invention. Figure 1 As shown, the present invention provides a novel wide-range high-precision temperature sensor circuit using CMOS technology, including: a temperature sensing front-end circuit and a SAR ADC readout circuit.

[0035] Figure 2 This is a circuit diagram of a temperature sensing front-end circuit in a new wide-range, high-precision temperature sensor circuit based on a BJT architecture provided by an embodiment of the present invention. Figure 2 As shown in FIG. 1 , the temperature sensing front end includes a temperature sensing core circuit, a bias current generating circuit, a chopper amplifier circuit, a proportional amplifier circuit with common-mode feedback, and a startup circuit. The high-precision bias current generating circuit provides the required bias current for the two substrate PNPs of the temperature sensor device. The output of the temperature sensing core is V BE1 and V BE2 The bias current generation circuit and the temperature sensing core circuit both use common source and common gate current mirrors, and use DEM technology to reduce mismatch. The chopper amplifier is used to reduce the impact of the operational amplifier offset voltage in the bias current circuit. Due to the limited number of bits in the ADC reading circuit, it is necessary to reduce ΔV BE Therefore, the V output by the temperature sensing core is amplified to a certain multiple. BE1 and V BE2 Connect to the differential input of the proportional amplifier circuit with common-mode feedback to amplify it to a set multiple. The startup circuit is used to ensure that the circuit is out of the zero current degenerate point and inject current into the tube when powered on.

[0036] In one embodiment of the present invention, the temperature sensing core circuit uses a PNP transistor as a temperature sensing device, and two 1:1 PMOS common source and common gate current mirrors are biased to the two 1:p PNP transistors respectively to obtain the CTAT voltage and the PTAT voltage, which are input to the back end for temperature reading. In order to reduce the impact of the current mirror mismatch, the DEM technology is used for the current mirror, so that the two current mirrors take turns as separate current sources, and a cycle is formed after two cycles, at which time the current mirror provides two completely identical currents.

[0037] It should be noted that the bias current generating circuit described above converts the PNP tube Q 1 and Q 2 The voltage difference ΔV caused by the op amp clamping BE,b Through a bias resistor (R 1 ) to generate a bias current (I bias =ΔV BE,b / R 1 ), the bias current has a positive temperature coefficient and can compensate for V BE The influence of nonlinearity. The common source and common gate current mirror and PNP tube size ratio setting of the bias current generation circuit and the DEM technology are consistent with the temperature sensing core circuit.

[0038] The startup circuit injects current into the tube when power is turned on to prevent the circuit from entering the zero current degenerate point. N1 The saturation current should be much larger than M P14 , you need to take M N1 The width-to-length ratio is much larger than M P14 , so M P14 Need to take the inverted ratio tube, M N1 Take the normal tube.

[0039] The proportional amplifier circuit is composed of a high-gain folding operational amplifier, a proportional capacitor and a continuous-time common-mode feedback loop. The common-mode level detection circuit is used to detect V outn and V outp The output DC level and the reference voltage V ref (V ref Yes V outn and V outp The error is amplified and added to M in the form of negative feedback. 11 and M 12 The gate (also serves as the bias voltage V cmfb ) to adjust the bias current in the common gate branch, thereby adjusting V outn and V outp The output DC level is adjusted to the desired value Vref .

[0040] It should be noted that the bias current generating circuit adds a limited current gain compensation part, and adding a β (limited current gain of BJT) compensation resistor can correct the V caused by β. BE In the bias circuit structure, the transistor V BE There is an error amount Adding this error, the transistor V BE The expression can be written as: To reduce the gain on V BE The influence of current gain compensation technology is adopted. The transistor Q 2 A compensation resistor R is connected in series with the base β . R β The size is R 1 / p, in this design, p = 5, and the following derivation is performed using the virtual short characteristic of the operational amplifier: At this time, the new bias current can be expressed as: If the bias current is used to bias the transistor Q 3 , V BE The β in the expression is cancelled, becoming: In this formula, ΔV BE The influence of β is relatively small. The application of current gain compensation technology can effectively suppress the effect of limited current gain β on V BE The influence of the system is very good.

[0041] It should be noted that the bias current generating circuit described above takes into account that the temperature-sensitive characteristics of the bias resistor will ultimately affect the curvature of the temperature-voltage relationship, and therefore performs second-order curvature compensation, which is characterized in that the resistor with a negative first-order temperature coefficient reduces the curvature, while the resistor with a positive temperature coefficient may increase the curvature. It can be proved that when the second-order curvature is zero, the theoretical optimal value of the bias resistor temperature coefficient is as shown below For typical values, η = 4, m = 1 and T r =300K, the optimal first-order temperature coefficient of resistance is -0.0033K -1 and 0.01K -1 In this design, after a lot of simulation tests in the early stage, we chose a temperature coefficient of -0.001K -1 The bias resistor has a temperature coefficient that can minimize the curvature of the final voltage-temperature curve. On the other hand, the temperature coefficient can be achieved by using a polysilicon resistor.

[0042] Figure 31 is a structural diagram of a SAR ADC in a new wide-range, high-precision temperature sensor circuit based on a BJT architecture provided by an embodiment of the present invention. Figure 3 As shown, the SAR ADC readout circuit includes a sampling and holding circuit, a comparator circuit, a DAC capacitor array circuit and a SAR logic circuit. The input signal of the SAR ADC circuit is the differential output signal OUTP and OUTN provided by the temperature sensing circuit, and the output signal is a 12-bit digital signal D11-D0. The SAR ADC circuit is used to complete the analog-to-digital conversion function.

[0043] Figure 4 This is a circuit diagram of a chopper amplifier circuit in a new wide-range, high-precision BJT architecture-based temperature sensor circuit provided by an embodiment of the present invention. In one embodiment of the present invention, the chopper operational amplifier modulates the offset to a high frequency, and the useful signal is located at a low frequency after a modulation and demodulation, and the high-frequency noise is filtered out by a low-pass filter, which can eliminate the offset and suppress the 1 / f noise of the operational amplifier. The input voltage V in First, the clock signal The controlled "chopper switch" periodically reverses the polarity of the input signal, which is equivalent to switching the input signal through a period of T = 1 / f ch The modulated signal is modulated by a square wave. os The differential amplifier at the output of the op amp, the amplified V in exist The second “chopping switch” will amplify the V in Demodulate back to DC, and at the same time convert the offset V os Modulate to The harmonics are then filtered out by the LPF, leaving only the amplified input signal without the offset component. In this process, V os Modulate only once, modulate to f ch At the frequency, it can be filtered out by LPF, while the input signal is modulated and demodulated and amplified normally.

[0044] Figure 5 This is a circuit diagram of a SAR logic circuit in a new wide-range, high-precision temperature sensor circuit based on a BJT architecture provided by an embodiment of the present invention. Figure 6As shown, the SAR logic circuit, the overall circuit structure is composed of a D flip-flop, including a sample-and-hold switch control signal Clks, a comparator control signal Clkc, and a DAC capacitor array switch control signal CLK1-CLK12. Clks is used to sample the input signal, using two clock cycles as the sampling phase to ensure that the sampling bandwidth is greater than the Nyquist frequency. The SAR ADC circuit requires 14 clock cycles for one conversion. At a sampling rate of 1MS / s, this design uses a global clock of 14MHz. Clkc is a comparator control signal that controls the comparator to compare the input signal according to a preset timing and generate a complementary output signal.

[0045] Figure 6 This is a circuit diagram of a DAC capacitor array circuit in a new wide-range, high-precision temperature sensor circuit based on a BJT architecture provided by an embodiment of the present invention. Figure 7 As shown, the DAC capacitor array circuit uses V cm -based strategy, in the initial stage, the bottom plates of the capacitors are reset to Vcm. When the comparator starts to compare under the control of the timing signal, the output signal of the comparator is fed back to the DAC array through the SAR logic module. According to the charge scaling principle, when V+ is greater than V- at this time, the lower plate of the capacitor on the V+ side will be connected to GND, so that the potential at V+ will drop, and the lower plate of the capacitor on the V- side will be connected to Vref, so that the potential at V- will rise; when V- is greater than V+ at this time, the lower plate of the capacitor on the V- side will be connected to GND, so that the potential at V- will drop, and the lower plate of the capacitor on the V+ side will be connected to Vref, so that the potential at V+ will rise.

[0046] Figure 7 This is a result schematic diagram of a novel wide-range, high-precision temperature sensor based on a BJT architecture provided by an embodiment of the present invention. It should be noted that the 12-bit digital signal output by the SAR ADC is processed in the digital backend, and the specific operations are as follows:

[0047] Let X = 3·ΔV BE / V BE2 , and is fitted with the temperature according to the following formula:

[0048]

[0049] If there is a certain linear relationship between the output error and the temperature, the following calibration scheme can be adopted:

[0050]

[0051] A small batch of temperature sensors are fitted through single-point calibration, and calibration is performed at a certain temperature point to obtain a calibration value k 1, the coefficient k for each set of data 2 Adjust so that the error is minimized at this temperature point.

[0052] After adopting the above calibration method, an example result of the present invention is as follows Figure 7 As shown (considering the calibration temperature error in actual production, an example of the present invention sets the calibration temperature error to ±0.3°C):

[0053] When the extreme temperature value, extreme process angle and extreme power supply voltage are 27℃ / TT / 3.3V, the error after single-point calibration is -0.584~0.406℃.

[0054] When the extreme temperature value, extreme process angle and extreme power supply voltage are 125℃ / FF / 3.6V, the error after single-point calibration is -0.584~0.539℃.

[0055] When the extreme temperature value, extreme process angle and extreme power supply voltage are -40℃ / SS / 3V, the error after single-point calibration is -0.805~0.402℃.

[0056] It can be seen from the above embodiments that the beneficial effects of the present invention are:

[0057] The present invention provides a novel wide-range and high-precision temperature sensor circuit based on a BJT architecture, including: a temperature sensing core circuit, a bias current generating circuit, a chopper amplifier, a startup circuit and a SAR ADC readout circuit. A common source and common gate current mirror is adopted, and the DEM technology is adopted in the circuit to reduce the mismatch. In order to reduce the impact of the operational amplifier offset voltage and 1 / f noise, compared with the traditional chopper operational amplifier, the present invention uses a new chopper technology for the operational amplifier to further reduce the offset voltage and noise. At the same time, the innovative introduction of limited current gain compensation, second-order curvature compensation and circuit gain detection is used to reduce the error. Compared with the existing technology, it can better realize the design of a higher-precision temperature sensor structure while having low noise, wide range and strong stability.

[0058] In addition, the BJT architecture-based temperature sensor proposed in the present invention can be used in aerospace, smart agriculture, wearable electronics, smart home and other fields, and has a wide range of applications.

[0059] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine different embodiments or examples described in this specification.

[0060] Although the present application is described herein in conjunction with various embodiments, in the process of implementing the claimed application, those skilled in the art may understand and implement other variations of the disclosed embodiments by viewing the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "one" or "an" does not exclude multiple situations. A single processor or other unit may implement several functions listed in a claim. Certain measures are recorded in different dependent claims, but this does not mean that these measures cannot be combined to produce good results.

[0061] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A novel wide range high precision temperature sensor circuit using CMOS technology, characterized in that: include: Temperature sensing front-end circuit, SAR ADC readout circuit; Among them: The temperature sensing front end includes a temperature sensing core circuit, a bias current generating circuit, a chopper amplifier circuit, a common mode feedback, a proportional amplifier circuit and a startup circuit. The high-precision bias circuit provides bias current for the two substrate PNPs of the temperature sensing device. The output of the temperature sensing core is V BE1 and V BE2 . The bias current generation circuit and the temperature sensing core circuit both use common source and common gate current mirrors, and the DEM technology is used in the circuit to reduce the mismatch, and the chopper amplifier is used to reduce the impact of the operational amplifier offset voltage in the bias circuit. Due to the limited number of bits in the ADC readout circuit, it is necessary to convert ΔV BE Amplify to a certain multiple, so the V output of the temperature sensing core BE1 and V BE2 Connect to the differential input of the proportional amplifier circuit with common-mode feedback and amplify to the set multiple. The startup circuit makes the circuit leave the zero current degenerate point and injects current into the tube when powered on. The SAR ADC readout circuit includes a sampling and holding circuit, a comparator circuit, a DAC capacitor array circuit and a SAR logic circuit. The input signal of the SAR ADC circuit is the differential output signal OUTP and OUTN provided by the temperature sensing circuit, and the output signal is a 12-bit digital signal D11-D0. The SAR ADC circuit is used to complete the analog-to-digital conversion function.

2. The temperature sensing core circuit according to claim 1, characterized in that: Using PNP transistors as temperature sensing devices, two 1:1 PMOS cascode current mirrors are used to bias two 1:p PNP transistors respectively to obtain CTAT voltage and PTAT voltage, which are input to the back end for temperature reading. In order to reduce the impact of current mirror mismatch, DEM technology is used for the current mirror, so that the two current mirrors take turns as separate current sources, and a cycle is formed after two cycles. At this time, the current mirror provides two completely identical currents. The bias current generating circuit according to claim 1, characterized in that: The voltage difference ΔV between PNP tubes Q1 and Q2 due to the op amp clamping effect BE，b A bias resistor (R1) is used to generate a bias current (I bias =ΔV BE，b / R1), the bias current has a positive temperature coefficient and can compensate for V BE The impact of nonlinearity. The size ratio of the common source and common gate current mirror and the PNP tube of the bias current generating circuit is consistent with that described in claim 2. At the same time, the DEM technology consistent with that described in claim 2 is adopted. The starting circuit according to claim 1, characterized in that When powered on, current is injected into the tube to prevent the circuit from entering the zero current degenerate point. N1 The saturation current should be much larger than M P14 , you need to take M N1 The width-to-length ratio is much larger than M P14 , so M P14 Need to take the inverse ratio tube, M N1 Take the normal tube. The proportional amplifier circuit as claimed in claim 1 is characterized in that it is composed of a high-gain folding operational amplifier, a proportional capacitor and a continuous-time common-mode feedback loop. The common-mode level detection circuit is used to detect V outn and V outp The output DC level and the reference voltage V ref (V ref Yes V outn and V outp The error is amplified and added to M in the form of negative feedback. 11 and M 12 The gate (also serves as the bias voltage V cmfb ) to adjust the bias current in the common gate branch, thereby adjusting V outn and V outp The output DC level is adjusted to the desired value V ref .

3. The chopper operational amplifier according to claim 2 is characterized in that the offset is modulated to a high frequency, and the useful signal is located at a low frequency after a modulation and demodulation, and the high frequency noise is filtered out by a low-pass filter, thereby eliminating the offset and suppressing the 1 / f noise of the operational amplifier. The input voltage V in First, the clock signal The "chopper switch" controlled by the circuit periodically reverses the polarity of the input signal, which is equivalent to switching the input signal through a period of T = 1 / f ch The modulated signal is modulated by a square wave. os The differential amplifier at the output of the op amp, the amplified V in exist The second "chopper switch" will amplify the V in Demodulate back to DC, and at the same time convert the offset V os Modulate to The harmonics are then filtered out by the LPF, leaving only the amplified input signal without the offset component. In this process, V os Modulate only once, modulate to f ch At the frequency, it can be filtered out by LPF, while the input signal is modulated and demodulated and amplified normally.

4. A bias current generating circuit according to claim 2 is added with a limited current gain compensation part, characterized in that adding a β (limited current gain of BJT) compensation resistor can correct the V caused by β BE In the bias circuit structure described in claim 2, the transistor V BE There is an error Adding this error, the transistor V BE The expression can be written as: To reduce the gain on V BE To reduce the influence of accuracy, a current gain compensation technique is used. A compensation resistor R is connected in series to the base of transistor Q2 in the bias circuit. β . R β The size of is R1 / p. In this design, p=5. The virtual short characteristic of the op amp is used to derive as follows: At this time, the new bias current can be expressed as: If the bias current is used to bias transistor Q3, V BE The β in the expression is cancelled, becoming: In this formula, ΔV BE The influence of β is relatively small. The application of current gain compensation technology can effectively suppress the effect of limited current gain β on V BE The impact is very good versatility.

5. According to the bias current generating circuit of claim 2, considering that the temperature-sensitive characteristic of the bias resistor will eventually affect the curvature of the temperature-voltage relationship, a second-order curvature compensation is performed, characterized in that a resistor with a negative first-order temperature coefficient reduces the curvature, while a resistor with a positive temperature coefficient may increase the curvature. It can be proved that when the second-order curvature is zero, the theoretical optimal value of the bias resistor temperature coefficient is as shown below For typical values, η = 4, m = 1 and T r =300K, the optimal first-order temperature coefficient of resistance is -0.0033K -1 and 0.01K -1 In this design, after a lot of simulation tests in the early stage, we chose a temperature coefficient of -0.001K -1 The bias resistor has a temperature coefficient that can minimize the curvature of the final voltage-temperature curve. On the other hand, the temperature coefficient can be achieved by using a polysilicon resistor.

6. The sample-and-hold circuit according to claim 1, wherein the gate-source voltage of the switch tube is set to a constant voltage value, thereby effectively reducing the attenuation that the input voltage signal may experience when passing through the sample-and-hold circuit. The sample-and-hold circuit is controlled by a clock signal and includes a MIM capacitor.

7. The comparator circuit according to claim 1 adopts a preamplifier + latch structure to improve the accuracy of the comparator and achieve the ability to distinguish small voltage differences. The pre-amplifier uses a cross-coupled MOS tube pair and a diode load pair as the load of the amplifier. Since the cross-coupled MOS tube introduces positive feedback in the circuit, it shows a negative resistance characteristic externally. The inputs VIN+ and VIN- of the latch are connected to VO+ and VO- of the preamplifier respectively. The preamplifier amplifies the input differential small signal into a larger differential voltage signal and serves as the input voltage signal of the latch.

8. The DAC capacitor array circuit according to claim 1, characterized in that: Using the Vcm-based strategy, in the initial stage, the bottom plates of the capacitors are reset to Vcm. When the comparator starts to compare under the control of the timing signal, the output signal of the comparator is fed back to the DAC array through the SAR logic module. According to the charge scaling principle, when V+ is greater than V- at this time, the lower plate of the capacitor on the V+ side will be connected to GND, so that the potential at V+ will drop, and the lower plate of the capacitor on the V- side will be connected to Vref, so that the potential at V- will rise; when V- is greater than V+ at this time, the lower plate of the capacitor on the V- side will be connected to GND, so that the potential at V- will drop, and the lower plate of the capacitor on the V+ side will be connected to Vref, so that the potential at V+ will rise.

9. The SAR logic circuit according to claim 1, characterized in that: The overall circuit structure is composed of a D flip-flop, including a sample-and-hold switch control signal Clks, a comparator control signal Clkc, and a DAC capacitor array switch control signal CLK1-CLK12. Clks is used to sample the input signal, using two clock cycles as the sampling phase to ensure that the sampling bandwidth is greater than the Nyquist frequency. The SAR ADC circuit requires 14 clock cycles for one conversion. At a sampling rate of 1MS / s, this design uses a 14MHz global clock. Clkc is a comparator control signal that controls the comparator to compare the input signal according to a preset timing and generate a complementary output signal.

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