Preparation method of plane transmission electron microscope sample

By setting a protective layer and mark at the target position of the chip sample and adjusting the FIB cutting angle using the contrast of the mark, the problem of not parallel to the selected surface in the preparation of the flat transmission electron microscope of the semiconductor chip is solved, and the information integrity and sample preparation success rate are improved.

CN120102248APending Publication Date: 2025-06-06SHANGHAI HUALI INTEGRATED CIRCUIT CORP
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Patent Information

Application Number
CN202510398506.0
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2025-03-31
Publication Date
2025-06-06

AI Technical Summary

Technical Problem

During the preparation of planar transmission electron microscope samples of semiconductor chips, it is difficult to ensure that the cutting direction and the selected plane are parallel, resulting in excessive etching of target positions, resulting in missing information, and increasing the difficulty of subsequent failure analysis.

Method used

A protective layer is provided at a target position of the chip sample, and more than three marking openings are formed in the protective layer, and a second material layer different from the protective layer material is filled to form marks. During the FIB cutting process, the cutting angle is adjusted using the contrast difference of the marks to make the cutting surface parallel to the selected surface.

Benefits of technology

By ensuring that the cutting direction and the selected surface are parallel, the TEM sample information integrity is maximized and the success rate of flat TEM sample preparation is improved.

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Abstract

The invention discloses a preparation method of a plane transmission electron microscope sample, which comprises the following steps: providing a chip sample, and forming a protective layer at a target position of the chip sample. And etching more than three mark openings on the protective layer, and filling a second material layer in the mark openings to form marks, wherein the material of the second material layer is different from that of the protective layer. FIB is adopted to perform plane cutting on the selected surface on the chip sample, and in the plane cutting process, the cutting angle is adjusted according to the contrast difference of the marks, so that the cutting surface of the plane cutting is parallel to the selected surface. According to the invention, the cutting direction is parallel to the selected surface, the information integrity of the TEM sample is ensured to the greatest extent, and the sample preparation success rate of the planar TEM sample is improved.
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Description

Technical Field

[0001] The present invention relates to a method for manufacturing a semiconductor integrated circuit, and in particular to a method for preparing a plane view transmission electron microscope (TEM) sample. Background Art

[0002] Transmission Electron Microscope (TEM) uses electron beam as light source and can achieve sub-nanometer resolution. It can be widely used to analyze the organizational morphology, crystal structure, constituent elements and chemical bond state of material micro-regions. It is one of the most powerful means of solid material analysis and the most important physical property analysis method in the analysis of advanced process integrated circuit chips.

[0003] With the continuous development of the semiconductor industry, the minimum critical size has reached less than 10 nanometers. There is no doubt that the application of TEM provides us with a huge space to better analyze the size, film thickness and chemical composition of key devices in the chip.

[0004] Focused ion beam (FIB) is often used to prepare TEM samples, mark and repair circuits in the field of failure analysis in the semiconductor chip manufacturing industry. As semiconductor manufacturing processes become increasingly miniaturized and complex, many structures in chips are becoming increasingly sophisticated, and it is difficult to accurately locate the failure position through conventional cross-section sample preparation methods. Therefore, it is necessary to use FIB to extract the failure area as a whole, and perform ion thinning to prepare a plane view transmission electron microscope sample, and then use TEM to observe the sample. The ultra-high resolution of TEM can accurately locate the failure position, that is, the plane view method. Generally, in the plane view TEM sample preparation process, the etching angle can be adjusted by changing the front and back structures, so as to obtain a thin slice with a thickness of about 150nm and complete information. However, when etching some samples whose tops have been processed to the target layer (top etching) and etching the sample silicon substrate (bottom etching), the etching angle cannot be adjusted according to the structure before the etching stop position, which will cause excessive etching of the target position, resulting in information loss, greatly increasing the difficulty of subsequent failure analysis, and even making subsequent TEM analysis impossible.

[0005] Currently, the preparation of this type of samples depends entirely on the operator's experience and there is no effective solution.

[0006] like Figure 1 FIG. 1 is a schematic diagram of a chip sample during FIB cutting in an existing method for preparing a planar transmission electron microscope sample; the TEM sample is obtained by further FIB cutting of the chip sample 101. Figure 1The figure shows cutting in two directions, namely, cutting from top to bottom, i.e., the -Z direction, corresponding to arrow line 102a, and cutting from bottom to top, i.e., the Z direction, corresponding to arrow line 102b. The XYZ coordinate system is Figure 1 It is marked in .

[0007] During the etching process (top etching) of some samples whose tops have been processed to the target layer and when etching the sample silicon substrate (bottom etching), for example, the etching corresponding to the arrow line 102a, that is, the FIB cutting corresponds to the top etching, and the etching corresponding to the arrow line 102b is the bottom etching. Since there is no corresponding structure for reference to adjust the cutting angle for the top etching and the bottom etching, the two etchings may deviate from the -Z and Z directions, resulting in over-etching.

[0008] like Figure 2 As shown, it is a TEM photo of the target area of ​​the TEM sample formed by the existing method for preparing the planar transmission electron microscope sample; Figure 2 , a photograph of metal lines and through holes (CT) is shown. It can be seen that structural defects are generated in a plurality of shared through holes corresponding to the dotted box 103, which is not conducive to subsequent analysis. Summary of the invention

[0009] The technical problem to be solved by the present invention is to provide a method for preparing a planar transmission electron microscope sample, which can ensure that the cutting direction is parallel to the selected surface, maximize the integrity of TEM sample information, and improve the success rate of planar TEM sample preparation.

[0010] In order to solve the above technical problems, the present invention provides a method for preparing a planar transmission electron microscope sample, comprising the following steps:

[0011] A chip sample is provided, and a protection layer is formed at a target position of the chip sample.

[0012] More than three mark openings are etched on the protection layer and a second material layer is filled in the mark openings to form marks, wherein the material of the second material layer is different from that of the protection layer.

[0013] The selected surface on the chip sample is plane cut by using FIB. During the plane cutting process, the cutting angle is adjusted by using the contrast difference of each mark so that the cutting surface of the plane cutting is parallel to the selected surface.

[0014] A further improvement is that the chip sample has been processed to a target layer, and all layers above the target layer have been thinned and removed.

[0015] A further improvement is that the target layer is formed on the semiconductor substrate, and the target layer has a graphic structure.

[0016] A further improvement is that the top surface of the protective layer is perpendicular to the selected surface, and the cutting direction of the plane cutting is from the top surface of the protective layer to the bottom of the protective layer.

[0017] A further improvement is that the plane cutting includes a first plane cutting and a second plane cutting; the cutting direction of the first plane cutting differs from the cutting direction of the second plane cutting by 180 degrees.

[0018] The first cutting surface is formed after the first plane cutting is completed, and the second cutting surface is formed after the second plane cutting is completed.

[0019] The first cutting surface and the second cutting surface are parallel.

[0020] A further improvement is that the protective layer includes a first protective layer and a second protective layer; the first protective layer and the second protective layer are located on two opposite surfaces of the chip sample; the first protective layer is used for the first plane cutting; and the second protective layer is used for the second plane cutting.

[0021] A further improvement is that the material of the protective layer includes C.

[0022] A further improvement is that the material of the second material layer includes Pt.

[0023] A further improvement is that the protective layer is formed by electron beam (E-beam) deposition.

[0024] A further improvement is that the marking opening is formed by electron beam etching.

[0025] A further improvement is that the second material layer is formed by electron beam deposition.

[0026] A further improvement is that the thickness between the first cutting surface and the second cutting surface meets the requirements of TEM photography.

[0027] A further improvement is that, when viewed in the direction toward the top surface of the protective layer, the shape of the protective layer is rectangular.

[0028] A further improvement is that the number of the marks includes 4, and each of the marks is distributed in four corner areas of the protective layer.

[0029] A further improvement is that, during the plane cutting process, the contrast image of each mark is adjusted by rotating the angle of the chip sample, and when the brightness of the contrast image of each mark is the same, the cutting surface of the plane cutting is parallel to the selected surface.

[0030] Before performing FIB cutting, i.e., plane cutting using FIB, the present invention sets a protective layer at the target position of the chip sample and forms more than three marking openings in the protective layer, and fills the marking openings with a material different from the protective layer to form marks. During the plane cutting process, the cutting angle can be adjusted according to the contrast difference of each mark to ensure that the cutting surface of the plane cutting is parallel to the selected surface. Therefore, the present invention can ensure that the cutting direction is parallel to the selected surface, maximize the integrity of TEM sample information, and improve the success rate of plane TEM sample preparation. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments:

[0032] Figure 1 It is a schematic diagram of a chip sample during FIB cutting in an existing method for preparing a planar transmission electron microscope sample;

[0033] Figure 2 It is a TEM photograph of a target area of ​​a TEM sample formed by an existing method for preparing a planar transmission electron microscope sample;

[0034] Figure 3 is a flow chart of a method for preparing a planar transmission electron microscope sample according to an embodiment of the present invention;

[0035] Figure 4A-4C It is a schematic diagram of a chip sample in each step of the method for preparing a planar transmission electron microscope sample according to an embodiment of the present invention;

[0036] Figure 5A-Figure 5C yes Figure 4A-4C corresponding electron beam image of the protective layer;

[0037] Fig. 6A It is an electron beam image when the cutting direction and the selected surface are not parallel in the etching, i.e., FIB cutting process of the method for preparing a planar transmission electron microscope sample in an embodiment of the present invention;

[0038] Figure 6B It is an electron beam image when the cutting direction is parallel to the selected surface during the etching process of the method for preparing a plane transmission electron microscope sample according to an embodiment of the present invention;

[0039] Figure 6C It is an electron beam image when a graphic structure appears on the cut surface during the etching process of the method for preparing a planar transmission electron microscope sample in an embodiment of the present invention;

[0040] Fig.6D It is a TEM photograph of a target area of ​​a TEM sample formed by the method for preparing a plane transmission electron microscope sample according to an embodiment of the present invention. DETAILED DESCRIPTION

[0041] like Figure 3FIG. 1 is a flow chart of a method for preparing a planar transmission electron microscope sample according to an embodiment of the present invention; FIG. 4A to FIG. 4C FIG. 2 is a schematic diagram of a chip sample 201 in each step of a method for preparing a planar transmission electron microscope sample according to an embodiment of the present invention. The method for preparing a planar transmission electron microscope sample according to an embodiment of the present invention comprises the following steps:

[0042] Step S101: Figure 4A As shown, a chip sample 201 is provided, and a protection layer 202 is formed at a target position of the chip sample 201 . Figure 4A In the embodiment, the chip sample 201 is in a rectangular parallelepiped structure. Figure 4A The coordinate system is also indicated in Figure 4A The protection layer 202 shown in FIG. 2 is located on the top surface of the chip sample 201 .

[0043] Figure 5A An electron beam image of the protective layer 202 is shown in FIG.

[0044] In the embodiment of the present invention, the chip sample 201 has been processed to the target layer, and all layers above the target layer have been thinned and removed.

[0045] The target layer is formed on the semiconductor substrate, and has a pattern structure thereon.

[0046] The protective layer 202 is formed by E-beam deposition. Before growing the protective layer 202, the chip sample 201 needs to be welded on the grid of the FIB device.

[0047] In some embodiments, the material of the protection layer 202 includes C.

[0048] Step S102: Figure 4B As shown, more than three mark openings 203 a are etched on the protection layer 202 and a second material layer is filled in the mark openings 203 a to form marks 203 . The material of the second material layer is different from that of the protection layer 202 .

[0049] In the embodiment of the present invention, the marking opening 203a is formed by electron beam etching.

[0050] The second material layer is formed by electron beam deposition.

[0051] In some embodiments, the material of the second material layer includes Pt.

[0052] In the embodiment of the present invention, when viewed from the top surface of the protective layer 202 , the shape of the protective layer 202 is a rectangle.

[0053] The number of the marks 203 includes 4, and each of the marks 203 is distributed in the 4 corner areas of the protective layer 202. Because 3 points that are not on the same straight line can determine a plane, in other embodiments, the number of the marks 203 can also be 3 or 5 or more.

[0054] Figure 5B FIG. 2 shows an electron beam image of the mark opening 203 a formed in the protective layer 202 .

[0055] Figure 5C An electron beam image of the mark 203 formed in the protective layer 202 is shown in FIG.

[0056] Step S103: Figure 4C As shown, FIB is used to perform planar cutting on the selected surface of the chip sample 201. During the planar cutting process, the contrast difference of each of the marks 203 is used to adjust the cutting angle so that the cutting surface of the planar cutting is parallel to the selected surface.

[0057] In the embodiment of the present invention, during the plane cutting process, the contrast image of each mark 203 is adjusted by rotating the angle of the chip sample 201. When the brightness of the contrast image of each mark 203 is the same, the cutting surface of the plane cutting is parallel to the selected surface.

[0058] like Fig. 6A , is an electron beam image when the cutting direction and the selected surface are not parallel during the etching, i.e., FIB cutting process of the preparation method of the plane transmission electron microscope sample according to the embodiment of the present invention; it can be seen that the brightness of the contrast image of the two marks 203 at the top is different from the brightness of the contrast image of the two marks 203 at the bottom. In the existing method, it is easy to have the situation that the cutting direction and the selected surface are not parallel, but it cannot be monitored in real time, and it is even more impossible to adjust accurately.

[0059] like Figure 6B As shown, it is an electron beam image when the cutting direction is parallel to the selected surface during the etching process of the method for preparing a plane transmission electron microscope sample according to an embodiment of the present invention; after adjusting the cutting angle, it can be seen that the brightness of the contrast images of the four marks 203 are the same, so the cutting direction is parallel to the selected surface.

[0060] like Figure 6C , is an electron beam image when a graphic structure appears on the cut surface during the etching process of the method for preparing a planar transmission electron microscope sample according to an embodiment of the present invention; it can be seen that the graphic structure is displayed on the cut surface.

[0061] In the embodiment of the present invention, the top surface of the protective layer 202 is perpendicular to the selected surface, and the cutting direction of the plane cutting is from the top surface of the protective layer 202 to the bottom of the protective layer 202 .

[0062] The plane cutting includes a first plane cutting and a second plane cutting; the cutting direction of the first plane cutting is 180 degrees different from the cutting direction of the second plane cutting.

[0063] The first cutting surface is formed after the first plane cutting is completed, and the second cutting surface is formed after the second plane cutting is completed.

[0064] The first cutting surface and the second cutting surface are parallel.

[0065] In the embodiment of the present invention, the thickness between the first cutting surface and the second cutting surface meets the requirements of TEM photography, for example, a few nanometers to tens of nanometers or more than 100 nanometers.

[0066] The protective layer 202 includes a first protective layer and a second protective layer; the first protective layer and the second protective layer are located on two opposite surfaces of the chip sample 201; the first protective layer is used for the first plane cutting; the second protective layer is used for the second plane cutting.

[0067] Combine the following Figure 4C The arrow lines 204a and 204b in the figure further illustrate the first plane cutting and the second plane cutting:

[0068] Figure 4C In the figure, the arrow line 204a indicates the cutting direction of the first plane cutting, which is from top to bottom, i.e., -Z direction; Figure 4C The protective layer 202 shown in FIG. 1 is the first protective layer. Since the cutting direction may deviate from the -Z direction during the first plane cutting process, the cutting direction may deviate from the -Z direction. Figure 4C The cutting direction of the plane cutting is adjusted by the contrast difference of each mark 203 shown in the figure, that is, the difference of the contrast image. When the brightness of the contrast images of each mark 203 is consistent, it means that the cutting direction of the first plane cutting is the -Z direction.

[0069] Figure 4C In the figure, the arrow line 204b indicates the cutting direction of the second plane cutting, which is from bottom to top, i.e., the Z direction. At this time, it is necessary to Figure 4C The bottom surface of the chip sample 201 shown forms the corresponding protective layer 202, i.e., the second protective layer, and the corresponding mark 203. Figure 4CThe structure of the bottom surface of the chip sample 201 is not shown. Similarly, by utilizing the contrast difference of the marks 203 on the bottom surface of the chip sample 201, the cutting direction of the second plane cutting corresponding to the arrow line 204b can be adjusted to the Z direction.

[0070] The embodiment of the present invention can achieve precise adjustment of the cutting direction of each plane cutting, and achieve cutting that is completely parallel to the selected surface, so that the cutting surface is parallel to the selected surface.

[0071] In the embodiment of the present invention, before FIB cutting, i.e., plane cutting using FIB, a protective layer 202 is provided at a target position of a chip sample 201, more than three marking openings 203a are formed in the protective layer 202, and a material different from that of the protective layer 202 is filled in the marking opening 203a to form a mark 203. In the process of plane cutting, the cutting angle can be adjusted according to the contrast difference of each mark 203 to ensure that the cutting surface of the plane cutting is parallel to the selected surface. Therefore, the embodiment of the present invention can ensure that the cutting direction is parallel to the selected surface, thereby maximally ensuring the integrity of TEM sample information and improving the success rate of plane TEM sample preparation.

[0072] like Fig.6D FIG. 1 is a TEM photo of a target area of ​​a TEM sample formed by the method for preparing a planar transmission electron microscope sample according to an embodiment of the present invention. Fig.6D In FIG. 2 , multiple metal lines and through holes (CT) are shown, wherein the multiple shared through holes (share CT) corresponding to the dotted circle 205 are complete in structure, overcoming the problem that Figure 2 The middle dotted circle 103 corresponds to a defect in which the multiple shared through-hole structures are incomplete.

[0073] In an embodiment of the present invention, the target position is found when the FIB prepares the sample, and the planar sample is first welded on the Grid in the target area. The etching angle is judged and adjusted in real time according to the mark difference until parallel etching is achieved. The desired TEM sample can be obtained by thinning the front and back surfaces to a filmable thickness.

[0074] In the embodiment of the present invention, when the plane view method is used to prepare a TEM sample, it is possible to determine whether the ion etching angle is parallel to the sample surface according to the MARK contrast difference.

[0075] The ion etching angle can be adjusted in real time to ensure that the etching angle is parallel to the sample surface, maximizing the information integrity, greatly improving the success rate of the plane view sample preparation method, and laying the foundation for subsequent failure analysis.

[0076] The operation is simple and this method is applicable to samples that have been processed to the target layer in the chip.

[0077] The present invention has been described in detail above through specific embodiments, but these do not constitute limitations of the present invention. Without departing from the principle of the present invention, those skilled in the art may also make many variations and improvements, which should also be considered as the protection scope of the present invention.

Claims

1. A method for preparing a planar transmission electron microscope sample, characterized in that: The steps include: Providing a chip sample, and forming a protective layer at a target position of the chip sample; Etching more than three mark openings on the protective layer and filling the mark openings with a second material layer to form a mark, wherein the material of the second material layer is different from that of the protective layer; The selected surface on the chip sample is plane cut by using FIB. During the plane cutting process, the cutting angle is adjusted by using the contrast difference of each mark so that the cutting surface of the plane cutting is parallel to the selected surface.

2. The method for preparing a planar transmission electron microscope sample according to claim 1, characterized in that: The chip sample has been processed to a target layer, and all layers above the target layer have been thinned and removed.

3. The method for preparing a planar transmission electron microscope sample according to claim 2, characterized in that: The target layer is formed on the semiconductor substrate, and has a pattern structure thereon.

4. The method for preparing a planar transmission electron microscope sample according to claim 2, characterized in that: The top surface of the protective layer is perpendicular to the selected surface, and the cutting direction of the plane cutting is from the top surface of the protective layer to the bottom of the protective layer.

5. The method for preparing a planar transmission electron microscope sample according to claim 4, characterized in that: The plane cutting includes a first plane cutting and a second plane cutting; the cutting direction of the first plane cutting differs from the cutting direction of the second plane cutting by 180 degrees; After the first plane cutting is completed, a first cutting surface is formed, and after the second plane cutting is completed, a second cutting surface is formed; The first cutting surface and the second cutting surface are parallel.

6. The method for preparing a planar transmission electron microscope sample according to claim 5, characterized in that: The protective layer includes a first protective layer and a second protective layer; the first protective layer and the second protective layer are located on two opposite surfaces of the chip sample; the first protective layer is used for the first plane cutting; the second protective layer is used for the second plane cutting.

7. The method for preparing a planar transmission electron microscope sample according to claim 1, characterized in that: The material of the protective layer includes C.

8. The method for preparing a planar transmission electron microscope sample according to claim 9, characterized in that: The material of the second material layer includes Pt.

9. The method for preparing a planar transmission electron microscope sample according to claim 1, characterized in that: The protective layer is formed by electron beam deposition.

10. The method for preparing a planar transmission electron microscope sample according to claim 9, characterized in that: The marking opening is formed by electron beam etching.

11. The method for preparing a planar transmission electron microscope sample according to claim 10, characterized in that: The second material layer is formed by electron beam deposition.

12. The method for preparing a planar transmission electron microscope sample according to claim 5, characterized in that: The thickness between the first cutting surface and the second cutting surface meets the requirements of TEM photography.

13. The method for preparing a planar transmission electron microscope sample according to claim 1, characterized in that: When viewed toward the top surface of the protective layer, the protective layer has a rectangular shape.

14. The method for preparing a planar transmission electron microscope sample according to claim 13, characterized in that: The number of the marks includes 4, and each of the marks is distributed in four corner areas of the protective layer.

15. The method for preparing a planar transmission electron microscope sample according to claim 1, characterized in that: During the plane cutting process, the contrast image of each mark is adjusted by rotating the angle of the chip sample. When the brightness of the contrast image of each mark is the same, the cutting surface of the plane cutting is parallel to the selected surface.

Citation Information

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