Frequency measuring device

Abstract

The invention relates to a frequency measuring device. The frequency measuring device comprises a multi-gear capacitor charging and discharging circuit and a gear switching module, charging voltage peak values formed by charging and discharging sub-circuits in the multi-gear capacitor charging and discharging circuit corresponding to the same clock signal to be measured are different, and output of different gears is formed. When the charging voltage peak value is larger than a first set voltage, the gear switching module enables the charging voltage peak value not to exceed the first set voltage through gear switching, so that voltage signals corresponding to the to-be-tested clock signals in a wide range do not exceed the first set voltage. While the requirement of the circuit for the voltage signal is met, the frequency of the clock signal to be detected can be calculated by using the charging voltage peak value which does not exceed the first set voltage, and wide frequency range detection can be realized.

Description

Technical Field

[0001] The present invention relates to the field of circuit technology, and in particular to a frequency measuring device. Background Art

[0002] The clock circuit provides a continuous working beat signal for the MCU (microcontroller) or SOC (system on chip). If the clock frequency deviation is too large, it will cause abnormal chip communication or even malfunction, so it is very important to accurately measure the clock frequency.

[0003] Since the method of directly sampling the clock signal and processing the sampled data to measure the clock frequency has high performance requirements for the sampling module and the processing module, and the cost is also high, the commonly used frequency measurement method is to use a frequency-voltage conversion circuit to convert the clock frequency into a DC voltage that is linearly related to the clock frequency, and then sample the DC voltage to obtain the clock frequency information by analyzing the sampled data. However, due to the voltage resistance requirements of the resistor and capacitor components in the circuit, the requirements of the ADC (analog-to-digital converter) for the input voltage used for sampling the voltage (such as the input voltage range of the ADC inside many MCUs is limited to 0-3.3V), and the low measurement accuracy of the ADC for weak signals, the existing frequency measurement device can measure a small frequency range. Summary of the invention

[0004] The present invention provides a frequency measuring device, which can ensure that voltage signals corresponding to clock signals to be measured in a wider range do not exceed a set voltage, thereby achieving frequency detection in a wider range while meeting the circuit's requirements for voltage signals.

[0005] The frequency measuring device provided by the present invention comprises:

[0006] A multi-level capacitor charging and discharging circuit, comprising a plurality of charging and discharging sub-circuits, each of which comprises a capacitor, and each of which is used to charge and discharge the corresponding capacitor in response to a clock signal to be measured after being enabled to convert the clock signal to be measured into a voltage signal, and the charging voltage peaks formed by each of the charging and discharging sub-circuits corresponding to the same clock signal to be measured are different;

[0007] A peak detection module, used to detect the charging voltage peak of the enabled charging and discharging sub-circuit;

[0008] a gear switching module, used for comparing the charging voltage peak value output by the peak detection module with a first set voltage, and when the charging voltage peak value is greater than the first set voltage, switching to enable another charging and discharging sub-circuit until the charging voltage peak value does not exceed the first set voltage; and

[0009] The frequency detection module is used to sample the charging voltage peak value and calculate the frequency of the clock signal to be measured using the charging voltage peak value that does not exceed the first set voltage.

[0010] Optionally, the frequency measurement device further includes:

[0011] A shaping module, used for shaping the clock signal to be measured into a square wave signal with a duty cycle of 50%;

[0012] Wherein, each of the charging and discharging sub-circuits charges and discharges the corresponding capacitor in response to the square wave signal after being enabled.

[0013] Optionally, the ratio of the charging current of each of the charging and discharging sub-circuits to the capacitance value of the corresponding capacitor is different.

[0014] Optionally, the capacitance values ​​of the capacitors in each of the charging and discharging sub-circuits are different, and the charging currents are the same; or, the capacitance values ​​of the capacitors in each of the charging and discharging sub-circuits are the same, and the charging currents are different; or, the capacitance values ​​of the capacitors in each of the charging and discharging sub-circuits are different, and the charging currents are different.

[0015] Optionally, the gear switching module first enables the charging and discharging sub-circuit with the largest ratio; when the charging voltage peak is greater than the first set voltage, the other charging and discharging sub-circuits are switched to enable in descending order of the ratios.

[0016] Optionally, each of the charging and discharging sub-circuits includes:

[0017] A constant current source, used for charging the corresponding capacitor;

[0018] an enable switch, coupled between the output end of the constant current source and the upper plate of the capacitor, the lower plate of the capacitor being grounded, the enable switch being turned on or off in response to an enable signal; and

[0019] The discharge switch is coupled between the upper plate and the lower plate of the capacitor, and the clock signal to be measured is coupled to the control end of the discharge switch.

[0020] Optionally, the multi-speed capacitor charging and discharging circuit further includes:

[0021] The gear selection subcircuit comprises a gear selection switch respectively coupled between the upper plate of the capacitor of each of the charging and discharging subcircuits and the input end of the peak detection module, wherein the enable switch in the charging and discharging subcircuit and the gear selection switch coupled to the same charging and discharging subcircuit are turned on or off in response to the same enable signal.

[0022] Optionally, the gear switching module and the frequency detection module are integrated in an MCU, wherein the MCU outputs the enable signal through a GPIO port; the frequency detection module includes an ADC unit and a frequency calculation unit arranged in the MCU, the ADC unit is used to sample the charging voltage peak value and perform analog-to-digital conversion, and the frequency calculation unit is used to calculate the frequency of the clock signal to be measured based on the charging voltage peak value not exceeding the first set voltage.

[0023] Optionally, the gear switching module includes:

[0024] A comparator, used for comparing the charging voltage peak value output by the peak detection module with the first set voltage;

[0025] A first D flip-flop and a second D flip-flop connected in cascade, wherein the CLK pins of the first D flip-flop and the second D flip-flop are connected to the output end of the comparator; and

[0026] The NOR gate logic is used to perform a NOR operation on the Q-end signal of the first D flip-flop and the Q-end signal of the second D flip-flop and output a first enable signal, the Q-end signal of the first D flip-flop and the Q-end signal of the second D flip-flop are respectively the second enable signal and the third enable signal, and the first enable signal, the second enable signal and the third enable signal are respectively enable signals for controlling the enable states of the three charging and discharging sub-circuits.

[0027] Optionally, the frequency measurement device further includes:

[0028] A limiting module is coupled to the output end of the multi-speed capacitor charging and discharging circuit, and the limiting module is used to limit the output end voltage of the multi-speed capacitor charging and discharging circuit to not exceed a second set voltage, and the second set voltage is greater than the first set voltage.

[0029] In the frequency measurement device provided by the present invention, the charging voltage peak values ​​formed by each of the charging and discharging sub-circuits corresponding to the same clock signal to be measured are different, that is, they constitute outputs of different gears. When the charging voltage peak value output by the peak detection module is greater than the first set voltage, the gear switching module switches to enable another charging and discharging sub-circuit until the charging voltage peak value does not exceed the first set voltage, that is, the charging voltage peak value is made to not exceed the first set voltage through gear switching. In this way, the voltage signals corresponding to the clock signals to be measured in a wider range do not exceed the first set voltage. While meeting the circuit requirements for voltage signals, the frequency of the clock signal to be measured can be calculated using the charging voltage peak value that does not exceed the first set voltage, and a wider frequency range detection can be achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 Schematic diagram of the structure of a frequency measurement device according to an embodiment of the present invention.

[0031] Figure 2 It is a circuit diagram of a shaping module in a frequency measurement device according to an embodiment of the present invention.

[0032] Figure 3 The present invention is a circuit diagram of a multi-level capacitor charging and discharging circuit, a peak detection module, and an amplitude limiting module in a frequency measurement device according to an embodiment of the present invention.

[0033] Figure 4 yes Figure 3 Schematic diagram of a charging and discharging sub-circuit in FIG.

[0034] Figure 5 It is a waveform diagram of the square wave signal and the voltage across the capacitor when the capacitor is charged and discharged according to a square wave signal.

[0035] Figure 6 yes Figure 3 Circuit diagram of the mid-range selector subcircuit.

[0036] Figure 7 yes Figure 3 Circuit diagram of the peak detection module.

[0037] Figure 8 1 is a waveform of a clock signal to be measured and an output signal waveform of a peak detection module when a charge and discharge subcircuit of a frequency measurement device according to an embodiment of the present invention is enabled.

[0038] Fig. 9 It is a structural schematic diagram of a frequency measurement device including an MCU module in an embodiment of the present invention.

[0039] Fig.10 FIG. 4 is a circuit diagram of a gear switching module in a frequency measurement device according to another embodiment of the present invention.

[0040] Fig.11 To use Fig.10 The shown graph shows the waveforms of the square wave signal, the first enable signal, the second enable signal and the third enable signal during the gear switching process of the gear switching module. DETAILED DESCRIPTION

[0041] The frequency measuring device of the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0042] As described in the background art, after the clock frequency is converted into a corresponding DC voltage using a frequency-voltage conversion circuit, if the DC voltage is directly sampled, the DC voltage may be very large or very small, exceeding the withstand voltage of the circuit components or not within the input voltage range of the sampling ADC, and affecting the accuracy of the ADC. For example, when the input frequency of a frequency-voltage conversion circuit is 1kHz, the output DC voltage is 1V. If the input frequency increases to 1000kHz, according to the linear relationship, the output DC voltage increases to 1000V, which usually exceeds the withstand voltage of the resistor and capacitor components in the circuit, and also exceeds the input voltage range of the ADC that samples the DC voltage. If the circuit parameters are adjusted so that the frequency-voltage conversion circuit outputs a DC voltage of 1mV at an input frequency of 1kHz, then when the input frequency increases to 1000kHz, the output DC voltage increases to 1V. Although 1V does not exceed the withstand voltage of the resistor and capacitor components and the maximum input voltage of the sampling ADC at this time, the conventional ADC has a very low sampling accuracy for small signals such as 1mV, which affects the accuracy of frequency measurement. Therefore, the frequency range that can actually be measured by existing frequency measurement devices is relatively small.

[0043] Compared with the prior art, the frequency measurement device of the embodiment of the present invention includes a multi-level capacitor charging and discharging circuit, which includes multiple charging and discharging sub-circuits. Each of the charging and discharging sub-circuits can realize frequency-voltage conversion, but the charging voltage peaks formed by each of the charging and discharging sub-circuits corresponding to the same clock signal to be measured are different, that is, voltage outputs of different levels are constituted. According to the different clock signals to be measured, by selecting the charging and discharging sub-circuit with suitable levels, the voltage signals corresponding to the clock signals to be measured in a wider range can not exceed the set voltage, which is convenient for meeting the withstand voltage requirements of the resistor and capacitor components in the circuit and the requirements of the sampling ADC for the input voltage, and a wider range of frequency detection can be achieved.

[0044] Figure 1 The structure of the frequency measuring device according to the embodiment of the present invention is shown. Figure 1 According to this embodiment, the frequency measurement device includes a multi-level capacitor charging and discharging circuit 110, a peak detection module 120, a level switching module 130, and a frequency detection module 140. The specific description is as follows.

[0045] like Figure 1As shown, in order to detect the frequency of the clock signal CLK to be measured, the clock signal CLK to be measured is input into the frequency measurement device. Optionally, the frequency measurement device further includes a shaping module 150, and the shaping module 150 is used to shape the clock signal CLK to be measured so as to control the charging and discharging sub-circuit in the multi-level capacitor charging and discharging circuit 110 to charge and discharge. In this embodiment, the shaping module 150 is used to shape the clock signal CLK to be measured of the frequency to be measured into a square wave signal with a duty cycle of 50%, and the square wave signal is connected to the multi-level capacitor charging and discharging circuit 110 to control the charging and discharging sub-circuit to charge and discharge, that is, each of the charging and discharging sub-circuits in the multi-level capacitor charging and discharging circuit 110 specifically responds to the square wave signal formed by the clock signal CLK to be measured to charge and discharge the corresponding capacitor after being enabled. Figure 2 An exemplary circuit of the shaping module 150 is shown. Figure 2 The shaping module 150, for example, receives the clock signal CLK to be measured, compares it with a reference voltage (such as +2V) using a comparator, and the output signal of the comparator is input into a D flip-flop for frequency division processing, thereby shaping the clock signal CLK to be measured into a square wave signal with a duty cycle of 50%.

[0046] Figure 3 An exemplary circuit of a multi-speed capacitor charge and discharge circuit 110, a peak detection module 120 and a limiting module 160 is shown, wherein the circuits of the first charge and discharge sub-circuit 111, the second charge and discharge sub-circuit 112 and the third charge and discharge sub-circuit 113 in the multi-speed capacitor charge and discharge circuit 110 are the same. Figure 4 FIG. 1 shows a circuit of the first charge-discharge subcircuit 111. Figure 1 , Figure 3 and Figure 4 The multi-level capacitor charging and discharging circuit includes a plurality of charging and discharging sub-circuits (such as the first charging and discharging sub-circuit 111, the second charging and discharging sub-circuit 112 and the third charging and discharging sub-circuit 113 shown in the figure), each of which includes a capacitor (such as Figure 4 The capacitor C1 in the capacitor C2 is configured to charge and discharge the corresponding capacitor in response to a clock signal CLK to be measured after being enabled, so as to convert the clock signal CLK to be measured into a voltage signal, and the charging voltage peak values ​​formed by each of the charging and discharging sub-circuits corresponding to the same clock signal CLK to be measured are different.

[0047] In the multi-level capacitor charging and discharging circuit 110, each charging and discharging subcircuit can realize frequency-voltage conversion, wherein the capacitor charging and discharging process satisfies the following relation (1):

[0048]

[0049] In equation (1), u is the voltage across the capacitor, i is the charging current, t is the time, and c is the capacitance value.

[0050] In this embodiment, the clock signal CLK to be tested that causes the charge-discharge subcircuit to perform charging and discharging is converted into a square wave signal with a duty cycle of 50% by the shaping module 150 . Figure 5 The waveform of the square wave signal and the voltage across the capacitor when the capacitor is charged and discharged according to a square wave signal is shown. Figure 5 , using a square wave signal to control the charging and discharging sub-circuit, the capacitor can be discharged in the positive half cycle of the square wave signal and charged in the negative half cycle. According to equation (1) and the relationship between cycle and frequency, after 1 / 2 cycle (charging time in response to a square wave signal with a duty cycle of 50%), the voltage u across the capacitor is the peak value of the charging voltage, which satisfies the following equation (2):

[0051]

[0052] In the relation (2), f is the charge and discharge frequency. It can be seen from the relation (2) that the charge and discharge frequency f is linearly related to the charging voltage peak. Therefore, when the charge and discharge frequency f changes, the charging voltage peak also changes, that is, frequency-voltage conversion is achieved. When the capacitor is charged and discharged in response to a clock signal CLK to be measured, the voltage u across the capacitor presents an AC signal, and the charging voltage peak can be obtained by detecting the AC signal. The charging voltage peak can be used to infer the charge and discharge frequency f and the frequency of the clock signal CLK to be measured before shaping. This embodiment performs frequency detection by sampling the charging voltage peak according to the above principle.

[0053] Reference Figure 3 and Figure 4 In the multi-speed capacitor charge and discharge circuit 110 of this embodiment, each of the charge and discharge sub-circuits includes a capacitor C1, a constant current source CCS, an enable switch SPST1 and a discharge switch T2. The constant current source CCS is used to charge and discharge the capacitor C1. The enable switch SPST1 is coupled between the output end of the constant current source CCS and the upper plate of the capacitor C1. The enable switch SPST1 is used to enable the corresponding charge and discharge sub-circuit by turning it on and to turn off the corresponding charge and discharge sub-circuit by turning it off. The lower plate of the capacitor C1 is grounded. The discharge switch T2 is coupled between the upper plate and the lower plate of the capacitor C1. The square wave signal formed by the clock signal CLK to be measured through the shaping module 150 is coupled to the control end of the discharge switch T2. When a charging and discharging sub-circuit is enabled, the enabling switch SPST1 in the charging and discharging sub-circuit is turned on, and in the positive half cycle of the square wave signal, the discharging switch T2 is turned on, and the voltage across the capacitor C1 is discharged from the charging voltage peak to zero. In the negative half cycle of the square wave signal, the discharging switch T2 is turned off, and the constant current source CCS charges the capacitor C1, so that the voltage across the capacitor C1 is charged from zero to the charging voltage peak.

[0054] According to the relationship (2), when the ratio of the charging current i to the capacitance c is changed, the proportional relationship between the charging and discharging frequency f and the charging voltage peak value of the charging and discharging sub-circuit can be changed. In the multi-speed capacitor charging and discharging circuit 110 of this embodiment, in each of the charging and discharging sub-circuits, the ratio of the charging current i output by the constant current source CCS to the capacitance value c of the corresponding capacitor C1 is different, so that the proportional relationship between the charging and discharging frequency f and the charging voltage peak value corresponding to each charging and discharging sub-circuit is different, so that when each charging and discharging sub-circuit charges the corresponding capacitor C1 in response to the same clock signal CLK to be measured, the charging voltage peak values ​​formed are different, and different charging voltage peak values ​​can be formed by switching the charging and discharging sub-circuit enable.

[0055] As an example, the capacitance values ​​of the capacitor C1 in each of the charging and discharging sub-circuits are different, while the charging current i of the constant current source CCS is the same, so that the ratios of the charging current i to the capacitance value c of the capacitor C1 are different; but not limited to this, in another embodiment, the ratios of the charging current i to the capacitance value c of the capacitor C1 in each of the charging and discharging sub-circuits are different, and the capacitance value c of the capacitor C1 in each of the charging and discharging sub-circuits is the same while the charging current i of the constant current source CCS is different, or the capacitance value c of the capacitor C1 in each of the charging and discharging sub-circuits is different and the charging current i of the constant current source CCS is different.

[0056] As an example, Figures 1 to 4 As shown, the multi-speed capacitor charge and discharge circuit 110 includes three charge and discharge sub-circuits, namely a first charge and discharge sub-circuit 111, a second charge and discharge sub-circuit 112 and a third charge and discharge sub-circuit 113, wherein the charging current i output by the constant current source CCS in the three charge and discharge sub-circuits is 15mA, and the capacitance value c of the capacitor C1 in the first charge and discharge sub-circuit 111 is 5nF, the capacitance value c of the capacitor C1 in the second charge and discharge sub-circuit 112 is 100nF, and the capacitance value c of the capacitor C1 in the third charge and discharge sub-circuit 113 is 2μF.

[0057] Figure 6 Shows Figure 3 The circuit of the mid-range position selection subcircuit 114. Figure 1 , Figure 3 as well as Figure 6Optionally, the multi-level capacitor charging and discharging circuit 110 further includes a level selection subcircuit 114, wherein the level selection subcircuit 114 includes a level selection switch SPST2 respectively coupled between the upper plate of the capacitor of each of the charging and discharging subcircuits and the input end of the peak detection module 120, wherein the enable switch SPST1 in the charging and discharging subcircuit and the level selection switch SPST2 coupled to the same charging and discharging subcircuit are turned on or off in response to the same enable signal, such as the enable switch SPS in the first charging and discharging subcircuit 111. T1 and the gear selection switch SPST2 coupled to the first charge-discharge sub-circuit 111 are both turned on and off in response to the first enable signal GPIO_1, the enable switch SPST1 in the second charge-discharge sub-circuit 112 and the gear selection switch SPST2 coupled to the second charge-discharge sub-circuit 112 are both turned on and off in response to the second enable signal GPIO_2, and the enable switch SPST1 in the third charge-discharge sub-circuit 113 and the gear selection switch SPST2 coupled to the third charge-discharge sub-circuit 113 are both turned on and off in response to the third enable signal GPIO_3. The output end of the gear selection sub-circuit 114 is the output end of the multi-gear capacitor charge-discharge circuit 110, and the output is the voltage across the capacitor C1 in the currently enabled charge-discharge sub-circuit, which is an AC signal. The gear selection sub-circuit 114 can be integrated into a chip, which includes gear selection switches SPST2 respectively used to couple the corresponding charge-discharge sub-circuits, and the gear selection switches SPST2 are controlled by the corresponding GPIO signals.

[0058] Figure 7 The circuit of the peak detection module 120 is shown. The peak detection module 120 is used to detect the charging voltage peak of the enabled charging and discharging subcircuit. As an example, in the peak detection module 120, the comparator U1 compares the output signal of the peak detection module 120 with the AC signal output by the gear selection subcircuit 114, charges the peak holding capacitor C4 through the diode D1, and the amplifier U2 acts as a follower to adjust the input and output impedance. Figure 8 1 shows the waveform of a square wave signal when a charging and discharging sub-circuit is enabled and the output signal waveform of the peak detection module 120. Figure 1 , Figure 7 and Figure 8 As an example, the first charge-discharge subcircuit 111 is enabled, the frequency of the square wave signal coupled to the first charge-discharge subcircuit 111 is 1 MHz, the AC signal output by the multi-speed capacitor charge-discharge circuit 110 (i.e., the signal output by the gear selection subcircuit 114) is the voltage signal across the capacitor C1 in the first charge-discharge subcircuit 111, and the peak detection module 120 detects the voltage signal to form a 1.5V DC voltage signal, which is output by the amplifier U2. The peak detection module 120 is not limited to Figure 7 The circuit structure shown may adopt various structures capable of sampling the peak voltage of the AC signal.

[0059] Reference Figure 1 and Figure 3 , the frequency measurement device may also include a limiting module 160, the limiting module 160 is coupled to the output end of the multi-speed capacitor charging and discharging circuit 110, and is used to limit the output end voltage of the multi-speed capacitor charging and discharging circuit 110 to not exceed the second set voltage to protect the back-end circuit. In this embodiment, the limiting module 160 is used to clamp the charging voltage peak at the second set voltage when the charging voltage peak output by the multi-speed capacitor charging and discharging circuit 110 is too large. When the charging voltage peak detected by the peak detection module 120 is the second set voltage, it is determined that the charging voltage peak corresponding to the currently enabled charging and discharging sub-circuit is too large, and a gear switching operation is required. By switching the gear, the enabling status of each charging and discharging sub-circuit in the multi-speed capacitor charging and discharging circuit 110 is adjusted so that the charging voltage peak detected by the peak detection module 120 is reduced.

[0060] Reference Figure 1 The gear switching module 130 is used to compare the charging voltage peak value output by the peak detection module 120 with the first set voltage. When the charging voltage peak value is greater than the first set voltage, it switches to enable another charging and discharging sub-circuit until the charging voltage peak value does not exceed the first set voltage. The purpose of switching gears is to make the charging voltage peak value output by the multi-gear capacitor charging and discharging circuit 110 meet the circuit's requirements for voltage signals (such as the withstand voltage requirements of resistors and capacitors and the input voltage requirements of the sampling ADC), and calculate the frequency of the clock signal to be measured based on the charging voltage peak value.

[0061] The gear switching module 130 can be implemented by using a hardware circuit, however, all or part of it can also be implemented by software, for example, by using a software program in conjunction with a device or apparatus.

[0062] Reference Figure 1The frequency measurement device of the embodiment of the present invention includes a gear switching module 130, and the gear switching module 130 is used to compare the charging voltage peak value of the currently enabled charging and discharging sub-circuit output by the peak detection module 120 with a first set voltage, and determine whether the charging voltage peak value is greater than the first set voltage. If the charging voltage peak value is too large, for example, if the charging voltage peak value is equal to the second set voltage after being limited by the limiting module 160 (the second set voltage is greater than the first set voltage), it means that the frequency-voltage conversion characteristic (specifically, for example, the ratio of charging current to capacitance value) of the currently enabled charging and discharging sub-circuit does not match the current clock signal CLK to be measured, and then the gear switching operation is performed. When switching the gear, the currently enabled charging and discharging sub-circuit can be no longer enabled by controlling the above-mentioned enabling switch SPST1, and another charging and discharging sub-circuit with a smaller ratio of charging current to capacitance value can be enabled. When the other charging and discharging sub-circuit is enabled, if the charging voltage peak value is still not less than the first set voltage, the gear switching continues until the charging voltage peak value does not exceed the first set voltage.

[0063] Reference Figure 1 The frequency measurement device of the embodiment of the present invention also includes a frequency detection module 140, which is used to sample the charging voltage peak value and use the charging voltage peak value that does not exceed the first set voltage to calculate the frequency of the clock signal to be measured that currently controls the charging and discharging of the charging and discharging sub-circuit.

[0064] like Fig. 9 As shown, in one embodiment, the gear switching module 130 and the frequency detection module 140 can be integrated in an MCU. The frequency detection module 140 may include an ADC unit and a frequency calculation unit arranged in the MCU, the ADC unit is used to sample the charging voltage peak value and perform analog-to-digital conversion, and the frequency calculation unit is used to calculate the frequency of the clock signal CLK to be measured based on the charging voltage peak value that does not exceed the first set voltage. Through gear adjustment, the charging voltage peak value corresponding to the current clock signal CLK to be measured does not exceed the first set voltage, which meets the circuit's requirements for voltage signals, and then the charging voltage peak value is used to calculate the frequency of the clock signal CLK to be measured.

[0065] In this embodiment, whether each charging and discharging sub-circuit is enabled can be controlled by the MCU, and the enable signal for controlling the enable switch SPST1 and the gear selection switch SPST2 can be output by the MCU through the GPIO port. Specifically, the output signal of the MCU module includes a first enable signal GPIO_1, a second enable signal GPIO_2 and a third enable signal GPIO_3, wherein the first enable signal GPIO_1 is used to control the enable switch SPST1 in the first charge and discharge sub-circuit 111 and the gear selection switch SPST2 coupled to the first charge and discharge sub-circuit 111 in the gear selection sub-circuit 114, the second enable signal GPIO_2 is used to control the enable switch SPST1 in the second charge and discharge sub-circuit 112 and the gear selection switch SPST2 coupled to the second charge and discharge sub-circuit 112 in the gear selection sub-circuit 114, and the third enable signal GPIO_3 is used to control the enable switch SPST1 in the third charge and discharge sub-circuit 113 and the gear selection switch SPST2 coupled to the third charge and discharge sub-circuit 113 in the gear selection sub-circuit 114.

[0066] As an example, frequency measurement using the above frequency measurement device including an MCU may include the following process:

[0067] First, the first enable signal GPIO_1 is used to enable the first charge-discharge sub-circuit 111 in the multi-speed capacitor charge-discharge circuit 110, and the speed selection switch SPST2 is controlled to couple the voltage across the capacitor in the first charge-discharge sub-circuit 111 to the peak detection module 120, and the first set voltage is, for example, 3V;

[0068] If the frequency of the square wave signal coupled to the first charge-discharge subcircuit 111 is between 500kHz and 10MHz, the peak value of the charging voltage output by the first charge-discharge subcircuit 111 is between 150mV and 3V. After the capacitor charging waveform is subjected to peak detection, the peak value of the charging voltage output by the peak detection module 120 sampled by the ADC unit is not greater than 3V, and it is determined that the current square wave frequency matches the first charge-discharge subcircuit 111. The frequency calculation unit calculates the frequency of the clock signal CLK to be measured according to the sampled peak value of the charging voltage.

[0069] If the frequency of the square wave signal coupled to the first charge-discharge sub-circuit 111 is less than 500kHz, the charging voltage peak value output by the first charge-discharge sub-circuit 111 will be greater than 3V, and due to the action of the limiting module 160, the charging voltage peak value is clamped at 3.3V, for example. At this time, the sampling result of the ADC unit is displayed as 3.3V, and 3.3V is greater than 3V, that is, it exceeds the first set voltage, then it is determined that the current square wave frequency does not match the first charge-discharge sub-circuit 111, and the MCU controls the first enable signal GPIO_1 to turn off the first charge-discharge sub-circuit 111 and the peak detection module 120 no longer detects the voltage across the capacitor of the first charge-discharge sub-circuit 111, and controls the second enable signal GPIO_2 to enable the second charge-discharge sub-circuit 112 and the peak detection module 120 detects the voltage across the capacitor of the second charge-discharge sub-circuit 112, so as to realize the gear switching from the first charge-discharge sub-circuit 111 to the second charge-discharge sub-circuit 112;

[0070] After switching to enable the second charge and discharge sub-circuit 112, if the frequency of the square wave signal coupled to the second charge and discharge sub-circuit 112 is between 25k and 500kHz, the peak value of the charging voltage sampled by the ADC unit is less than 3V, and it is judged that the current square wave frequency matches the second charge and discharge sub-circuit 112, and the frequency of the clock signal CLK to be measured is calculated according to the sampling result of the ADC unit; if the sampling result of the ADC unit is still greater than 3V, that is, it exceeds the first set voltage, it means that the square wave signal frequency is less than 25kHz, and it is judged that the current square wave frequency does not match the second charge and discharge sub-circuit 112, then the gear switching continues, switching from the second charge and discharge sub-circuit 112 to the third charge and discharge sub-circuit 113, and so on until the selected charge and discharge sub-circuit is enabled, the peak value of the charging voltage sampled by the ADC unit is less than 3V, and the frequency calculation unit calculates the frequency of the clock signal CLK to be measured according to the peak value of the charging voltage that does not exceed the first set voltage.

[0071] According to the above relationship (2), for the same clock signal to be measured, when the ratio of the charging current to the capacitance value is larger, the corresponding charging voltage peak value output by the charging and discharging sub-circuit is larger. Therefore, in each of the charging and discharging sub-circuits, if the charging voltage peak value generated by a charging and discharging sub-circuit is too large and makes the charging and discharging sub-circuit mismatch with the current clock signal CLK to be measured, since the charging voltage peak value output by the charging and discharging sub-circuit with a larger ratio is larger, it is not necessary to switch to enable the charging and discharging sub-circuit with a larger ratio, and only the charging and discharging sub-circuit with a smaller ratio needs to be selected to be enabled. When the frequency of the square wave signal is completely unknown, in order to facilitate the rapid selection of the charging and discharging sub-circuit whose charging voltage peak value does not exceed the first set voltage, in the gear switching module 130, the charging and discharging sub-circuit with the largest ratio of charging current to capacitance value can be enabled first. When the charging voltage peak value is greater than the first set voltage, the other charging and discharging sub-circuits are switched to be enabled in the order of the ratio from large to small. In addition, since the greater the ratio of the charging current to the capacitance value, the greater the corresponding charging voltage peak value, enabling the charging and discharging sub-circuit with the larger ratio first can avoid the detected charging voltage peak value being too small, thereby avoiding the peak detection module 120 from outputting a weak signal as much as possible. The measurement accuracy of the ADC unit when sampling a weak signal may be low, so switching the charging and discharging sub-circuit enable in the order of the ratio from large to small helps to ensure the measurement accuracy of the ADC unit and improve the accuracy of frequency detection. It can be understood that when the approximate frequency range of the square wave signal is known, the charging and discharging sub-circuit that matches the approximate frequency range can also be directly selected to enable, and whether to switch gears can be automatically selected according to the actual output situation.

[0072] The gear switching module 130 may compare the charging voltage peak value with the first set voltage and perform gear switching without using an MCU, but may be implemented using discrete devices. Fig.10 FIG. 2 shows a circuit diagram of the gear shift module 130 in another embodiment. Figure 1 and Fig.10In another embodiment of the frequency measurement device, the gear switching module 130 includes a comparator, a cascaded first D flip-flop and a second D flip-flop, and an NOR gate logic; wherein the comparator is used to compare the charging voltage peak output by the peak detection module 120 with the first set voltage (for example, +3V). The first D flip-flop and the second D flip-flop are cascaded, and the CLK pins of the first D flip-flop and the second D flip-flop are connected to the output end of the comparator. The NOR gate logic is used to perform an NOR operation on the Q-end (i.e., positive logic output end) signal of the first D flip-flop and the Q-end signal of the second D flip-flop, and output a first enable signal GPIO_1, the Q-end signal of the first D flip-flop is the second enable signal GPIO_2, and the Q-end signal of the second D flip-flop is the third enable signal GPIO_3. The first enable signal GPIO_1, the second enable signal GPIO_2 and the third enable signal GPIO_3 can be respectively used as enable signals for controlling the above-mentioned first charge and discharge sub-circuit 111, the second charge and discharge sub-circuit 112 and the third charge and discharge sub-circuit 113. Specifically, the first enable signal GPIO_1 is used to control the enable switch SPST1 in the first charge and discharge sub-circuit 111 and the gear selection switch SPST2 connected to the first charge and discharge sub-circuit 111 in the gear selection sub-circuit 114, the second enable signal GPIO_2 is used to control the enable switch SPST1 in the second charge and discharge sub-circuit 112 and the gear selection switch SPST2 connected to the second charge and discharge sub-circuit 112 in the gear selection sub-circuit 114, and the third enable signal GPIO_3 is used to control the enable switch SPST1 in the third charge and discharge sub-circuit 113 and the gear selection switch SPST2 connected to the third charge and discharge sub-circuit 113 in the gear selection sub-circuit 114.

[0073] As an example, using Fig.10 The gear switching module 130 shown may perform gear switching by the following process:

[0074] First, in the power-on stage of the circuit, a charging and discharging sub-circuit with the largest ratio of charging current to capacitance value, i.e., the first charging and discharging sub-circuit 111, is set to an enabled state. For example, the first enabling signal GPIO_1 is set to a high level, i.e., the first charging and discharging sub-circuit 111 is enabled. At this time, the clock signal CLK to be measured has not been input, and the peak detection module 120 detects the capacitor voltage of the first charging and discharging sub-circuit 111. The output charging voltage peak value is 0, so the comparator output is a low level, such as Fig.11 As shown in the power-on stage, the Q terminals of the first D flip-flop and the second D flip-flop, i.e., the second enable signal GPIO_2 and the third enable signal GPIO_3, are both at a low level, and the output of the NOR gate logic, i.e., the first enable signal GPIO_1, is at a high level;

[0075] Then, the frequency measurement is performed. If the frequency of the square wave signal obtained by shaping the clock signal CLK to be measured and connected to the multi-speed capacitor charging and discharging circuit 110 is greater than 500kHz, and the charging voltage peak value output by the peak detection module 120 is less than 3V (i.e., less than the first set voltage), then there is no need to switch gears, and the states of the enable signals (GPIO_x) remain unchanged;

[0076] If the frequency of the square wave signal is less than 500kHz, the charging voltage peak value output by the peak detection module 120 is greater than 3V (ie, greater than the first set voltage), Fig.10 The output signal of the comparator shown in FIG. 1 changes from a low level to a high level. Under the trigger of this rising edge, Fig.11 As shown in the "frequency is less than 100kHz" stage, the Q-end output signal of the first D flip-flop, i.e., the second enable signal GPIO_2, will become high level, and the Q-end output signal of the second D flip-flop, i.e., the third enable signal GPIO_3, will continue to maintain a low level. After the NOR gate logic processing, the first enable signal GPIO_1 becomes a low level, so that the first charge and discharge sub-circuit 111 is enabled and closed, and the second charge and discharge sub-circuit 112 is enabled, and the state of the corresponding gear selection switch SPST2 is also changed, so that the peak detection module 120 detects the charging voltage peak of the second charge and discharge sub-circuit 112;

[0077] When the second charging and discharging subcircuit 112 is enabled, if the frequency of the square wave signal is greater than 25kHz, the charging voltage peak value output by the peak detection module 120 is less than 3V (i.e., less than the first set voltage), and there is no need to switch gears, and the states of the enable signals (GPIO_x) remain unchanged. However, if the frequency of the square wave signal is less than 25kHz, the charging voltage peak value output by the peak detection module 120 is greater than 3V (i.e., greater than the first set voltage). Fig.10 The output signal of the comparator shown in FIG. 1 changes from a low level to a high level. Under the trigger of this rising edge, Fig.11 As shown in the "frequency is less than 25kHz" stage, the Q-end output signal of the first D flip-flop, i.e., the second enable signal GPIO_2, becomes a low level, and the Q-end output signal of the second D flip-flop, i.e., the third enable signal GPIO_3, becomes a high level, while the first enable signal GPIO_1 continues to maintain a low level, so that the first charge and discharge sub-circuit 111 and the second charge and discharge sub-circuit 112 are enabled and closed, while the third charge and discharge sub-circuit 113 is enabled, and the state of the corresponding gear selection switch SPST2 is also changed, so that the peak detection module 120 detects the charging voltage peak of the third charge and discharge sub-circuit 113.

[0078] By using the gear switching module 130 to switch gears, after a charging and discharging subcircuit is enabled, the charging voltage peak value output by the peak detection module 120 can be less than the first set voltage. The frequency detection module 140 (for example, integrated in an MCU) can sample the charging voltage peak value that does not exceed the first set voltage and calculate the frequency of the corresponding clock signal CLK to be measured.

[0079] In the frequency measurement device described in the above embodiment, the charging voltage peak values ​​formed by each of the charging and discharging sub-circuits corresponding to the same clock signal CLK to be measured are different, that is, they constitute outputs of different gears. When the charging voltage peak value output by the peak detection module 120 is greater than the first set voltage, the gear switching module 130 is adjusted to enable another charging and discharging sub-circuit, that is, the gear adjustment is performed until the charging voltage peak value does not exceed the first set voltage. In this way, the voltage signals corresponding to the clock signals to be measured in a wider range do not exceed the first set voltage. While meeting the circuit requirements for voltage signals, the frequency of the clock signal CLK to be measured can be calculated using the charging voltage peak value that does not exceed the first set voltage, and a wider frequency range detection can be achieved.

[0080] The above description is only a description of the preferred embodiment of the present invention, and is not any limitation on the scope of rights of the present invention. Any technical personnel in this field can make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the protection scope of the technical solution of the present invention.

Claims

1. A frequency measuring device, It is characterized in that include: A multi-level capacitor charging and discharging circuit, comprising a plurality of charging and discharging sub-circuits, each of which comprises a capacitor, and each of which is used to charge and discharge the corresponding capacitor in response to a clock signal to be measured after being enabled to convert the clock signal to be measured into a voltage signal, and the charging voltage peaks formed by each of the charging and discharging sub-circuits corresponding to the same clock signal to be measured are different; A peak detection module, used to detect the charging voltage peak of the enabled charging and discharging sub-circuit; a gear switching module, used for comparing the charging voltage peak value output by the peak detection module with a first set voltage, and when the charging voltage peak value is greater than the first set voltage, switching to enable another charging and discharging sub-circuit until the charging voltage peak value does not exceed the first set voltage; as well as The frequency detection module is used to sample the charging voltage peak value and calculate the frequency of the clock signal to be measured using the charging voltage peak value that does not exceed the first set voltage.

2. The frequency measuring device according to claim 1, It is characterized in that Also includes: A shaping module, used for shaping the clock signal to be measured into a square wave signal with a duty cycle of 50%; Wherein, each of the charging and discharging sub-circuits charges and discharges the corresponding capacitor in response to the square wave signal after being enabled.

3. The frequency measuring device according to claim 1, It is characterized in that The ratio of the charging current of each of the charging and discharging sub-circuits to the capacitance value of the corresponding capacitor is different.

4. The frequency measuring device according to claim 3, It is characterized in that The capacitance values ​​of the capacitors in each of the charging and discharging sub-circuits are different, and the charging currents are the same; or, the capacitance values ​​of the capacitors in each of the charging and discharging sub-circuits are the same, and the charging currents are different; or, the capacitance values ​​of the capacitors in each of the charging and discharging sub-circuits are different, and the charging currents are different.

5. The frequency measuring device according to claim 3, It is characterized in that The gear switching module first enables the charging and discharging sub-circuit with the largest ratio; when the charging voltage peak is greater than the first set voltage, the other charging and discharging sub-circuits are switched to enable in the order of the ratio from large to small.

6. The frequency measuring device according to claim 1, It is characterized in that Each of the charging and discharging sub-circuits comprises: A constant current source, used for charging the corresponding capacitor; an enable switch, coupled between the output end of the constant current source and the upper plate of the capacitor, the lower plate of the capacitor being grounded, the enable switch being turned on or off in response to an enable signal; and The discharge switch is coupled between the upper plate and the lower plate of the capacitor, and the clock signal to be measured is coupled to the control end of the discharge switch.

7. The frequency measuring device according to claim 6, It is characterized in that The multi-level capacitor charging and discharging circuit further includes: The gear selection subcircuit comprises a gear selection switch respectively coupled between the upper plate of the capacitor of each of the charging and discharging subcircuits and the input end of the peak detection module, wherein the enable switch in the charging and discharging subcircuit and the gear selection switch coupled to the same charging and discharging subcircuit are turned on or off in response to the same enable signal.

8. The frequency measuring device according to claim 6, It is characterized in that The gear switching module and the frequency detection module are integrated in an MCU, wherein the MCU outputs the enable signal through a GPIO port; the frequency detection module includes an ADC unit and a frequency calculation unit arranged in the MCU, the ADC unit is used to sample the charging voltage peak value and perform analog-to-digital conversion, and the frequency calculation unit is used to calculate the frequency of the clock signal to be measured based on the charging voltage peak value that does not exceed the first set voltage.

9. The frequency measuring device according to any one of claims 1 to 8, It is characterized in that The gear switching module comprises: A comparator, used for comparing the charging voltage peak value output by the peak detection module with the first set voltage; A first D flip-flop and a second D flip-flop connected in cascade, wherein the CLK pins of the first D flip-flop and the second D flip-flop are connected to the output end of the comparator; and The NOR gate logic is used to perform a NOR operation on the Q-end signal of the first D flip-flop and the Q-end signal of the second D flip-flop and output a first enable signal, the Q-end signal of the first D flip-flop and the Q-end signal of the second D flip-flop are respectively the second enable signal and the third enable signal, and the first enable signal, the second enable signal and the third enable signal are respectively enable signals for controlling the enable states of the three charging and discharging sub-circuits.

10. The frequency measuring device according to any one of claims 1 to 8, It is characterized in that Also includes: A limiting module is coupled to the output end of the multi-speed capacitor charging and discharging circuit, and the limiting module is used to limit the output end voltage of the multi-speed capacitor charging and discharging circuit to not exceed a second set voltage, and the second set voltage is greater than the first set voltage.

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