Device and method for simulating BCI test

Abstract

The invention discloses a device for simulating a BCI test, and the device comprises a hardware control board, the input end of the hardware control board is connected with a signal generator and two DC power supplies, and the output end of the hardware control board is connected with a chip to be tested; the hardware control board comprises an LC network, and the LC network is connected with two direct-current power supplies through two switches. The equivalent interference is directly conducted to the test port of the chip to be tested, so that the test equipment is simplified, the test cost is reduced, and fault analysis is facilitated.

Description

Technical Field

[0001] The present invention belongs to the field of automotive chips, and more specifically, relates to a testing method and device for simulating BCI testing to implement chip testing. Background Art

[0002] Bulk Current Injection (BCI) test is a common test item for automotive electronics and other products. The interference signal is induced into the wiring harness through the current injection probe to test the product's anti-interference ability to couple to the wiring harness. The national standard GB / T 33014.4 defines the test method. The BCI test system is required to be completed in a shielded room. The signal source outputs the RF signal to the power amplifier, and the power amplifier amplifies the signal and directly outputs it to the current injection probe. The system can be controlled by professional test software to complete the test.

[0003] Chips are an important part of automotive electronic products, and their reliability will directly affect the BCI test results of electronic products. Usually, after the chips are returned, they need to be tested by BCI to ensure the stability and reliability of the chips.

[0004] BCI testing needs to be conducted in a professional laboratory, which is expensive. If there is a problem with the test, it is necessary to repeatedly test and analyze the problem, which will incur high testing costs. At the same time, during the BCI test, the chip is in a shielded room, and the internal state of the chip cannot be well monitored, which limits many analysis methods and makes problem analysis difficult.

[0005] After searching, it was found that a Chinese patent with publication number CN110794429B disclosed a BCI electromagnetic effect equivalent replacement test method for drone GPS modules on February 14, 2020. Its defects are: the test requires a complex equipment environment, such as signal generators, power amplifiers, directional couplers, attenuators and injection probes, etc. In order to meet BCI tests of different frequencies, power amplifiers with different bandwidths need to be replaced; and due to the non-fixed conduction attenuation and spatial radiation attenuation, the actual injection power needs to be frequently adjusted according to the frequency, which is inefficient.

[0006] A Chinese patent application with publication number CN117723867A disclosed a large current injection device on March 19, 2024. Its defects are: using a signal generator for direct output, the output power of the signal generator is limited, and ordinary signal generators cannot output high power when the frequency exceeds 1MHz. It is not compatible with high frequency and high power, and the control is complex. Summary of the invention

[0007] In order to solve the problems of complex analysis and high testing cost in BCI testing, the present invention provides a device and method for simulating BCI testing, which simplifies the testing equipment, reduces the testing cost and facilitates fault analysis by directly conducting equivalent interference to the test port of the chip to be tested.

[0008] According to one aspect of the invention specification, there is provided a device for simulating BCI testing, comprising a hardware control board, wherein an input end of the hardware control board is connected to a signal generator and two DC power supplies, and an output end is connected to a chip to be tested; the hardware control board comprises an LC network, and the LC network is respectively connected to two DC power supplies through two switches.

[0009] As a further technical solution, the LC network includes a length-controllable wiring harness and a capacitor, one end of the length-controllable wiring harness is connected to the output of the switch, the other end is connected to the capacitor and the chip to be tested, and the other end of the capacitor is grounded.

[0010] As a further technical solution, the output voltages of the two DC power supplies are adjustable.

[0011] As a further technical solution, the voltages of the two DC power supplies are adjusted according to a 5V, 12V or 24V power supply system.

[0012] As a further technical solution, the output end of the signal generator is also connected to the control end of the chip to be tested.

[0013] As a further technical solution, the phase relationship between the two output ends of the signal generator is adjustable.

[0014] As a further technical solution, the output end of the hardware control board is connected to the power supply of the chip to be tested.

[0015] According to one aspect of the present invention, a method for simulating BCI testing is provided, which is implemented using the device, and the method comprises: After the device is connected, set the outputs of the two DC power supplies so that the power supply of the chip under test has a stable voltage input; Connect the debugger to the chip under test and download the test program to the chip under test; Set the output frequency of the signal generator to generate interference on the power supply of the chip under test; According to the working state of the chip under test during the interference period, it is determined whether an abnormality occurs in the chip under test during the test.

[0016] As a further technical solution, the method further includes: The other output terminal of the signal generator is connected to the reset pin of the chip under test, and the moment when the interference occurs in the chip under test is adjusted by adjusting the phase of the two output terminals of the signal generator.

[0017] Compared with the prior art, the present invention has the following beneficial effects: 1. The experimental environment and equipment of the present invention are simple, and the BCI test of the chip is carried out in a low-cost manner.

[0018] 2. The present invention only requires a power supply, a signal generator and a hardware control board to achieve interference injection of different frequencies and powers.

[0019] 3. During the testing process, the present invention can be connected to various measuring and debugging equipment, which is conducive to problem analysis and location.

[0020] 4. The present invention uses direct conduction injection instead of space radiation injection, which is simple to debug and efficient to use.

[0021] 5. The present invention can accurately control the moment when interference occurs and can test each stage of chip operation in a targeted manner. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, a brief introduction is given below to the drawings used in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0023] Figure 1 It is a schematic diagram of a testing device provided in an embodiment of the present invention.

[0024] Figure 2 It is a schematic diagram of a testing device provided in yet another embodiment of the present invention.

[0025] Figure 3 It is a test connection schematic diagram provided by an embodiment of the present invention.

[0026] Figure 4 It is a schematic diagram of interference waveform provided by an embodiment of the present invention.

[0027] Figure 5 It is a schematic diagram of a test flow provided by an embodiment of the present invention.

[0028] Figure 6 This is a test connection diagram provided by another embodiment of the present invention. DETAILED DESCRIPTION

[0029] In order to facilitate the effective analysis of BCI test problems and failures and reduce the test cost, the present invention proposes a device and method for simulating BCI testing using a simple device, which can be used for chip testing. Specifically, the present invention simulates the effect of BCI testing by interfering with the power supply (VDD) and general input and output ports (GPIO) of the chip.

[0030] The essence of BCI testing is that electromagnetic interference acts on the chip under test through spatial coupling. However, spatial coupling has extremely high requirements on the performance, type and environmental stability of the equipment. Therefore, the test is susceptible to external interference and the debugging process is complicated. In order to solve this problem, the present invention focuses on the core demand of anti-interference and adopts a method of directly conducting equivalent interference to the test port of the chip under test, which simplifies the test equipment, stabilizes the environment, and improves the convenience of debugging.

[0031] Through the method of the present invention, the entire test process is easy to operate, has low environmental requirements, does not need to be tested in a shielded room, and can flexibly connect and debug equipment, thereby facilitating rapid problem analysis and location. This method can not only serve as a preliminary test before the formal BCI test, reducing test costs, but also improve test efficiency and reduce equipment and environmental requirements.

[0032] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention. In addition, the technical features in the various embodiments or single embodiments provided by the present invention are arbitrarily combined with each other to form a new technical solution. This combination is not restricted by the sequence of steps and / or the structural composition mode, but must be based on the ability of ordinary technicians in this field to achieve. When the combination of technical solutions is contradictory or cannot be achieved, it should be considered that this combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0033] The present invention provides a simple test device to simulate BCI equivalent test, such as Figure 1 As shown, the test device includes: two DC power supplies, a hardware control board, and a signal generator. The hardware control board is mainly composed of a length-controllable wiring harness, capacitors, and two switches K1 / K2. The key component of the K1 / K2 switch is a high-speed MOS, and the opening and closing speed can reach 20+ns. The entire test equipment can generate directional interference with a maximum frequency of 50MHz, adjustable amplitude, and adjustable power.

[0034] Connect DC power supply 1, DC power supply 2 and signal generator to the hardware control board. Adjust the output voltage of DC power supply 1 and DC power supply 2 according to the typical 5V, 12V or 24V power supply system. For example, in a 5V system, the output of DC power supply 1 can be set to 8V, and the output of DC power supply 2 can be set to 3V. At the same time, control the signal generator to output PWM wave, and then control the conduction state of K1 and K2, so that a 3V~8V voltage oscillation is formed at node A.

[0035] One end of the controllable length harness in the control board is connected to the output of the K1 / K2 switch, and the other end is connected to the capacitor to the ground. The high-speed level change will cause resonance after passing through the LC network, and the resonant frequency is When the capacitance is constant, oscillations of different frequencies can be achieved by controlling the length of the wiring harness, so that the hardware control board outputs power interference of a specific frequency.

[0036] Optional, in Figure 1 On this basis, we can increase the control of chip signals, such as the control of reset pins, so as to achieve precise adjustment of the time when interference signals occur. Specifically, for example, for MCU chips, by controlling the timing of MCU reset signal and K1 / K2 switch, the time when interference occurs can be controlled.

[0037] The specific implementation method is as follows: Figure 1 On the basis of , connect the output terminal 2 of the signal generator to the control pin of the chip. Set the output terminal 1 of the signal generator to output the PWM wave, and the output terminal 2 of the signal generator to output the control signal. By adjusting the phase relationship between the output terminals 1 and 2 of the signal generator, the interference signal can be accurately controlled to occur at a specific time when the chip is running, such as Figure 2 shown.

[0038] When the device of the present invention is implemented, first connect the output of DC power supply 1, the output of DC power supply 2, and the input of the signal generator to the input of the hardware control board, and connect the output of the hardware control board to the power supply (VDD) of the chip under test. Then, set the output voltage of DC power supply 1 and DC power supply 2, and set the output of the signal generator to PWM.

[0039] After completing the above steps, the test begins. You can connect an oscilloscope or other equipment to observe the status of the chip under test. Figure 3 shown.

[0040] Figure 5 Taking the MCU chip as an example, the specific implementation steps are described as follows: Step 1. Connect all devices as required. The output of the hardware control board is connected to the power supply (VDD) of the MCU chip.

[0041] Step 2. Connect the MCU chip VDD and other signals to an oscilloscope and observe the waveform of its power supply (VDD).

[0042] Step 3. Set the output of DC power supply 1 to 8V and the output of DC power supply 2 to 3V, and set the signal generator to output a low level. At this time, the MCU chip VDD input has a stable 3V voltage.

[0043] Step 4. Connect the debugger to the MCU chip and download the program to the MCU chip to make the MCU flash the LED light periodically.

[0044] Step 5. Set the signal generator to output a PWM wave with a frequency of 1MHz. At this time, interference will occur on the MCU chip VDD, and the waveform is as follows: Figure 4 shown.

[0045] Step 6. Observe the LED flashing frequency to determine the working status of the MCU chip. If the LED flashing cycle changes, it can be determined that the MCU chip has an abnormality during the interference period.

[0046] Step 7. Stop the interference and observe whether the LED flashes normally. If not, the MCU chip has an abnormality during the test.

[0047] As a preferred embodiment, in order to control the time when interference occurs (for example, to control interference to occur when the MCU runs at different clocks), the present invention provides another device connection diagram as shown in FIG. Figure 6 shown.

[0048] The specific implementation is as follows: Step S1. Connect all devices as required, and the output of the hardware control board is connected to the power supply (VDD) of the MCU chip.

[0049] Step S2: Connect the MCU chip VDD and other signals to an oscilloscope to observe the waveform of its power supply (VDD).

[0050] Step S3. Set the output of DC power supply 1 to 8V, the output of DC power supply 2 to 3V, and set the output terminal 1 of the signal generator to output a low level. At this time, the VDD input of the MCU chip stabilizes the voltage of 3V.

[0051] Step S4. Set the signal generator output terminal 2 to connect the reset pin of the MCU chip and output a high level.

[0052] Step S5. MCU is connected to the debugger, and the program is downloaded to the MCU to make the MCU LED flash periodically, and when the MCU switches the clock (internal low-speed clock is switched to PLL high-speed clock), the MCU chip output port 1 (GPO1) is pulled low.

[0053] Step S6. Set the frequency of the signal generator output terminal 2 to 10KHz.

[0054] Step S7. Adjust the phase of the signal generator output terminal 1 and the signal generator output terminal 2 to adjust the interference to occur at a certain time when the MCU is running. Adjust the appropriate phase to control the interference to occur when the MCU is running with the internal clock.

[0055] Step S8. Set the output frequency of the signal generator output terminal 1 to 10KHz, generating interference on the power supply (VDD) of the MCU chip.

[0056] Step S9: After testing for a period of time, stop interfering and observe whether the LED flashes normally.

[0057] Step S10: Turn off the DC power output and then turn it on again to power off / on the MCU.

[0058] Step S11. Adjust the phase of the signal generator output terminal 1 and the signal generator output terminal 2 again to control the interference to occur when the MCU runs at the PLL high-speed clock.

[0059] Step S12: Set the output frequency of the signal generator output terminal 1 to 10KHz, and generate interference on the power supply (VDD) of the MCU chip.

[0060] Step S13: After testing for a period of time, stop interfering and observe whether the LED flashes normally.

[0061] It should be noted that the present invention can also connect the output of the hardware control board to the general input and output port (GPIO) to achieve interference with the GPIO, thereby simulating the effect of the BCI test. The test method and steps in this embodiment are the same as those of interfering with VDD, so they are not repeated here.

[0062] In summary, the present invention achieves a similar BCI test effect through a set of simple devices. The present invention uses a signal generator, a DC power supply and a hardware control board to generate a directional interference with a maximum frequency of 50MHz, an adjustable injection power, and compatibility with a 5V~24V battery system, and then directly couples the interference to the chip end to be tested to simulate a real BCI test. The test environment described in the present invention is simple, can significantly reduce test costs, and improve test efficiency.

[0063] The terms "including" and "having" and any variations thereof in the specification and claims of the present invention and the above-mentioned drawings are intended to cover non-exclusive inclusions, for example, a process, method, system, product or apparatus comprising a series of steps or units is not necessarily limited to the steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products or apparatuses.

[0064] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the technical solutions of the embodiments of the present invention.

Claims

1. A device for simulating BCI testing, characterized in that: It comprises a hardware control board, the input end of which is connected to a signal generator and two DC power supplies, and the output end is connected to a chip to be tested; the hardware control board comprises an LC network, and the LC network is respectively connected to the two DC power supplies through two switches.

2. A device for simulating BCI testing according to claim 1, characterized in that: The LC network includes a length-controllable wiring harness and a capacitor. One end of the length-controllable wiring harness is connected to the output of the switch, and the other end is connected to the capacitor and the chip to be tested. The other end of the capacitor is grounded.

3. The device for simulating BCI testing according to claim 1, characterized in that: The output voltages of the two DC power supplies are adjustable.

4. The device for simulating BCI testing according to claim 3, characterized in that: Regulates the voltage of two DC power supplies according to 5V, 12V or 24V power supply system.

5. The device for simulating BCI testing according to claim 1, characterized in that: The output end of the signal generator is also connected to the control end of the chip to be tested.

6. The device for simulating BCI testing according to claim 5, characterized in that: The phase relationship between the two output ends of the signal generator is adjustable.

7. The device for simulating BCI testing according to claim 1, characterized in that: The output end of the hardware control board is connected to the power supply of the chip to be tested.

8. A method for simulating BCI testing, implemented by the device according to any one of claims 1 to 7, characterized in that: The method comprises: After the device is connected, set the outputs of the two DC power supplies so that the power supply of the chip under test has a stable voltage input; Connect the debugger to the chip under test and download the test program to the chip under test; Set the output frequency of the signal generator to generate interference on the power supply of the chip under test; According to the working state of the chip under test during the interference period, it is determined whether an abnormality occurs in the chip under test during the test.

9. A method for simulating BCI testing according to claim 8, characterized in that: The method further comprises: The other output terminal of the signal generator is connected to the reset pin of the chip under test, and the moment when the interference occurs in the chip under test is adjusted by adjusting the phase of the two output terminals of the signal generator.

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