Navigation signal capturing method based on reconfigurable PMF-FFT algorithm

Abstract

The invention relates to a navigation signal capturing method based on a reconfigurable PMF-FFT algorithm, and belongs to the technical field of satellite navigation. The method comprises the following steps: generating a partial correlation value from input data containing frequency offset / code offset through partial matched filtering (PMF); zero padding is carried out on the result to 2n points, and then the result is input into a reconfigurable FFT module for multi-stage radix-2 operation; by dynamically configuring FFT points (32 / 64 / 128) and multiplexing a twiddle factor ROM (Read Only Memory), resource occupation is optimized; and calculating the frequency offset based on peak detection and threshold judgment. Through ping-pong RAM cache, FIFO switching and cascade butterfly operation, high throughput rate data processing is realized, the problems of resource solidification, data overflow and insufficient resolution in a traditional scheme are solved, the frequency offset estimation error is less than or equal to 5Hz, the power consumption is reduced by 40%, and the method is suitable for real-time signal acquisition in a high dynamic environment.

Description

Technical Field

[0001] The invention belongs to the technical field of satellite navigation and relates to a navigation signal capture method based on a reconfigurable PMF-FFT algorithm. Background Art

[0002] With the widespread application of satellite navigation systems in high-dynamic environments, signal capture technology faces severe challenges such as drastic changes in Doppler frequency deviation and rapid offset of pseudo-code phase. Although the traditional time-domain serial search algorithm has a simple structure, its traversal search mechanism causes the capture time to grow exponentially with the frequency deviation range, making it difficult to meet the millisecond-level real-time requirements in high-dynamic scenarios. Although the cyclic correlation algorithm based on frequency-domain parallel processing shortens the code phase search time through FFT acceleration, its hardware implementation consumes a large amount of multiplier resources, and the resolution of Doppler frequency deviation is limited by the number of FFT points. When the frequency deviation range is expanded, it faces the problem of a surge in storage resources and rising power consumption.

[0003] In recent years, the PMF-FFT (partially matched filter-fast Fourier transform) algorithm has attracted attention due to its code / frequency two-dimensional parallel search capability. The algorithm reduces the frequency domain processing complexity through segmented correlation operations, and theoretically can expand the frequency offset capture range while maintaining high sensitivity. However, the existing hardware implementation scheme has significant defects: (1) The resources are severely fixed. The FFT module is fixed to a single operation point and cannot adaptively adjust the calculation granularity according to the dynamic environment, resulting in insufficient resolution in low carrier-to-noise ratio scenarios or resource waste in high dynamic scenarios; (2) The data path is rigid. A static buffer mechanism is used between the partial matched filter (PMF) output and the FFT input. When the FFT calculation cycle and the PMF output rate do not match, it is easy to cause data overflow or interruption; (3) The rotation factor storage is redundant. Each level of the traditional FFT is equipped with an independent ROM to store the rotation factor, which causes repeated occupation of storage resources in the reconfigurable mode.

[0004] The patent with publication number CN109977347A proposes a variable-point FFT processor that realizes different point transformations by configuring the butterfly operation series, but it does not solve the problem of coordinated control of PMF segment correlation and FFT dynamic reconstruction, and the rotation factor addressing mechanism is not optimized, resulting in an increase in reconfigurable switching delay. Another document, "High-dynamic GNSS Signal Rapid Capture Method", uses a multi-channel PMF parallel structure to improve throughput, but the FFT module is still a fixed 128-point design and cannot be downgraded to 64-point or 32-point mode as needed in a resource-constrained environment, limiting the applicability of the algorithm on embedded platforms. Therefore, there is an urgent need for a reconfigurable PMF-FFT hardware architecture that combines flexible resource configuration, efficient data scheduling, and accurate frequency offset estimation capabilities to break through the technical bottleneck of high-dynamic navigation signal capture. Summary of the invention

[0005] In view of this, the purpose of the present invention is to provide a navigation signal acquisition method based on a reconfigurable PMF-FFT algorithm. The method takes advantage of the flexible configuration of hardware resources on a reconfigurable computing platform to achieve efficient hardware implementation of the PMF-FFT algorithm, providing a flexible, efficient, and low-cost solution for high-dynamic satellite signal acquisition.

[0006] In order to achieve the above object, the present invention provides the following technical solutions:

[0007] The present invention provides a navigation signal capture method based on a reconfigurable PMF-FFT algorithm. Based on a partial matching filter module, a storage, a reconfigurable FFT operation module, a peak detection and threshold decision module. The method comprises the following steps:

[0008] Partial matched filtering: Input the signal with frequency offset and symbol phase offset into the partial matched filtering module to perform partial correlation operation and obtain partial correlation value;

[0009] Data storage: Each partial matched filter value is sent to the ping-pong RAM in the specified order;

[0010] Data zero padding: Perform N-point zero padding operation on the data stored in the Ping-Pong RAM;

[0011] Reconfigurable FFT operation: The zero-filled data is sent to the reconfigurable FFT module for fast Fourier transform operation;

[0012] Peak detection: square the modulus of the calculated data and compare the square value to the maximum value to obtain the maximum peak value and its index value;

[0013] Threshold decision: compare the maximum peak value with the preset threshold value. If it exceeds the preset threshold value, the frequency deviation estimate is calculated.

[0014] Furthermore, the method further comprises:

[0015] The length of the matched filter X depends on the actual frequency deviation range f of the system. d To determine, the frequency deviation range estimated by the algorithm is f d . According to the frequency deviation range f d The frequency resolution Δf is obtained u =f d / N;

[0016] N=L*(f s / f c )

[0017] N is the total data length and also the total correlation length, L is the pseudo code length used for matched filtering, and f c is the spreading code rate;

[0018] f d =f s / X

[0019] f d is the frequency deviation range that can be estimated by the PMF-FFT algorithm, f s is the sampling rate of the spread spectrum code, X is the length of the partial matched filter and the number of points for partial correlation operation;

[0020] Δf z =f d / Z

[0021] Δf z is the computational resolution of the PMF-FFT algorithm, f d is the frequency deviation range that can be estimated by the PMF-FFT algorithm, and Z is the number of points for FFT after zero padding.

[0022] Furthermore, the design of the partial coherent integration module adopts multiple parallel correlation operation modules.

[0023] Furthermore, the method of the plurality of parallel related operation modules includes:

[0024] Step 1: Create 60 parallel correlators for I and Q paths respectively. The specific number can be modified according to actual indicators and hardware resources.

[0025] Step 2: Create a read-only memory ROM to store the sampled local pseudo code;

[0026] Step 3: The partial correlation operation module groups the N stored data into D groups, where D represents the number of partial matched filters in the partial correlation operation module, and each group has X data, that is, the length of each sub-matched filter, N=DX; the local pseudo code phase is slid, and each parallel correlator slides a code phase, so 60 parallel correlators can detect 60 code phases at a time, and each sliding code sequence is sent to the partial matched filter for correlation operation with the received signal to obtain the data after the correlation operation.

[0027] Furthermore, the data after the relevant operations are sequentially sent to the ping-pong cache, and the ping-pong cache address state machine controls the reading and writing of the data. The storage method includes:

[0028] The correlation operation data from the first correlator is stored in the 0th position of the ping RAM, the correlation operation data from the second correlator is stored in the Dth position of the ping RAM, the data from the third correlator is stored in the 2Dth position of the ping RAM, and the data from the last correlator is stored in the 60D-1 position of the ping RAM. After 2X clocks, the correlation operation data from the first correlator is stored in the 1st position of the RAM, the data from the second correlator is stored in the 2D+1th position of the RAM... All data are stored in the corresponding RAM positions in sequence.

[0029] Furthermore, the zero-filling module fills the end of the partial correlation value of point D stored in the RAM with the power of n points 0 to 2 to form point Z.

[0030] Furthermore, the FFT module adopts a reconfigurable design concept and has reconfigurability, and the number of calculation points of the FFT module can be flexibly configured according to actual hardware requirements and the Doppler frequency deviation range.

[0031] Furthermore, the reconfigurable FFT module includes input and output data, calculation point signal, M-level radix-2 FFT operation and output stage, and the radix-2 FFT operation stage is mainly composed of a FIFO cache module, a butterfly operation module, a complex multiplication module and a ROM rotation factor storage module.

[0032] Furthermore, the butterfly operation module further includes:

[0033] A complex adder, used for generating a first output signal (OUT0);

[0034] A complex subtractor, used for generating a second output signal (OUT1);

[0035] The butterfly operation unit is implemented by the base-2 algorithm, and the input (X m [p],X m [q]) The output is:

[0036]

[0037] Where m is the current level, k is the rotation factor index, and resource consumption is reduced by multiplexing adders and subtractors.

[0038] Furthermore, the complex multiplication module is only included in the first M-1 stages of radix-2 FFT operations, and the Mth stage does not include the complex multiplication module.

[0039] Further, the FIFO buffer module includes:

[0040] In each level of operation, FIFO receives data from different sources alternately, namely input data IN and butterfly operation output OUT1. Whenever the cached data reaches N / 2, m The data source is changed when the FIFO buffer is used; the data in the FIFO buffer is output alternately to different modules, which are the input IN0 of the butterfly operation and the input of the complex multiplier. Whenever the output data reaches N / 2 m The output direction is changed when N is the total number of FFT points, and m is the current operation level (m∈[1,M], M is the total level).

[0041] Furthermore, the ROM rotation factor storage module includes two partitioned sub-ROMs, which are respectively used to store the real part (COS) and the imaginary part (SIN) of the pre-calculated rotation factor value; the ROM rotation factor storage module is only included in the first M-1 level radix-2 FFT operation, and the Mth level does not include the ROM rotation factor storage module.

[0042] The M-1th level ROM rotation factor storage module has a depth of 2 and stores the rotation factor W. Z (0)-W Z (1);

[0043] The ROM twiddle factor storage module depth of level M-2 is 2 2 , the stored rotation factor is W Z (0)-W Z (2 2 -1);

[0044] The ROM twiddle factor storage module depth of level M-3 is 2 3 , the stored rotation factor is W Z (0)-W Z (2 3 -1);

[0045] …

[0046] The ROM twiddle factor memory block depth of level 1 is 2 M-1 , the stored rotation factor is W Z (0)-W Z (2 M-1 -1);

[0047] Further, the real and imaginary parts of the FFT output are squared and their square modulus is calculated, and the frequency index corresponding to each FFT output value is obtained, as shown below:

[0048] |X[k]| 2 =(Re[k]) 2 +(Im[k]) 2

[0049] Where k∈[0,N-1], N is the number of FFT points, and the value represents the energy of the kth frequency point.

[0050] Furthermore, the method for calculating the frequency offset estimation value includes:

[0051] Compare the maximum peak value with a preset threshold value;

[0052] If it is lower than the threshold, the acquisition is not successful; if it is higher than the threshold, the acquisition is successful. At this time, the index value of the corresponding coordinate of the peak is taken to obtain the frequency deviation estimation value:

[0053] f d =(Z*(1-Max_x / Z)+1) / (Z*X*(1 / f s ))

[0054] f d is the frequency offset estimate, Z is the number of fft points, Max_x is the index value corresponding to the highest peak, and X is the length of each matched filter.

[0055] The beneficial effects of the present invention are:

[0056] Beneficial effects of the present invention

[0057] (1) Through the hierarchical control mechanism of the reconfigurable FFT module, the FFT operation points (such as 32 / 64 / 128 points) can be dynamically selected according to the actual frequency deviation range. In low signal-to-noise ratio scenarios, the high-point mode is enabled to improve the frequency resolution (Δf_u=fd / Z), and in high-dynamic scenarios, it switches to the low-point mode to reduce the calculation delay. Compared with the fixed-point FFT design, the hardware resource consumption is reduced by more than 40% (such as 35% reduction in DSP slices and 52% reduction in BRAM occupancy), and the Doppler frequency deviation capture range is expanded to ±50kHz, meeting the real-time requirements of high-dynamic carriers (such as supersonic aircraft).

[0058] (2) A ping-pong RAM and state machine-controlled FIFO cache collaborative architecture is used to achieve seamless connection between PMF output and FFT input. By dynamically switching the data source (IN / OUT1) and output direction (IN0 / complex multiplier), the next batch of data is preloaded during the FFT calculation cycle, avoiding the data overflow problem caused by traditional static buffering. Actual measurements show that when the PMF output rate reaches 20MS / s, the data throughput efficiency is increased to 98.7%, which is 32% higher than the traditional solution.

[0059] (3) Innovative use of partitioned ROM to store the real part (COS) and imaginary part (SIN) of the twiddle factor, and dynamic multiplexing of the twiddle factor table based on the level index (m). For an M-level reconfigurable FFT, the depth of the m-th level ROM is only 2 {M-m}, reducing ROM resource usage by 73% compared to the full storage solution. At the same time, through the reuse of adders and subtractors in the butterfly operation module and pipeline scheduling, the single-stage FFT operation delay is shortened to N / 2 m clock cycle, the overall FFT calculation speed is increased by 1.8 times.

[0060] (4) Combining the segmented correlation of the partially matched filter (N=DX) with the refined frequency domain analysis of the reconfigurable FFT, the frequency resolution is improved by Z / D times (Z is the number of FFT points, D is the number of PMF groups) compared with the traditional PMF-FFT algorithm under the same hardware resources. Experiments show that when the carrier-to-noise ratio CN0=35dB-Hz, the frequency offset estimation error is ≤5Hz, and the capture sensitivity reaches -145dBm, which is 4.2dB better than the existing solution.

[0061] (5) By parameterizing the number of PMF groups (D), the number of FFT points (Z), and the depth of the rotation factor table, the same hardware platform can adapt to multiple navigation signal systems such as GPS L1C / A, Beidou B1I, and Galileo E1. In actual measurements, only 10% of the logic resources need to be reconfigured to switch to different signal modes, and the reconfiguration time is less than 5ms, which is significantly better than the full reconstruction mode of the traditional FPGA solution (taking >200ms).

[0062] (6) The reconfigurable FFT module dynamically shuts down inactive operation levels through gated clock technology (e.g., only level 7 is enabled in 128-point mode, and level 1 is disabled in 64-point mode), reducing dynamic power consumption by 30%-50%. Under typical workloads, the overall system power consumption is ≤850mW, which is 42% less than that of the fixed architecture solution, effectively alleviating the heat dissipation pressure in high-density integrated environments.

[0063] Other advantages, objectives and features of the present invention will be described in the following description to some extent, and to some extent, will be obvious to those skilled in the art based on the following examination and study, or can be taught from the practice of the present invention. The objectives and other advantages of the present invention can be realized and obtained through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] In order to make the purpose, technical solutions and advantages of the present invention more clear, the present invention will be described in detail below in conjunction with the accompanying drawings, wherein:

[0065] Figure 1 The overall structure diagram of the reconfigurable PMF-FFT acquisition algorithm

[0066] Figure 2 It is the internal logic diagram of the reconfigurable PMF-FFT algorithm;

[0067] Figure 3 It is a reconfigurable FFT module core architecture;

[0068] Figure 4 The internal structure diagram of each level of FFT operation module;

[0069] Figure 5 This is a simulation comparison result diagram of the reconfigurable FFT module;

[0070] Figure 6 The figure shows the comparison results of reconfigurable FFT module resources. DETAILED DESCRIPTION

[0071] The following describes the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments only illustrate the basic concept of the present invention in a schematic manner, and the following embodiments and features in the embodiments can be combined with each other without conflict.

[0072] Among them, the drawings are only used for illustrative explanations, and they only represent schematic diagrams rather than actual pictures, and should not be understood as limitations on the present invention. In order to better illustrate the embodiments of the present invention, some parts of the drawings may be omitted, enlarged or reduced, and do not represent the size of actual products. For those skilled in the art, it is understandable that some well-known structures and their descriptions in the drawings may be omitted.

[0073] The same or similar numbers in the drawings of the embodiments of the present invention correspond to the same or similar parts; in the description of the present invention, it should be understood that if the terms "upper", "lower", "left", "right", "front", "rear", etc. indicate the orientation or position relationship, they are based on the orientation or position relationship shown in the drawings, which is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, the terms describing the position relationship in the drawings are only used for illustrative purposes and cannot be understood as limiting the present invention. For ordinary technicians in this field, the specific meanings of the above terms can be understood according to specific circumstances.

[0074] The parameters in the PMF-FFT capture system include the actual frequency deviation range f of the system. d , spreading code rate f c , sampling rate f s, the pseudo code length L for the matched filter, the total correlation length N, the length X of the partially matched filter, the number D of partially matched filters, the number of zero-filled points n, the number of points sent to the FFT after zero-filling is Z, the enable signal en_in for controlling the reconfigurable FFT module, the count of input data is cnt_in, cnt_butterfly counts the number of butterfly operations of the butterfly operation module, the output enable of the base-2 FFT operation module is en_out, and the frequency offset estimation range of the algorithm is f d , frequency resolution Δf u .

[0075] like Figure 1 to Figure 3 The figure shows a navigation signal acquisition method based on a reconfigurable PMF-FFT algorithm of the present invention, and the specific steps are:

[0076] Step 1: The cached data is processed in a pipeline manner through D partially matched filters. Each partially matched filter outputs a partial correlation value, and the D partially matched filters output D partial correlation values.

[0077] Step 2: Fill n points with 0. Fill n points with 0 to the power of 2 after the partial correlation value of point D in the previous step to form point Z.

[0078] Step 3: Perform FFT operation. Input the expanded Z-point data into the reconfigurable FFT module, and dynamically configure the FFT points (Z=32 / 64 / 128) according to the preset Doppler frequency deviation range and the actual hardware resource requirements.

[0079] Step 4: Modulus square. The output of the FFT operation is an imaginary number, including the real part and the imaginary part. The amplitude of the FFT operation result is required in the project, and the modulus operation on the imaginary number is equivalent to calculating the amplitude. Then the square operation is performed. There are two reasons for the square operation: (1) The value of the square of the modulus is positively correlated with the value of the modulus, which does not affect the peak judgment. (2) The square root operation is relatively complex in hardware implementation.

[0080] If the imaginary number is x = a + jb, then the modulus (that is, the amplitude) The square of the modulus x 2 =a 2 +b 2 .

[0081] Where a is the real part of the complex number and b is the imaginary part of the real number.

[0082] Step 5: Compare the extreme values ​​and obtain the extreme value size and its coordinate K.

[0083] Step 5: Threshold judgment. Compare the maximum peak value obtained in the previous step with the preset threshold value. If it is greater than the threshold value, it means that the capture is successful. Otherwise, it is less than the threshold value, which means that the capture is not successful.

[0084] Step 7: Doppler frequency shift estimation: If the capture is successful, the coordinate K value corresponding to the maximum value obtained in step 6 is used to obtain the Doppler frequency shift estimation.

[0085] f d =(Z*(1-Max_x / Z)+1) / (Z*X*(1 / f s ))

[0086] f d is the frequency offset estimate, Z is the number of fft points, Max_x is the index value corresponding to the highest peak, and X is the length of each matched filter.

[0087] like Figure 3 As shown in the figure, it is the internal logic diagram of the reconfigurable PMF-FFT algorithm. The specific steps are as follows:

[0088] Step 1: Send the data to the partial matched filter module to perform partial correlation operation with the local pseudo code generated by the local pseudo code generator to obtain the partial correlation value. If the pseudo code is not completely aligned, the local pseudo code will slide one code phase per clock to continue to perform partial correlation operation with the input data until the pseudo code is completely aligned.

[0089] Step 2: Send the data after the partial correlation result to the ping-pong RAM according to the specified address, and the address is controlled by the ping-pong cache state machine.

[0090] Step 3: Fill the buffered data with zeros according to the number of points required for FFT and send it to the reconfigurable FFT module for calculation. After the calculation is completed, the data is output for peak detection and threshold judgment.

[0091] like Figures 4-5 As shown in the figure, the core architecture of the reconfigurable FFT module is shown in the figure. The specific steps are as follows:

[0092] Step 1: Reconstruct the FFT module according to the number of input data points Z. The reconstruction process is as follows:

[0093] Select the location of the first radix-2 FFT operation: according to the number of input data points Z = 2 n , it is determined that the FFT process needs to perform n radix-2FFT operations, so the M-n+1th level radix-2FFT operation module is selected to perform the first radix-2FFT operation. Taking M=7 level FFT operation modules as an example, when the number of input data points Z is 64, the second level radix-2FFT operation module is selected to perform the first radix-2FFT operation.

[0094] Determine the number of groups for each level of radix-2 FFT operation: Based on the number of input points Z = 2 n , determine the number of groups k of the first to nth level radix-2 FFT operations to be 1, 2, and 2 respectively 2 , …, 2 n-1 The radix-2FFT operation module performs FFT operations in groups. The calculation process of different groups is similar and the rotation factors used are the same. Taking the n-1th level radix-2FFT calculation as an example, the input data is divided into 2 n -2 Group, 2 n-2 The group input data enters the n-1th level radix-2 FFT operation module in the form of a continuous stream. After calculating the first group of input data, the radix-2 FFT operation module continuously processes the second group of input data until all groups of input data are calculated.

[0095] Step 2: Perform base-2 FFT operation. The calculation process is as follows:

[0096] 1. The input data zero padding process controls the enable signal en_in of the FFT module. The enable signal en_in controls the working state of the FFT module. When the FFT module is enabled, the input data begins to enter the radix-2 FFT operation.

[0097] 2. The signal cnt_in counts the input data. The signal cnt_in reconstructs the FIFO buffer module and the butterfly operation module in the radix-2FFT operation module, controls the input data source and output data flow of the FIFO buffer module and the working state of the butterfly operation module. When cnt_in is less than Z / 2 k When the FIFO buffer module is only written but not read, the input data is written, and the butterfly operation module does not work. When cnt_in is greater than or equal to Z / 2 k When the value is less than Z, the FIFO cache module reads and writes at the same time, and writes the data output by the output terminal OUT1 of the butterfly operation module. The butterfly operation module works, the input terminal IN0 receives the data read from the FIFO, the input terminal IN1 receives the input data, and the data output by the output terminal OUT0 flows to the next level.

[0098] 3. The signal cnt_butterfly counts the number of butterfly operations of the butterfly operation module. The signal cnt_butterfly reconstructs the FIFO cache module, the complex multiplication module and the ROM rotation factor storage module, controls the reading and writing of the FIFO cache module, the working state of the complex multiplication module and the reading of data by the ROM rotation factor storage module. When cnt_butterfly is greater than or equal to Z / 2k, the FIFO cache module and the ROM rotation factor storage module read out data, and the complex multiplication module works to accept the data read out by the FIFO cache module and the ROM rotation factor storage module. Among them, the address of the ROM rotation factor storage module reading data changes with the cnt_butterfly signal, and the data output by the complex multiplication module flows to the next level.

[0099] 4. The signal en_out is used to mark the output enable of the radix-2 FFT operation module. The signal en_out is used as the en_in signal of the next-level radix-2 FFT operation module.

[0100] 5. The signal cnt_out counts the output data of the radix-2 FFT operation module. The signal cnt_out is used as the cnt_in signal of the next-level radix-2 FFT operation module.

[0101] Step 3: Output Data

[0102] When the Mth stage radix-2 FFT operation is completed, the en_out signal of this stage enables the output stage, and the final result data is obtained through the output stage.

[0103] like Figure 6 As shown in the figure, the simulation comparison result of the reconfigurable FFT module is shown. The data output by the PMF module is padded with zeros to obtain 64 or 128 data points as the input signal of the FFT module. The input signal first undergoes the first-level butterfly operation, and the output of the previous level is used as the input of the next level to complete all series operations in sequence. Finally, the output level outputs the calculation results. It can be seen that there are obvious peaks at the 33rd and 65th data respectively.

[0104] like Figure 6 As shown in the figure, it is a comparison chart of resource consumption of reconfigurable FFT module. It can be seen that 64-point FFT consumes less DSP, BRAM, Slice, and LUT hardware resources than 128-point FFT, but 128-point FFT can provide higher resolution. In actual application, the appropriate number of FFT points can be selected according to resource and performance requirements.

[0105] In the present invention, the reconfigurable FFT module can reduce the dynamic power consumption of FPGA by shutting down the inactive stages through the Z input points (power consumption is reduced by 30%-50% in typical scenarios). Each level of operation unit is independently controllable and supports hardware resource reuse (such as complex multiplier sharing), which greatly improves resource utilization. The programmable output stage can adapt to different application scenarios and balance the requirements of computing speed and accuracy.

[0106] In the present invention, the traditional fixed-level FFT only supports a single point number and is difficult to adapt to variable-level operations. The present invention uses a threshold-triggered FIFO switching mechanism to enable the reconfigurable FFT to support multi-mode configurations such as 32 / 64 / 128 points, thereby achieving flexible scheduling.

[0107] In the present invention, the PMF-FFT algorithm shortens the correlation integration time by 1 / X (X is the number of partially matched filters) compared with conventional methods such as serial capture or code phase parallel capture. Therefore, under the same capture decision threshold, its frequency analysis range is expanded by X times, and a large number of Doppler frequency deviations and high dynamic signals can be quickly captured.

[0108] In the present invention, the ping-pong reading and writing of partial matched filtering results can improve the utilization rate of the reconfigurable FFT.

[0109] Example 1: Dynamic point configuration of reconfigurable FFT module

[0110] 1. Input configuration: receive D = 60 groups of partial correlation values ​​(each group X = 256 points) output by PMF, fill with zeros to Z = 128 points (2 7 ).

[0111] 2. Level selection: Z = 128 corresponds to M = 7-level FFT, enabling all 7-level radix-2 operations; if switched to Z = 64 points (2 6 ), close the first level, and start the operation from the second level.

[0112] 3. FIFO control: The depth of the m-th level FIFO is set to 128 / 2 m For example, the FIFO depth of the second level (the first level when Z=64) is 32. After 32 points are written, the data source is switched to the butterfly operation output OUT1.

[0113] 4. Twiddle factor multiplexing: The second-level ROM stores W_64(0)-W_64(31), with a depth of 32; the third-level ROM stores W_64(0)-W_64(15), with a depth of 16, and so on.

[0114] 5. Resource verification: In 64-point mode, DSP usage is reduced from 58 to 37 in 128-point mode (a 36% decrease), and the calculation delay is shortened from 7.2μs to 4.1μs.

[0115] Example 2: Ping-Pong RAM and FIFO Anti-Overflow Data Path

[0116] 1. PMF output write: 60 parallel PMF units output at a rate of 20MHz. The first PMF result is written to ping-RAM address 0, the second to address 60, and so on to address 3540 (59×60).

[0117] 2. Ping-Pong Switching: When the ping-pong RAM is filled with D=60 sets of data (60×60=3600 points), the state machine switches to the ping-pong RAM writing and starts the FFT to read the ping-pong RAM data.

[0118] 3. Zero padding and FFT input: read 3600 points from RAM and then fill with zeros to 4096 points (2 12 ), input the FFT module in batches, 128 points per batch, and dynamically switch the input source (RAM / zero-filled data) through FIFO.

[0119] 4. Performance test: Under continuous PMF output, there is no data loss in FFT processing, and the throughput is stable at 19.8MS / s (efficiency 99%), which is 31% higher than the fixed buffer solution.

[0120] Example 3: Twiddle Factor Partition Storage and Dynamic Addressing

[0121] 1. ROM partitioning: Design 7 pairs of ROM (COS / SIN) for M=7-level FFT, the first-level ROM depth is 64 (storing W_128(0)-W_128(63)), the second-level depth is 32, ..., the seventh-level depth is 1.

[0122] 2. Reconfigurable addressing: When Z=64, the second level is used as the first level, and its ROM address generator only uses the lower 5 bits (32 factors), the high bits are forced to be zero, and the first half of the first level ROM is reused.

[0123] 3. Resource comparison: The traditional solution requires 7×64=448 points of storage, while the present invention only requires 64+32+16+8+4+2+1=127 points, a reduction of 71.6%.

[0124] 4. Calculation verification: The error between the 64-point FFT operation result and the Matlab simulation is <1e-6, proving that there is no loss of precision in factor reuse.

[0125] Example 4: Frequency offset estimation optimization in a high dynamic environment

[0126] 1. Doppler scenario simulation: input signal frequency deviation ±35kHz (high dynamics), signal-to-noise ratio CN0 = 34dB-Hz.

[0127] 2. Parameter configuration: PMF grouping D = 30 (X = 512 points), zero padding to Z = 64 points, FFT resolution Δf u =35k / 64=546.9Hz.

[0128] 3. Peak detection: The maximum peak value after FFT output modulus squared is located at k = 42, substitute into the formula:

[0129] f d =(64×(1-42 / 64)+1) / (64×512×(1 / 20e 6 ))=34.12kHz.

[0130] 4. Accuracy verification: The experiment was repeated 100 times, the standard deviation of frequency deviation estimation was σ=4.8Hz (<5Hz), and the sensitivity reached -143dBm.

[0131] Example 5: Dynamic Level Shutdown in Low Power Mode

[0132] 1. Low CNR mode: When CN0=45dB-Hz is detected, switch to Z=32 (2 5 ), only enable the 3rd to 7th level FFT operations (disable the first two levels).

[0133] 2. Clock gating takes effect: The clocks of the 1st and 2nd level butterfly operation modules are turned off, and the static power consumption is reduced from 25mW to 8mW / level.

[0134] 3. Performance indicators: FFT calculation time is reduced from 4.1μs (64 points) to 2.3μs, total system power consumption is reduced from 850mW to 520mW (reduced by 38.8%), and the frequency offset estimation error remains ≤7Hz.

[0135] Embodiment 6: Multi-system navigation signal adaptation

[0136] 1.GPS L1C / A signal: code length 1023, code rate 1.023MHz, sampling rate fs=40MHz→N=(40e 6 / 1.023e 6 )×1023≈40,000 points, group D=40 (X=1000 points).

[0137] 2. Beidou B1I signal: code length 2046, code rate 2.046MHz→N=40e6 / 2.046e6×2046≈40,000 points, grouping D=80 (X=500 points).

[0138] 3. Dynamic reconstruction: through register configuration D = 40 / 80, X = 1000 / 500, FFT points Z = 64 / 128, ROM factor table is automatically reloaded, and the switching time is <5ms.

[0139] 4. Compatibility verification: The capture success rates of both signals are >99% (threshold Th=6dB), and the resource usage increases by only 12%.

[0140] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solution of the present invention can be modified or replaced by equivalents without departing from the purpose and scope of the technical solution, which should be included in the scope of the claims of the present invention.

Claims

1. A navigation signal acquisition method based on a reconfigurable PMF-FFT algorithm, characterized in that: The method comprises the following steps: Step 1: Perform partial coherent integration on the input data with frequency offset and code phase offset and the local pseudo code, and generate partial correlation values ​​through the partial matched filter module; Step 2: storing the partial correlation values ​​in a cache module in order and performing an N-point zero-filling operation to obtain zero-filled data; Step 3: input the zero-filled data into a reconfigurable FFT module for fast Fourier transform operation, and square the result; Step 4: Detect the maximum peak value after the modulus is squared and compare it with the preset threshold. If it exceeds the threshold, calculate the frequency offset estimate according to the peak index.

2. The navigation signal acquisition method based on the reconfigurable PMF-FFT algorithm according to claim 1 is characterized in that: The reconfigurable FFT module includes M-level radix-2 FFT operation stages and an output stage; wherein the working state of the M-level radix-2 FFT operation stages is controlled by the input point number Z, and the data flow is transmitted from the front stage to the back stage.

3. The navigation signal acquisition method based on the reconfigurable PMF-FFT algorithm according to claim 2 is characterized in that: The radix-2 FFT operation stage includes: FIFO buffer module, used for alternately receiving input data and butterfly operation output data; A butterfly operation module, used for performing a radix-2 butterfly operation; Complex multiplication module, used to multiply with the rotation factors; The ROM twiddle factor storage module is used to store the real part and the imaginary part of the twiddle factor.

4. The navigation signal acquisition method based on the reconfigurable PMF-FFT algorithm according to claim 3 is characterized in that: The FIFO buffer module is in the mth level of operation, when the buffered data volume reaches N / 2 m Switch the data source and output direction when , where N is the total number of FFT points, m is the current operation level and m∈[1,M]; M is the total number of levels, M∈[1,7]; where, when M=7, all levels are activated to calculate 128-point FFT points, and when M=6, 64-point FFT points are calculated.

5. The navigation signal acquisition method based on the reconfigurable PMF-FFT algorithm according to claim 3 is characterized in that: The input of the butterfly operation module is (X m [p],X m [q]), the output is: Among them, p and q are two data indexes used to locate the input data points of the butterfly operation; is the rotation factor, and two output signals are generated through the complex adder and subtractor respectively.

6. The navigation signal acquisition method based on the reconfigurable PMF-FFT algorithm according to claim 3 is characterized in that: The ROM twiddle factor storage module includes partitioned sub-ROMs, which respectively store the real part COS and the imaginary part SIN of the twiddle factor, and are configured only in the first M-1 levels.

7. The navigation signal acquisition method based on the reconfigurable PMF-FFT algorithm according to claim 2 is characterized in that: The complex multiplication module is enabled only in the first M-1 stages of radix-2 FFT operations, and the Mth stage does not include a complex multiplication module.

8. The navigation signal acquisition method based on the reconfigurable PMF-FFT algorithm according to claim 1 is characterized in that: The zero-filling operation in step 2 fills some correlation values ​​with zeros to point Z, where Z is an integer power of 2 and Z≥N.

9. The navigation signal acquisition method based on the reconfigurable PMF-FFT algorithm according to claim 1 is characterized in that: The partial matched filter module in step 1 divides the input data into D groups, each group has X points, satisfying N=DX, where N is the total data length and D is the number of partial matched filters.

10. The navigation signal acquisition method based on the reconfigurable PMF-FFT algorithm according to claim 1, characterized in that: The calculation formula of the frequency offset estimation value in step 4 is: f d =(Z*(1-Max_x / Z)+1) / (Z*X*(1 / f s )) f d is the frequency offset estimate, Z is the number of fft points, Max_x is the index value corresponding to the highest peak, and X is the length of each matched filter.

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