NVMe command processing method based on linked list

Abstract

The invention provides a chain table-based NVMe command processing method, which comprises the following steps of: storing a chain head and a chain tail of a first chain table by a command fetching module, acquiring a command from a position pointed by the chain head of the first chain table, hanging the chain head of the first chain table to the chain tail of a second chain table, and taking a next chain table node of the first chain table as the chain head; the hardware acceleration module is used for storing a chain head and a chain tail of the second chain table, acquiring a command from a position pointed by the chain head of the second chain table and processing the command, hanging the chain head of the second chain table to the chain tail of the third chain table after the command is processed, and taking the next chain table node of the second chain table as the chain head; and the return completion processing module is used for storing the chain head and the chain tail of the third chain table, acquiring and processing a command from the position pointed by the chain head of the third chain table, hanging the chain head of the third chain table to the chain tail of the first chain table after the processing is completed, and taking the next chain table node of the third chain table as the chain head. The NVMe command related information is transmitted among the hardware acceleration modules in a linked list mode, meanwhile, all linked lists share the same storage entity, and the circuit area is optimized while the command processing speed is increased.

Description

Technical Field

[0001] The present invention relates to the field of solid state drive storage, and more specifically to an NVMe command processing method based on a linked list. Background Art

[0002] When the existing NVMe controller processes a command, it first stores the command in a buffer, then sends the command to the CPU, which reads the command and drives different hardware acceleration modules to process the response command. In this structure, all commands need to pass through the CPU, which increases the time required for command processing. At the same time, due to the limitation of the CPU processing speed, the speed at which the NVMe controller processes commands will be limited. At the same time, when the CPU drives different hardware acceleration modules, it needs to send some repeated command information to different hardware acceleration modules. Therefore, each hardware acceleration module needs to provide a certain amount of space to store this information, which makes the controller design complicated, and the circuit interface power consumption and other overheads will also increase. Summary of the invention

[0003] The purpose of the present invention is to provide an NVMe command processing method based on a linked list with a higher command processing speed.

[0004] According to one aspect of the present invention, a linked list-based NVMe command processing method includes:

[0005] A command fetching module stores the head and tail of the first linked list, obtains a command from the position pointed to by the head of the first linked list, hangs the head of the first linked list to the tail of the second linked list, and the next linked list node of the first linked list is the head of the chain;

[0006] A hardware acceleration module stores the head and tail of the second linked list, obtains a command from the position pointed to by the head of the second linked list and processes it, and after the processing is completed, hangs the head of the second linked list to the tail of the third linked list, and the next linked list node of the second linked list is the head of the chain;

[0007] Return to the completion processing module, store the head and tail of the third linked list, obtain a command from the position pointed to by the head of the third linked list and process it, and after the processing is completed, hang the head of the third linked list to the tail of the first linked list, and the next linked list node of the third linked list is the head of the chain.

[0008] In some implementations, there may be one or more hardware acceleration modules.

[0009] In some implementations, the linked lists corresponding to the command fetching module, the hardware acceleration module, and the return completion processing module are all stored in the same linked list storage entity.

[0010] In some implementations, the command fetching module fetches an idle position from the head of the corresponding linked list as the command storage space, the command fetching module obtains the command from the host side, and stores the command in the command storage space.

[0011] In some implementations, each of the commands occupies a linked list node.

[0012] In some implementations, after the command is acquired, all information of the command is stored in the linked list node occupied by the command.

[0013] The beneficial effect is that the present invention adopts a linked list method to transfer NVMe command-related information between various hardware acceleration modules. At the same time, all linked lists share the same storage entity. While speeding up command processing, the circuit area is also optimized.

[0014] The command fetching module, hardware acceleration module and return completion processing module of the present invention process all steps of NVMe command processing in series, without the intervention of the main controller CPU of the SSD, thus reducing the command processing delay and improving the command processing speed. At the same time, all linked lists share a storage entity, reducing the area of ​​the circuit and reducing the power consumption of the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 An initial linked list structure intention of an NVMe command processing method based on a linked list according to an embodiment of the present invention;

[0016] Figure 2 The present invention is an embodiment of an NVMe command processing method based on a linked list, in which an acceleration processing module completes processing of a command, and shows a linked list structure intention. DETAILED DESCRIPTION

[0017] The present invention will be further described below in conjunction with the accompanying drawings.

[0018] Figure 1 and Figure 2 A linked list-based NVMe command processing method of the present invention is schematically shown.

[0019] like Figure 1 As shown, the NVMe controller includes a command fetching module, a first hardware acceleration module, a second hardware acceleration module, and a return completion processing module. All NVMe commands that need to be processed are completed in a linked list manner. For the convenience of explanation, Figure 1The first hardware acceleration module and the second hardware acceleration module are illustrated in FIG. In practical applications, the number of hardware acceleration modules can be determined according to functional requirements. Each module only needs to store the head and tail of the corresponding linked list. That is, the command module stores the head and tail of the first linked list, the first hardware acceleration module stores the head and tail of the second linked list, the second hardware acceleration module stores the head and tail of the third linked list, and the return completion processing module stores the head and tail of the fourth linked list. The head of the linked list is used to obtain the first command to be executed. Each module will obtain the command to be executed from the head of the linked list. The tail of the linked list is to allow more commands to be mounted on this linked list and queued to be executed.

[0020] All command information required in the processing process is stored in the same linked list storage entity, that is, a storage register or other storage medium for storing command information stored in each node of the linked list. After the command on the linked list node at the head of the first linked list is executed, the linked list node at the head of the first linked list will be removed from the first linked list and hung at the end of the second linked list. The linked list node originally at the second position of the first linked list will be considered as the head of the linked list, and the command on the linked list node hung at the second position will be at the head of the linked list.

[0021] The specific processing process is as follows Figure 2 As shown,

[0022] The command fetching module takes an empty position from the head of the first chain list as the command storage space; the command fetching module obtains the command from the host and stores the command in the command storage space. Figure 2 As shown, after completing command fetching, the command fetching module links the node pointed to by the linked list to the end of the linked list of the corresponding second linked list of the first hardware acceleration module.

[0023] The first hardware acceleration module takes a command from the position specified by the head of the corresponding second linked list for execution. After the first hardware acceleration module completes executing the command, it removes the head of the linked list from the second linked list corresponding to the first hardware acceleration module and links it to the tail of the third linked list corresponding to the second hardware acceleration module. The second hardware acceleration module takes a command from the position specified by the head of the corresponding third linked list for execution.

[0024] After the second hardware acceleration module completes the execution of the command, it removes the linked list from the third linked list corresponding to the second hardware acceleration module and hangs it on the tail of the fourth linked list corresponding to the return completion processing module. Specifically, the command fetching module fetches commands one by one, and each command occupies a linked list node. After the command is fetched, all the information of the command will be stored in the node specified by the linked list. Before the command is fetched, the content stored in the node is invalid. The execution of a command requires multiple steps, and each step has a hardware acceleration module. Every time a command is obtained, a node will be removed from the linked list of the command fetching module and hung on the next hardware acceleration module for execution. The order of execution is based on the order of the linked list. The return completion processing module fetches a command from the position specified by the head of the corresponding fourth linked list for execution. After the execution is completed, all processing of the command is completed.

[0025] Return to the completion processing module, re-hang the completed linked list to the tail of the command fetching module, and execute the next command. After the command processing is completed by returning to the completion processing module, the linked list node with the command is re-hanged to the tail of the first linked list corresponding to the command fetching module, thereby completing all the processing of a command. Return to the completion processing module, re-hang the completed linked list to the tail of the command fetching module, and the linked list will be recycled.

[0026] The command fetching module, the first hardware acceleration module, the second hardware acceleration module and the return completion processing module of the present invention process all the steps of NVMe command processing in series, without the intervention of the main controller CPU of the SSD, thereby reducing the command processing delay and improving the command processing speed. At the same time, all linked lists share a storage entity, reducing the area of ​​the circuit and reducing the power consumption of the circuit.

[0027] The above are only some embodiments of the present invention, which are only used to illustrate the technical solutions of the present invention, but not to limit them. For those skilled in the art, without departing from the creative concept of the present invention, the technical solutions recorded in the above embodiments are modified, or some or all of the technical features are replaced by equivalents, which all belong to the protection scope of the present invention.

Claims

1. A linked list-based NVMe command processing method, characterized in that: include: A command fetching module stores the head and tail of the first linked list, obtains a command from the position pointed to by the head of the first linked list, hangs the head of the first linked list to the tail of the second linked list, and the next linked list node of the first linked list is the head of the chain; A hardware acceleration module stores the head and tail of the second linked list, obtains a command from the position pointed to by the head of the second linked list and processes it, and after the processing is completed, hangs the head of the second linked list to the tail of the third linked list, and the next linked list node of the second linked list is the head of the chain; Return to the completion processing module, store the head and tail of the third linked list, obtain a command from the position pointed to by the head of the third linked list and process it, and after the processing is completed, hang the head of the third linked list to the tail of the first linked list, and the next linked list node of the third linked list is the head of the chain.

2. The NVMe command processing method based on a linked list according to claim 1, characterized in that: The hardware acceleration module may be one or more.

3. The NVMe command processing method based on a linked list according to claim 1, characterized in that: The linked lists corresponding to the command fetching module, the hardware acceleration module and the return completion processing module are all stored in the same linked list storage entity.

4. The NVMe command processing method based on a linked list according to claim 1, characterized in that: The command fetching module fetches an idle position from the head of the corresponding linked list as a command storage space, and the command fetching module obtains a command from the host end and stores the command in the command storage space.

5. The NVMe command processing method based on a linked list according to claim 1, characterized in that: Each of the commands occupies a linked list node.

6. The NVMe command processing method based on a linked list according to claim 5, characterized in that: After obtaining the command, all information of the command will be stored in the linked list node occupied by the command.

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