Storage device control method, storage device and computer storage medium

Abstract

The invention provides a control method of storage equipment, the storage equipment and a computer storage medium. The method comprises the following steps: taking data read under initial threshold voltage as original data; symmetrically shifting the initial threshold voltage by taking the initial threshold voltage as a center, and reading data again as bias data; the mutually symmetrical bias data are logically processed, and judgment data are obtained; the original data and the judgment data are combined, a partition array is obtained, the credibility of the partition array is obtained through a lookup table, and the credibility and the accuracy of the judgment data are in positive correlation; the judgment data with high confidence reliability are preferentially judged, and the judgment data are decoded and processed; when decoding processing is started, the number of times of symmetrical offset initial threshold voltage is increased, and data are read again to serve as bias voltage data of the next round; and the step of obtaining the judgment data, the step of obtaining the credibility and the decoding process are cycled until decoding succeeds or the number of symmetric offset times reaches an offset time threshold value.

Description

Technical Field

[0001] The present invention relates to the field of storage technology, and in particular to a control method for a storage device, a storage device, and a computer storage medium. Background Art

[0002] Low density parity check (LDPC) is widely used in communication systems due to its high coding efficiency and good error correction capability. By selecting a suitable decoding algorithm, such as belief propagation or minimum sum algorithm, the original information of the stored information can be effectively restored. Even in the presence of noise, low density parity check still has a high error correction capability. Therefore, LDPC codes are also often used in error checking and correction of storage devices using flash memory as storage media.

[0003] In storage devices that use flash memory as storage media, LDPC codes are used in the soft decoding process. The more bits of soft information in soft decoding, the stronger the decoding error correction capability, while the more complex the probability combinations that need to be processed by decoding, the longer the decoding delay. Therefore, how to balance the decoding capability and decoding delay is directly related to the storage reliability and storage performance of the storage device. Summary of the invention

[0004] The object of the present invention is to provide a control method for a storage device, a storage device, and a computer storage medium, which can improve the efficiency of soft decoding during data rereading, balance the decoding delay and decoding capability of the storage device, thereby improving the data storage reliability of the storage device, and improving the performance of the storage device.

[0005] In order to solve the above technical problems, the present invention is achieved through the following technical solutions: The present invention provides a method for controlling a storage device, comprising the following steps: The data read out at the initial threshold voltage is taken as the original data; Taking the initial threshold voltage as the center, symmetrically shifting the initial threshold voltage, and re-reading data as bias data; Logically processing the mutually symmetrical bias data to obtain decision data; Combining the original data and the decision data to obtain a partition array, and obtaining the credibility of the partition array through a lookup table, wherein the credibility is positively correlated with the accuracy of the decision data; Prioritizing the decision data with high credibility, and decoding and processing the decision data; At the beginning of the decoding process, the number of times the initial threshold voltage is symmetrically shifted is increased, and data is re-read out as bias data for the next round; and The steps of obtaining the judgment data, obtaining the credibility and the decoding process are repeated in a loop until the decoding is successful or the number of symmetric shifts reaches a shift number threshold.

[0006] In one embodiment of the present invention, the step of acquiring the bias voltage data includes: Setting the bias amplitude and the number of quantization bits; and Respectively left-biasing and right-biasing the initial threshold voltage, and obtaining a left-biased voltage and a right-biased voltage, wherein the voltage offset amplitudes of the left-biased processing and the right-biased processing are the bias amplitude or an integer multiple of the bias amplitude, and the number of the left-biased voltage and the right-biased voltage is equal to the current number of quantization bits; and Data are read out at the left bias voltage and the right bias voltage respectively to obtain left bias data and right bias data, wherein the left bias voltage and the right bias voltage are symmetrical about the initial threshold voltage.

[0007] In one embodiment of the present invention, in the step of obtaining the decision data, the left-biased data and the right-biased data that are symmetrical to each other are XOR-processed to obtain the decision data.

[0008] In one embodiment of the present invention, in the step of shifting the initial threshold voltage, as the rounds of acquiring the bias data increase, the number of quantization bits increases arithmetic progression, and the number of bias data is in a linear or exponential relationship with the number of quantization bits.

[0009] In one embodiment of the present invention, in the step of shifting the initial threshold voltage, the voltage difference between adjacent left bias voltages is the bias voltage amplitude, and the voltage difference between adjacent right bias voltages is the bias voltage amplitude.

[0010] In one embodiment of the present invention, in the step of shifting the initial threshold voltage, when the initial threshold voltage is shifted in the next round, the bias data obtained at the same threshold voltage in the current round is used or the new bias data is re-read at the shifted threshold voltage.

[0011] In one embodiment of the present invention, when the decoding processing step fails, the judgment data and the credibility are obtained based on the bias data of the next round, and the decoding processing step and the parallel process of reading the bias data of the next round are started until the decoding processing obtains a result.

[0012] In one embodiment of the present invention, when the decoding process is successful, the successfully decoded data is used as the read data, all invalid data in the decoding process is deleted, and the read process ends.

[0013] The present invention provides a computer storage medium, wherein the computer storage medium stores computer instructions, and when the computer instructions are executed by a processor, the steps of the control method of the storage device as described in any one of the above items are implemented.

[0014] The present invention provides a storage device, comprising: Flash memory chips; A readout module, used to read out data from the flash memory chip at a set threshold voltage, wherein the data read out at an initial threshold voltage is original data; A bias module, used to symmetrically shift the initial threshold voltage with the initial threshold voltage as the center, wherein data read out at the threshold voltage after the shift is bias data; A decision module, used for logically processing the mutually symmetrical bias data to obtain decision data; A confidence module, used for combining the original data and the decision data to obtain a partition array, and obtaining the credibility of the partition array through a lookup table, wherein the credibility is positively correlated with the accuracy of the decision data; A decoding module, used for giving priority to the decision data with high credibility, and decoding and processing the decision data; A timing control module for controlling the start-up timing of all processes in the storage device, wherein when the decoding process starts, the timing control module outputs a trigger signal to increase the number of times the initial threshold voltage is symmetrically shifted and start the next round of the bias data acquisition step; and A loop control module is used to loop the steps of obtaining the judgment data, obtaining the credibility and the decoding process until the decoding is successful or the number of symmetric shifts reaches a shift number threshold.

[0015] As described above, the present invention provides a control method for a storage device, a storage device, and a computer storage medium, which can dynamically adjust the threshold voltage and improve the reliability of data storage. And the present invention is based on a credibility-driven parallel decoding mechanism, and utilizes the acquisition of multiple rounds of judgment data, so that it can take into account the occupancy control of storage resources while improving the efficiency of data decoding. The present invention preferentially decodes high-credibility data and can accelerate the error correction process. The decoding process is executed in parallel with the next round of bias data reading, reducing overall delays, improving reading efficiency, and supporting the reuse of historical bias data or dynamically generating new data, balancing computational overhead and accuracy requirements. The present invention supports modular design and algorithm design, realizes flexible adaptation to different flash memory chips, and the algorithm can be deployed through a computer storage medium, which is convenient for firmware upgrades. The storage device provided by the present invention is suitable for the use of high-density flash memories such as MLC / TLC / QLC, alleviates the threshold voltage interference problem caused by the increase in the number of writes, and can meet the requirements of high-speed data access and low-power design.

[0016] Of course, any product implementing the present invention does not necessarily need to achieve all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for describing the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0018] Figure 1 The flowchart of the control method of the storage device in one embodiment of the present invention.

[0019] Figure 2 FIG. 2 is a flow chart of step S200 in an embodiment of the present invention.

[0020] Figure 3 FIG. 4 is a schematic diagram of voltage offset when the number of quantization bits is 1 according to an embodiment of the present invention.

[0021] Figure 4 FIG. 4 is a schematic diagram of voltage offset when the number of quantization bits is 2 according to an embodiment of the present invention.

[0022] Figure 5 2 is a flow chart of steps S500 to S700 in one embodiment of the present invention.

[0023] Figure 6 FIG. 4 is a schematic diagram of the structure of a storage device in an embodiment of the present invention.

[0024] Figure 7 FIG. 4 is a schematic diagram of the structure of a computer storage medium in one embodiment of the present invention.

[0025] In the figure: 10, main controller; 11, read-out module; 12, bias module; 13, decision module; 14, confidence module; 15, decoding module; 16, timing control module; 17, loop control module; 20, flash memory chip; 30, processor; 40, computer storage medium; 41, computer instructions. DETAILED DESCRIPTION

[0026] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0027] See also Figure 1 , Figure 6 and Figure 7 As shown, the present invention provides a control method for a storage device, a storage device, and a computer storage medium 40. The storage is an embedded storage device, such as an embedded MultiMedia Card (eMMC), a universal flash storage (UFS), etc. In the present invention, the storage medium used by the storage device to store user data is a flash memory chip 20, and specifically a NAND flash memory. The storage device includes a processor 30 and a flash memory chip 20, and the processor 30 and the flash memory chip 20 are electrically connected. The processor 30 can implement the control method of the storage device provided by the present invention by executing computer instructions, thereby realizing the control of the read process of the flash memory chip 20. In the present invention, the computer storage medium 40 is a memory for storing control firmware, such as a read-only memory (ROM). In another embodiment of the present invention, the processor 30 can also implement the control method of the storage device provided by the present invention in the form of a functional circuit by means of a component functional module. In this embodiment, the processor 30 is, for example, an ARM processor 30.

[0028] See also Figure 1 As shown, the control method of the storage device provided by the present invention includes steps S100 to S700.

[0029] Step S100: The data read out at the initial threshold voltage is taken as the original data.

[0030] Step S200 , taking the initial threshold voltage as the center, symmetrically shifting the initial threshold voltage, and then re-reading data as bias data.

[0031] Step S300: logically process mutually symmetrical bias data to obtain decision data.

[0032] Step S400: combine the original data and the judgment data to obtain a partition array, and obtain the credibility of the partition array by looking up a table, wherein the credibility is positively correlated with the accuracy of the judgment data.

[0033] Step S500: prioritize the decision data with high credibility, and decode and process the decision data.

[0034] Step S600: When the decoding process starts, the number of times the initial threshold voltage is symmetrically shifted is increased, and the data is read out again as the bias data for the next round.

[0035] Step S700, looping the steps of obtaining judgment data, obtaining credibility and decoding process until the decoding is successful or the number of symmetric shifts reaches the shift number threshold.

[0036] See also Figure 1 As shown, in the present invention, when obtaining data from the flash memory chip 20, a data reading process and an error correction process are involved. In this embodiment, the decoding method used in the error correction process may be a low-density parity check code (LDPC). In the data reading process, the data is read according to the default or set threshold voltage. When the data reading fails, the data can be reread. In this embodiment, the initial threshold voltage may be the threshold voltage used when the data reading fails, or it may be the default voltage preset when triggering the data rereading or the optimal voltage obtained by training. The original data obtained in step S100 may be the hard-decoded data directly called after the hard decoding fails, or it may be the data read again according to the initial threshold voltage. It should be noted that in one embodiment of the present invention, the initial threshold voltage will not be changed after it is determined. If all decoding processes fail, it is determined that the data cannot be read. In another embodiment of the present invention, when all decoding processes fail, the initial threshold voltage may be adjusted, and steps S100 to S700 may be re-executed, and so on, until the decoding is successful or the initial threshold voltage that can be obtained is traversed. The initial threshold voltage may be a value set in a voltage table or a value obtained through training calculation.

[0037] See also Figure 1 and Figure 2 As shown, in the present invention, in step S200, in each round of the step of acquiring bias data, the number of bias data is an even number, and the step of acquiring bias data includes steps S210 to S230.

[0038] Step S210: setting the bias voltage amplitude and the number of quantization bits.

[0039] Step S220, respectively left-bias processing and right-bias processing of the initial threshold voltage, and obtaining the left-bias voltage and the right-bias voltage, wherein the voltage offset amplitude of the left-bias processing and the right-bias processing is the bias amplitude or an integer multiple of the bias amplitude, and the number of the left-bias voltage and the right-bias voltage is equal to the current number of quantization bits.

[0040] Step S230 , reading out data under the left bias voltage and the right bias voltage respectively to obtain left bias data and right bias data, wherein the left bias voltage and the right bias voltage are symmetric with respect to the initial threshold voltage.

[0041] See also Figures 1 to 3As shown, in one embodiment of the present invention, in step S210, a bias voltage range is obtained. For example, -1.28V represents a logic level of 1, and 1.27V represents a logic level of 0, and the bias voltage range is -1.28V to 1.27V. As the storage device is used, the voltage range used to determine the logic level may overlap. Figure 3 As shown in the figure, the parabolic curve is used to represent the value curve of the read voltage, and the red straight line area is used to indicate the range of logic level overlap. When the read voltage value is in the overlapping area, the read logic level may be regarded as 0 or 1. Therefore, the read data in this voltage overlap area is inaccurate. Figure 3 The Vth shown represents the initial threshold voltage. In the present embodiment, a bias frequency threshold is set to limit the number of biases, wherein the bias frequency threshold is an even number. Left bias once and right bias once represent two bias processes. In other embodiments of the present invention, the threshold voltage threshold may also be used to limit the number of biases. In one embodiment of the present invention, the bias range may be divided into a plurality of gears according to the bias range and the bias frequency threshold, and the bias amplitude may be determined according to the gear. For example, the bias amplitude is set to 1 gear. In another embodiment of the present invention, the bias amplitude is set to, for example, 1~30mV, and specifically may be 10mV. In the present embodiment, the optimal bias range may be set to, for example, 1~5mV.

[0042] See also Figures 1 to 3 As shown, in one embodiment of the present invention, in step S210, the number of quantization bits is used to set the number of left bias voltages and right bias voltages obtained each time, and is used to limit the number of bias data obtained. Wherein, as the number of rounds of obtaining bias data increases, the number of quantization bits increases arithmetic difference. The initial number of quantization bits is set to 1, and while decoding the decision data obtained when the number of quantization bits is 1, the number of quantization bits is increased to 2, and the bias data of the next round is obtained according to the new number of quantization bits, and so on. In this embodiment, the increment of the number of quantization bits per round is 1. In the present invention, the number of bias data is linearly related or exponentially related to the number of quantization bits. In this embodiment, the number of bias data is twice the number of quantization bits. For example, when the number of quantization bits is 1, that is, the left bias is once and the right bias is once, 2 bias data are obtained. For example, when the number of quantization bits is 2, that is, the left bias is twice and the right bias is twice, 4 bias data are obtained. In another embodiment of the present invention, the number of bias data is calculated with 2 as the base and the number of quantization bits as the exponent. For example, when the number of quantization bits is 1, that is, the left bias is applied once and the right bias is applied once, 2 bias data are obtained. When the number of quantization bits is 3, that is, the left bias is applied four times and the right bias is applied four times, 8 bias data are obtained. And so on.

[0043] See also Figures 1 to 4As shown, in one embodiment of the present invention, in step S220, the initial threshold voltage is shifted to the left, and the offset is one times the bias amplitude or multiple times the bias amplitude to obtain a left-biased voltage. In this embodiment, when the left-biased process is performed for the first time, the offset is one times the bias amplitude. When the left-biased process is performed for the Nth time, the offset is N times the bias amplitude. Similarly, the initial threshold voltage is shifted to the right, and the offset is one times the bias amplitude or multiple times the bias amplitude to obtain a right-biased voltage. When the right-biased process is performed for the Nth time, the offset is N times the bias amplitude. Wherein N is an integer. Wherein the offset can be performed with the initial threshold voltage as a reference for offset processing. Therefore, for multiple left-biased processes and multiple right-biased processes, the voltage difference between adjacent left-biased voltages is the bias amplitude, and the voltage difference between adjacent right-biased voltages is the bias amplitude. In this embodiment, in each round of bias processing, the number of left-biased times and the number of right-biased times are equal, and the number of left-biased voltages and right-biased voltages obtained is equal to the current number of quantization bits. In the present embodiment, in each round of bias processing, the left bias voltage and the right bias voltage are offset symmetrically about the initial threshold voltage. In step S230, data are read out at the left bias voltage and the right bias voltage respectively to obtain left bias data and right bias data. In the embodiment, when the number of quantization bits is 1, for example, 1 left bias data and for example 1 right bias data are obtained. When the number of quantization bits is 2, for example, 2 left bias data and for example 2 right bias data are obtained. When the number of quantization bits is 3, for example, 3 left bias data and for example 3 right bias data are obtained, or for example, 4 left bias data and for example 4 right bias data are obtained. It should be noted that in the present embodiment, when the bias amplitude remains unchanged, when the number of quantization bits is 2, one set of bias data is the bias data obtained when the number of quantization bits is 1. Therefore, when the number of quantization bits increases and the bias amplitude remains unchanged, when obtaining bias data in the next round, the bias data obtained at the same threshold voltage in the current round can be directly used to save readout time, or the data can be re-read at the threshold voltage as new bias data to improve the accuracy of the readout data. By dynamically increasing the number of biases and adjusting the bias amplitude over multiple rounds, the optimal threshold voltage is gradually approached to adapt to voltage distribution changes caused by flash memory aging or environmental changes.

[0044] See also Figures 1 to 4 As shown, in one embodiment of the present invention, it should be noted that for the overlapping area of ​​the decision, such as the red line area, the left bias voltage and the right bias voltage can divide the overlapping area of ​​the decision into multiple areas. Figure 3 and Figure 4As shown, as the number of left bias voltages and right bias voltages increases, the number of parts into which the overlapping region of the decision is divided also increases, thereby dividing the overlapping region into finer parts, and being able to more clearly judge each divided part, thereby determining the actual logic level value of the corresponding region. Therefore, in this embodiment, the bias voltage amplitude can be set to 1-5 mV, thereby subdividing the overlapping region of the decision as much as possible.

[0045] See also Figures 1 to 4 As shown, in one embodiment of the present invention, in step S300, the logic processing is, for example, an XOR processing. The objects of the XOR processing are mutually symmetrical left-biased data and right-biased data. For example, the left-biased data read under a left-biased voltage with a left offset of 10 mV, and the right-biased data read under a right-biased voltage with a right offset of 10 mV, these two data are mutually symmetrical bias data. After XOR processing the mutually symmetrical left-biased data and right-biased data, the data obtained is used as judgment data. By generating multiple groups of bias data with a symmetrical offset centered on the initial threshold voltage, and combining the logic processing to generate judgment data, the read errors caused by threshold voltage drift can be effectively identified, thereby improving data reliability.

[0046] See also Figures 1 to 4 As shown, in one embodiment of the present invention, in step S400, the partition array includes the original data and all the judgment data. It should be noted that, for the data to be read, each bit corresponds to an original data and at least one judgment data, so each bit corresponds to a partition array. In the decoding process, each bit is decoded and judged. Figure 3 As shown in FIG. 1 , when only one round of voltage is offset, there is only one set of judgment data, which can be distinguished without numbering. Figure 4 As shown, in the case of two or more rounds of voltage offset, each round of judgment data is distinguished by number or name. In the partition array, the first data is the original data, the second data is the judgment data of the first round, the third data is the judgment data of the second round, and so on. The mth data in the partition array is the judgment data of the m-1th round. In this embodiment, the value of the credibility corresponding to the partition array is found by looking up the table. In this embodiment, the higher the absolute value of the credibility, the higher the accuracy of the judgment data.

[0047] See also Figures 1 to 4 As shown, in one embodiment of the present invention, in step S400, the credibility can be obtained by directly finding the credibility value corresponding to the partition array in a lookup table, or by calculating the credibility value corresponding to the partition array. The credibility is the log-likelihood ratio (LLR). Figure 3As shown, when the voltage is shifted in the first round, the partition arrays obtained are, for example, (1, 0), (1, 1), (0, 1) and (0, 0), where the first bit of data represents the original data and the second bit of data represents the decision data. The corresponding partition arrays have credibility values ​​of -7, -3, 3 and 7, respectively, where the negative credibility value plus 16 represents the negative credibility value, so -7 credibility can also be represented as 0×9, and -3 credibility can also be represented as 0×D. Figure 4 As shown, when the voltage is offset in the second round, the partition arrays obtained are, for example, (1, 0, 0), (1, 0, 1), (1, 1, 1), (0, 1, 1), (0, 0, 1) and (0, 0, 0), wherein the first bit of data represents the original data, the second bit of data represents the decision data of the bias voltage in the first round, and the third bit of data represents the decision data of the bias voltage in the second round. The credibility values ​​of the corresponding partition arrays are -7, -5, -3, 3, 5 and 7, respectively, and the negative credibility value plus 16 represents the negative credibility value, so -7 credibility can also be represented as 0×9, -5 credibility can also be represented as 0×B, and -3 credibility can also be represented as 0×D.

[0048] See also Figures 1 to 5 As shown, in one embodiment of the present invention, in step S500, the decision data is decoded by LDPC code. The decision data with high credibility can be trusted first, while the data with low credibility is questioned first. The present invention does not limit the specific decision process of the decoding process. Specifically, step S500 includes step S510 and step S520.

[0049] Step S510: Setting the trust priority of the judgment data according to the credibility of the judgment data.

[0050] Step S520, start the iterative process of decoding processing and trigger step S600.

[0051] See also Figure 5 As shown, in one embodiment of the present invention, in step S510, for example, when iterative decoding is performed for the first time, the judgment data with credibility of -3 and 3 are preferentially identified as erroneous data. The judgment data with credibility of 9 and 7 are preferentially identified as correct data. Based on this judgment, iterative decoding is started. In step S520, the iterative decoding process of the decoding process is started, and at the same time as the iterative decoding process is started, the execution of step S600 is triggered. The execution of step S600 can be triggered by generating a signal, establishing a task queue and task content. In this embodiment, the decoding iteration method can be a decoding iteration of an LDPC code. In each iteration, the accuracy of each judgment data is guessed based on the credibility.

[0052] See also Figures 1 to 5As shown, in one embodiment of the present invention, in step S600, when the decoding process starts, the number of times the initial threshold voltage is symmetrically shifted is increased, and the data is re-read as the bias data for the next round. In step S700, the steps of obtaining the judgment data, obtaining the credibility, and the decoding process are looped until the decoding is successful or the number of symmetrical shifts reaches the shift number threshold. Step S600 includes step S610 and step S620.

[0053] Step S610: Increase the number of quantization bits by one.

[0054] Step S620, triggering the execution of step S200 to obtain the bias data of the next round.

[0055] See also Figures 1 to 5 As shown, in one embodiment of the present invention, in step S610, after triggering step S600, the number of quantization bits is increased by one compared to the value set in this round. Then in step S620, after the number of quantization bits is increased by one, step 200 is triggered to offset the initial threshold voltage and obtain a new round of bias data. In this embodiment, step S200 is performed in the form of establishing a task project. It should be noted that step S520 and step S600 are performed synchronously. The process of decoding iteration can be performed separately by the decoder, and the step of reacquiring bias data can be performed by the processor 30. In step S700, the process of decoding iteration and the readout process of the bias data of the next round are monitored to trigger the execution of the loop process. In this embodiment, multiple processors 30 can be set, and different processors 30 can be divided to realize the monitoring of the loop while reading the bias data. Wherein step S700 includes steps S710 to step S760.

[0056] Step S710: Determine whether the decoding is successful.

[0057] Step S720: When the decoding is successful, the bias data that has been acquired is deleted or the process of acquiring the bias data is terminated.

[0058] Step S730: When the decoding is successful, the decoded data is output.

[0059] Step S740: When decoding fails, determine whether the number of iterations reaches an upper limit threshold. If the number of iterations does not reach the upper limit threshold, proceed to the next iteration.

[0060] Step S750: When the decoding fails and the number of iterations reaches an upper limit threshold, a loop signal is triggered.

[0061] Step S760: under the triggering of the cyclic signal, trigger the execution of step S300 and step S400.

[0062] See also Figures 1 to 5 As shown, in one embodiment of the present invention, in step S700, the decoding process and the process of reading bias data are executed synchronously, but the speed of the decoding process and the speed of reading bias data are uncontrollable, so after the decoding is successful, the bias data may have been read out or may not have been read out. Therefore, after the decoding is successful, if the bias data has been read out, the acquired bias data is deleted. After the decoding is successful, if the bias data has not been read out, the process of reading bias data is terminated and the redundant data is deleted. The process of deleting bias data and the step of outputting the successfully decoded data can be executed synchronously or sequentially. In this embodiment, an upper limit threshold of the number of decoding iterations can be set. When the number of decoding iterations reaches the upper limit threshold and the decoding is not successful, it is determined that the decoding process under the current offset voltage has failed. If the decoding fails and the number of iterations has not reached the upper limit threshold, the next iteration is continued until the decoding is successful or the number of iterations reaches the upper limit threshold. When the decoding fails and the number of iterations reaches the upper limit threshold, the occurrence of the loop signal is triggered, and the execution of steps S300 and S400 is triggered under the triggering of the loop signal. Under the triggering of the cyclic signal, according to the bias data of the next round acquired in advance, the decision data and the credibility of the decision data continue to be acquired, and step S500 is restarted according to the bias data, the decision data and the credibility. At the same time as the decoding iteration of step S500 starts, the bias data of the next round continues to be acquired, and so on, until the decoding is successful or the offset voltage range is traversed. In this embodiment, the current data readout failure can be determined according to the decoding failure and the traversal of the offset voltage range. In another embodiment of the present invention, the current data readout failure can also be determined according to the decoding failure and the reaching of the offset number threshold.

[0063] See also Figure 1 and Figure 6As shown, the present invention provides a storage device, which includes a main controller 10 and a flash memory chip 20. The main controller 10 and the flash memory chip 20 are electrically connected, and control the data reading and writing of the flash memory chip 20, as well as the address management of the flash memory chip 20. The main controller 10 includes a read module 11, an error correction module, a bias module 12, a judgment module 13, a confidence module 14, a decoding module 15, a timing control module 16 and a cycle control module 17. The read module 11 is used to read data from the flash memory chip 20 at a set threshold voltage, wherein the data read at the initial threshold voltage is the original data. The bias module 12 is used to symmetrically shift the initial threshold voltage with the initial threshold voltage as the center, wherein the data read at the shifted threshold voltage is the bias data. The judgment module 13 is used to logically process the mutually symmetrical bias data to obtain the judgment data. The confidence module 14 is used to combine the original data and the judgment data, obtain the partition array, and obtain the credibility of the partition array through the lookup table, wherein the credibility is positively correlated with the accuracy of the judgment data. The decoding module 15 is used to give priority to the decision data with high credibility and decode the decision data. The timing control module 16 is used to control the startup timing of all processes in the storage device, wherein at the beginning of the decoding process, the timing control module 16 outputs a trigger signal to increase the number of times the initial threshold voltage is symmetrically offset and start the next round of bias data acquisition steps. The loop control module 17 is used to loop the steps of acquiring decision data, acquiring credibility and the decoding process until the decoding is successful or the number of symmetrical offsets reaches the offset number threshold.

[0064] See also Figure 1 and Figure 6 As shown, in one embodiment of the present invention, the timing control module 16 includes a plurality of clock triggering units to control the process of the control method of the storage device. The first clock unit is used to control the occurrence of the bias signal, wherein the bias signal is used to trigger the execution of step S600. In this embodiment, when the hard decoding fails, the voltage offset processing is performed for the first time, and when the decoding process of the decision data begins, the occurrence of the bias signal is triggered. In this embodiment, the bias signal can be used to trigger the acquisition of bias data and the parallel execution of decoding. The second clock unit is used to control the occurrence of the cycle signal, which occurs when the decoding fails and the number of iterations reaches the upper limit threshold. The cycle signal is used to trigger the execution of steps S300 and S400 according to the bias data acquired in advance. In this embodiment, for each set step, there is a corresponding timing signal to trigger the execution. In another embodiment of the present invention, by setting a task queue and setting the form of the task item, the task item is set according to the control method of the storage device, and the tasks in the task queue are executed in sequence according to the task queue and the task priority. The task priority is set according to the control method of the storage device.

[0065] See also Figure 1 , Figure 6 and Figure 7 As shown, the present invention further provides a computer storage medium 40, which stores computer instructions 41. When the computer instructions 41 are executed by the processor 30, the steps of the control method of the storage device provided by the present invention are implemented, so as to successfully read data from the flash memory chip 20, or terminate the reading process in time to avoid excessive resource occupation. The processor 30 may be an ARM processor 30. The computer storage medium 40 may be a read-only memory.

[0066] The embodiments of the present invention disclosed above are only used to help illustrate the present invention. The embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made according to the content of this specification. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can understand and use the present invention well. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A method for controlling a storage device, characterized in that: The following steps are involved: The data read out at the initial threshold voltage is taken as the original data; Taking the initial threshold voltage as the center, symmetrically shifting the initial threshold voltage, and re-reading data as bias data; Logically processing the mutually symmetrical bias data to obtain decision data; Combining the original data and the decision data to obtain a partition array, and obtaining the credibility of the partition array through a lookup table, wherein the credibility is positively correlated with the accuracy of the decision data; Prioritizing the decision data with high credibility, and decoding and processing the decision data; At the beginning of the decoding process, the number of times the initial threshold voltage is symmetrically shifted is increased, and data is re-read out as bias data for the next round; as well as The steps of obtaining the judgment data, obtaining the credibility and decoding are repeated repeatedly until the decoding is successful or the number of symmetric shifts reaches a shift number threshold.

2. A storage device control method according to claim 1, characterized in that: The step of obtaining the bias voltage data comprises: Setting the bias amplitude and the number of quantization bits; and Respectively left-biasing and right-biasing the initial threshold voltage, and obtaining a left-biased voltage and a right-biased voltage, wherein the voltage offset amplitudes of the left-biased processing and the right-biased processing are the bias amplitude or an integer multiple of the bias amplitude, and the number of the left-biased voltage and the right-biased voltage is equal to the current number of quantization bits; and Data are read out at the left bias voltage and the right bias voltage respectively to obtain left bias data and right bias data, wherein the left bias voltage and the right bias voltage are symmetrical about the initial threshold voltage.

3. A storage device control method according to claim 2, characterized in that: In the step of obtaining the decision data, the left-biased data and the right-biased data which are symmetrical to each other are XOR-processed to obtain the decision data.

4. The method for controlling a storage device according to claim 2, characterized in that: In the step of shifting the initial threshold voltage, as the round of acquiring the bias data increases, the number of quantization bits increases arithmetic progression, and the number of the bias data is in a linear relationship or an exponential relationship with the number of quantization bits.

5. The method for controlling a storage device according to claim 2, characterized in that: In the step of shifting the initial threshold voltage, the voltage difference between adjacent left bias voltages is the bias voltage amplitude, and the voltage difference between adjacent right bias voltages is the bias voltage amplitude.

6. The method for controlling a storage device according to claim 1, characterized in that: In the step of shifting the initial threshold voltage, when the initial threshold voltage is shifted in the next round, the bias data obtained at the same threshold voltage in the current round is used or new bias data is re-read at the shifted threshold voltage.

7. The method for controlling a storage device according to claim 1, characterized in that: When the decoding process fails, the decision data and the credibility are obtained according to the bias data of the next round, and the decoding process and the parallel process of reading the bias data of the next round are started until the decoding process obtains a result.

8. The method for controlling a storage device according to claim 1, characterized in that: When the decoding process is successful, the successfully decoded data is used as the read data, all invalid data in the decoding process is deleted, and the read process ends.

9. A storage device, characterized in that: include: Flash memory chips; A readout module, used to read out data from the flash memory chip at a set threshold voltage, wherein the data read out at an initial threshold voltage is original data; A bias module, used to symmetrically shift the initial threshold voltage with the initial threshold voltage as the center, wherein data read out at the threshold voltage after the shift is bias data; A decision module, used for logically processing the mutually symmetrical bias data to obtain decision data; A confidence module, used for combining the original data and the decision data to obtain a partition array, and obtaining the credibility of the partition array through a lookup table, wherein the credibility is positively correlated with the accuracy of the decision data; A decoding module, used for giving priority to the decision data with high credibility, and decoding and processing the decision data; A timing control module, used to control the start timing of all processes in the storage device, wherein when the decoding process starts, the timing control module outputs a trigger signal to increase the number of times the initial threshold voltage is symmetrically shifted and start the next round of the bias data acquisition step; as well as A loop control module is used to loop through the steps of obtaining the judgment data, obtaining the credibility, and decoding processing until the decoding is successful or the number of symmetric shifts reaches a shift number threshold.

10. A computer storage medium storing computer instructions, characterized in that: When the computer instructions are executed by a processor, the steps of the storage device control method according to any one of claims 1 to 8 are implemented.

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