Kernel space data transceiving method, device, storage medium and program product

Abstract

This application provides a kernel space data transmission and reception method, device, storage medium, and program product. The method includes transmitting and receiving kernel space data via a kernel transceiver thread in the kernel space of a controller based on a first preset cycle. For each first preset cycle, the kernel transceiver thread reads a first control instruction from a first shared memory, sends the first control instruction to multiple target actuators via an industrial internet bus, causing the multiple target actuators to send first feedback information to the kernel transceiver thread, and the kernel transceiver thread writes the first feedback information into a second shared memory. The first and second shared memories are obtained by mapping kernel space addresses to user space. The kernel space data transmission and reception method provided in this application avoids excessive function call overhead and facilitates efficient kernel space data transmission and reception between master and slave stations.

Description

Technical Field

[0001] This application relates to the field of humanoid robot technology, and in particular to a kernel space data transmission and reception method, device, storage medium and program product. Background Technology

[0002] With the development of technology, the communication needs of humanoid robots are constantly increasing and changing.

[0003] In related technologies, wired communication methods such as serial communication can be used to realize data transmission between sensors and actuators and controllers in humanoid robots.

[0004] However, in the process of realizing this application, the inventors discovered at least the following problems in the prior art: the data transmission and reception efficiency of the above methods is low. Summary of the Invention

[0005] This application provides a kernel space data transmission and reception method, device, storage medium, and program product to improve data transmission and reception efficiency.

[0006] In a first aspect, embodiments of this application provide a kernel space data transmission and reception method applied to a humanoid robot. The humanoid robot includes a controller and multiple target actuators. The controller is connected to the multiple target actuators via an EtherCAT bus. The method includes:

[0007] Data transmission and reception in the kernel space are performed through the kernel transceiver thread in the kernel space of the controller based on the first preset cycle;

[0008] For each of the first preset cycles, the kernel transceiver thread obtains the address number of the first control instruction, reads the first control instruction from the first shared memory based on the address number, and sends the first control instruction to the plurality of target executors via the EtherCAT bus, so that the plurality of target executors send the first feedback information to the kernel transceiver thread; the first feedback information is obtained by the target executor executing the second control instruction; the second control instruction is the instruction read in the previous first preset cycle; the first control instruction is written to the first shared memory by the data exchange thread in the user space of the controller, and is issued by the control algorithm in the user space;

[0009] The kernel transceiver thread obtains the address sequence number of the first feedback information, and writes the first feedback information into the second shared memory based on the address sequence number of the first feedback information; the first feedback information is used to read through the data exchange thread and send the first feedback information to the control algorithm in user space; the first shared memory and the second shared memory are obtained by mapping the address of the kernel space to the user space.

[0010] In one possible design, the first control instruction address number is used to indicate a first address in the first shared memory; the step of reading the first control instruction from the first shared memory based on the first control instruction address number includes:

[0011] Based on the first control instruction address number, read the first control instruction from the first address;

[0012] Accordingly, the first feedback information address number is used to indicate the second address in the second shared memory; the step of writing the first feedback information into the second shared memory based on the first feedback information address number includes:

[0013] Based on the first feedback information address number, the first feedback information is written to the third address in the first shared memory. After the first feedback information is written, the first feedback information address number is used to indicate the third address to obtain the second feedback information address number, and the second feedback information address number is stored in the preset storage space in the kernel space; the third address is the address after the second address.

[0014] In one possible design, obtaining the address sequence number of the first control instruction through the kernel transceiver thread includes:

[0015] The kernel transceiver thread acquires a spinlock, and under spinlock protection, the address sequence number of the first control instruction is obtained.

[0016] The step of obtaining the address sequence number of the first feedback information through the kernel transceiver thread includes:

[0017] The kernel transceiver thread acquires a spinlock, and under spinlock protection, obtains the address sequence number of the first feedback information.

[0018] In one possible design, obtaining the address sequence number of the first control instruction through the kernel transceiver thread includes:

[0019] Determine the trigger time of the first target corresponding to the current first preset cycle;

[0020] If the time difference between the current time and the trigger time of the first target is greater than the first preset threshold, then sleep is initiated based on the first preset step size;

[0021] If the time difference between the current time and the first target trigger time is less than or equal to the first preset threshold, then spin waiting is performed until the first target trigger time is reached, and then the first control instruction address sequence number is obtained through the kernel transceiver thread.

[0022] In one possible design, the first preset period is determined based on the data processing period of the control algorithm.

[0023] In one possible design, the method further includes:

[0024] Data transmission and reception in user space are performed through a data exchange thread in user space based on a second preset period; the second preset period is consistent with the first preset period;

[0025] For each of the second preset cycles, the second control instruction address number is obtained through the data exchange thread, and the first control instruction is written into the first shared memory based on the second control instruction address number;

[0026] The second feedback information address number is obtained through the data exchange thread, and the first feedback information is read from the second shared memory based on the second feedback information address number.

[0027] In one possible design, obtaining the second control instruction address number through the data exchange thread and writing the first control instruction into the first shared memory based on the second control instruction address number includes:

[0028] The data exchange thread retrieves a second control instruction address number from a preset storage space in the kernel space based on a preset function; the second control instruction address number is used to indicate a fourth address in the first shared memory; the fourth address is the address preceding the first address.

[0029] Based on the second control instruction address number, the first control instruction is written to the first address. After the first control instruction is written, the first control instruction address number is used to indicate the first address to obtain the first control instruction address number, and the second control instruction address number is stored in the preset storage space.

[0030] Accordingly, reading the first feedback information from the second shared memory through the data exchange thread includes:

[0031] The second feedback information address number is obtained from the preset storage space through the data exchange thread based on a preset function;

[0032] Based on the address sequence number of the second feedback information, the first feedback information is read from the third address.

[0033] In one possible design, obtaining the address number of the second control instruction through the data exchange thread includes:

[0034] Based on a preset function, a first target request is sent to the target processing function in the kernel space through a data exchange thread in the user space.

[0035] In response to the first target request, the target processing function acquires a spinlock and, under spinlock protection, sends the second control instruction address sequence number to the data exchange thread;

[0036] Accordingly, obtaining the second feedback information address sequence number through the data exchange thread includes:

[0037] Based on a preset function, a second target request is sent to the target processing function in the kernel space through a data exchange thread in the user space.

[0038] In response to the second target request, the target processing function acquires a spinlock and, under spinlock protection, sends the second feedback information address sequence number to the data exchange thread.

[0039] In one possible design, obtaining the address number of the second control instruction through the data exchange thread includes:

[0040] Determine the trigger time of the second target corresponding to the current second preset cycle;

[0041] If the time difference between the current time and the trigger time of the second target is greater than the second preset threshold, then sleep is initiated based on the second preset step size;

[0042] If the time difference between the current time and the second target trigger time is less than or equal to the second preset threshold, then spin waiting is performed until the second target trigger time is reached, and then the second control instruction address sequence number is obtained through the data exchange thread.

[0043] Secondly, embodiments of this application provide a kernel space data transceiver device, comprising:

[0044] The transceiver module is used to send and receive data in the kernel space through the kernel transceiver thread in the kernel space of the controller based on a first preset period.

[0045] The read module is used to, for each of the first preset cycles, obtain the address sequence number of a first control instruction through the kernel transceiver thread, read the first control instruction from the first shared memory based on the first control instruction address sequence number, and send the first control instruction to the plurality of target executors through the EtherCAT bus, so that the plurality of target executors send first feedback information to the kernel transceiver thread; the first feedback information is obtained by the target executor executing a second control instruction; the second control instruction is the instruction read in the previous first preset cycle; the first control instruction is written to the first shared memory by the data exchange thread in the user space of the controller, and is issued by the control algorithm in the user space;

[0046] The write module is used to obtain the address sequence number of the first feedback information through the kernel transceiver thread, and write the first feedback information into the second shared memory based on the address sequence number of the first feedback information; the first feedback information is used to be read by the data exchange thread and sent to the control algorithm in the user space; the first shared memory and the second shared memory are obtained by mapping the address of the kernel space to the user space.

[0047] Thirdly, embodiments of this application provide a kernel space data transceiver device, including: at least one processor and a memory;

[0048] The memory stores computer-executed instructions;

[0049] The at least one processor executes computer execution instructions stored in the memory, causing the at least one processor to perform the method described in the first aspect above and various possible designs of the first aspect.

[0050] Fourthly, embodiments of this application provide a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, implement the method described in the first aspect and various possible designs of the first aspect.

[0051] Fifthly, embodiments of this application provide a computer program product, including a computer program that, when executed by a processor, implements the method described in the first aspect and various possible designs of the first aspect.

[0052] This embodiment provides a kernel space data transmission and reception method, device, storage medium, and program product. The method includes transmitting and receiving kernel space data through a kernel transceiver thread in the kernel space of a controller based on a first preset cycle. For each first preset cycle, the kernel transceiver thread obtains a first control instruction address sequence number, reads a first control instruction from a first shared memory based on the first control instruction address sequence number, and sends the first control instruction to multiple target actuators via an industrial internet bus, so that the multiple target actuators send first feedback information to the kernel transceiver thread. The first feedback information is obtained by the target actuators executing a second control instruction, which is an instruction read in the previous first preset cycle. The first control instruction is written to the first shared memory by a data exchange thread in the user space of the controller and is issued by a control algorithm in the user space. The kernel transceiver thread obtains a first feedback information address sequence number, writes the first feedback information to a second shared memory based on the first feedback information address sequence number, and the first feedback information is used to read through the data exchange thread and send the first feedback information to the control algorithm in the user space. The first shared memory and the second shared memory are obtained by mapping addresses in the kernel space to the user space. The kernel space data transmission and reception method provided in this application maps the kernel space address to the user space and realizes data transmission and reception between the low-level communication program in the kernel space and the upper-level control program in the user space in a shared memory manner. This enables the kernel space to communicate with multiple target actuators (such as motors in a humanoid robot) on the EtherCAT bus without excessive function call overhead, and facilitates efficient data transmission and reception between the master station and slave station on EtherCAT. Attached Figure Description

[0053] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0054] Figure 1 A schematic diagram illustrating an application scenario of the kernel space data transmission and reception method provided in this embodiment of the disclosure;

[0055] Figure 2 A flowchart illustrating the kernel space data transmission and reception method provided in this application embodiment;

[0056] Figure 3 A schematic diagram illustrating the principle of shared memory provided in this application embodiment;

[0057] Figure 4This is a schematic diagram illustrating the process of kernel space data transmission and reception by the kernel transceiver thread in the kernel space, as provided in the embodiments of this application.

[0058] Figure 5 A schematic diagram illustrating the process of sending and receiving kernel space data in a data exchange thread in user space, as provided in an embodiment of this application;

[0059] Figure 6 This is a schematic diagram of the process for detecting whether the trigger time has been reached, provided in an embodiment of this application.

[0060] Figure 7 A schematic diagram of the structure of a kernel space data transceiver device provided in an embodiment of this application;

[0061] Figure 8 A schematic diagram of the hardware structure of the kernel space data transceiver device provided in the embodiments of this application. Detailed Implementation

[0062] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0063] It should be noted that the kernel space data transmission and reception method provided in this application can be used in the field of humanoid robot technology, or in any field other than the field of humanoid robot technology. The application field of the kernel space data transmission and reception method provided in this application is not limited.

[0064] Ethernet for Control Automation Technology (EtherCAT) buses are used to connect controllers (such as industrial PCs) and actuators (such as motors), enabling the former to send control commands to the latter and collect feedback information from the latter.

[0065] Existing master station software includes TwinCAT on Windows, while in the field of humanoid robots with extremely high real-time requirements, SOME and IgH on Linux are widely used due to technical requirements. The former runs in Linux user space and needs to go through the operating system's network stack for data transmission and reception, while the latter runs in Linux kernel space and uses adapted network card drivers to avoid context switching and interrupt requests between user space and kernel space.

[0066] The first challenge in performing EtherCAT data transmission and reception in Linux kernel space is how to transmit data bidirectionally between user space and kernel space. Although data transmission and reception occur in kernel space, the data sent to the slave station originates from the control program in user space, and it is also necessary to transmit the data received from the slave station to the control program in user space.

[0067] In related technologies, the ioctl() function can be used to directly send and receive kernel space data between kernel space and user space. However, since the amount of data transferred each time is more than a few bytes, using ioctl() to directly transfer data here will result in a lot of function call overhead, and the efficiency of kernel space data transmission and reception is low.

[0068] To address the aforementioned technical problems, the inventors of this application have discovered that data exchange between kernel space and user space can be achieved using shared memory. For example, mmap() can be used to map a segment of addresses in kernel space to user space. Based on this, embodiments of this application provide a method for sending and receiving kernel space data.

[0069] Figure 1 This is a schematic diagram illustrating an application scenario of the kernel space data transmission and reception method provided in this embodiment of the disclosure. For example... Figure 1 As shown, the humanoid robot includes a controller 101 and multiple actuators 102. Data transmission and reception between the controller and the actuators are achieved via an EtherCAT bus, an industrial internet-connected system. Optionally, the actuators may include servo motors, stepper motors, hydraulic actuators, starter actuators, linear actuators, or electromagnetic actuators, etc.

[0070] In the specific implementation, EtherCAT data frames are sent by the EtherCAT master software running on the controller. Through the cables connecting the controller and each actuator serially, they are processed sequentially by the EtherCAT slave software. During this process, each slave software retrieves the control commands it needs from the corresponding positions within the data frame and writes its feedback information to the appropriate locations. After processing by the last slave, the data frame is returned to the master. The master software can use IgH on Linux, which runs in kernel space. Since the data sent from the master to the slaves originates from the control program in user space, it also needs to transmit data received from the slaves to the control program in user space. During the data transmission and reception process between kernel space and user space, data transmission and reception in kernel space can be performed through the kernel transceiver thread in the kernel space of the controller based on a first preset cycle. For each first preset cycle, the kernel transceiver thread obtains the address sequence number of the first control instruction, reads the first control instruction from the first shared memory based on the address sequence number, and sends the first control instruction to multiple target actuators through the industrial internet bus. This causes the multiple target actuators to send first feedback information to the kernel transceiver thread. The first feedback information is obtained by the target actuators executing the second control instruction, which is the instruction read in the previous first preset cycle. The first control instruction is written to the first shared memory by the data exchange thread in the user space of the controller and is issued by the control algorithm in the user space. The kernel transceiver thread obtains the address sequence number of the first feedback information, writes the first feedback information to the second shared memory based on the address sequence number, and uses the first feedback information to read and send the first feedback information to the control algorithm in the user space. The first shared memory and the second shared memory are obtained by mapping the addresses in kernel space to user space. The kernel space data transmission and reception method provided in this application maps the kernel space address to the user space and realizes data transmission and reception between the low-level communication program in the kernel space and the upper-level control program in the user space in a shared memory manner. This enables the kernel space to communicate with multiple target actuators (such as motors in a humanoid robot) on the EtherCAT bus without excessive function call overhead, and facilitates efficient data transmission and reception between the master station and slave station on EtherCAT.

[0071] It should be noted that, Figure 1 The schematic diagram shown is merely an example. The kernel space data transmission and reception method and scenario described in the embodiments of this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided in the embodiments of this application. As those skilled in the art will know, with the evolution of the system and the emergence of new business scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0072] The technical solutions of this application will be described in detail below with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.

[0073] Figure 2 This is a flowchart illustrating the kernel space data transmission and reception method provided in an embodiment of this application. Figure 2 As shown, this method is applied to a humanoid robot, which includes a controller and multiple target actuators. The controller is connected to the multiple target actuators via an EtherCAT bus. The method includes:

[0074] 201. Based on the first preset cycle, data is sent and received in the kernel space through the kernel transceiver thread in the kernel space of the controller.

[0075] The execution entity in this embodiment is the controller where the main station software is located, or a humanoid robot or other device to which the controller belongs.

[0076] Specifically, in order to meet real-time requirements, improve system stability, and optimize resource utilization, the kernel transceiver thread in the kernel space can periodically send and receive data.

[0077] In some embodiments, to improve the real-time performance of the control algorithm, the first preset period can be determined based on the data processing period of the control algorithm. For example, the first preset period can be set to match the data processing period of the control algorithm, thereby enabling the control algorithm to obtain new feedback information in real time and generate new control commands based on the new feedback information, thus improving real-time performance.

[0078] 202. For each of the first preset cycles, the kernel transceiver thread obtains the address number of the first control instruction, reads the first control instruction from the first shared memory based on the address number of the first control instruction, and sends the first control instruction to the plurality of target executors through the EtherCAT bus, so that the plurality of target executors send the first feedback information to the kernel transceiver thread; the first feedback information is obtained by the target executor executing the second control instruction; the second control instruction is the instruction read in the previous first preset cycle; the first control instruction is written to the first shared memory by the data exchange thread in the user space of the controller, and is issued by the control algorithm in the user space.

[0079] Specifically, the mmap() function can be used for address mapping. In kernel space, N memory segments (N greater than or equal to 3) are statically allocated as the first shared memory for data transmission and reception of control instructions from kernel space to user space. For example, three memory segments. Different memory addresses correspond to different control instruction address numbers.

[0080] In some embodiments, the first control instruction address number is used to indicate a first address in the first shared memory; reading the first control instruction from the first shared memory based on the first control instruction address number may include: reading the first control instruction from the first address based on the first control instruction address number.

[0081] For example, such as Figure 3 As shown, the variable storing the address sequence number of the control instruction in kernel space can be named OI (Ordinal Instruction). The value of OI can be 1, 2, or 3. It instructs the kernel transceiver thread in the underlying communication program to retrieve the control instruction from one of the three memory addresses used to store the control instruction (i.e., the address segment with the sequence number OI) and then send it to the motor. It also instructs the data exchange thread in the upper-level control program to write the control instruction passed from the control algorithm into one of the three segments (i.e., the address segment with the sequence number OI plus 1; for example, if OI equals 3, then it needs to be written to the first segment address). The write thread always performs the write operation at the address segment below the address indicated by the sequence number. After the write operation is completed, the sequence number is updated so that the read thread can read the written data from the address indicated by the updated sequence number.

[0082] In some embodiments, the first control instruction address number may be stored in a preset storage space within the kernel space; the first control instruction is a control instruction sent by the controller to the target actuator via the Industrial Internet bus.

[0083] 203. Obtain the address sequence number of the first feedback information through the kernel transceiver thread, and write the first feedback information into the second shared memory based on the address sequence number of the first feedback information; the first feedback information is used to read through the data exchange thread and send the first feedback information to the control algorithm in the user space; the first shared memory and the second shared memory are obtained by mapping the address of the kernel space to the user space.

[0084] Specifically, the mmap() function can be used for address mapping. In kernel space, N memory segments (N greater than or equal to 3) are statically allocated as the second shared memory for kernel space data transmission and reception of feedback information from user space to kernel space. For example, there are 3 memory segments. Different memory addresses correspond to different feedback information address numbers. In each cycle, the data transmission thread writes the control instructions transmitted by the control algorithm into the first shared memory, so that the kernel transmission thread reads and modifies the control instructions and writes them into a data packet. This data packet is then sent to each target actuator (e.g., a motor) via the EtherCAT bus. The target actuator writes the feedback information generated based on the previous control instruction into this data packet and feeds it back to kernel space via the EtherCAT bus. Kernel space writes this feedback information into the second shared memory, and then the data transmission thread reads the feedback information written by the kernel transmission thread into the second shared memory and feeds it back to the control algorithm, so that the control algorithm can generate new control instructions based on this feedback information.

[0085] In some embodiments, the first feedback information address sequence number is used to indicate a second address in the second shared memory; the step of writing the first feedback information into the second shared memory based on the first feedback information address sequence number may include: writing the first feedback information into a third address in the first shared memory based on the first feedback information address sequence number; after writing the first feedback information, indicating the third address with the first feedback information address sequence number to obtain a second feedback information address sequence number, and storing the second feedback information address sequence number into a preset storage space in the kernel space; the third address is the address following the second address.

[0086] For example, such as Figure 3 As shown, the variable storing the sequence number of the feedback information address can be named OF (OrdinalFeedback). The value of OF can be 1, 2, or 3, indicating which of the three memory segments used to store the feedback information (the segment with the sequence number OF plus 1; if OF equals 3, the first segment) the kernel transceiver thread in the underlying communication program should write the information fed back from the motor to. It also indicates which of the three segments (the segment with the sequence number OF) the data exchange thread in the upper-level control program should retrieve the feedback information from and pass it to the control algorithm. The write thread always performs the write operation at the address segment below the address indicated by the sequence number. After the write operation is completed, the sequence number is updated so that the read thread can read the written data from the address indicated by the updated sequence number.

[0087] In some embodiments, the first feedback information address number may be stored in a preset storage space within the kernel space; the target feedback information is information fed back by the target actuator to the controller through the industrial internet bus.

[0088] In some embodiments, obtaining the first control instruction address sequence number through the kernel transceiver thread may include: obtaining a spinlock through the kernel transceiver thread, and obtaining the first control instruction address sequence number under spinlock protection; obtaining the first feedback information address sequence number through the kernel transceiver thread may include: obtaining a spinlock through the kernel transceiver thread, and obtaining the first feedback information address sequence number under spinlock protection.

[0089] Specifically, how to protect data in shared memory from read and write operations has become a key issue. Related technologies use mutexes for read protection. However, the same mutex cannot be used in user space and kernel space. Therefore, the inventors of this application have discovered that spinlocks can be used to protect operations such as reading and updating sequence numbers. Spinlocks are used to protect the kernel transceiver thread when reading OI (Original Address). Spinlocks are also used to protect the kernel transceiver thread when reading and updating OF (Original Address). In this embodiment, by using spinlocks to protect the access to the two read address sequence numbers in the kernel space's handling function for responding to changes from user space and obtaining read address sequence numbers via ioctl(), and also using spinlocks in the kernel transceiver thread to protect their access, read and write protection of data in shared memory can be achieved, improving the accuracy of data transmission and reception in kernel space.

[0090] The following combination Figure 4 The data transmission and reception loop process of the kernel's transmit and receive thread is illustrated with an example, such as... Figure 4 As shown, the kernel space EtherCAT transceiver thread starts, obtains the value of OF, receives EtherCAT data and writes the feedback information to the address next to the address indicated by OF. After writing, it updates the value of OF so that OF indicates the address to which the feedback information was just written. It obtains the value of OI, reads the control instruction from the address indicated by OI and sends the data through EtherCAT. When the next trigger time is reached, the next transceiver cycle begins, and the above steps are repeated.

[0091] In this embodiment, there are several ways to send and receive EtherCAT data frames at fixed time intervals. The first method involves a sleep mode, specifically using `usleep_range()` to sleep and wake up just before the send / receive operation. However, because the wake-up time deviates from the set value—this deviation can be as long as nearly 200 microseconds on soft real-time Linux—the accuracy is low. The second method involves a spin-wait mode; however, during the wait, the kernel send / receive thread completely occupies one CPU, resulting in significant performance consumption. The third method combines the `usleep_range()` sleep mode and the spin-wait mode for the kernel thread's timed data sending and receiving, greatly reducing the average fluctuation of the send / receive cycle. Specifically, when the time difference between the current time and the target trigger time is greater than 12% of the send / receive cycle, `usleep_range()` is continuously used to sleep for one step time—approximately 4% to 8% of the send / receive cycle—until the time difference is closer to the target trigger time (less than 12% of the send / receive cycle), at which point spin-wait is used until the target trigger time is reached, after which data sending and receiving can proceed. During the spin wait period, the thread continuously checks whether the trigger time has been reached, sacrificing full CPU usage for the timeliness of data transmission and reception.

[0092] In some embodiments, obtaining the first control instruction address sequence number through the kernel transceiver thread may include: determining the first target trigger time corresponding to the current first preset cycle; if the time difference between the current time and the first target trigger time is greater than a first preset threshold, then sleeping based on a first preset step size; if the time difference between the current time and the first target trigger time is less than or equal to the first preset threshold, then spinning wait until the first target trigger time is reached, and then obtaining the first control instruction address sequence number through the kernel transceiver thread.

[0093] For example, such as Figure 6 As shown, it enters sleep mode. If it is currently in sleep mode, it uses usleep_range() to sleep for one step of time. After waking up, it gets the current time. If the current time is greater than the target trigger time by a preset duration, it continues to sleep for one step of time. After waking up, it gets the current time again. If the current time is less than or equal to the target trigger time by a preset duration, it closes sleep mode and enters spin waiting until the trigger time is reached.

[0094] The kernel space data transmission and reception method provided in this embodiment maps the kernel space address to the user space and realizes data transmission and reception between the low-level communication program in the kernel space and the upper-level control program in the user space in a shared memory manner. This enables the kernel space to communicate with multiple target actuators (such as motors in a humanoid robot) on the EtherCAT bus without excessive function call overhead, and facilitates efficient data transmission and reception between the master station and slave station on EtherCAT.

[0095] In some embodiments, based on the above embodiments, for example in Figure 2 Based on the illustrated embodiment, the method may further include: performing data transmission and reception in the user space via a data exchange thread in the user space based on a second preset period; the second preset period is consistent with the first preset period; for each second preset period, obtaining a second control instruction address sequence number through the data exchange thread, and writing the first control instruction into the first shared memory based on the second control instruction address sequence number; obtaining a second feedback information address sequence number through the data exchange thread, and reading the first feedback information from the second shared memory based on the second feedback information address sequence number.

[0096] Specifically, to meet real-time requirements, improve system stability, and optimize resource utilization, the data transceiver thread in user space can periodically perform data transmission and reception. In each cycle, the data transceiver thread writes the control instructions transmitted by the control algorithm into the first shared memory, enabling the kernel transceiver thread to read and modify the control instructions and write them into a data packet. This data packet is then sent to each target actuator (e.g., a motor) via the EtherCAT bus. The target actuator writes feedback information generated based on the previous control instruction into this data packet and feeds it back to the kernel space via the EtherCAT bus. The kernel space writes this feedback information into the second shared memory. The data transceiver thread then reads the feedback information written to the second shared memory by the kernel transceiver thread and feeds it back to the control algorithm, enabling the control algorithm to generate new control instructions based on this feedback.

[0097] In some embodiments, obtaining the second control instruction address number through the data exchange thread and writing the first control instruction into the first shared memory based on the second control instruction address number may include: obtaining the second control instruction address number from a preset storage space in the kernel space through the data exchange thread based on a preset function; the second control instruction address number is used to indicate a fourth address in the first shared memory; the fourth address is the address preceding the first address; writing the first control instruction to a first address based on the second control instruction address number; after writing the first control instruction, indicating the first address with the first control instruction address number to obtain the first control instruction address number, and storing the second control instruction address number in the preset storage space; correspondingly, reading the first feedback information from the second shared memory through the data exchange thread includes: obtaining the second feedback information address number from the preset storage space through the data exchange thread based on a preset function; and reading the first feedback information from the third address based on the second feedback information address number.

[0098] Specifically, such as Figure 3 As shown, the variable storing the address number of the control instruction in kernel space can be named OI (Ordinal Instruction). The value of OI can be 1, 2, or 3, indicating which of the three memory segments (the segment with the OI value) the kernel transceiver thread in the underlying communication program retrieves the control instruction from and sends it to the motor. It also indicates which of the three segments the data exchange thread in the upper-level control program writes the control instruction from the control algorithm to (the segment with the OI value plus 1; if OI equals 3, the first segment). The write thread always performs the write operation at the address segment following the address indicated by the sequence number. After the write operation is complete, the sequence number is updated so that the read thread can read the written data from the address indicated by the updated sequence number. The variable storing the sequence number of the feedback information address can be named OF (Ordinal Feedback). The value of OF can be 1, 2, or 3, indicating which of the three memory segments (the segment with the OF value plus 1, or the first segment if OF equals 3) the kernel transceiver thread in the underlying communication program should write the information fed back from the motor to (the segment with the OF value plus 1). It also indicates which segment (the segment with the OF value) the data exchange thread in the upper-level control program should retrieve the feedback information from and pass it to the control algorithm. The write thread always performs the write operation at the address segment following the one indicated by the OF value. After the write operation is complete, the OF value is updated, allowing the read thread to read the written data from the address indicated by the updated OF value.

[0099] In some embodiments, obtaining the second control instruction address number through the data exchange thread may include: sending a first target request to a target processing function in the kernel space through a data exchange thread in user space based on a preset function; in response to the first target request, the target processing function acquires a spinlock and, under spinlock protection, sends the second control instruction address number to the data exchange thread; correspondingly, obtaining the second feedback information address number through the data exchange thread may include: sending a second target request to a target processing function in the kernel space through a data exchange thread in user space based on a preset function; in response to the second target request, the target processing function acquires a spinlock and, under spinlock protection, sends the second feedback information address number to the data exchange thread.

[0100] Specifically, spinlocks can be used to protect operations such as reading and updating sequence numbers. The default function is the `ioctl()` function. Requests to read and update OI (Original Address) variables sent by the data exchange thread to the underlying communication program via `ioctl()` are handled by the request handling function in the underlying communication program, and spinlocks also protect the function's access to OI variables. Similarly, requests to read OF (Original Address) variables sent by the data exchange thread to the underlying communication program via `ioctl()` are handled by the underlying communication program's request handling function, and spinlocks also protect the function's access to OF variables. In this embodiment, by using spinlocks to protect the access to the two read address variables in the kernel space's handling function for responding to changes from user space and obtaining read address sequence numbers via `ioctl()`, and also using spinlocks to protect their access in the kernel transceiver thread, read-write protection of data in shared memory can be achieved, improving the accuracy of data transmission and reception in kernel space.

[0101] The following combination Figure 5 An example is provided to illustrate the data sending and receiving loop process of the data sending and receiving thread, such as... Figure 5 As shown, the user space data exchange thread starts, obtains the value of OF, reads feedback information from the address indicated by OF and passes it to the control algorithm, obtains the value of OI, writes the control instructions passed by the control algorithm into the address next to the address indicated by OI, updates the value of OI so that OI indicates the address to which the control instructions were just written, and enters the next transmit / receive cycle when the next trigger time is reached, repeating the above steps.

[0102] In some embodiments, obtaining the second control instruction address sequence number through the data exchange thread may include: determining the second target trigger time corresponding to the current second preset period; if the time difference between the current time and the second target trigger time is greater than a second preset threshold, then putting the device to sleep based on a second preset step size; if the time difference between the current time and the second target trigger time is less than or equal to the second preset threshold, then performing a spin wait until the second target trigger time is reached, and then obtaining the second control instruction address sequence number through the data exchange thread.

[0103] In this embodiment, the second preset threshold can be equal to the first preset threshold.

[0104] For example, such as Figure 6 As shown, it enters sleep mode. If it is currently in sleep mode, it uses usleep_range() to sleep for one step of time. After waking up, it gets the current time. If the current time is greater than the target trigger time by a preset duration, it continues to sleep for one step of time. After waking up, it gets the current time again. If the current time is less than or equal to the target trigger time by a preset duration, it closes sleep mode and enters spin waiting until the trigger time is reached.

[0105] The kernel space data transmission and reception method provided in this embodiment maps the kernel space address to the user space and realizes data transmission and reception between the low-level communication program in the kernel space and the upper-level control program in the user space in a shared memory manner. This enables the kernel space to communicate with multiple target actuators (such as motors in a humanoid robot) on the EtherCAT bus without excessive function call overhead, and facilitates efficient data transmission and reception between the master station and slave station on EtherCAT.

[0106] Figure 7 This is a schematic diagram of the structure of a kernel space data transceiver device provided in an embodiment of this application. Figure 7 As shown, the kernel space data transceiver device 70 includes: a transceiver module 701, a read module 702, and a write module 703.

[0107] The transceiver module 701 is used to send and receive data in the kernel space through the kernel transceiver thread in the kernel space of the controller based on a first preset period.

[0108] The read module 702 is configured to, for each of the first preset cycles, obtain the address sequence number of a first control instruction through the kernel transceiver thread, read the first control instruction from the first shared memory based on the first control instruction address sequence number, and send the first control instruction to the plurality of target executors through the EtherCAT bus, so that the plurality of target executors send first feedback information to the kernel transceiver thread; the first feedback information is obtained by the target executor executing a second control instruction; the second control instruction is an instruction read in the previous first preset cycle; the first control instruction is written to the first shared memory by the data exchange thread in the user space of the controller, and is issued by the control algorithm in the user space;

[0109] The write module 703 is used to obtain the address sequence number of the first feedback information through the kernel transceiver thread, and write the first feedback information into the second shared memory based on the address sequence number of the first feedback information; the first feedback information is used to be read by the data exchange thread and sent to the control algorithm in the user space; the first shared memory and the second shared memory are obtained by mapping the address of the kernel space to the user space.

[0110] The kernel space data transceiver device provided in this application provides a way to map kernel space addresses to user space and use shared memory to enable data transmission and reception between the kernel space's low-level communication program and the user space's upper-level control program. This avoids excessive function call overhead and facilitates efficient data transmission and reception between the master station and slave station on EtherCAT by mapping kernel space addresses to user space and using shared memory.

[0111] In some embodiments, the first control instruction address number is used to indicate a first address in the first shared memory; the read module 702 is specifically used to: read the first control instruction from the first address based on the first control instruction address number; correspondingly, the first feedback information address number is used to indicate a second address in the second shared memory; the write module 703 is specifically used to: write the first feedback information to a third address in the first shared memory based on the first feedback information address number, and after writing the first feedback information, indicate the third address with the first feedback information address number to obtain a second feedback information address number, and store the second feedback information address number in a preset storage space in the kernel space; the third address is the address following the second address.

[0112] In some embodiments, the read module 702 is specifically used to: acquire a spinlock through the kernel transceiver thread, and acquire the first control instruction address sequence number under spinlock protection; the write module 703 is specifically used to: acquire a spinlock through the kernel transceiver thread, and acquire the first feedback information address sequence number under spinlock protection.

[0113] In some embodiments, the read module 702 is specifically used to: determine the first target trigger time corresponding to the current first preset period; if the time difference between the current time and the first target trigger time is greater than a first preset threshold, then sleep based on a first preset step size; if the time difference between the current time and the first target trigger time is less than or equal to the first preset threshold, then spin-wait until the first target trigger time is reached, then obtain the first control instruction address sequence number through the kernel transceiver thread.

[0114] In some embodiments, the first preset period is determined based on the data processing period of the control algorithm.

[0115] In some embodiments, the transceiver module 701 is further configured to: perform data transmission and reception in the user space through a data exchange thread in the user space based on a second preset period; the second preset period is consistent with the first preset period; the write module 703 is further configured to: for each second preset period, obtain a second control instruction address sequence number through the data exchange thread, and write the first control instruction into the first shared memory based on the second control instruction address sequence number; the read module 702 is further configured to: obtain a second feedback information address sequence number through the data exchange thread, and read the first feedback information from the second shared memory based on the second feedback information address sequence number.

[0116] In some embodiments, the write module 703 is specifically used to: obtain a second control instruction address sequence number from a preset storage space in the kernel space based on a preset function through the data exchange thread; the second control instruction address sequence number is used to indicate a fourth address in the first shared memory; the fourth address is the address preceding the first address; based on the second control instruction address sequence number, write the first control instruction to the first address; after the first control instruction is written, indicate the first address with the first control instruction address sequence number to obtain the first control instruction address sequence number, and store the second control instruction address sequence number in the preset storage space; the read module 702 is specifically used to: obtain a second feedback information address sequence number from the preset storage space based on a preset function through the data exchange thread; and read the first feedback information from the third address based on the second feedback information address sequence number.

[0117] In some embodiments, the write module 703 is specifically configured to: send a first target request to a target processing function in the kernel space through a data exchange thread in the user space based on a preset function; in response to the first target request, the target processing function acquires a spinlock and, under spinlock protection, sends the second control instruction address sequence number to the data exchange thread; the read module 702 is specifically configured to: send a second target request to a target processing function in the kernel space through a data exchange thread in the user space based on a preset function; in response to the second target request, the target processing function acquires a spinlock and, under spinlock protection, sends the second feedback information address sequence number to the data exchange thread.

[0118] In some embodiments, the write module 703 is specifically used to: determine the second target trigger time corresponding to the current second preset period; if the time difference between the current time and the second target trigger time is greater than the second preset threshold, then sleep based on the second preset step size; if the time difference between the current time and the second target trigger time is less than or equal to the second preset threshold, then spin wait until the second target trigger time is reached, and then obtain the second control instruction address sequence number through the data exchange thread.

[0119] The kernel space data transceiver device provided in this application embodiment can be used to execute the above method embodiment. Its implementation principle and technical effect are similar, and will not be described again here.

[0120] Figure 8 This is a schematic diagram of the hardware structure of a kernel space data transceiver device provided in an embodiment of this application. The device may be a controller, a humanoid robot, etc.

[0121] Device 80 may include one or more of the following components: processing component 801, memory 802, power supply component 803, multimedia component 804, audio component 805, input / output (I / O) interface 806, sensor component 807, and communication component 808.

[0122] Processing component 801 typically controls the overall operation of device 80, such as operations associated with display, telephone calls, data communication, camera operation, and recording. Processing component 801 may include one or more processors 809 to execute instructions to complete all or part of the steps of the methods described above. Furthermore, processing component 801 may include one or more modules to facilitate interaction between processing component 801 and other components. For example, processing component 801 may include a multimedia module to facilitate interaction between multimedia component 804 and processing component 801.

[0123] Memory 802 is configured to store various types of data to support the operation of device 80. Examples of such data include instructions for any application or method operating on device 80, contact data, phonebook data, messages, pictures, videos, etc. Memory 802 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.

[0124] Power supply component 803 provides power to various components of device 80. Power supply component 803 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to device 80.

[0125] Multimedia component 804 includes a screen that provides an output interface between the device 80 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touchscreen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touches, swipes, and gestures on the touch panel. The touch sensors may sense not only the boundaries of the touch or swipe action but also the duration and pressure associated with the touch or swipe operation. In some embodiments, multimedia component 804 includes a front-facing camera and / or a rear-facing camera. When the device 80 is in an operating mode, such as a shooting mode or a video mode, the front-facing camera and / or the rear-facing camera may receive external multimedia data. Each front-facing camera and rear-facing camera may be a fixed optical lens system or have focal length and optical zoom capabilities.

[0126] Audio component 805 is configured to output and / or input audio signals. For example, audio component 805 includes a microphone (MIC) configured to receive external audio signals when device 80 is in an operating mode, such as call mode, recording mode, and voice recognition mode. The received audio signals may be further stored in memory 802 or transmitted via communication component 808. In some embodiments, audio component 805 also includes a speaker for outputting audio signals.

[0127] I / O interface 806 provides an interface between processing component 801 and peripheral interface modules, such as keyboards, click wheels, buttons, etc. These buttons may include, but are not limited to, home buttons, volume buttons, power buttons, and lock buttons.

[0128] Sensor assembly 807 includes one or more sensors for providing state assessments of various aspects of device 80. For example, sensor assembly 807 can detect the on / off state of device 80, the relative positioning of components such as the display and keypad of device 80, changes in the position of device 80 or a component of device 80, the presence or absence of user contact with device 80, the orientation or acceleration / deceleration of device 80, and temperature changes of device 80. Sensor assembly 807 may include a proximity sensor configured to detect the presence of nearby objects without any physical contact. Sensor assembly 807 may also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, sensor assembly 807 may also include an accelerometer, a gyroscope, a magnetometer, a pressure sensor, or a temperature sensor.

[0129] Communication component 808 is configured to facilitate wired or wireless communication between device 80 and other devices. Device 80 can access wireless networks based on communication standards, such as WiFi, 2G, or 3G, or combinations thereof. In one exemplary embodiment, communication component 808 receives broadcast signals or broadcast-related information from an external broadcast management system via a broadcast channel. In one exemplary embodiment, communication component 808 also includes a near-field communication (NFC) module to facilitate short-range communication. For example, the NFC module may be implemented based on radio frequency identification (RFID) technology, Infrared Data Association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology, and other technologies.

[0130] In an exemplary embodiment, device 80 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), host computers, micro-host computers, microprocessors, or other electronic components to perform the methods described above.

[0131] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 802 including instructions, which can be executed by a processor 809 of device 80 to perform the above-described method. For example, the non-transitory computer-readable storage medium may be a ROM, random access memory (RAM), CD-ROM, magnetic tape, floppy disk, and optical data storage device, etc.

[0132] The aforementioned computer-readable storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk. The readable storage medium can be any available medium accessible to a general-purpose or special-purpose computer.

[0133] An exemplary readable storage medium is coupled to a processor, enabling the processor to read information from and write information to the readable storage medium. Of course, the readable storage medium can also be a component of the processor. The processor and the readable storage medium can reside in an Application Specific Integrated Circuit (ASIC). Alternatively, the processor and the readable storage medium can exist as discrete components in the device.

[0134] Those skilled in the art will understand that all or part of the steps of the above-described method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When executed, the program performs the steps of the above-described method embodiments; and the aforementioned storage medium includes various media capable of storing program code, such as ROM, RAM, magnetic disks, or optical disks.

[0135] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the kernel space data transceiver method executed by the kernel space data transceiver device described above.

[0136] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A kernel space data transmission and reception method, characterized in that, Applied to a humanoid robot, the humanoid robot including a controller and multiple target actuators, the controller being connected to the multiple target actuators via an EtherCAT bus, the method includes: Data transmission and reception in the kernel space are performed through the kernel transceiver thread in the kernel space of the controller based on the first preset cycle; For each of the first preset cycles, the kernel transceiver thread obtains the address number of a first control instruction, reads the first control instruction from the first shared memory based on the address number, and sends the first control instruction to the plurality of target executors via the EtherCAT bus, so that the plurality of target executors send first feedback information to the kernel transceiver thread; the first feedback information is obtained by the target executor executing a second control instruction; the second control instruction is the instruction read in the previous first preset cycle; the first control instruction is written to the first shared memory by the data exchange thread in the user space of the controller, and is issued by the control algorithm in the user space; The kernel transceiver thread obtains the address sequence number of the first feedback information, and writes the first feedback information into the second shared memory based on the address sequence number of the first feedback information; the first feedback information is used to read through the data exchange thread and send the first feedback information to the control algorithm in user space; the first shared memory and the second shared memory are obtained by mapping the address of the kernel space to the user space.

2. The method according to claim 1, characterized in that, The first control instruction address number is used to indicate a first address in the first shared memory; the step of reading the first control instruction from the first shared memory based on the first control instruction address number includes: Based on the first control instruction address number, read the first control instruction from the first address; Accordingly, the first feedback information address number is used to indicate the second address in the second shared memory; the step of writing the first feedback information into the second shared memory based on the first feedback information address number includes: Based on the first feedback information address number, the first feedback information is written to the third address in the first shared memory. After the first feedback information is written, the first feedback information address number is used to indicate the third address to obtain the second feedback information address number, and the second feedback information address number is stored in the preset storage space in the kernel space; the third address is the address after the second address.

3. The method according to claim 1, characterized in that, The step of obtaining the address sequence number of the first control instruction through the kernel transceiver thread includes: The kernel transceiver thread acquires a spinlock, and under spinlock protection, the address sequence number of the first control instruction is obtained. The step of obtaining the address sequence number of the first feedback information through the kernel transceiver thread includes: The kernel transceiver thread acquires a spinlock, and under spinlock protection, obtains the address sequence number of the first feedback information.

4. The method according to claim 1, characterized in that, The step of obtaining the address sequence number of the first control instruction through the kernel transceiver thread includes: Determine the trigger time of the first target corresponding to the current first preset cycle; If the time difference between the current time and the trigger time of the first target is greater than the first preset threshold, then sleep is initiated based on the first preset step size; If the time difference between the current time and the first target trigger time is less than or equal to the first preset threshold, then spin waiting is performed until the first target trigger time is reached, and then the first control instruction address sequence number is obtained through the kernel transceiver thread.

5. The method according to claim 1, characterized in that, The first preset period is determined based on the data processing period of the control algorithm.

6. The method according to any one of claims 1-5, characterized in that, The method further includes: Data transmission and reception in user space are performed through a data exchange thread in user space based on a second preset period; the second preset period is consistent with the first preset period; For each of the second preset cycles, the second control instruction address number is obtained through the data exchange thread, and the first control instruction is written into the first shared memory based on the second control instruction address number; The second feedback information address number is obtained through the data exchange thread, and the first feedback information is read from the second shared memory based on the second feedback information address number.

7. The method according to claim 6, characterized in that, The step of obtaining the second control instruction address number through the data exchange thread and writing the first control instruction into the first shared memory based on the second control instruction address number includes: The data exchange thread retrieves a second control instruction address number from a preset storage space in the kernel space based on a preset function; the second control instruction address number is used to indicate a fourth address in the first shared memory; the fourth address is the address preceding the first address; Based on the second control instruction address number, the first control instruction is written to the first address. After the first control instruction is written, the first control instruction address number is used to indicate the first address to obtain the first control instruction address number, and the second control instruction address number is stored in the preset storage space. Accordingly, reading the first feedback information from the second shared memory through the data exchange thread includes: The second feedback information address number is obtained from the preset storage space through the data exchange thread based on a preset function; Based on the address sequence number of the second feedback information, the first feedback information is read from the third address.

8. The method according to claim 6, characterized in that, The step of obtaining the second control instruction address number through the data exchange thread includes: Based on a preset function, a first target request is sent to the target processing function in the kernel space through a data exchange thread in the user space. In response to the first target request, the target processing function acquires a spinlock and, under spinlock protection, sends the second control instruction address sequence number to the data exchange thread; Accordingly, obtaining the second feedback information address sequence number through the data exchange thread includes: Based on a preset function, a second target request is sent to the target processing function in the kernel space through a data exchange thread in the user space. In response to the second target request, the target processing function acquires a spinlock and, under spinlock protection, sends the second feedback information address sequence number to the data exchange thread.

9. The method according to claim 6, characterized in that, The step of obtaining the second control instruction address number through the data exchange thread includes: Determine the trigger time of the second target corresponding to the current second preset cycle; If the time difference between the current time and the trigger time of the second target is greater than the second preset threshold, then sleep is initiated based on the second preset step size; If the time difference between the current time and the second target trigger time is less than or equal to the second preset threshold, then spin waiting is performed until the second target trigger time is reached, and then the second control instruction address sequence number is obtained through the data exchange thread.

10. A kernel space data transceiver device, characterized in that, include: At least one processor and memory; The memory stores computer-executed instructions; The at least one processor executes computer execution instructions stored in the memory, causing the at least one processor to perform the kernel space data transmission and reception method as described in any one of claims 1 to 9.

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