Tlc flash memory reading redundancy size calculation method and device, electronic equipment and storage medium

Abstract

Embodiments of the present application provide a TLC flash memory read redundancy size calculation method and device, electronic equipment and storage medium, relating to the technical field of TLC flash memory. By writing known randomly generated binary data into the TLC flash memory, calculating the expected data mask, performing multiple offsets for each read level, reading the binary data to obtain the actual data mask, comparing the actual data mask with the expected data mask, and statistically calculating the offset step length of each read level, and then adding the offset step lengths to obtain the read redundancy size of the TLC flash memory. Thus, the read redundancy size of TLC flash memory of different manufacturers can be calculated, and the reliability of TLC flash memory of different manufacturers can be compared.

Description

Technical Field

[0001] The present invention relates to the technical field of TLC flash memory, and in particular to a method, device, electronic device and storage medium for calculating the read redundancy size of a TLC flash memory. Background Art

[0002] NAND flash memory is a non-volatile storage technology that stores data by controlling the charge in a memory cell. Each memory cell can represent one or more bits of information, differentiated by different voltage threshold (Vt) states. In NAND flash memory, data reading, programming (writing), and erasing operations are performed by changing the Vt of the memory cell.

[0003] As NAND flash memory evolves, different manufacturers have introduced their own products. However, each focuses on a different aspect of their products, resulting in variations in the programming behavior of each manufacturer's chips. Different programmed Vt distributions lead to varying read redundancies between NAND flash memories. Without knowing the read redundancy of different manufacturers' products, it's difficult to determine the accuracy of data reads and the reliability of storage cells. Summary of the Invention

[0004] In view of this, an object of embodiments of the present invention is to provide a method, device, electronic device, and storage medium for calculating the read redundancy size of a TLC flash memory to at least partially improve the above-mentioned problem.

[0005] In order to achieve the above objectives, the technical solutions adopted in the embodiments of the present invention are as follows:

[0006] In a first aspect, an embodiment of the present invention provides a method for calculating a read redundancy size of a TLC flash memory, the method comprising:

[0007] Randomly generate binary data and write the binary data into a TLC flash memory; the TLC flash memory includes a plurality of word lines, the word lines include three pages, the pages include a plurality of memory cells, the memory cells include eight states, and the eight states are isolated by seven read levels;

[0008] Calculating an expected data mask for each of the pages based on the binary data;

[0009] For each of the read levels of each of the pages of each of the word lines, shift the read level in a first direction and read data to obtain a first actual data mask, and calculate a first shift step length of the read level based on the first actual data mask and the expected data mask;

[0010] Repeating the first direction shifting of the reading level until a first preset condition is reached, and calculating a final first shift step length of the reading level;

[0011] performing a second direction shift on the read level and performing data reading to obtain a second actual data mask, and calculating a second shift step length of the read level according to the second actual data mask and the expected data mask;

[0012] Repeating the second direction shifting of the reading level until a preset condition is met, and calculating a final second shift step length of the reading level;

[0013] cyclically calculating a first direction offset step length and a second direction offset step length for each of the read levels of each of the pages of each of the word lines;

[0014] The read redundancy size of the TLC flash memory is calculated by adding the first direction offset step lengths and the second direction offset step lengths.

[0015] Optionally, performing a first direction shift on the read level and reading data to obtain a first actual data mask, and calculating a first shift step length of the read level according to the first actual data mask and the expected data mask, includes:

[0016] Finding a corresponding first state value according to the read level and the first direction offset;

[0017] Determining whether the data reading is the first data reading;

[0018] If the data is read for the first time, the offset is set to 0, and a default read is performed to obtain a first actual data mask;

[0019] calculating a failure bit count of the data currently read based on the first actual data mask and the expected data mask, and setting a first offset step size of the read level and a pass flag based on the failure bit count; the pass flag includes a pass and a fail flag, wherein the pass flag indicates that the failure bit count currently read meets the judgment standard of the TLC flash memory, and the pass flag indicates that the failure bit count currently read does not meet the judgment standard of the TLC flash memory;

[0020] If the data reading is not the first data reading, taking the offset as the offset of the preset rule, performing offset reading to obtain a first actual data mask;

[0021] The failure bit count of the current data read is calculated according to the first actual data mask and the expected data mask, and the first offset step of the read level is calculated according to the failure bit count, the pass flag and the number of data reads.

[0022] Optionally, calculating a failure bit count of the current data read according to the first actual data mask and the expected data mask, and setting a first offset step size and a pass flag of the read level according to the failure bit count, includes:

[0023] comparing the first actual data mask and the expected data mask to obtain error data;

[0024] For any of the erroneous data, finding the expected value of the position corresponding to the first actual data mask according to the position of the erroneous data on the page;

[0025] If the expected value matches the first state value, incrementing the fault bit count of the first state value by one;

[0026] Traversing each of the erroneous data to obtain a failure bit count of the first state value;

[0027] Determining whether the fault bit count is less than a preset fault number;

[0028] If so, setting the first offset step of the read level to a first preset offset, and recording the pass flag as passed;

[0029] If not, the first offset step of the read level is set to a second preset offset, and the pass flag is recorded as failure.

[0030] Optionally, calculating a failure bit count of the current data read according to the first actual data mask and the expected data mask, and calculating a first offset step of the read level according to the failure bit count, the pass flag, and the number of data reads includes:

[0031] comparing the first actual data mask and the expected data mask to obtain error data;

[0032] For any of the erroneous data, finding the expected value of the position corresponding to the first actual data mask according to the position of the erroneous data on the page;

[0033] If the expected value matches the first state value, incrementing the fault bit count of the first state value by one;

[0034] Traversing each of the erroneous data to obtain a failure bit count of the first state value;

[0035] Determining whether the fault bit count is less than a preset fault number;

[0036] If so, determine whether it is the second offset and the pass flag is passed;

[0037] If it is the second shift and the pass flag is passed, the first shift step of the read level is set to the first preset shift step, and the first direction shift is ended;

[0038] If it is not the second offset or the pass flag is failure, subtract the first offset step of the read level by a value of a preset rule;

[0039] If not, determine whether it is the second offset and the pass flag is failure;

[0040] If it is the second shift and the pass flag is failure, the first shift step of the read level is set to the second preset shift step, and the first direction shift is ended;

[0041] If it is not the second offset or the pass flag is passed, the first offset step length of the read level is added with a value of a preset rule.

[0042] Optionally, performing a second direction shift on the read level and reading data to obtain a second actual data mask, and calculating a second shift step length of the read level according to the second actual data mask and the expected data mask, includes:

[0043] Finding a corresponding second state value according to the read level and the second direction offset;

[0044] Determining whether the data reading is the first data reading;

[0045] If the data reading is the first data reading, the offset is set to 0, and a default reading is performed to obtain a second actual data mask;

[0046] calculating a failure bit count of the data currently read based on the second actual data mask and the expected data mask, and setting a second offset step size of the read level and a pass flag based on the failure bit count; the pass flag includes a pass and a fail flag, wherein the pass flag indicates that the failure bit count currently read meets the judgment standard of the TLC flash memory, and the pass flag indicates that the failure bit count currently read does not meet the judgment standard of the TLC flash memory;

[0047] If the data reading is not the first data reading, taking the offset as the offset of the preset rule, performing offset reading to obtain a second actual data mask;

[0048] The failure bit count of the current data read is calculated according to the second actual data mask and the expected data mask, and the second offset step of the read level is calculated according to the failure bit count, the pass flag and the number of data reads.

[0049] Optionally, calculating a failure bit count of the current data read according to the second actual data mask and the expected data mask, and setting a second offset step size and a pass flag of the read level according to the failure bit count, includes:

[0050] comparing the second actual data mask with the expected data mask to obtain error data;

[0051] For any of the erroneous data, finding the expected value of the position corresponding to the second actual data mask according to the position of the erroneous data on the page;

[0052] If the expected value matches the second state value, incrementing the fault bit count of the second state value by one;

[0053] Traversing each of the erroneous data to obtain a failure bit count of the second state value;

[0054] Determining whether the fault bit count is less than a preset fault number;

[0055] If so, setting the second offset step of the read level to a second preset offset, and recording the pass flag as passed;

[0056] If not, the second offset step of the read level is set to the first preset offset, and the pass flag is recorded as failure.

[0057] Optionally, calculating a failure bit count of the current data read according to the second actual data mask and the expected data mask, and calculating a second offset step of the read level according to the failure bit count, the pass flag, and the number of data reads, includes:

[0058] comparing the second actual data mask with the expected data mask to obtain error data;

[0059] For any of the erroneous data, finding the expected value of the position corresponding to the second actual data mask according to the position of the erroneous data on the page;

[0060] If the expected value matches the second state value, incrementing the fault bit count of the second state value by one;

[0061] Traversing each of the erroneous data to obtain a failure bit count of the second state value;

[0062] Determining whether the fault bit count is less than a preset fault number;

[0063] If so, determine whether it is the second offset and the pass flag is passed;

[0064] If it is the second shift and the pass flag is passed, the second shift step length of the read level is set to the first preset shift step length, and the second direction shift is ended;

[0065] If it is not the second offset or the pass flag is failure, the second offset step length of the read level is added with a value of a preset rule;

[0066] If not, determine whether it is the second offset and the pass flag is failure;

[0067] If it is the second shift and the pass flag is failure, the second shift step length of the read level is set to the second preset shift step length, and the second direction shift is ended;

[0068] If it is not the second offset or the pass flag is passed, the second offset step length of the read level is reduced by a value of a preset rule.

[0069] In a second aspect, an embodiment of the present invention provides a device for calculating a read redundancy size of a TLC flash memory, the device comprising:

[0070] a data writing unit, configured to randomly generate binary data and write the binary data into a TLC flash memory; the TLC flash memory comprising a plurality of word lines, each word line comprising three pages, each page comprising a plurality of memory cells, each memory cell comprising eight states, each of the eight states being isolated by seven read levels;

[0071] an expected data calculation unit, configured to calculate an expected data mask for each of the pages based on the binary data;

[0072] a first offset step length calculation unit, configured to, for each read level of each page of each word line, perform a first direction offset on the read level and read data to obtain a first actual data mask, and calculate a first offset step length of the read level based on the first actual data mask and the expected data mask;

[0073] a final first offset step length calculation unit, configured to repeatedly perform a first direction offset on the reading level until a first preset condition is reached, and calculate a final first offset step length of the reading level;

[0074] a second offset step length calculation unit, configured to perform a second direction offset on the read level and read data to obtain a second actual data mask, and calculate a second offset step length of the read level according to the second actual data mask and the expected data mask;

[0075] a final second offset step length calculation unit, configured to repeatedly perform a second direction offset on the reading level until a preset condition is met, and calculate a final second offset step length of the reading level;

[0076] a cyclic calculation unit, configured to cyclically calculate a first direction offset step length and a second direction offset step length for each of the read levels of each of the pages of each of the word lines;

[0077] The read redundancy size calculation unit is used to add each first direction offset step length and each second direction offset step length to calculate the read redundancy size of the TLC flash memory.

[0078] In a third aspect, an embodiment of the present invention provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements any of the above-described methods when executing the program.

[0079] In a fourth aspect, an embodiment of the present invention provides a storage medium having a computer program stored thereon, wherein the computer program implements any of the above-described methods when executed by a processor.

[0080] Embodiments of the present invention provide a method, device, electronic device, and storage medium for calculating the read redundancy size of a TLC flash memory. The method performs multiple offsets on a read level, ultimately calculating a first-direction offset step length and a second-direction offset step length of the read level. All first-direction offset step lengths and second-direction offset step lengths are added together to obtain the read redundancy size of the TLC flash memory. This allows calculation of the read redundancy sizes of TLC flash memories from different manufacturers, and further comparison of the reliability of TLC flash memories from different manufacturers.

[0081] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0082] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without paying any creative work.

[0083] Figure 1 A schematic structural block diagram of an electronic device provided by an embodiment of the present invention;

[0084] Figure 2 A schematic diagram of a flow chart of a method for calculating the read redundancy size of a TLC flash memory provided by an embodiment of the present invention;

[0085] Figure 3 A Vt distribution diagram of a TLC flash memory provided by an embodiment of the present invention;

[0086] Figure 4 A schematic diagram of a process of step S230 provided in an embodiment of the present invention;

[0087] Figure 5 A schematic structural diagram of a TLC flash memory read redundancy size calculation device provided by an embodiment of the present invention.

[0088] Icons: 100-electronic device; 101-memory; 102-communication interface; 103-processor; 104-bus; 300-TLC flash memory read redundancy size calculation device; 310-data write unit; 320-expected data calculation unit; 330-first offset step calculation unit; 340-final first offset step calculation unit; 350-second offset step calculation unit; 360-final second offset step calculation unit; 370-loop calculation unit; 380-read redundancy size calculation unit. DETAILED DESCRIPTION

[0089] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings herein can be arranged and designed in various different configurations.

[0090] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention as claimed, but rather merely represents selected embodiments of the present invention. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of the present invention without creative effort are intended to fall within the scope of protection of the present invention.

[0091] It should be noted that similar reference numerals and letters represent similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings. At the same time, in the description of the present invention, the terms "first", "second", etc. are used only to distinguish the description and should not be understood as indicating or implying relative importance.

[0092] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or device comprising the element.

[0093] As NAND flash memory evolves, different manufacturers have introduced their own products. However, each focuses on a different aspect of their products, resulting in variations in the programming behavior of each manufacturer's chips. Different programmed Vt distributions lead to varying read redundancies between NAND flash memories. Without knowing the read redundancy of different manufacturers' products, it's difficult to determine the accuracy of data reads and the reliability of storage cells.

[0094] Based on the above, embodiments of the present invention provide a method, device, electronic device, and storage medium for calculating the read redundancy size of TLC flash memory, relating to the technical field of TLC flash memory. This method involves writing known randomly generated binary data into the TLC flash memory, calculating an expected data mask, performing multiple offsets on each read level, reading the binary data, and obtaining an actual data mask. The actual data mask is then compared with the expected data mask, and the offset step size for each read level is statistically calculated. The offset step sizes are then summed to obtain the read redundancy size of the TLC flash memory. This method can thus calculate the read redundancy size of TLC flash memory from different manufacturers, allowing for comparison of the reliability of TLC flash memory from different manufacturers.

[0095] To implement the process steps and functions of each example of the present invention, please refer to Figure 1 , Figure 1 This is a schematic block diagram of the structure of an electronic device provided by an embodiment of the present invention. The electronic device 100 includes a memory 101 and a processor 103. The memory 101 and processor 103 are electrically connected to each other directly or indirectly to enable data transmission or interaction. For example, these components can be electrically connected to each other via one or more communication buses 104 or signal lines. The memory 101 can be used to store software programs and modules, and the processor 103 executes the software programs and modules stored in the memory 101 to perform various functional applications and data processing.

[0096] The electronic device 100 may be, but is not limited to, a personal computer (PC), a server, a distributed computer, or the like. It is understood that the electronic device 100 is not limited to a physical server and may also be a virtual machine on a physical server, a virtual machine built on a cloud platform, or other computer that provides the same functionality as the server or virtual machine. The operating system of the electronic device 100 may be, but is not limited to, Windows, Linux, or the like.

[0097] The memory 101 may be, but is not limited to, a random access memory (RAM), a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), etc.

[0098] The communication connection between the electronic device 100 and an external device is achieved through at least one communication interface 102 (which can be wired or wireless).

[0099] Processor 103 may be an integrated circuit chip with signal processing capabilities. During implementation, each step of the embodiments of the present invention may be completed by hardware integrated logic circuits in processor 103 or by software instructions. Processor 103 may be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it may also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0100] I understand. Figure 1 The structure shown is for illustration only. The electronic device 100 may further include Figure 1 More or fewer components than shown, or with Figure 1 Different configurations shown. Figure 1Each component shown in the figure can be implemented by hardware, software or a combination thereof.

[0101] The following is an exemplary description of the TLC flash memory read redundancy size calculation method provided by the present invention. Specifically, Figure 2 A flow chart of a method for calculating the read redundancy size of a TLC flash memory provided by an embodiment of the present invention is shown in FIG. Figure 2 , the execution subject of this method can be the above Figure 1 The electronic device 100 shown in FIG. 1 includes the following steps: Figure 2 The following steps are shown:

[0102] S210: Randomly generate binary data, and write the binary data into the TLC flash memory.

[0103] Among them, TLC flash memory includes multiple word lines, a word line (WL) includes three pages, a page includes multiple storage cells, a storage cell includes eight states, and the eight states are isolated by seven read levels.

[0104] A WL of TLC flash memory can store 3 bits of data, corresponding to 3 pages, namely low position (LP), middle position (MP), and upper position (UP).

[0105] S220: Calculate the expected data mask of each page according to the binary data.

[0106] See also Figure 3 , Figure 3 A Vt distribution diagram of a TLC flash memory provided by an embodiment of the present invention shows that one WL corresponds to three pages, and the page number is a number corresponding to all WLs. For example, WL1 corresponds to page numbers 0, 1, and 2, and WL2 corresponds to page numbers 3, 4, and 5. The data mask is a combination of the data of the three page numbers corresponding to the WLs. For example, if WL1 corresponds to page0, page1, and page2, and the data of page0 is 0110110, the data of page1 is 1001101, and the data of page2 is 1101100, then the data mask obtained by page2<<2|page1<<1|page0 is 6516712.

[0107] S230: For each read level of each page of each word line, shift the read level in a first direction and read data to obtain a first actual data mask, and calculate a first shift step of the read level based on the first actual data mask and the expected data mask.

[0108] See also Figure 3 , perform a first direction offset on the read level, which may be a left offset, and calculate the first offset step of the even edge (EvenEdge), where Even Edge corresponds to E0, E2, E4…E12.

[0109] The first offset step size indicates that the read level is offset by the first offset step size, and the data read from the TLC flash memory is still accurate.

[0110] S240: Repeat step S230 until the first preset condition is met, and calculate the final first offset step length of the reading level.

[0111] Through multiple offsets, the final first offset step of the reading level is calculated.

[0112] S250: Shifting the read level in a second direction and reading data to obtain a second actual data mask, and calculating a second shift step length of the read level according to the second actual data mask and the expected data mask.

[0113] See also Figure 3 , perform a second direction offset on the read level, which may be a rightward offset, and calculate the second offset step of the odd edge (OddEdge). Odd Edge corresponds to E1, E3, E5...E13.

[0114] S260: Repeat step S250 until a preset condition is met, and calculate the final second offset step length of the reading level.

[0115] S270 : cyclically calculating the first direction offset step length and the second direction offset step length of each read level of each page of each word line.

[0116] The above steps S230 to S260 are looped to calculate the first direction offset step length and the second direction offset step length of each read level of each page of the TLC flash memory.

[0117] The specific loop steps may be to first loop all WLs, starting from the first WL, loop each page of the WL, and then loop each read level.

[0118] Optionally, refer to Figure 3 , including 7 read levels, namely 1, 2, 3, 4, 5, 6, and 7. The read levels can be divided into LP[1, 5], MP[2, 4, 6], and UP[3, 7] according to the data characteristics. LP[1, 5] means that the low-order data is different, MP[2, 4, 6] means that the middle-order data is different, and UP[3, 7] means that the high-order data is different. Therefore, LP[1, 5] or MP[2, 4, 6] or LP[1, 5] can be offset at the same time to reduce the number of cycles.

[0119] S280: Add each first direction offset step length and each second direction offset step length to calculate a read redundancy size of the TLC flash memory.

[0120] The calculated first direction offset step length or the second direction offset step length may be a negative number. For example, if the offset is to the left, the offset amount is a negative number. Therefore, each first direction offset step length and each second direction offset step length are added together.

[0121] The method performs multiple offsets on the read level and ultimately calculates the first-direction offset step length and the second-direction offset step length of the read level. All the first-direction offset step lengths and the second-direction offset step lengths are added together to obtain the read redundancy size of the TLC flash memory. This method can calculate the read redundancy size of TLC flash memories of different manufacturers and further compare the reliability of TLC flash memories of different manufacturers.

[0122] For ease of understanding, the first direction offset is set to a left offset, and the second direction offset is set to a right offset. There is no limitation in actual use.

[0123] There are many ways to calculate the first offset step. In one possible implementation, see Figure 4 , Figure 4 A schematic flow chart of step S230 provided in an embodiment of the present invention, wherein step S230 may include: Figure 4 The following steps are shown:

[0124] S231: Find a corresponding first state value according to the read level and the first direction offset.

[0125] See also Figure 3 If the read level is number 1 and the first direction offset is leftward, the first state value is 7.

[0126] S232: Determine whether the data reading is the first data reading; if so, execute step S233; if not, execute step S235.

[0127] S233: Taking the offset as 0, performing default reading, and obtaining the first actual data mask.

[0128] That is, the first data reading part performs an offset and directly reads the data to obtain a first actual data mask.

[0129] S234: Calculate the failure bit count of the current data read according to the first actual data mask and the expected data mask, and set a first offset step size and a pass flag of the read level according to the failure bit count.

[0130] Among them, the pass flag includes pass and fail. The pass flag is pass, which indicates that the fault bit count obtained by the current read meets the judgment standard of the TLC flash memory. The pass flag is fail, which indicates that the fault bit count obtained by the current read does not meet the judgment standard of the TLC flash memory.

[0131] See also Figure 3 Taking read level 1 as an example, the expected data is 76402315. If the actual read data is 76402315, it indicates that the read is correct. If the actual read data is 66402315, it indicates that the read is wrong. By comparing the data of the current page in this way, the fault bit count can be obtained.

[0132] Specifically, step S234 may include:

[0133] S2341: Compare the first actual data mask and the expected data mask to obtain error data.

[0134] As above, the expected data is 76402315. If the actual read data is 66402315, it indicates that the read is wrong. However, the actual read data is 66412320, which has more position errors. By comparing the first actual data mask and the expected data mask, all the error data are obtained.

[0135] S2342: For any erroneous data, find the expected value of the position corresponding to the first actual data mask according to the position of the erroneous data in the page.

[0136] As shown above, the first digit was mistakenly read as 6, and the expected value of the corresponding position was found. The expected value of the first digit was 7; the eighth digit was mistakenly read as 0, and its expected value was 5.

[0137] S2343: If the expected value matches the first state value, increase the fault bit count of the first state value by one.

[0138] In the above example, if the first state value is 7 and the first bit expected value is 7, only when the position is read incorrectly will it be recorded as a failed bit count.

[0139] S2344: traverse each erroneous data to obtain a failure bit count of the first state value.

[0140] All erroneous data are processed in step S2343, and the fault bits of the first state value are counted.

[0141] S2345: Determine whether the fault bit count is less than a preset fault number. If so, execute step S2346; if not, execute step S2347.

[0142] S2346: setting the first offset step of the read level to a first preset offset, and recording the pass flag as passed;

[0143] Whether the fault bit count is less than the preset fault number indicates that the current read voltage meets the judgment standard of the TLC flash memory, that is, without offset, the judgment standard of the TLC flash memory meets the requirements, the current first offset step is set to the first preset offset, the first preset offset is -128, and a record pass flag is stored as pass.

[0144] S2347: Set the first offset step of the read level to the second preset offset, and record the pass flag as failure.

[0145] In contrast to step S2346, the current first offset step is set to the second preset offset, the second preset offset is 127, and a record passing flag is stored as failure.

[0146] S235: Taking the offset as the offset of the preset rule, performing offset reading to obtain a first actual data mask.

[0147] The second and subsequent reads require an offset to the read level. This offset can be set according to specific rules. For example, since the offset range provided by various manufacturers is -128 to 127, in units of 10mV, a binary offset can be used. The second read is the same as the first offset, with the maximum offset applied. If the offset is to the left, the offset is -128, and if it is to the right, the offset is 127. Subsequent offsets are halved or increased by half.

[0148] S236: Calculate the failure bit count of the current data read according to the first actual data mask and the expected data mask, and calculate the first offset step of the read level according to the failure bit count, the pass flag, and the number of data reads.

[0149] Specifically, step S236 may include:

[0150] S23601: Compare the first actual data mask and the expected data mask to obtain error data.

[0151] S23602: For any erroneous data, find the expected value of the position corresponding to the first actual data mask according to the position of the erroneous data in the page.

[0152] S23603: If the expected value matches the first state value, increase the fault bit count of the first state value by one.

[0153] S23604: traverse each erroneous data to obtain a failure bit count of the first state value.

[0154] Steps S23601-S23604 are the same as the above steps S2341-S2344, and finally the fault bit count of the first state value is calculated.

[0155] S23605: Determine whether the fault bit count is less than the preset fault number; if so, execute step S23606; if not, execute step S23609.

[0156] S23606: Determine whether this is the second offset and the pass flag is passed. If so, execute step S23607; if not, execute step S23608.

[0157] S23607: If it is the second shift and the pass flag is passed, the first shift step of the read level is set to the first preset shift step, and the first direction shift is ended.

[0158] The pass mark indicates the default read, which meets the judgment standard of TLC flash memory. The second offset is -128, which still meets the judgment standard of TLC flash memory, indicating that the maximum left offset value still meets the standard and cannot be offset to the left anymore. The first offset step is directly set to the first preset offset step. The first preset offset step is smaller than -128, which means that the first offset step of this read level is wide enough. For example, it can be set to 200, ending this offset calculation.

[0159] S23608: If it is not the second offset or the pass flag is failure, the first offset step of the read level is subtracted from the value of the preset rule.

[0160] The default rules are , where time is the number of reads.

[0161] S23609: If not, determine whether it is the second offset and the pass flag is failure; if so, execute step S23610; if not, execute step S23611.

[0162] S23610: If it is the second shift and the pass flag is failure, the first shift step of the read level is set to the second preset shift step, and the first direction shift is ended.

[0163] The pass mark of failure indicates the default read, which does not meet the judgment standard of TLC flash memory. The second offset is +127, which still does not meet the judgment standard of TLC flash memory. The performance of this read level is very poor. The first offset step is directly set to the second preset offset step, for example, it can be set to -200, to end this offset calculation.

[0164] S23611: If it is not the second offset or the pass flag is passed, the first offset step of the read level is added to the value of the preset rule.

[0165] The following example illustrates a common situation. In the left offset calculation, the first default reading meets the standard, and the first offset step is set to -128. The second reading at the position of -128 does not meet the standard, so the value of the preset rule needs to be added. , the first offset step is -128+64=-64, and the third reading is performed at the position of -64. If it meets the standard, the value of the preset rule needs to be subtracted, which is , the first offset step is -64-32=-96, the fourth reading is at the position of -96, which does not meet the standard, so the value of the preset rule needs to be added, which is , the first offset step is -96+16=-80, the fifth reading is at the position of -80, which meets the standard, then the value of the preset rule needs to be subtracted, which is , the first offset step is -80-8=-88, the sixth reading is at the position of -88, which does not meet the standard, so the value of the preset rule needs to be added, which is , the first offset step is -88+4=-84, the seventh reading is at the position of -84, which meets the standard, then the value of the preset rule needs to be subtracted, which is , the first offset step is -80-2=-82, the eighth reading is at the position of -82, which does not meet the standard, so the value of the preset rule needs to be added, which is , the first offset step is -82+1=-81. The calculation can be ended after the eighth calculation. That is, the preset condition in step S240 can be ended after 8 calculations. Figure 3 , it can be considered that the read level 1 is offset to the left by 81, which still meets the judgment standard of TLC flash memory, and the size of E0 can be considered to be 81.

[0166] There are also multiple ways to calculate the second offset step length. In one possible implementation, step S250 may include the following steps:

[0167] S251: Find the corresponding second state value according to the read level and the second direction offset.

[0168] See also Figure 3 If the read level is number 1 and the first direction offset is rightward, the first state value is 6.

[0169] S252: Determine whether the data reading is the first data reading; if so, execute step S253; if not, execute step S255.

[0170] S253: Taking the offset as 0, performing default reading, and obtaining a second actual data mask.

[0171] S254: Calculate the failure bit count of the current data read according to the second actual data mask and the expected data mask, and set the second offset step size and the pass flag of the read level according to the failure bit count.

[0172] Among them, the pass flag includes pass and fail. The pass flag is pass, which indicates that the fault bit count obtained by the current read meets the judgment standard of the TLC flash memory. The pass flag is fail, which indicates that the fault bit count obtained by the current read does not meet the judgment standard of the TLC flash memory.

[0173] Specifically, step S254 may include:

[0174] S2541: Compare the second actual data mask and the expected data mask to obtain error data.

[0175] S2542: For any erroneous data, find the expected value of the position corresponding to the second actual data mask according to the position of the erroneous data in the page.

[0176] S2543: If the expected value matches the second state value, the failure bit count of the second state value is increased by one.

[0177] S2544: traverse each erroneous data to obtain a failure bit count of the second state value.

[0178] S2545: Determine whether the fault bit count is less than a preset fault number. If so, execute step S2546; if not, execute step S2547.

[0179] S2546: Set the second offset step of the read level to a second preset offset, and record the pass flag as passed.

[0180] S2547: Set the second offset step of the read level to the first preset offset, and record the pass flag as failure.

[0181] S255: If the data read is not the first data read, take the offset as the offset of the preset rule, perform offset reading, and obtain a second actual data mask;

[0182] S256: Calculate the failure bit count of the current data read according to the second actual data mask and the expected data mask, and calculate the second offset step of the read level according to the failure bit count, the pass flag, and the number of data reads.

[0183] Specifically, step S256 may include:

[0184] S25601: Compare the second actual data mask and the expected data mask to obtain erroneous data.

[0185] S25602: For any erroneous data, find the expected value of the position corresponding to the second actual data mask according to the position of the erroneous data in the page.

[0186] S25603: If the expected value matches the second state value, the fault bit count of the second state value is increased by one.

[0187] S25604: traverse each error data to obtain a fault bit count of a second state value;

[0188] S25605: Determine whether the fault bit count is less than the preset fault number; if so, execute step S25606; if not, execute step S25609.

[0189] S25606: If yes, determine whether it is the second offset and the pass flag is passed; if yes, execute step S25607; if not, execute step S25608.

[0190] S25607: If it is the second shift and the pass flag is passed, the second shift step of the read level is set to the first preset shift step, and the second direction shift is ended.

[0191] S25608: If it is not the second offset or the pass flag is failure, the second offset step of the read level is added to the value of the preset rule.

[0192] S25609: If not, determine whether it is the second offset and the pass mark is failure; if so, execute step S25610; if not, execute step S25611.

[0193] S25610: If it is the second shift and the pass flag is failure, the second shift step of the read level is set to the second preset shift step, and the second direction shift is ended.

[0194] S25611: If it is not the second offset or the pass flag is passed, the second offset step of the read level is subtracted from the value of the preset rule.

[0195] The logic of steps S251-S256 is similar to that of steps S231-S236, but the specific operations are opposite. The logical principle of steps S251-S256 will not be repeated here. The following example illustrates a common situation. In the rightward offset calculation, the first default reading meets the standard, and the second offset step is set to 127. The second reading at the position of 127 does not meet the standard, so the value of the preset rule needs to be subtracted. , the second offset step is 127-64=63, and the third reading is performed at position 63. If it meets the standard, the value of the preset rule needs to be added, which is , the second offset step is 63+32=95, the fourth reading is performed at the position of 95, which does not meet the standard, and the preset rule value is subtracted , the second offset step is -95-16=79, the fifth reading is performed at the position of 79, which meets the standard, and the preset rule value is added , the second offset step is 79+8=87, the sixth reading is performed at the position of 87, which does not meet the standard, and the preset rule value is subtracted , the second offset step is 87-4=83, the seventh reading is performed at the position of 83, which meets the standard, and the preset rule value is added , the second offset step is 83+2=85, the eighth reading is performed at the position of -85, which does not meet the standard, and the preset rule value is subtracted , the second offset step is 85-1=84. The calculation ends after the eighth calculation. Refer to Figure 3 It can be considered that the reading level 1 is offset to the right by 84, which still meets the judgment standard of TLC flash memory, and it can be considered that the size of E1 is 84.

[0196] Further, the embodiment of the present application also provides a TLC flash memory reading redundancy size calculation device, referring to Figure 5 The TLC flash memory reading redundancy size calculation device 300 comprises:

[0197] A data writing unit 310 is configured to randomly generate binary data and write the binary data into a TLC flash memory. The TLC flash memory comprises a plurality of word lines, each word line comprises three pages, each page comprises a plurality of storage units, and each storage unit comprises eight states which are isolated by seven reading levels.

[0198] A prospective data calculation unit 320 is configured to calculate a prospective data mask of each page according to the binary data.

[0199] A first offset step calculation unit 330 is configured to offset each reading level in a first direction and perform data reading to obtain a first actual data mask, and calculate a first offset step of the reading level according to the first actual data mask and the prospective data mask.

[0200] A final first offset step calculation unit 340 is configured to repeatedly offset the reading level in the first direction until a first preset condition is reached, and calculate a final first offset step of the reading level.

[0201] A second offset step calculation unit 350 is configured to offset the reading level in a second direction and perform data reading to obtain a second actual data mask, and calculate a second offset step of the reading level according to the second actual data mask and the prospective data mask.

[0202] The final second offset step length calculation unit 360 is used to repeatedly perform the second direction offset on the reading level until a preset condition is met, and calculate the final second offset step length of the reading level.

[0203] The loop calculation unit 370 is configured to loop calculate the first direction offset step length and the second direction offset step length of each read level of each page of each word line.

[0204] The read redundancy size calculation unit 380 is configured to add the first direction offset step lengths and the second direction offset step lengths to calculate the read redundancy size of the TLC flash memory.

[0205] In summary, the embodiments of the present invention provide a method, device, electronic device, and storage medium for calculating the read redundancy size of TLC flash memory. These methods write known randomly generated binary data into the TLC flash memory, calculate an expected data mask, perform multiple offsets on each read level, read the binary data, and obtain an actual data mask. The actual data mask is then compared with the expected data mask, and the offset step size for each read level is statistically calculated. The offset step sizes are then added together to obtain the read redundancy size of the TLC flash memory. This allows calculation of the read redundancy size of TLC flash memory from different manufacturers, allowing for comparison of the reliability of TLC flash memory from different manufacturers.

[0206] In the embodiments provided by the present invention, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device embodiments described above are merely illustrative. For example, the flowcharts and block diagrams in the accompanying drawings show the possible architectures, functions, and operations of the devices, methods, and computer program products according to multiple embodiments of the present invention. In this regard, each box in the flowchart or block diagram can represent a module, program segment, or part of the code, which contains one or more executable instructions for implementing the specified logical functions. It should also be noted that in some alternative implementations, the functions marked in the boxes can also occur in an order different from that marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, as well as the combination of boxes in the block diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified functions or actions, or can be implemented using a combination of dedicated hardware and computer instructions.

[0207] In addition, the functional modules in the various embodiments of the present invention may be integrated together to form an independent part, or each module may exist independently, or two or more modules may be integrated to form an independent part.

[0208] If the functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the present application or the parts of the present application that essentially contribute to the prior art or the parts of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a computer readable storage medium and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the embodiments of the present application. The aforementioned storage medium includes a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and various media that can store program codes.

[0209] The above merely describes the preferred embodiments of the present application and is not intended to limit the present application. For those skilled in the art, the present application can have various modifications and changes. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

[0210] It is obvious for those skilled in the art that the present application is not limited to the details of the above exemplary embodiments, and the present application can be implemented in other specific forms without departing from the spirit or essential characteristics of the present application. Therefore, the embodiments should be regarded as exemplary and non-limiting, and the scope of the present application is defined by the appended claims rather than the above description, and all changes falling within the meaning and scope of the equivalent elements of the claims are intended to be included in the present application. Any reference signs in the claims should not be regarded as limiting the claims.

Claims

1. A method for calculating the read redundancy size of a TLC flash memory, characterized in that: The method comprises: S210: Randomly generate binary data and write the binary data into a TLC flash memory; the TLC flash memory includes a plurality of word lines, the word lines include three pages, the pages include a plurality of memory cells, the memory cells include eight states, and the eight states are isolated by seven read levels; S220: Calculating an expected data mask for each of the pages based on the binary data; S230: For each read level of each page of each word line, shift the read level in a first direction and read data to obtain a first actual data mask, and calculate a first shift step length of the read level based on the first actual data mask and the expected data mask; the first shift direction is a leftward shift; S240: Repeat the first direction shift of the reading level until a first preset condition is reached, and calculate a final first shift step length of the reading level; S250: Shifting the read level in a second direction and reading data to obtain a second actual data mask, and calculating a second shift step length of the read level according to the second actual data mask and the expected data mask; the second shift direction is a rightward shift; S260: Repeat the second direction shifting of the reading level until a preset condition is met, and calculate a final second shift step length of the reading level; S270 : looping through steps S230 to S260 to calculate a final first offset step length and a final second offset step length for each of the read levels of each of the pages of each of the word lines; S280: Add up all the final first offset step sizes and all the final second offset step sizes to calculate the read redundancy size of the TLC flash memory.

2. The method according to claim 1, characterized in that The step of performing a first direction shift on the read level and reading data to obtain a first actual data mask, and calculating a first shift step length of the read level according to the first actual data mask and the expected data mask, includes: Finding a corresponding first state value according to the read level and the first direction offset; Determining whether the data reading is the first data reading; If the data is read for the first time, the offset is set to 0, and a default read is performed to obtain a first actual data mask; calculating a fault bit count of the data currently read based on the first actual data mask and the expected data mask, and setting a first offset step size of the read level and a pass flag based on the fault bit count; the pass flag includes a pass and a fail flag, wherein the pass flag indicates that the fault bit count currently read meets a judgment criterion of the TLC flash memory, and the pass flag indicates that the fault bit count currently read does not meet the judgment criterion of the TLC flash memory; the judgment criterion of the TLC flash memory is that the fault bit count is less than a preset fault number; If the data reading is not the first data reading, taking the offset as the offset of the preset rule, performing offset reading to obtain a first actual data mask; The failure bit count of the current data read is calculated according to the first actual data mask and the expected data mask, and the first offset step of the read level is calculated according to the failure bit count, the pass flag and the number of data reads.

3. The method according to claim 2, characterized in that The step of calculating a failure bit count of the current data read according to the first actual data mask and the expected data mask, and setting a first offset step size and a pass flag of the read level according to the failure bit count, comprises: comparing the first actual data mask and the expected data mask to obtain error data; For any of the erroneous data, finding the expected value of the position corresponding to the first actual data mask according to the position of the erroneous data on the page; If the expected value matches the first state value, incrementing the fault bit count of the first state value by one; Traversing each of the erroneous data to obtain a failure bit count of the first state value; Determining whether the fault bit count is less than the preset fault number; If so, setting the first offset step of the read level to a first preset offset, and recording the pass flag as passed; If not, the first offset step of the read level is set to a second preset offset, and the pass flag is recorded as failure.

4. The method according to claim 2, characterized in that The step of calculating a failure bit count of the current data read according to the first actual data mask and the expected data mask, and calculating a first offset step of the read level according to the failure bit count, the pass flag, and the number of data reads, includes: comparing the first actual data mask and the expected data mask to obtain error data; For any of the erroneous data, finding the expected value of the position corresponding to the first actual data mask according to the position of the erroneous data on the page; If the expected value matches the first state value, incrementing the fault bit count of the first state value by one; Traversing each of the erroneous data to obtain a failure bit count of the first state value; Determining whether the fault bit count is less than the preset fault number; If so, determine whether it is the second offset and the pass flag is passed; If it is the second shift and the pass flag is passed, the first shift step of the read level is set to the first preset shift step, and the first direction shift is ended; If it is not the second offset or the pass flag is failure, add the first offset step of the read level to the value of the preset rule; If not, determine whether it is the second offset and the pass flag is failure; If it is the second shift and the pass flag is failure, the first shift step of the read level is set to the second preset shift step, and the first direction shift is ended; If it is not the second offset or the pass flag is passed, the first offset step length of the read level is subtracted from a value of a preset rule.

5. The method according to claim 1, wherein The step of performing a second direction shift on the read level and reading data to obtain a second actual data mask, and calculating a second shift step length of the read level according to the second actual data mask and the expected data mask, includes: Finding a corresponding second state value according to the read level and the second direction offset; Determining whether the data reading is the first data reading; If the data reading is the first data reading, the offset is set to 0, and a default reading is performed to obtain a second actual data mask; calculating a fault bit count of the data currently read based on the second actual data mask and the expected data mask, and setting a second offset step size of the read level and a pass flag based on the fault bit count; the pass flag includes a pass and a fail flag, wherein the pass flag indicates that the fault bit count currently read meets a judgment criterion of the TLC flash memory, and the pass flag indicates that the fault bit count currently read does not meet the judgment criterion of the TLC flash memory; the judgment criterion of the TLC flash memory is that the fault bit count is less than a preset fault number; If the data reading is not the first data reading, taking the offset as the offset of the preset rule, performing offset reading to obtain a second actual data mask; The failure bit count of the current data read is calculated according to the second actual data mask and the expected data mask, and the second offset step of the read level is calculated according to the failure bit count, the pass flag and the number of data reads.

6. The method according to claim 5, characterized in that The step of calculating a failure bit count of the current data read according to the second actual data mask and the expected data mask, and setting a second offset step size and a pass flag of the read level according to the failure bit count, comprises: comparing the second actual data mask with the expected data mask to obtain error data; For any of the erroneous data, finding the expected value of the position corresponding to the second actual data mask according to the position of the erroneous data on the page; If the expected value matches the second state value, incrementing the fault bit count of the second state value by one; Traversing each of the erroneous data to obtain a failure bit count of the second state value; Determining whether the fault bit count is less than the preset fault number; If so, setting the second offset step of the read level to a second preset offset, and recording the pass flag as passed; If not, the second offset step of the read level is set to the first preset offset, and the pass flag is recorded as failure.

7. The method according to claim 5, characterized in that The step of calculating a failure bit count of the current data read according to the second actual data mask and the expected data mask, and calculating a second offset step of the read level according to the failure bit count, the pass flag, and the number of data reads, includes: comparing the second actual data mask with the expected data mask to obtain error data; For any of the erroneous data, finding the expected value of the position corresponding to the second actual data mask according to the position of the erroneous data on the page; If the expected value matches the second state value, incrementing the fault bit count of the second state value by one; Traversing each of the erroneous data to obtain a failure bit count of the second state value; Determining whether the fault bit count is less than the preset fault number; If so, determine whether it is the second offset and the pass flag is passed; If it is the second shift and the pass flag is passed, the second shift step length of the read level is set to the first preset shift step length, and the second direction shift is ended; If it is not the second offset or the pass flag is failure, the second offset step length of the read level is added with a value of a preset rule; If not, determine whether it is the second offset and the pass flag is failure; If it is the second shift and the pass flag is failure, the second shift step length of the read level is set to the second preset shift step length, and the second direction shift is ended; If it is not the second offset or the pass flag is passed, the second offset step length of the read level is reduced by a value of a preset rule.

8. A TLC flash memory read redundancy size calculation device, characterized in that: The device comprises: a data writing unit, configured to randomly generate binary data and write the binary data into a TLC flash memory; the TLC flash memory comprising a plurality of word lines, each word line comprising three pages, each page comprising a plurality of memory cells, each memory cell comprising eight states, each of the eight states being isolated by seven read levels; an expected data calculation unit, configured to calculate an expected data mask for each of the pages based on the binary data; a first offset step length calculation unit, configured to, for each read level of each page of each word line, perform a first direction offset on the read level and read data to obtain a first actual data mask, and calculate a first offset step length of the read level based on the first actual data mask and the expected data mask; the first direction offset is a leftward offset; a final first offset step length calculation unit, configured to repeatedly perform a first direction offset on the reading level until a first preset condition is reached, and calculate a final first offset step length of the reading level; a second offset step length calculation unit, configured to perform a second direction offset on the read level and read data to obtain a second actual data mask, and calculate a second offset step length of the read level according to the second actual data mask and the expected data mask; the second direction offset is a rightward offset; a final second offset step length calculation unit, configured to repeatedly perform a second direction offset on the reading level until a preset condition is met, and calculate a final second offset step length of the reading level; a cyclic calculation unit, configured to cyclically call a first offset step calculation unit, a final first offset step calculation unit, a second offset step calculation unit, and a final second offset step calculation unit to calculate a final first offset step and a final second offset step for each read level of each page of each word line; The read redundancy size calculation unit is configured to add up all the final first offset step sizes and all the final second offset step sizes to calculate the read redundancy size of the TLC flash memory.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the computer program, the method according to any one of claims 1 to 7 is implemented.

10. A storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 1 to 7 is implemented.

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