Channel binding method, device, equipment, medium and program product

Abstract

The invention relates to the technical field of high-speed interfaces, and discloses a channel binding method, device, equipment, medium and program product.The method is applied to the receiving direction of an FPGA chip and comprises the steps that a data transmission protocol is obtained, and the number of channels is determined according to the data transmission protocol; determining a primary channel and a secondary channel based on the number of channels; when the main channel receives target data and confirms a target frame header of the target data, the main channel is controlled to send out an alignment signal; the alignment signal is transmitted to the secondary channel through the whole internet; when the secondary channel receives the alignment signal, a first-in first-out queue read pointer corresponding to the secondary channel is adjusted, so that the secondary channel is aligned with the primary channel; and after the first-in first-out queue read pointers corresponding to the secondary channels are adjusted, reading data from the first-in first-out queues corresponding to the secondary channels, and outputting the data from a data port in the receiving direction of the physical coding sub-layer. The method can meet the requirements of different protocols for the number of bound channels, and greatly improves the flexibility of channel binding.

Description

Technical Field

[0001] The present invention relates to the technical field of high-speed interfaces, and in particular to a channel binding method, device, equipment, medium and program product. Background Art

[0002] In the field of high-speed interfaces, different high-speed interface users have different Channel Bonding requirements. For example, when using the JESD204B protocol, users need to use 10-lane bonding at the PCS layer; when using the Ethernet protocol, users need to use 2-lane / 4-lane / 10-lane bonding at the PCS layer.

[0003] In traditional SOC (System on Chip) design, designers will design a fixed number of channel binding functions based on the currently used protocol. For example, when designing an Ethernet protocol PCS that uses a 4-lane binding function, designers usually only design 4-lane binding logic. In FPGA design, users often require SerDes (Serializer / Deserializer) to be highly flexible, that is, it can support different protocols and have the function of supporting binding of different numbers of channels.

[0004] Therefore, there is an urgent need for a channel binding method that can support channel binding requirements of different protocols. Summary of the invention

[0005] In view of this, the present application provides a channel binding method, apparatus, device, medium and program product, which can support the channel binding requirements of different protocols. The technical solution is as follows.

[0006] In a first aspect, the present invention provides a channel bonding method, which is applied to a receiving direction of an FPGA chip, wherein the FPGA chip includes a fully interconnected network and a physical coding sublayer, wherein the physical coding sublayer is provided with a plurality of channels, wherein the plurality of channels are isolated by a first-in-first-out queue, and wherein the plurality of channels are interconnected through the fully interconnected network, wherein the method includes:

[0007] Obtain a data transmission protocol, and confirm the number of channels according to the data transmission protocol;

[0008] Based on the number of channels, the primary channel and the secondary channel are determined;

[0009] When the primary channel receives the target data and confirms the target frame header of the target data, the primary channel is controlled to send an alignment signal; and the alignment signal is transmitted to the secondary channel through the entire Internet;

[0010] When the secondary channel receives the alignment signal, the first-in-first-out queue read pointer corresponding to the secondary channel is adjusted so that the secondary channel is aligned with the primary channel;

[0011] When the read pointers of the first-in-first-out queues corresponding to the sub-channels are adjusted, data is read from the first-in-first-out queues corresponding to the sub-channels and output from the data port in the receiving direction of the physical coding sublayer.

[0012] In an optional embodiment, the adjusting the read pointer of the first-in-first-out queue corresponding to the secondary channel includes: when the secondary channel receives the alignment signal, obtaining the data stored in the first-in-first-out queue corresponding to the secondary channel; based on the data stored in the first-in-first-out queue and the alignment signal, adjusting the read pointer of the first-in-first-out queue corresponding to the secondary channel.

[0013] In an optional implementation, aligning the secondary channel with the primary channel includes: controlling a first-in-first-out queue read pointer corresponding to the secondary channel to point to a position corresponding to the target frame header, so that output data of the secondary channel is aligned with target data of the primary channel.

[0014] In an optional implementation, the confirming of the primary channel and the secondary channel includes: determining the primary channel from the channels and determining the remaining channels as secondary channels according to a preset channel selection condition; the preset channel selection condition includes the number, performance or stability of the channel.

[0015] A channel binding method provided by the present invention has the following advantages.

[0016] The channel binding method of the present invention is applied to the receiving direction of an FPGA chip. The FPGA chip includes a fully interconnected network and a physical coding sublayer. The physical coding sublayer is provided with a plurality of channels. The plurality of channels are isolated by a first-in-first-out queue. The plurality of channels are connected to each other through the fully interconnected network. The method first obtains a data transmission protocol and confirms the number of channels according to the protocol. Then, according to the number, performance or stability of the channels, one channel is determined as a main channel from the determined channels, and the remaining channels are secondary channels. The method operates each channel independently in the receiving direction. When the transmitted data is received, the frame header of the data is confirmed, and an alignment signal is sent through the main channel. Then, the alignment signal is sent to each secondary channel through the full Internet. After the secondary channel receives the alignment signal, the first-in-first-out queue read pointer corresponding to the secondary channel is adjusted so that the secondary channel is aligned with the main channel. Specifically, the first-in-first-out queue read pointer corresponding to the secondary channel is controlled to point to the position corresponding to the target frame header so that the output data of the secondary channel is aligned with the target data of the main channel. When the first-in-first-out queue read pointers corresponding to each sub-channel are adjusted, data is read from the first-in-first-out queue corresponding to the sub-channel and output from the data port in the receiving direction of the physical coding sublayer. The channel binding method of the present invention can support the channel binding requirements of different protocols, can adapt to the number requirements of different protocols for bound channels, and greatly increases the flexibility of channel binding.

[0017] In a second aspect, the present invention provides a channel binding device, which is applied to the receiving direction of an FPGA chip, the FPGA chip includes a fully interconnected network and a physical coding sublayer, the physical coding sublayer is provided with a plurality of channels, the plurality of channels are isolated by a first-in-first-out queue, and the plurality of channels are interconnected through the fully interconnected network, the device includes:

[0018] A protocol acquisition module is used to acquire a data transmission protocol and confirm the number of channels according to the data transmission protocol;

[0019] A primary channel confirmation module, used for confirming the primary channel and the secondary channel based on the channel quantity;

[0020] An alignment signal sending module is used to control the main channel to send an alignment signal when the main channel receives the target data and confirms the target frame header of the target data; and transmit the alignment signal to the secondary channel through the entire Internet;

[0021] A channel alignment module, when the secondary channel receives the alignment signal, adjusts a first-in-first-out queue read pointer corresponding to the secondary channel so that the secondary channel is aligned with the primary channel;

[0022] The output module is used to read data from the first-in-first-out queues corresponding to each sub-channel after the read pointers of the first-in-first-out queues corresponding to each sub-channel are adjusted, and output data from the data port of the receiving direction of the physical coding sublayer.

[0023] In an optional implementation, the channel alignment module is specifically used for:

[0024] When the secondary channel receives the alignment signal, the data stored in the first-in-first-out queue corresponding to the secondary channel is obtained;

[0025] Based on the data stored in the FIFO queue and the alignment signal, the FIFO queue read pointer corresponding to the secondary channel is adjusted.

[0026] In an optional embodiment, the channel alignment module is further used for:

[0027] The first-in-first-out queue read pointer corresponding to the secondary channel is controlled to point to the position corresponding to the target frame header, so that the output data of the secondary channel is aligned with the target data of the primary channel.

[0028] In a third aspect, the present invention provides a computer device, comprising: a memory and a processor, the memory and the processor are communicatively connected to each other, computer instructions are stored in the memory, and the processor executes the channel binding method of the first aspect or any corresponding embodiment thereof by executing the computer instructions.

[0029] In a fourth aspect, the present invention provides a computer-readable storage medium having computer instructions stored thereon, the computer instructions being used to enable a computer to execute the channel binding method of the first aspect or any corresponding embodiment thereof.

[0030] In a fifth aspect, the present invention provides a computer program product, including computer instructions, which are used to enable a computer to execute the channel binding method of the first aspect or any corresponding embodiment thereof. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0032] Figure 1 is a schematic diagram of a traditional PCS 4-lane bonding solution according to an exemplary embodiment.

[0033] Figure 2It is a schematic diagram of a design of a channel binding method according to an exemplary embodiment.

[0034] Figure 3 The present invention is a flow chart of a method for channel binding according to an exemplary embodiment.

[0035] Figure 4 It is a connection diagram of a broadcast mode 8-lane binding scenario according to an exemplary embodiment.

[0036] Figure 5 It is a connection diagram of a daisy chain 8-lane binding scenario according to an exemplary embodiment.

[0037] Figure 6 is a schematic diagram of an offset tolerance according to an exemplary embodiment.

[0038] Figure 7 is a schematic diagram of multi-lane alignment according to an exemplary embodiment.

[0039] Figure 8 FIG. 1 is a schematic diagram of a single SEQ channel bonding sequence according to an exemplary embodiment.

[0040] Fig. 9 FIG. 4 is a schematic diagram of a double SEQ channel bonding sequence according to an exemplary embodiment.

[0041] Fig.10 It is a structural schematic diagram of a channel binding device provided in an embodiment of the present application.

[0042] Fig.11 It is a structural schematic diagram of a computer device provided by an optional embodiment of the present invention. DETAILED DESCRIPTION

[0043] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of this application.

[0044] It should be understood that the "indication" mentioned in the embodiments of the present application can be a direct indication, an indirect indication, or an indication of an association relationship. For example, A indicates B, which can mean that A directly indicates B, for example, B can be obtained through A; it can also mean that A indirectly indicates B, for example, A indicates C, and B can be obtained through C; it can also mean that there is an association relationship between A and B.

[0045] In the description of the embodiments of the present application, the term "corresponding" may indicate a direct or indirect correspondence between two items, or an association relationship between the two items, or a relationship between indication and being indicated, configuration and being configured, and the like.

[0046] In an embodiment of the present application, "predefinition" can be achieved by pre-saving corresponding codes, tables or other methods that can be used to indicate relevant information in a device (for example, including a terminal device and a network device). The present application does not limit its specific implementation method.

[0047] First, the terms involved in this application are introduced.

[0048] Channel Bonding: Channel bonding usually works in the Physical Coding Sublayer (PCS), but may also involve the Physical Medium Attachment (PMA) or other related layers.

[0049] 2lane, 10lane, 16lane: all refer to the number of data transmission channels, where lane is the basic unit or channel for data transmission. Each lane represents an independent data transmission path that can send and receive data at the same time, thereby increasing data throughput and network bandwidth.

[0050] FIFO: First In First Out, a first-in-first-out queue, is a data structure used to store a series of elements, and these elements are removed in the order they are added to the queue. FIFO is also often implemented as a hardware component in electronic design, especially in the field of digital circuits and embedded systems, for data buffering and temporary storage.

[0051] FIFO Read Pointer and Write Pointer: FIFO's Read Pointer and Write Pointer are the core components of FIFO. They are used to track the read and write positions of data in FIFO respectively. The Read Pointer is used to indicate the position of the data currently to be read in FIFO. When reading data from FIFO, the Read Pointer moves forward to point to the next data item to be read. The initial position of the Read Pointer is usually set to the starting address of FIFO (that is, the position of the first data item).

[0052] Chbondo / Chbondi signals: used to describe input / output (I / O) interfaces or signals related to channel bonding. In a channel bonding scenario, Chbondo / Chbondi signals allow the master transceiver to control the clock correction and channel alignment of all bonded transceivers, thereby ensuring that data can be transmitted correctly and synchronously on multiple channels.

[0053] In the field of high-speed interfaces, users have different Channel Bonding requirements for different high-speed interfaces. For example, when using the JESD204B protocol, users need to use 10-lane bonding at the PCS layer; when using the Ethernet protocol, users need to use 2-lane / 4-lane / 10-lane bonding at the PCS layer. In traditional SOC (System on Chip) design, designers will design a bonding function with a fixed number of channels based on the currently used protocol. For example, when designing an Ethernet protocol PCS that uses a 4-lane bonding function, designers usually only design 4-lane bonding logic.

[0054] Taking 4-lane bonding as an example, the traditional PCS channel bonding design scheme Figure 1 shown.

[0055] In the TX direction (transmit direction), the transmit data will be broadcast to the 4 lanes of the PCS and then sent out separately by the PMA.

[0056] In the RX direction (receiving direction), the data of each lane received by the PMA is not aligned. Data misalignment means that the data transmission on different lanes is not synchronized as expected, which may be manifested as misaligned data beats, asynchronous clocks, inconsistent reset states, physical layer problems or protocol layer problems, etc. This misalignment will affect the correct reception and analysis of data, resulting in communication failure or system instability. Therefore, FIFO isolation is required. The read pointer of the FIFO is given by the read pointer of a lane. After the data of the four lanes are aligned, they are read out from the FIFO, merged, and finally output from the PCS RX direction data port.

[0057] In FPGA design, users often require SerDes (Serializer / Deserializer) to be highly flexible, that is, to support different protocols and to support binding of different numbers of channels.

[0058] Therefore, based on the flexible configuration characteristics of FPGA technology, an embodiment of the present invention provides a channel binding method that can support channel binding requirements of different protocols. The method is applied to the receiving direction of an FPGA chip. The FPGA chip includes a fully interconnected network (PMA) and a physical coding sublayer (SWH). The physical coding sublayer is provided with a plurality of channels. The plurality of channels are isolated by a first-in-first-out queue, and the plurality of channels are interconnected through the fully interconnected network. Still taking 4-lane binding as an example, the structural diagram of the channel binding method provided in this embodiment is as follows: Figure 2 As shown, compared with the traditional channel bonding strategy, the periphery of the FPGA design is equipped with a configurable fully interconnected network (SWH) to achieve arbitrary port interconnection under timing constraints.

[0059] The channel bonding method provided in this embodiment is no different from the traditional solution in the TX direction. The TX data is broadcast to each lane in the PCS and is finally sent out by the PMA.

[0060] In the RX direction, this solution will operate each lane independently, that is, add control logic outside each FIFO so that it can independently output the chbondo signal to indicate that the channel bonding of the channel has been completed. The specific process is as follows Figure 3 As shown, the following steps are included.

[0061] S301, obtaining a data transmission protocol, and confirming the number of channels according to the data transmission protocol.

[0062] Specifically, different data transmission protocols have different numbers of channel binding requirements. Before performing channel binding, the number of channels that need to be channel bound needs to be extracted from the data transmission protocol.

[0063] S302: Based on the number of channels, confirm the primary channel and the secondary channel.

[0064] Optionally, based on the number, performance or stability of the channels, one channel may be determined as a primary channel from among the channels, and the remaining channels may be determined as secondary channels.

[0065] S303: When the primary channel receives the target data and confirms the target frame header of the target data, the primary channel is controlled to send an alignment signal; and the alignment signal is transmitted to the secondary channel through the entire Internet.

[0066] Specifically, after the main channel receives the data, it will send out a chbondo signal, which is an alignment signal, and transmit the alignment signal to each secondary channel through broadcasting based on the entire Internet.

[0067] S304: When the secondary channel receives the alignment signal, the first-in-first-out queue read pointer corresponding to the secondary channel is adjusted so that the secondary channel is aligned with the primary channel.

[0068] Specifically, each secondary channel receives a chbondo signal from the primary channel through a chbondi interface, and then aligns the secondary channel with the primary channel through a read pointer of a FIFO of each secondary channel.

[0069] S305: After the read pointers of the FIFO queues corresponding to the sub-channels are adjusted, data is read from the FIFO queues corresponding to the sub-channels, and output from the data port in the receiving direction of the physical coding sublayer.

[0070] Specifically, when all secondary channels have completed alignment with the primary channel, that is, the entire channel binding requirement is completed, data can be output from the data port in the receiving direction of the physical coding sublayer.

[0071] Optionally, in step S304, when the secondary channel receives the alignment signal, the data stored in the FIFO queue corresponding to the secondary channel is obtained; based on the data stored in the FIFO queue and the alignment signal, the read pointer of the FIFO queue corresponding to the secondary channel is adjusted.

[0072] In the above steps, the FIFO queue read pointer corresponding to the secondary channel can be controlled to point to the position corresponding to the target frame header, so that the output data of the secondary channel is aligned with the target data of the primary channel.

[0073] For example, Figure 4 A schematic diagram of an 8-lane binding network is given. Figure 4 Lane 0 of SerDes0 is the main lane. The main lane sends chbondo to notify other lanes that they need to be aligned with this lane. After other lanes receive the alignment information through chbondi, they adjust the FIFO read pointer to find the frame header of this lane and output RX data. This process can achieve the alignment of each lane.

[0074] Figure 4 In the embodiment, through the fully interconnected network, the chbondo of any master lane can be connected to the chbondi of any lane. Therefore, if the external timing does not allow a lane to broadcast the chbondo signal, this embodiment also provides a daisy chain method to help any number of lanes complete the reception of the chbondo signal. Figure 5The connection diagram of the daisy chain 8-lane bonding scenario is shown. Specifically, lane0 of SerDes0 is the first lane to send out the chbondo signal, which will be connected to the chbondi of lane1 of SerDes0. Then SerDes0lane1 will send out the chbondo signal to chnbondi of SerDes0lane2, and so on. Finally, all 8 lanes in the two SerDes can receive the channel bonding indication signal.

[0075] In addition, similar to the conventional design, the channel bonding method provided in this embodiment needs to consider factors such as the data transmission rate in actual applications, the actual physical distance between channels, and the signal propagation delay when setting the maximum offset tolerance of the channel bonding sequence to ensure that there are no data errors or synchronization problems, such as Figure 6 As shown in Figure 1, if the actual channel skew exceeds the set maximum offset tolerance, it may cause data reception errors.

[0076] Taking 16-lane binding as an example, the maximum offset tolerance of the channel binding method provided in this embodiment is ±14 symbols (one symbol is 8 bits). Since the lanes are not routed consistently through SERDES and PCS, the time it takes to reach the destination is different. The receiving end adjusts the read pointer through FIFO to receive the data uniformly. The waterline of FIFO is adjustable, so that the jitter of ±14 symbols can be offset.

[0077] The schematic diagram of multi-lane alignment is as follows Figure 7 As shown, due to different protocols, the channel bonding sequences are different. In order to be compatible with the requirements of different protocols, the channel bonding method provided in this embodiment is designed to have configurable channel bonding sequences. Figure 8 Shows a single SEQ channel bonding sequence. Fig. 9 The dual SEQ channel bonding sequence is shown, where SEQ0~N, each SEQ is 8 bits, and the sequence in 8 bits can be replaced with different sequences according to protocol requirements.

[0078] In summary, the channel binding method provided by the embodiment of the present invention is applied to the receiving direction of the FPGA chip, the FPGA chip includes a fully interconnected network, a physical coding sublayer, the physical coding sublayer is provided with a plurality of channels, the plurality of channels are isolated by a first-in-first-out queue, the plurality of channels are connected to each other through the fully interconnected network, the method first obtains the data transmission protocol and confirms the number of channels according to the protocol, and then determines a channel as the main channel from the determined channels according to the number, performance or stability of the channel, and the remaining channels are secondary channels. This method operates each channel independently in the receiving direction, and when the transmitted data is received, the frame header of the data is confirmed, and an alignment signal is sent through the main channel, and then the alignment signal is sent to each secondary channel through the full Internet. After the secondary channel receives the alignment signal, the first-in-first-out queue read pointer corresponding to the secondary channel is adjusted so that the secondary channel is aligned with the main channel. Specifically, the first-in-first-out queue read pointer corresponding to the secondary channel is controlled to point to the position corresponding to the target frame header, so that the output data of the secondary channel is aligned with the target data of the main channel. When the first-in-first-out queue read pointers corresponding to each sub-channel are adjusted, data is read from the first-in-first-out queue corresponding to the sub-channel and output from the data port in the receiving direction of the physical coding sublayer. The channel binding method of the present invention can support the channel binding requirements of different protocols, can adapt to the number requirements of different protocols for bound channels, and greatly increases the flexibility of channel binding.

[0079] In the embodiments of the present application, a channel binding device is also provided, which is used to implement the above embodiments and preferred implementation modes, and the descriptions that have been made will not be repeated. As used below, the term "module" can implement a combination of software and / or hardware for a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, the implementation of hardware, or a combination of software and hardware, is also possible and conceivable.

[0080] The embodiment of the present application provides a channel binding device, Fig.10 : is a schematic diagram of the structure of a channel binding device provided in an embodiment of the present application, the device is applied to the receiving direction of an FPGA chip, the FPGA chip includes a fully interconnected network and a physical coding sublayer, the physical coding sublayer is provided with a plurality of channels, the plurality of channels are isolated by a first-in-first-out queue, the plurality of channels are interconnected through the fully interconnected network, and the device includes:

[0081] The protocol acquisition module 1001 is used to acquire a data transmission protocol and confirm the number of channels according to the data transmission protocol;

[0082] A primary channel confirmation module 1002 is used to confirm the primary channel and the secondary channel based on the channel quantity;

[0083] The alignment signal sending module 1003 is used to control the main channel to send an alignment signal when the main channel receives the target data and confirms the target frame header of the target data; and transmit the alignment signal to the secondary channel through the entire Internet;

[0084] The channel alignment module 1004 adjusts the first-in-first-out queue read pointer corresponding to the secondary channel when the secondary channel receives the alignment signal, so that the secondary channel is aligned with the primary channel;

[0085] The output module 1005 is used to read data from the FIFO queues corresponding to the respective sub-channels after the read pointers of the FIFO queues corresponding to the respective sub-channels are adjusted, and output the data from the data port of the receiving direction of the physical coding sublayer.

[0086] In an optional implementation, the channel alignment module 1004 is specifically configured to:

[0087] When the secondary channel receives the alignment signal, the data stored in the first-in-first-out queue corresponding to the secondary channel is obtained;

[0088] Based on the data stored in the FIFO queue and the alignment signal, the FIFO queue read pointer corresponding to the secondary channel is adjusted.

[0089] In an optional implementation, the channel alignment module 1004 is further used to:

[0090] The first-in-first-out queue read pointer corresponding to the secondary channel is controlled to point to the position corresponding to the target frame header, so that the output data of the secondary channel is aligned with the target data of the primary channel.

[0091] The further functional description of each of the above modules and units is the same as that of the above corresponding embodiments and will not be repeated here.

[0092] The channel binding device in this embodiment is presented in the form of a functional unit, where the unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that executes one or more software or fixed programs, and / or other devices that can provide the above functions.

[0093] The embodiment of the present invention also provides a computer device having the above Fig.10 Channel bonding device shown.

[0094] See also Fig.11 , Fig.11 is a schematic diagram of the structure of a computer device provided by an optional embodiment of the present invention, such as Fig.11As shown, the computer device includes: one or more processors 10, a memory 20, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. Various components are connected to each other using different buses for communication, and can be installed on a common mainboard or installed in other ways as needed. The processor can process instructions executed in the computer device, including instructions stored in or on the memory to display graphic information in a graphical user interface on an external input / output device (such as a display device coupled to an interface). In some optional embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Similarly, multiple computer devices can be connected, and each device provides some necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system). Fig.11 A processor 10 is taken as an example.

[0095] The processor 10 may be a central processing unit, a network processor or a combination thereof. The processor 10 may further include a hardware chip. The hardware chip may be a dedicated integrated circuit, a programmable logic device or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general purpose array logic or any combination thereof.

[0096] The memory 20 stores instructions executable by at least one processor 10, so that the at least one processor 10 executes the method shown in the above embodiment.

[0097] The memory 20 may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function; the data storage area may store data created according to the use of the computer device, etc. In addition, the memory 20 may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some optional embodiments, the memory 20 may optionally include a memory remotely arranged relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0098] The memory 20 may include a volatile memory, such as a random access memory; the memory may also include a non-volatile memory, such as a flash memory, a hard disk or a solid state drive; the memory 20 may also include a combination of the above types of memory.

[0099] The computer device also includes an input device 30 and an output device 40. The processor 10, the memory 20, the input device 30 and the output device 40 may be connected via a bus or other means. Fig.11 The example of connecting through bus is taken in the following.

[0100] The embodiment of the present invention also provides a computer-readable storage medium. The method according to the embodiment of the present invention can be implemented in hardware, firmware, or can be implemented as a computer code that can be recorded in a storage medium, or can be implemented as a computer code that is originally stored in a remote storage medium or a non-temporary machine-readable storage medium and will be stored in a local storage medium through a network download, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only storage memory, a random access memory, a flash memory, a hard disk or a solid-state hard disk, etc.; further, the storage medium can also include a combination of the above types of memories. It can be understood that a computer, a processor, a microprocessor controller, or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by a computer, a processor, or hardware, the method shown in the above embodiment is implemented.

[0101] A part of the present invention may be applied as a computer program product, such as a computer program instruction, which, when executed by a computer, can call or provide the method and / or technical solution according to the present invention through the operation of the computer. Those skilled in the art should understand that the existence of the computer program instruction in a computer-readable medium includes, but is not limited to, a source file, an executable file, an installation package file, etc., and accordingly, the way in which the computer program instruction is executed by the computer includes, but is not limited to: the computer directly executes the instruction, or the computer compiles the instruction and then executes the corresponding compiled program, or the computer reads and executes the instruction, or the computer reads and installs the instruction and then executes the corresponding installed program. Here, the computer-readable medium may be any available computer-readable storage medium or communication medium accessible to the computer.

[0102] Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A channel binding method, characterized in that: The method is applied to a receiving direction of an FPGA chip, the FPGA chip includes a fully interconnected network and a physical coding sublayer, the physical coding sublayer is provided with a plurality of channels, the plurality of channels are isolated by a first-in-first-out queue, and the plurality of channels are interconnected through the fully interconnected network, the method includes: Obtaining a data transmission protocol, and confirming the number of channels according to the data transmission protocol; Based on the number of channels, identifying a primary channel and a secondary channel; When the primary channel receives the target data and confirms the target frame header of the target data, the primary channel is controlled to send an alignment signal; and the alignment signal is transmitted to the secondary channel through the entire Internet; When the secondary channel receives the alignment signal, the read pointer of the first-in-first-out queue corresponding to the secondary channel is adjusted so that the secondary channel is aligned with the primary channel; After the read pointers of the first-in-first-out queues corresponding to the sub-channels are adjusted, data are read from the first-in-first-out queues corresponding to the sub-channels and output from the data port of the receiving direction of the physical coding sublayer.

2. The method according to claim 1, characterized in that The adjusting the first-in-first-out queue read pointer corresponding to the secondary channel includes: When the secondary channel receives the alignment signal, the secondary channel obtains the data stored in the first-in-first-out queue corresponding to the secondary channel; Based on the data stored in the FIFO queue and the alignment signal, the FIFO queue read pointer corresponding to the secondary channel is adjusted.

3. The method according to claim 2, characterized in that The step of aligning the secondary channel with the primary channel comprises: The first-in-first-out queue read pointer corresponding to the secondary channel is controlled to point to the position corresponding to the target frame header, so that the output data of the secondary channel is aligned with the target data of the primary channel.

4. The method according to claim 3, characterized in that The confirmation of the primary channel and the secondary channel comprises: According to preset channel selection conditions, a main channel is determined from the channels, and the remaining channels are determined as secondary channels; the preset channel selection conditions include channel number, performance or stability.

5. A channel binding device, characterized in that: The device is applied to the receiving direction of the FPGA chip, the FPGA chip includes a fully interconnected network and a physical coding sublayer, the physical coding sublayer is provided with a plurality of channels, the plurality of channels are isolated by a first-in-first-out queue, the plurality of channels are interconnected through the fully interconnected network, and the device includes: A protocol acquisition module, used to acquire a data transmission protocol and confirm the number of channels according to the data transmission protocol; A primary channel confirmation module, used for confirming the primary channel and the secondary channel based on the number of channels; An alignment signal sending module is used to control the main channel to send an alignment signal when the main channel receives the target data and confirms the target frame header of the target data; and transmit the alignment signal to the secondary channel through the entire Internet; a channel alignment module, which adjusts a first-in-first-out queue read pointer corresponding to the secondary channel when the secondary channel receives the alignment signal, so that the secondary channel is aligned with the primary channel; The output module is used to read data from the first-in-first-out queues corresponding to each sub-channel after the read pointers of the first-in-first-out queues corresponding to each sub-channel are adjusted, and output data from the data port of the receiving direction of the physical coding sublayer.

6. The device according to claim 5, characterized in that The channel alignment module is specifically used for: When the secondary channel receives the alignment signal, the secondary channel obtains the data stored in the first-in-first-out queue corresponding to the secondary channel; Based on the data stored in the FIFO queue and the alignment signal, the FIFO queue read pointer corresponding to the secondary channel is adjusted.

7. The device according to claim 6, characterized in that The channel alignment module is further used for: The first-in-first-out queue read pointer corresponding to the secondary channel is controlled to point to the position corresponding to the target frame header, so that the output data of the secondary channel is aligned with the target data of the primary channel.

8. A computer device, characterized in that: include: A memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the channel binding method according to any one of claims 1 to 4 by executing the computer instructions.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a computer to execute the channel binding method according to any one of claims 1 to 4.

10. A computer program product, characterized in that The method comprises computer instructions, wherein the computer instructions are used to cause a computer to execute the channel bonding method according to any one of claims 1 to 4.

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