Bit-serial computing transmission structure for high speed data processing in chip interconnect systems

Abstract

The application discloses a bit serial computing transmission structure for high-speed data processing in a chip interconnection system, and belongs to the technical field of semiconductor integrated circuits. The structure mainly integrates two bit serial multiply-accumulate modules, a bit serial adder and a high-speed voltage mode logic VML physical interface. The VML interface mainly comprises a driver, an equalizer, a comparator, a bias current source and an RS flip-flop. The structure directly connects the computation and data transmission without passing through parallel-serial conversion or serial-parallel conversion circuits, and has the potential to reduce the delay and energy consumption. The scalable chip interconnection component can be the basis of a future modular algorithm accelerator. Different accelerator hardware structures are formed by expanding or reconfiguring the basic component, so that different algorithms are adapted, and the reconfigurability of the system is improved.

Description

TECHNICAL FIELD

[0001] The application relates to a bit-serial compute-in-transit architecture, in particular to a bit-serial compute-in-transit architecture for high-speed data processing in chip interconnection systems, and belongs to the technical field of semiconductor integrated circuits. BACKGROUND

[0002] With the growing demand for data-intensive applications such as real-time image processing, artificial intelligence, and high-performance computing, the limitations of traditional computing architectures in addressing bandwidth bottlenecks and hardware efficiency are increasingly apparent. Traditional systems often face a trade-off between computation and data transmission, where the high overhead of transmitting intermediate results between computation units severely limits overall system performance.

[0003] A promising solution is the compute-in-transit architecture, which integrates computation and data transmission functions into a unified hardware structure. This architecture has the potential to reduce latency and energy consumption by eliminating the intermediate buffering and data alignment steps typically required in traditional systems.

[0004] In this context, bit-serial processing offers unique advantages due to its simplicity, high-speed operation, and ability to handle data in a compact format. Bit-serial data formats are mainly divided into single-precision data and double-precision data. In bit-serial computation, double-precision data is usually composed of three parts: low bits, high bits, and head bits. Among them, low bits and high bits correspond to the low bits and high bits of data, respectively, while head bits are used to identify the starting position of data and control the operation of bit-serial circuits.

[0005] Therefore, a bit-serial compute-in-transit architecture for high-speed data processing is proposed, which is suitable for chip interconnection systems and integrates computation and transmission functions in a unified framework. SUMMARY

[0006] The technical problem to be solved by the application is to provide a bit-serial compute-in-transit architecture for high-speed data processing in chip interconnection systems, which directly connects bit-serial processing units to high-speed physical layers through a custom-designed voltage-mode logic (VML) interface, as shown in Figure 1 , allowing closer integration between computation and communication, thereby achieving high throughput and high transmission frequency.

[0007] To solve the above technical problems, the technical solution adopted by the application is to connect two bit-serial multiply-accumulators 2 and one bit-serial adder 8 through a high-speed serial transmission interface VML module. Figure 2 The entire structure design combines digital circuits and analog circuits to form an efficient computation and data transmission architecture. Figure 8

[0008] ​In this structure, 2 accepts input signals x1 and y1, or x2 and y2, which represent two multipliers respectively. After these input data are processed, they are output by o1_l and o1_h, or o2_l and o2_h respectively, representing the low and high bits of the multiplication and accumulation result output from 2.

[0009] Taking the multiplication of two eight-bit fixed-point numbers as an example, the head signal is output after passing through seven D flip-flops 100. This allows the output head signal to be aligned with the output data o1_l and o1_h, or o2_l and o2_h.

[0010] The two 2-structures share the clock signal and the head signal, meaning their calculations are performed synchronously, effectively improving the parallelism and efficiency of the computation process. The signals transmitted via the VML interface are synchronized through D flip-flop 101 and the clk_rx signal before being input into the 8-structure.

[0011] In the structure, 8 is responsible for receiving the calculation results of two 2 structures transmitted through the VML interface. 8 adds the results from these two 2 structures, and the final result is output through the low-order bit out_l and the high-order bit out_h. At the same time, the h signal serves as a header signal to identify the validity and alignment information of the output result.

[0012] For the calculation of 2 in eight-bit fixed-point signed number multiplication, a radix-4 Booth encoding circuit is used, as shown in the figure. Figure 3 3. Bit-series radix-4 Booth multiplier Figure 7 It consists of an adder 7 suitable for multiply-accumulate calculations and several registers 200.

[0013] The primary function of 3 is to perform multiplication operations. It can efficiently handle fixed-point multiplication and generate bit-sequential products, reducing the hardware resources required for parallel computing. In this architecture, the collaboration between 3 and 7 determines the overall computational performance of 2.

[0014] 7 is a key component in the multiply-accumulate calculation process. It receives the bit-by-bit product from 3 and adds it to the previous result, thus achieving efficient computation. In this architecture, 7 uses a serial bit-by-bit addition method, which can efficiently complete the addition operation with minimal hardware resources.

[0015] To ensure proper alignment of each bit in bit-serial computation, the 200s act as a buffer module, playing a crucial role in the process. They store and cache the result of the previous computation cycle and ensure that the new serial input is aligned with the previous result. This design is essential for bit-serial computation because it smoothly transfers the bit-serial data stream to the 7s for accumulation, avoiding data misalignment or misplacing during computation.

[0016] The VML interface design adopts a VML driver circuit 9 as shown in Figure 9 which is responsible for transmitting serial data from the transmitting end of the VML interface to the receiving end in the form of differential signals.

[0017] At the receiving end of the VML interface, the structure includes two cascaded equalizers 10 as shown in Figure 10 which are used to compensate for signal attenuation and distortion during transmission, ensuring data integrity and stability. The role of 10 is to enhance the high-frequency part of the signal, reduce signal attenuation caused by factors such as transmission line bandwidth limitations, crosstalk or noise, and thus improve data transmission quality.

[0018] 10 is then connected to a differential signal comparator 12 as shown in Figure 12 which can accurately identify the received signal and convert it into a digital signal. Due to the possibility of high-speed signal transmission being affected by noise, clock offset and other problems, 12 receives signals in differential mode, greatly improving the anti-interference ability and reliability of the signal.

[0019] Bias voltage or bias current is used to provide a stable operating point for the circuit, ensuring that the amplifier works in the appropriate area. Although bias current or voltage can be introduced externally, in order to reduce the dependence on peripheral circuits and simplify the system, the invention uses an internal current source to provide bias. As shown in Figure 11 this internal bias current source 11 not only provides a stable bias point for the circuit, but also enhances the integration and robustness of the structure. 10 and 12 both use 11 as a supporting module.

[0020] In addition, the receiving end of the VML interface is also equipped with an RS flip-flop module for signal shaping. The main role of the RS flip-flop is to shape the received signal, remove high-frequency noise and unnecessary waveform distortion, to ensure the stability and accuracy of the signal in the subsequent processing process. In this way, the RS flip-flop can effectively improve the signal processing capability of the structure, ensuring high precision in the data transmission process.

[0021] In order to accurately simulate the loss effect of the transmission line, the transmitting end 9 of the VML interface and the receiving end 10 of the VML interface are connected by a distributed model simulation differential transmission line. At high frequencies, the signal will experience a certain degree of attenuation in the transmission line, and the use of a distributed model can make a more accurate simulation of the transmission performance of the entire system.

[0022] The whole structure adopts a modular and scalable architecture, which makes the structure flexible to deal with large-scale data. In traditional computing architecture, as the amount of data increases, bandwidth bottleneck and power consumption often become the main limiting factors of the performance of the structure. The design combining bit-serial architecture and VML interface greatly reduces the bandwidth demand of the computing system. This serial transmission method can achieve higher transmission rate while maintaining low power consumption, and has great advantages in long-distance transmission. BRIEF DESCRIPTION OF DRAWINGS

[0023] Figure 1 is a schematic diagram of a bit-serial computing and transmission structure for high-speed data processing in a chip interconnection system according to the present application;

[0024] Figure 2 is a schematic diagram of a bit-serial multiplier-accumulator according to the present application;

[0025] Figure 3 is a schematic diagram of a bit-serial multiplier of a bit-serial multiplier-accumulator according to the present application;

[0026] Figure 4 is a schematic diagram of a least significant bit circuit of a bit-serial multiplier according to the present application;

[0027] Figure 5 is a schematic diagram of a middle bit circuit of a bit-serial multiplier according to the present application;

[0028] Figure 6 is a schematic diagram of a most significant bit circuit of a bit-serial multiplier according to the present application;

[0029] Figure 7 is a schematic diagram of a bit-serial adder of a bit-serial multiplier-accumulator according to the present application;

[0030] Figure 8 is a schematic diagram of a bit-serial adder according to the present application;

[0031] Figure 9 is a schematic diagram of a driver circuit of a VML interface according to the present application;

[0032] Figure 10 is a schematic diagram of an equalizer circuit of a VML interface according to the present application;

[0033] Figure 11 is a schematic diagram of a bias current source circuit of an equalizer and a differential comparator of a VML interface according to the present application;

[0034] Figure 12 is a schematic diagram of a differential signal comparator circuit of a VML interface according to the present application. DETAILED DESCRIPTION

[0035] In order to make the technical solutions adopted by the present application to achieve the predetermined technical purposes clear, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application, and the technical means or technical features in the embodiments of the present application can be replaced without creative labor. The present application will be described in detail below with reference to the drawings.

[0036] As shown in Figure 2 , the rstn signal is an asynchronous reset signal of the D flip-flop. It should be noted that 3 itself does not depend on the rstn signal reset, but is controlled by the head signal and the input data. Specifically, when the head signal is set to 1, the input data is set to zero, and the output data of 3 is reset to 0 in a serial manner. In 2, the clock signal clk of the structure controls the synchronization of all operations, ensuring that each calculation step is strictly coordinated in time sequence. The out signal represents the final bit-serial product output, which is usually accumulated by 7 after the multiplication calculation is completed to finally obtain the required calculation result of the structure. out_d is an intermediate signal that delays the output for seven clock cycles, which plays a buffering role when the adder receives and processes the bit-serial calculation result, thereby avoiding data errors caused by different time sequences.

[0037] 3 in 2 has a base-4 Booth encoding circuit. Base-4 Booth encoding is a technique for optimizing the binary multiplication process, which can effectively reduce the hardware complexity and area of the multiplier by reducing the number of partial products. Base-4 Booth encoding reduces the number of partial products by effectively grouping and encoding the input data, thereby reducing the hardware resources required for calculation. Specifically, Figure 4 、 Figure 5 and Figure 6 represent the basic components that make up 3, in which the base-4 Booth encoding circuit is divided into two parts: one is to determine whether to perform addition or subtraction operation when the Booth encoding is not zero; the other part determines whether the Booth encoding needs to perform a right shift operation, i.e. multiplying some partial products by 2, thereby reducing the complexity of multiplication calculation.

[0038] Take the multiplication of two 8-bit signed numbers as an example, 3 usually needs 8 units to implement the bit-by-bit multiplication calculation before the introduction of base-4 Booth encoding, and each unit is responsible for calculating a multiplication bit and the corresponding partial product. By introducing base-4 Booth encoding, 3 only needs four units to complete the same calculation task. This optimization not only reduces the hardware resources required for calculation, but also significantly reduces the area and power consumption of 3. With the increase of the scale of calculation, this optimization can bring significant hardware savings, and provide strong support for high-performance, low-power computing systems.

[0039] For bit-serial adders, 7 and 8 have slight differences, mainly in the control of the head bit. Since 3 outputs 8-bit data every ten cycles, there is a time difference and delay when the bit-serial output result of 7 is fed back to 7. Specifically, since 3 completes a complete multiplication operation every ten cycles, the output of 8-bit data needs to be transmitted for two clock cycles before it can be fully delivered to 7. This means that the result output by 7 will have a delay of two clock cycles before entering 7. In order to effectively handle this delay, the control head bit of 7 needs to be adjusted appropriately to ensure that 7 can correctly handle the carry and accumulation process of bit-serial data. Therefore, the head bit of 7 needs to be delayed for a total of three clock cycles before controlling the carry logic of the high and low bits of 7. Since 8 does not have a feedback operation, its head bit only needs to be delayed by one clock cycle.

[0040] As the core module of the entire VML system, 9 is mainly used to convert full-swing serial CMOS digital signals into low-voltage differential analog signals LVDS. When designing 9, not only does it need to ensure that the structure can meet the required high transmission rate, but it must also fully consider the integrity of the signal and sufficient driving ability to ensure that the data is not distorted during high-speed transmission and can operate stably in different working environments. The voltage dividing circuit is composed of resistors R1-R9 and MOS tubes M31-M46, and is controlled by digital voltages Ctrl1-Ctrl4. When Ctrl1-Ctrl4 signals are low, the corresponding resistance network path is activated and participates in the work of the voltage dividing circuit. By adjusting the state of these four control signals, up to 15 different voltage dividing circuit configurations can be achieved, providing 15 different driving signal swings to meet the requirements of different transmission environments for signal strength. In addition, the voltage dividing circuit is also used in the startup circuit of the subsequent self-bias amplifier, playing an auxiliary role.

[0041] Figure 9The self-biased differential amplifier A1 in 900 is composed of MOS transistors M10, M13, M15-M17, and forms a two-stage operational amplifier with M1. In order to reduce the capacitance value and ensure sufficient stability, the circuit uses MOS capacitor M7 as Miller compensation capacitor to improve the stability of the operational amplifier. In 900, by adjusting the voltage of the upper node of the differential drive transistor and the voltage of the node in the voltage divider circuit, the two input terminals of the self-biased amplifier are formed, thereby realizing the negative feedback mechanism, and V OH is clamped within the voltage range set by the voltage divider circuit. Figure 9 The working principle of operational amplifier A2 in 901 is similar to this.

[0042] However, in actual work, the area of M3-M6 transistors is large, the parasitic capacitance is high, and the working frequency far exceeds the bandwidth of the operational amplifier, resulting in V OH and V OL may be unstable. Therefore, in order to suppress these fluctuations, two larger MOS capacitor M47 and M48 are added to the circuit to stabilize the fluctuations of V OH and V OL . This can effectively improve the stability of the signal and prevent signal distortion caused by parasitic effects.

[0043] In addition, an enable signal V en is added to the circuit, which controls the switching of the drive circuit through the pass of transistors M9, M14, M20, M25, etc. When V en is high, M9 and M20 will be turned on, respectively pulling the lower node to high level and the upper node to low level, and then stopping the normal work of M1 and M2, thereby turning off the drive circuit.

[0044] The self-starting circuit of 900 is composed of M11-M13. When V en is low, the circuit enters normal working state, M11 remains in the open state, and M12 and M13 provide a current path to ground through diode connection to prevent the circuit from being in zero current state. This design ensures that the circuit can start smoothly, and after the operational amplifier works normally, by adjusting the width-length ratio of M12, the source voltage of M12 satisfies V gs -V th ≤0, finally making the starting circuit current zero. The starting circuit design on the 901 side is similar.

[0045] In order to ensure the accuracy of data transmission and reduce the bit error rate, signal equalization technology is usually introduced in the structure design. Figure 10The active continuous-time linear equalizer 10 shown in FIG. 1 is an important component to solve the signal attenuation and distortion. 10 is a fully differential circuit structure, whose input is connected to the source through a differential pair. The source is connected to a resistor R2 and a capacitor C2, respectively. For the signal, the resistor R2 acts as an all-pass filter, which has no significant effect on the frequency response of the signal, while the capacitor C2 provides a dedicated high-frequency signal channel. The combination of the two elements is equivalent to form a high-pass filter, which can effectively supplement the high-frequency components of the signal, thereby making up for the signal distortion caused by the attenuation of the high-frequency components in the transmission process. In this way, 10 restores the output signal to a state close to the original by compensating for the high-frequency part of the signal, ensuring the recognizability of the signal at the receiving end.

[0046] Furthermore, when the functions of the resistor and the capacitor are implemented by MOS tubes, the circuit not only can adjust the size of the resistor and the capacitor, but also can adjust the current and the gain and bandwidth of the signal by controlling the gate voltage. This adjustability enables 10 to flexibly cope with signal attenuation under different transmission conditions and adapt to various channel environments. By adjusting the V BP gate voltage, the current flowing through the M1 and M5 tubes is controlled, thereby adjusting the transconductance g m , and further controlling the gain and frequency response of the circuit. Specifically, adjusting the V BP gate voltage can change the location of the zero-pole in the circuit, thereby affecting the amplitude and phase characteristics of the signal.

[0047] Figure 11 The bias current source 11 shown in FIG. 1 is used to provide a stable operating point for the circuit, thereby ensuring that the amplifier works in the appropriate region. By selecting an appropriate number of bipolar transistors and appropriate resistance values, the target reference current can be accurately generated. The design of the reference current not only needs to meet the biasing requirements of the circuit module, but also needs to consider the temperature compensation characteristics to ensure stable performance within the operating temperature range.

[0048] For the start-up problem of 11, at the moment of system power-on, the initial current of all transistors may be zero. Since zero current is allowed to pass in the loop at this time, the entire circuit may fall into a "zero-current lock" state, also known as the degeneracy problem. Therefore, 11 introduces a self-starting circuit composed of devices such as NM3, NM4 and PM3, which forces the circuit to escape from the zero-current state. Specifically, the self-starting circuit injects a start-up current at the moment of power-on to push the main circuit into a normal working state. When the bias current is established, the self-starting circuit automatically exits the working state to avoid affecting the normal operation of the circuit. In 11, NM3 and NM4 are part of the start-up path, which provides a short current path through the control signal, while PM3 assists in forming the start-up loop. When the circuit enters a steady-state working condition, the current of the self-starting circuit will drop to zero and no longer affect the main circuit.

[0049] As Figure 12 The differential signal comparator 12 is one of the core components in the high-speed data receiving end circuit. Its main function is to process the analog differential signal received from the transmission channel and convert it into a full-swing CMOS digital signal for subsequent digital circuit processing. 12 adopts a two-stage operational amplifier structure. The first stage operational amplifier is a differential input and double-ended output amplifier responsible for amplifying the weak differential signal input. The core components of this stage are the cross-coupled MOS transistors M3 and M4, which are coupled with the input differential signal as load resistors. This cross-coupled structure effectively amplifies the difference between the two input signals. The MOS transistors M3 and M4 in the cross-coupled structure have complementary operating characteristics, which can enhance the positive and negative differences of the input signal, thereby increasing the gain and reducing the distortion of the circuit. In addition, the first stage amplifier also contains diode-connected MOS transistors M5 and M6, which form a current mirror component to form a current replicator. M5 and M6 control the current from the first stage operational amplifier output through the current mirror and transmit it to the two branches of the second stage amplifier. In this way, the output current of the first stage amplifier is evenly distributed to the second stage, ensuring that the operation of the second stage amplifier remains consistent and stable.

[0050] The second stage operational amplifier of 12 adopts a differential input and single-ended output structure, responsible for converting the amplified signal from the first stage into a single-ended output to adapt to the input requirements of the digital circuit. At this stage, the signal has been amplified enough to drive the CMOS logic circuit to work. The core components of the second stage amplifier are the two pairs of MOS transistors M8 and M10, which are affected by the differential input signal through the current mirror, and then control the swing of the output. With the change of the input signal, the current flowing through M5 and M6 will change significantly. This current difference will eventually be transmitted to M8 and M10, causing the current difference between the two MOS transistors to gradually increase. When the current difference reaches a certain level, M8 will enter the deep linear region, i.e., its operating state changes from the normal linear amplification region to the strong nonlinear region, at which time the output signal will quickly reach a full-swing digital level. This process is the decision-making process of 12, in which the input signal is successfully converted into a clear logic level.

[0051] The two MACs and one adder are directly connected through the VML physical interface without the parallel-serial conversion or serial-parallel conversion circuit in the physical layer, and the convolution calculation of two layers is realized. Meanwhile, only one MAC can be reserved to perform the signal processing task similar to the Gaussian filter, or multiple MACs can form a higher-dimensional convolution calculation unit. This scalable chip interconnection component can be the basis of a future modular algorithm accelerator, which can be expanded or reconfigured by the basic components to form different accelerator hardware structures, thereby adapting to different algorithms and improving the reconfigurability of the system.

[0052] The above is only a preferred embodiment of the present application, and does not limit the present application in any form. Although the present application has been disclosed as above with a preferred embodiment, it is not intended to limit the present application. Any person skilled in the art can make some changes or modifications to the above disclosed technical content to obtain equivalent embodiments with equivalent changes, without departing from the technical solution of the present application. Any simple modification, equivalent replacement and improvement of the above embodiments, as long as it does not depart from the technical solution of the present application, is within the protection scope of the present application.

Claims

1. A bit-serial computation transmission device for high-speed data processing in a chip interconnection system, characterized in that: at least two bit-serial multiply-accumulators, each bit-serial multiply-accumulator being configured to receive input signals and compute a product result, the input signals including low, high and sign bits, wherein each multiply-accumulator has a bit-serial multiplier with a radix-4 Booth encoding circuit, an adder suitable for multiply-accumulate computation and a plurality of registers, and the multiply-accumulator outputs a result in bit-serial format including low and high output signals; at least one bit-serial adder configured to receive the output results of the bit-serial multiply-accumulators and perform accumulation, the bit-serial adder outputs a result in low and high signals and performs accumulation in bit-serial fashion, and the computation result is output in serial fashion; a high-speed serial transmission interface for connection, the bit-serial multiply-accumulators and the bit-serial adder being connected through a custom-designed voltage-mode logic (VML) interface, wherein the VML interface includes a driver circuit configured to convert serial data from a transmitting end into a differential signal and transmit the differential signal to a receiving end, an equalizer configured in a differential structure to compensate for signal attenuation and distortion during transmission and enhance high-frequency components to ensure integrity of the signal, a differential signal comparator configured to accurately identify the received differential signal and convert it into a digital signal to ensure accuracy of high-speed data transmission, a bias current source configured to provide a stable working point for the circuit, and an RS flip-flop configured to shape the signal, remove high-frequency noise and unnecessary waveform distortion, and ensure high accuracy of data transmission. Clock signals and sign bits in the bit-serial multiply-accumulator sharing structure are synchronized to achieve synchronization of the computation process. The bit-serial adder in the bit-serial multiply-accumulator includes a sign bit control signal with appropriate delay to ensure correct alignment of the bit-serial data during accumulation. The driver circuit includes a voltage divider circuit capable of providing different signal driving strengths to adapt to different transmission environments. The equalizer adopts a differential structure, effectively enhances the high-frequency components of the signal through an all-pass filter and a high-frequency signal channel, and reduces the impact of signal attenuation.

2. The bit-serial computing fabric for high-speed data processing in a chip interconnect system of claim 1, wherein: The differential signal comparator works through a two-stage operational amplifier structure, can accurately identify and convert the received high-speed signal, and enhances the anti-interference capability of the structure.

3. The bit-serial computing fabric of claim 1, wherein: the plurality of computing nodes are configured to perform a plurality of operations on the plurality of data streams; and the plurality of computing nodes are configured to perform the plurality of operations on the plurality of data streams in parallel. Modular design is adopted, supporting different combinations of multiply-accumulators and adders, and being able to flexibly extend according to different algorithm requirements.

4. The bit-serial computing fabric of claim 1, wherein: Digital circuits and analog circuits are combined to form an efficient computation and data transmission architecture with low power consumption and high transmission rate.

5. The bit-serial computing fabric of claim 1, wherein: the plurality of computing nodes are configured to perform a plurality of operations on the plurality of data streams; and the plurality of computing nodes are configured to perform the plurality of operations on the plurality of data streams in parallel. ​ 6. The bit-serial computing fabric for high-speed data processing in a chip interconnect system of claim 1, wherein: ​ 7. The bit-serial computing fabric of claim 1, wherein: the plurality of computing nodes are configured to perform a plurality of operations on the plurality of data streams; and the plurality of computing nodes are configured to perform the plurality of operations on the plurality of data streams in parallel. ​ 8. The bit-serial computing fabric of claim 1, wherein: the plurality of processing elements are configured to perform a plurality of operations on the plurality of data streams; and the plurality of processing elements are configured to perform the plurality of operations on the plurality of data streams in parallel. ​

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