Segmented balance cost calculation method and system

Abstract

The invention relates to the technical field of circuit segmentation, and particularly discloses a segmented balance cost calculation method and system.The method comprises the steps that the arrival time of a driving node and the required time of a load node are obtained firstly, a criticality formula is established to amplify the criticality of a specific node, a graph G and a balance cost formula are established, and the criticality is calculated, sorted and stored in a queue; and creating a set Tree to execute a routing algorithm, and obtaining a final routing path through node processing and iterative optimization. By establishing the criticality formula, the criticality formula is preferentially processed in the routing, the circuit performance is guaranteed, and the balance cost formula comprehensively considers the total routing and key node cost, adapts to different scenes and balances the relation between the total routing and the key node cost. According to the method, nodes are sorted according to criticality and then are processed, key nodes are processed preferentially, generation of a routing path is accelerated, local optimum is avoided through an iterative optimization mechanism, the reliability and efficiency of a circuit are improved, the defects of a traditional method in the background technology are effectively overcome, and the segmentation cost calculation accuracy and the circuit design quality are improved.

Description

Technical Field

[0001] The present invention relates to the technical field of circuit segmentation, and in particular to a method and system for calculating a balanced cost of segmentation. Background Art

[0002] In the field of electronic design automation (EDA), circuit segmentation operations run through various processes and stages. Its purpose is to segment the overall circuit into a specified number of parts to achieve operations such as parallel synthesis of RTL-level design, use of diversified optimization strategies for different segmented parts (including area, timing, power consumption optimization, etc.), and physical location matching and evaluation of routing costs in the layout stage after synthesis. As a key indicator to measure the quality of segmentation methods, the accuracy of segmentation cost calculation has a very important impact on the entire circuit design process.

[0003] Traditional calculation methods usually use the total routing cost as the segmentation cost, that is, add up all the Net connection costs when the parts communicate signals through the Net. However, this method has significant defects. In actual circuits, the Net consists of a driving node and multiple load nodes, and each load node has different timing requirements. Among them, the critical load nodes with the minimum required time (RT) play a key role in circuit operation and need to be focused on and prioritized. However, existing methods do not take such special nodes into consideration, and only focus on the timing optimization of the overall Net, which makes it difficult to meet the specific timing requirements of individual load nodes.

[0004] Furthermore, for load nodes with different RT values, attention and processing priority should be reasonably allocated according to their importance. Load nodes with smaller RT need to be given more attention and priority, while load nodes with larger RT should be appropriately lowered in priority to free up more routing resources for key load nodes. At the same time, it is not wise to completely ignore the overall cost, because the overall cost determines the average routing cost of all load nodes, which also has an important impact on the overall circuit performance.

[0005] In summary, the existing segmentation cost calculation method cannot effectively balance the overall routing cost and the timing requirements of key load nodes, resulting in inaccurate segmentation cost evaluation, which in turn affects the target positioning of the segmentation method and the performance indicators such as the clock cycle of the final chip. Therefore, a segmentation balanced cost calculation method and system are urgently needed to solve these problems in order to improve the efficiency and quality of circuit design. Summary of the invention

[0006] The object of the present invention is to provide a method and system for calculating the balanced cost of segmentation to solve the technical problems raised in the above-mentioned background technology.

[0007] To achieve the above object, the present invention provides the following technical solutions:

[0008] A method for calculating a split balance cost, characterized by comprising:

[0009] Get the arrival time (AT) of the driver node and the required time (RT) of each load node;

[0010] Establishing a criticality calculation formula according to the arrival time (AT) and the required time (RT), and amplifying the criticality of the load node with a smaller AT requirement through the criticality calculation formula;

[0011] Construct a graph G representing the segmentation layout results and routing line constraints, establish a balance cost calculation formula based on the graph G, and calculate the segmentation balance cost Cost i of Net i by using the formula;

[0012] Input the partitioning layout result, calculate the criticality of each load node, sort them from large to small, and store them in queue q;

[0013] Create a set Tree containing driver nodes D and execute the routing algorithm Routing;

[0014] For the unprocessed node Node_Try, add it to the Tree and regenerate the MST to calculate the balanced split cost COST. If COST is less than COST_OLD, add Node_Try to the Tree and update COST_OLD to COST, otherwise do nothing.

[0015] Mark Node_Try as a processed node, repeat the above operation on Node_Try, add unprocessed nodes until the cost cannot be reduced, then pop up a node in q and add it to the Tree, repeat the above unprocessed node processing and node pop-up and addition steps until q is empty. At this time, the obtained Tree and the corresponding MST are the final routing path.

[0016] Further, the step of obtaining the arrival time (AT) of the driving node and the required time (RT) of each load node includes:

[0017] For each Net in the circuit, it consists of a driver node (D) and N load nodes (L1, L2, ..., LN), and the arrival time (AT) of the driver node obtained is determined by the previous node and is the maximum delay time of the signal emitted from the Q end of the trigger to the driver node;

[0018] The required time (RT) of each load node is obtained, which is determined by the subsequent nodes and is the minimum delay time from the D terminal of the next level trigger to the load node.

[0019] Furthermore, the criticality calculation formula is:

[0020]

[0021] Where e is a natural constant, and α and β are both configurable parameters greater than zero;

[0022] Calculate the criticality Crt of each load node i i ,The criticality of the load nodes with smaller arrival time (AT) requirements is amplified through the criticality calculation formula.

[0023] Furthermore, the steps of constructing a graph G representing the segmentation layout results and routing line constraints are:

[0024] Set the channel path between each segmented part as edge e, the total number of edges as E, and the weight W of edge e represents the cost of a signal passing through the edge, representing the degree of channel congestion;

[0025] In Figure G, the solid nodes represent Net nodes and the hollow nodes represent transit nodes.

[0026] Furthermore, the step of calculating the splitting balance cost Cost i of Net i is:

[0027] The balance cost calculation formula is:

[0028]

[0029] Where A and B are adjustable parameters greater than or equal to zero, which are used to balance the proportion of the total routing cost and the routing cost of key nodes. E is the total number of edges in the graph G. When the routing path passes through the kth edge, δ k is equal to 1, otherwise it is equal to 0. Crt i represents the criticality of the load node in the above formula, Max represents the maximum value, and Path Weight d→i Represents the total path cost from driver node d to load node i.

[0030] The present invention also discloses a split balance cost calculation system, comprising:

[0031] A first acquisition module is used to acquire the arrival time (AT) of the driving node;

[0032] The second acquisition module is used to obtain the required time (RT) of each load node;

[0033] A first establishing module is used to establish a criticality calculation formula according to the arrival time (AT) and the required time (RT), and to amplify the criticality of the load node with a smaller AT requirement through the criticality calculation formula;

[0034] The second building module is used to construct a graph G representing the segmentation layout results and routing line constraints;

[0035] A third establishing module is used to establish a balance cost calculation formula based on the graph G, and calculate the split balance cost Cost i of Neti by using the formula;

[0036] The transfer module is used to input the segmentation layout results, calculate the criticality of each load node, sort them from large to small, and store them in queue q;

[0037] Create a module to create a set Tree containing driver nodes D and execute the routing algorithm Routing;

[0038] The first processing module is used to add the unprocessed node Node_Try to the Tree and regenerate the MST to calculate the balanced segmentation cost COST. If COST is less than COST_OLD, Node_Try is added to the Tree and COST_OLD is updated to COST, otherwise no processing is performed;

[0039] The second processing module is used to mark Node_Try as a processed node, repeat the above operation on Node_Try, add unprocessed node steps until the cost cannot be reduced, then pop up a node in q to add to Tree, repeat the above unprocessed node processing and node pop-up and addition steps until q is empty. At this time, the obtained Tree and the corresponding MST are the final routing path.

[0040] Furthermore, the second establishing module includes:

[0041] A setting unit is used to set the channel path between each segmented part as edge e, the total number of edges is E, and the weight W of edge e represents the cost of a certain signal passing through the edge, representing the channel congestion degree;

[0042] Representative unit, used in graph G. Solid nodes represent Net nodes and hollow nodes represent transit nodes.

[0043] The present application also provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of the above method when executing the computer program.

[0044] The present application also provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the steps of the above method are implemented.

[0045] The beneficial effects of this application are:

[0046] The present invention has coherent steps from obtaining node time to constructing formulas and graphs, and then to node processing and routing path generation, and clarifies the operation details of each step, which is conducive to accurate implementation by technical personnel and improves repeatability and reliability. By establishing a criticality formula, the focus on key load nodes is highlighted, and the criticality of key nodes is amplified by functions, so that they are given priority in routing to ensure circuit performance. The balanced cost formula comprehensively considers the total route and the cost of key nodes, adapts to different scenarios, and balances the relationship between the two. In addition, the present invention sorts and processes nodes according to their criticality, gives priority to key nodes, accelerates routing path generation, and iterates The optimization mechanism avoids local optimality, ensures the optimal routing path, improves circuit reliability and efficiency, effectively solves the defects of traditional methods in the background technology, and improves the accuracy of segmentation cost calculation and circuit design quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1 The figure is a schematic diagram of a method flow of an embodiment of the present application.

[0048] Figure 2 FIG. 1 is a schematic diagram of criticality calculation according to an embodiment of the present application.

[0049] Figure 3 A schematic diagram of cost calculation according to an embodiment of the present application.

[0050] Figure 4 This is a schematic diagram illustrating an algorithm for a set Tree according to an embodiment of the present application.

[0051] Figure 5 A schematic diagram of a method for calculating a final routing result according to an embodiment of the present application.

[0052] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0053] It should be understood that the specific embodiments described herein are only used to explain the present invention, and are not used to limit the present invention.

[0054] like Figure 1 As shown, the present application provides a method for calculating the balanced cost of segmentation, which is characterized by comprising:

[0055] S1, obtain the arrival time (AT) of the driver node and the required time (RT) of each load node;

[0056] S2, establishing a criticality calculation formula according to the arrival time (AT) and the required time (RT), and amplifying the criticality of the load node with a smaller AT requirement through the criticality calculation formula;

[0057] S3, constructing a graph G representing the segmentation layout results and routing line constraints, establishing a balance cost calculation formula based on the graph G, and calculating the segmentation balance cost Cost i of Net i by using the formula;

[0058] S4, input the partitioning layout result, calculate the criticality of each load node, sort them from large to small, and store them in queue q;

[0059] S5, create a set Tree containing the driver node D and execute the routing algorithm Routing;

[0060] S6, for the unprocessed node Node_Try, add it to the Tree and regenerate the MST to calculate the balanced split cost COST. If COST is less than COST_OLD, add Node_Try to the Tree and update COST_OLD to COST, otherwise do nothing;

[0061] S7, mark Node_Try as a processed node, repeat the above operation on Node_Try, add unprocessed nodes until the cost cannot be reduced, then pop up a node in q and add it to Tree, repeat the above unprocessed node processing and node pop-up and addition steps until q is empty. At this time, the obtained Tree and the corresponding MST are the final routing path.

[0062] According to the above steps S1-S7, the present invention has coherent steps from obtaining node time to constructing formulas and graphs, and then to node processing and routing path generation. For example, the operation details of each step are clarified, which is conducive to accurate implementation by technical personnel and improves repeatability and reliability. By establishing a criticality formula, the focus on key load nodes is highlighted, and the criticality of key nodes is amplified by functions, so that they are given priority in routing to ensure circuit performance. The balanced cost formula comprehensively considers the total route and the cost of key nodes, adapts to different scenarios, and balances the relationship between the two. In addition, the present invention sorts and processes nodes according to their criticality, gives priority to key nodes, accelerates routing path generation, and iterates The optimization mechanism avoids local optimality, ensures the optimal routing path, improves circuit reliability and efficiency, and effectively solves the defects of traditional methods in the background technology, improves the accuracy of segmentation cost calculation and circuit design quality.

[0063] Specifically, the steps of obtaining the arrival time (AT) of the driving node and obtaining the required time (RT) of each load node include:

[0064] For each Net in the circuit, it consists of a driver node (D) and N load nodes (L1, L2, ..., LN), and the arrival time (AT) of the driver node obtained is determined by the previous node and is the maximum delay time of the signal emitted from the Q end of the trigger to the driver node;

[0065] The required time (RT) of each load node is obtained, which is determined by the subsequent nodes and is the minimum delay time from the D terminal of the next level trigger to the load node.

[0066] Specifically, the criticality calculation formula is:

[0067]

[0068] Where e is a natural constant, and α and β are both configurable parameters greater than zero;

[0069] Calculate the criticality Crt of each load node i i ,The criticality of the load nodes with smaller arrival time (AT) requirements is amplified through the criticality calculation formula.

[0070] Through the above calculation formula, it is clearly stipulated that AT is determined by the preceding node, specifically the maximum delay time from the signal emitted from the Q end of the trigger to the driving node. This definition method clarifies the source and calculation basis of AT, so that technicians can accurately obtain the parameter, and provide a reliable basis for subsequent steps such as criticality calculation. For example, in actual circuit design, technicians can accurately determine the AT of each driving node according to the specific connection of the circuit and the characteristics of the trigger, avoiding calculation errors caused by vague parameter definitions. Similarly, the present invention clearly points out that RT is determined by the subsequent node, that is, the minimum delay time from the D end of the next level trigger to the load node. This definition echoes AT, fully describes the relevant information of the node time in the circuit, and helps to comprehensively evaluate the timing characteristics of the circuit. For example, when considering the timing constraints of the circuit, the accurate acquisition of RT can help determine which load nodes have more stringent timing requirements, so as to give special attention in the subsequent criticality calculation and routing path generation.

[0071] As configurable parameters greater than zero, α and β provide guarantees for the flexibility and adaptability of the formula. Technicians can adjust the values ​​of α and β according to different circuit design requirements and actual conditions to achieve the best criticality calculation effect. For example, in circuits with high timing requirements, the value of α can be appropriately increased to make the formula more effective in amplifying the criticality of load nodes with smaller AT requirements, thereby highlighting the importance of critical nodes; and in some scenarios with high overall balance requirements, the value of β can be adjusted to balance the criticality calculation results.

[0072] Through the design of negative exponential functions, the criticality of load nodes with smaller arrival time (AT) requirements can be effectively amplified. This feature allows nodes with more urgent timing requirements in the circuit to receive more attention and optimization in subsequent processing, which is in line with the principle of giving priority to key nodes in circuit design. For example, for some key load nodes with extremely strict timing requirements, their criticality will be significantly amplified, making them more likely to be given priority in subsequent steps such as routing path generation, which helps to improve the overall performance and stability of the circuit.

[0073] To understand the above formula, please refer to Figure 2 , Assume that a Net consists of D, L1, L2, L3 in the figure, where D is the driver node, L1, L2, L3 are load nodes. The arrival time of D is AT, and the required time of L1, L2, L3 is RT1, RT2, RT3, then the criticality Crt i of load node i is defined as:

[0074]

[0075] Where e is a natural constant, α and β are configurable parameters, both greater than zero. The purpose of designing the criticality as a negative exponential function is to amplify the criticality of load nodes with smaller AT requirements, that is, the AT requirements are smaller. Load nodes with tighter timing requirements have greater criticality than nodes with loose timing requirements, so that when calculating the cost, more attention is paid to and priority is given to load nodes with tight timing.

[0076] Specifically, the steps of constructing a graph G representing the segmentation layout results and routing line constraints are:

[0077] Set the channel path between each segmented part as edge e, the total number of edges as E, and the weight W of edge e represents the cost of a signal passing through the edge, representing the degree of channel congestion;

[0078] In Figure G, the solid nodes represent Net nodes and the hollow nodes represent transit nodes.

[0079] The present invention sets the channel path between each segmented part as edge e, the total number of edges is E, and specifies that the weight W of edge e represents the cost of a signal passing through the edge, and this weight directly represents the degree of channel congestion. The definition is concise and clear, allowing technicians to quickly understand the physical meaning and role of the edge in the graph model, that is, the weight of the edge reflects the difficulty of signal transmission and the busyness of the channel. For example, in actual circuit layout analysis, the weight W can be used to intuitively see which channel paths may have congestion problems, providing an important reference for subsequent routing path planning.

[0080] In the graph G, the solid nodes represent Net nodes, and the hollow nodes represent transit nodes. This node classification and representation method clearly distinguishes different types of nodes, which helps to accurately identify and process various node information in the graph model. For example, when designing and implementing routing algorithms, different processing strategies and rules can be adopted according to the type of node (Net node or transit node), which improves the pertinence and accuracy of the algorithm.

[0081] Specifically, the steps of calculating the splitting balance cost Cost i of Net i are:

[0082] The balance cost calculation formula is:

[0083]

[0084] Where A and B are adjustable parameters greater than or equal to zero, which are used to balance the proportion of the total routing cost and the routing cost of key nodes. E is the total number of edges in the graph G. When the routing path passes through the kth edge, δ k is equal to 1, otherwise it is equal to 0. Crt i represents the criticality of the load node in the above formula, Max represents the maximum value, and Path Weight d→i Represents the total path cost from driver node d to load node i.

[0085] The above formula takes into account several key factors. Among them, The part represents the total routing cost, taking into account the weight of each edge in the graph G and the situation where the routing path passes through the edge, reflecting the overall routing cost and channel congestion; The routing cost of key nodes is highlighted in part, through the load node criticality Crt i Path Weight is the sum of the path costs from the driver node to the load node. d→i The product of takes the maximum value, ensuring the importance of key nodes in cost calculation. This comprehensive consideration makes the cost calculation more comprehensive and accurate, and can better reflect the actual situation and needs of circuit segmentation.

[0086] A and B in the formula are adjustable parameters greater than or equal to zero, which are used to balance the proportion of the total routing cost and the routing cost of key nodes. This adjustability allows the formula to adapt to different circuit design scenarios and optimization goals. For example, in some circuits with extremely high requirements for the timing of key nodes, the value of B can be appropriately increased to increase the weight of the routing cost of key nodes in the split balance cost, thereby guiding the routing algorithm to pay more attention to the optimization of key nodes; in the case of being more sensitive to the overall routing cost, the value of A can be adjusted to balance the relationship between the two, so that the cost calculation is more in line with actual needs, enhancing the flexibility and practicality of the formula.

[0087] like Figure 3 As shown in the figure, if a Net has two load nodes, assume that its driver node and load node are split and laid out and placed, as shown in the solid nodes. The hollow nodes represent the transfer nodes. Assuming that the routing path of the Net passes through the three edges indicated by the dotted lines, the calculation method of the split balance cost is as follows Figure 3 shown.

[0088] like Figure 4 and Figure 5 As shown, a simple example is used to illustrate. First, add L1 to the Tree according to the criticality. At this time, the Tree contains nodes D and L1. Generate an MST containing D and L1 in G. Then Edges contains the edge DB, B-L1, and the Cost is A x(1+1)+B x(2x(1+1)). Assume A=B=1.

[0089] Then traverse the remaining nodes {A, B, L2} in G except the nodes in the Tree, and try to add them to the Tree to determine whether the Cost can be reduced. It is found that adding no node can reduce the Cost.

[0090] Then, add the second critical load node L2 to the Tree to generate the minimum spanning tree MST. Then Edges includes the edges L1-L2, D-L2, and the Cost is (1.5+1.5)+(2x(1.5+1.5))=9. Then traverse the remaining nodes {A,B} in G and remove the nodes in the Tree, and try to add them to the Tree. It is found that adding the B node to the Tree to generate the MST, then Edges includes DB, B-L1, D-L2, and the Cost is (1+1+1.5)+(2x(1+1))=7.5. It is found that the Cost is reduced, so the B node is added to the Tree. It is precisely because of the calculation method of the balanced partition cost and the algorithm for finding the routing path designed by the scheme that the more critical nodes can obtain a faster routing path, and the total routing length is also balanced. Finally, all the nodes in the Net have completed the routing. At this time, the Edges of the MST are the final routing path of the Net, and the Cost is the final balanced partition cost.

[0091] The present invention also discloses a split balance cost calculation system, comprising:

[0092] A first acquisition module is used to acquire the arrival time (AT) of the driving node;

[0093] The second acquisition module is used to obtain the required time (RT) of each load node;

[0094] A first establishing module is used to establish a criticality calculation formula according to the arrival time (AT) and the required time (RT), and to amplify the criticality of the load node with a smaller AT requirement through the criticality calculation formula;

[0095] The second building module is used to construct a graph G representing the segmentation layout results and routing line constraints;

[0096] A third establishing module is used to establish a balance cost calculation formula based on the graph G, and calculate the split balance cost Cost i of Neti by using the formula;

[0097] The transfer module is used to input the segmentation layout results, calculate the criticality of each load node, sort them from large to small, and store them in queue q;

[0098] Create a module to create a set Tree containing driver nodes D and execute the routing algorithm Routing;

[0099] The first processing module is used to add the unprocessed node Node_Try to the Tree and regenerate the MST to calculate the balanced segmentation cost COST. If COST is less than COST_OLD, Node_Try is added to the Tree and COST_OLD is updated to COST, otherwise no processing is performed;

[0100] The second processing module is used to mark Node_Try as a processed node, repeat the above operation on Node_Try, add unprocessed node steps until the cost cannot be reduced, then pop up a node in q to add to Tree, repeat the above unprocessed node processing and node pop-up and addition steps until q is empty. At this time, the obtained Tree and the corresponding MST are the final routing path.

[0101] Furthermore, the second establishing module includes:

[0102] A setting unit is used to set the channel path between each segmented part as edge e, the total number of edges is E, and the weight W of edge e represents the cost of a certain signal passing through the edge, representing the channel congestion degree;

[0103] Representative unit, used in graph G. Solid nodes represent Net nodes and hollow nodes represent transit nodes.

[0104] The present application also provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of the above method when executing the computer program.

[0105] The present application also provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the steps of the above method are implemented.

[0106] Those of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it may include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, value library or other media provided in this application and used in the embodiments may include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (SSRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0107] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, device, article or method including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, device, article or method. In the absence of further restrictions, an element defined by the sentence "includes a ..." does not exclude the presence of other identical elements in the process, device, article or method including the element.

[0108] The above description is only a preferred embodiment of the present invention, and does not limit the patent scope of the present invention. Any equivalent results or equivalent process changes made using the contents of the present invention description and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A method for calculating the balanced cost of segmentation, characterized in that: include: Get the arrival time (AT) of the driver node and the required time (RT) of each load node; Establishing a criticality calculation formula according to the arrival time (AT) and the required time (RT), and amplifying the criticality of the load node with a smaller AT requirement through the criticality calculation formula; Construct a graph G representing the segmentation layout results and routing line constraints, establish a balance cost calculation formula based on the graph G, and calculate the segmentation balance cost Cost i of Net i by using the formula; Input the partitioning layout result, calculate the criticality of each load node, sort them from large to small, and store them in queue q; Create a set Tree containing driver nodes D and execute the routing algorithm Routing; For the unprocessed node Node_Try, add it to the Tree and regenerate the MST to calculate the balanced split cost COST. If COST is less than COST_OLD, add Node_Try to the Tree and update COST_OLD to COST, otherwise do nothing. Mark Node_Try as a processed node, repeat the above operation on Node_Try, add unprocessed nodes until the cost cannot be reduced, then pop up a node in q and add it to the Tree, repeat the above unprocessed node processing and node pop-up and addition steps until q is empty. At this time, the obtained Tree and the corresponding MST are the final routing path.

2. The method for calculating the balanced cost of segmentation according to claim 1, characterized in that: The step of obtaining the arrival time (AT) of the driving node and the required time (RT) of each load node comprises: For each Net in the circuit, it consists of a driver node (D) and N load nodes (L1, L2, ..., LN), and the arrival time (AT) of the driver node obtained is determined by the previous node and is the maximum delay time of the signal emitted from the Q end of the trigger to the driver node; The required time (RT) of each load node is obtained, which is determined by the subsequent nodes and is the minimum delay time from the D terminal of the next level trigger to the load node.

3. The method for calculating the balanced cost of segmentation according to claim 1, characterized in that: The criticality calculation formula is: Where e is a natural constant, and α and β are both configurable parameters greater than zero; Calculate the criticality Crt of each load node i i ,The criticality of the load nodes with smaller arrival time (AT) requirements is amplified through the criticality calculation formula.

4. The method for calculating the balanced cost of segmentation according to claim 3, characterized in that: The steps of constructing the graph G representing the segmentation layout results and the routing line constraints are: Set the channel path between each segmented part as edge e, the total number of edges as E, and the weight W of edge e represents the cost of a signal passing through the edge, representing the degree of channel congestion; In Figure G, the solid nodes represent Net nodes and the hollow nodes represent transit nodes.

5. The method for calculating the balanced cost of segmentation according to claim 1, characterized in that: The steps of calculating the splitting balance cost Cost i of Net i are: The balance cost calculation formula is: Where A and B are adjustable parameters greater than or equal to zero, which are used to balance the proportion of the total routing cost and the routing cost of key nodes. E is the total number of edges in the graph G. When the routing path passes through the kth edge, δ k is equal to 1, otherwise it is equal to 0. Crt i represents the criticality of the load node in the above formula, Max represents the maximum value, and Path Weigh t d→i Represents the total path cost from driver node d to load node i.

6. A split balance cost calculation system, characterized in that: include: A first acquisition module is used to acquire the arrival time (AT) of the driving node; The second acquisition module is used to obtain the required time (RT) of each load node; A first establishing module is used to establish a criticality calculation formula according to the arrival time (AT) and the required time (RT), and to amplify the criticality of the load node with a smaller AT requirement through the criticality calculation formula; The second building module is used to construct a graph G representing the segmentation layout results and routing line constraints; A third establishing module is used to establish a balance cost calculation formula based on the graph G, and calculate the split balance cost Cost i of Net i by using the formula; The transfer module is used to input the segmentation layout results, calculate the criticality of each load node, sort them from large to small, and store them in queue q; Create a module to create a set Tree containing driver nodes D and execute the routing algorithm Routing; The first processing module is used to add the unprocessed node Node_Try to the Tree and regenerate the MST to calculate the balanced segmentation cost COST. If COST is less than COST_OLD, Node_Try is added to the Tree and COST_OLD is updated to COST, otherwise no processing is performed; The second processing module is used to mark Node_Try as a processed node, repeat the above operation on Node_Try, add unprocessed node steps until the cost cannot be reduced, then pop up a node in q to add to Tree, repeat the above unprocessed node processing and node pop-up and addition steps until q is empty. At this time, the obtained Tree and the corresponding MST are the final routing path.

7. The split balance cost calculation system according to claim 6, characterized in that: The second establishing module comprises: A setting unit is used to set the channel path between each segmented part as edge e, the total number of edges is E, and the weight W of edge e represents the cost of a certain signal passing through the edge, representing the channel congestion degree; Representative unit, used in graph G. Solid nodes represent Net nodes and hollow nodes represent transit nodes.

8. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 5 are implemented.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 5 are implemented.

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