Design technology collaborative optimization method and device

Abstract

The invention discloses a design technology collaborative optimization method. The method comprises the following steps: step 1, forming a limited design rule according to a design rule; 2, forming a first graph according to the limited design rule by adopting a graph generator, wherein the first graph is a graph with the limited design rule; and 3, simulating the first graph by adopting the TCAD model to obtain a first simulation result. And 4, simulating the first graph by adopting an OPC model to obtain a second simulation result. And step 5, combining the first simulation result and the second simulation result to check the design rule and modify the design rule. And repeating the step 1 to the step 5 until the first simulation result and the second simulation result meet requirements. The invention further provides a design technology collaborative optimization device. According to the method, the limited design rule graph formed by the graph generator is applied to TCAD and OPC simulation so as to realize design technology collaborative optimization, and the optimal device electrical performance and the optimal process window of chip manufacturing can be obtained.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a design technology collaborative optimization (DTCO) method. The present invention also relates to a design technology collaborative optimization device. Background Art

[0002] According to Moore's Law, the key dimensions of advanced technology nodes are getting smaller and smaller, and design rules need to drive increasingly stringent process specifications. In this case, designers need to collaboratively optimize the design to obtain the best device electrical performance and the best process window for chip manufacturing (FAB).

[0003] Transistor step (pitch) scaling drives the evolution of chip design, and the design constraints of active transistors and interconnect layers and their impact on performance / power / area (PPA) and resistance-capacitance (RC) performance, as well as design rule checking (DRC), need to be co-optimized. Summary of the invention

[0004] The technical problem to be solved by the present invention is to provide a method for collaborative optimization of design technology, which can further optimize the electrical performance of the device and the process window of chip manufacturing. To this end, the present invention also provides a device for collaborative optimization of design technology.

[0005] In order to solve the above technical problems, the method for collaborative optimization of design technologies provided by the present invention comprises the following steps:

[0006] Step 1: forming restricted design rules according to design rules.

[0007] Step 2: forming a first pattern according to the restricted design rule and using a pattern generator, wherein the first pattern is a restricted design rule pattern.

[0008] Step three: Use the TCAD model to simulate the first graphic and obtain a first simulation result.

[0009] Step 4: Use the OPC model to simulate the first graphic and obtain a second simulation result.

[0010] Step 5: Perform a design rule check based on the first simulation result and the second simulation result and modify the design rule.

[0011] Repeat steps 1 to 5 until the first simulation result and the second simulation result meet the requirements.

[0012] A further improvement is that, in step 1, it includes: creating good graphics and bad graphics corresponding to the restricted design rules in accordance with the design rules.

[0013] A further improvement is that, in step 1, it also includes: designing a standard device unit in accordance with the design rule as the restricted design rule, and the standard device unit also matches electrical performance.

[0014] A further improvement is that the generated first graph is stored in a graph database.

[0015] A further improvement is that in step 3, the process parameters of the TCAD model include: MTT, spec; MTT represents the average value of the target line width, and spec represents the specification;

[0016] The first simulation result includes the 3D morphology of each process layer from FEOL to BEOL.

[0017] A further improvement is that, in step 4, the second simulation result includes a lithography profile diagram and a PV-band diagram, wherein the PV-band represents a process variation bandwidth.

[0018] A further improvement is that, in step 4, it also includes combining retarget and AF to form the second simulation result, where retarget means resetting the target and AF means auxiliary graphics.

[0019] In order to solve the above technical problems, the device for collaborative optimization of design technology provided by the present invention comprises:

[0020] The restricted design rule generation module is used to realize: forming restricted design rules according to design rules.

[0021] The pattern generator is used to realize: forming a first pattern according to the restricted design rule and using the pattern generator, wherein the first pattern is a restricted design rule pattern.

[0022] The TCAD simulation module is used to implement: using the TCAD model to simulate the first graphic and obtain a first simulation result.

[0023] The OPC simulation module is used to implement: using the OPC model to simulate the first graphic and obtain a second simulation result.

[0024] The design rule checking module is used to implement: performing design rule checking in combination with the first simulation result and the second simulation result and modifying the design rule.

[0025] A further improvement is that, in the restricted design rule generating module, the function of implementing further includes: creating good graphics and bad graphics corresponding to the restricted design rule in accordance with the design rule.

[0026] A further improvement is that, in the restricted design rule generating module, the implementation function further includes: designing a standard device unit in accordance with the design rule as the restricted design rule, and the standard device unit also matches the electrical performance.

[0027] A further improvement is that it also includes: a graphic database for storing the first graphic.

[0028] A further improvement is that the process parameters of the TCAD model include: MTT, spec; MTT represents the average value of the target line width, and spec represents the specification.

[0029] The first simulation result includes the 3D morphology of each process layer from FEOL to BEOL.

[0030] A further improvement is that the second simulation result includes a lithography profile diagram and a PV-band diagram, wherein the PV-band represents a process variation bandwidth.

[0031] A further improvement is that, in the OPC simulation module, it also includes combining retarget and AF to form the second simulation result, where retarget means resetting the target and AF means auxiliary graphics.

[0032] The present invention realizes the application of the restricted design rule graphics formed by the graphics generator to TCAD and OPC simulation to realize the collaborative optimization of design technology, and can obtain the best device electrical performance and the best process window for chip manufacturing. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments:

[0034] Figure 1 is a flow chart of a method for collaborative optimization of design technologies according to an embodiment of the present invention;

[0035] Figure 2 It is a schematic diagram of the structure of a device for collaborative optimization of design technology according to an embodiment of the present invention;

[0036] Figure 3 is an example layout of good graphics and bad graphics corresponding to restricted design rules in the method for collaborative optimization of design technologies in an embodiment of the present invention;

[0037] Figure 4A is a stereogram corresponding to the first simulation result in the method for collaborative optimization of design technology according to an embodiment of the present invention;

[0038] Figure 4B yes Figure 4A The corresponding two-dimensional plane image observed along the AA direction;

[0039] Figure 5Ais a PV-band diagram corresponding to the second simulation result in the method for collaborative optimization of design technology according to an embodiment of the present invention;

[0040] Figure 5B Yes Figure 5A An error marker diagram obtained by performing a design rule check on the second simulation result;

[0041] Fig. 6A It is a target layout, a PV-band map and an error marking map corresponding to the spacing process window in the method for collaborative optimization of design technology in an embodiment of the present invention;

[0042] Figure 6B It is a target layout, a PV-band map and an error marking map corresponding to the line width process window in the method for collaborative optimization of design technology in an embodiment of the present invention;

[0043] Figure 6C It is the target layout, PV-band map and error marking map corresponding to the line end process window in the method for collaborative optimization of design technology in an embodiment of the present invention. DETAILED DESCRIPTION

[0044] like Figure 1 , which is a flow chart of a method for collaborative optimization of design technologies according to an embodiment of the present invention; the method for collaborative optimization of design technologies according to an embodiment of the present invention comprises the following steps:

[0045] Step 1: forming restricted design rules according to design rules.

[0046] In the method of the embodiment of the present invention, in step 1, as Figure 3 As shown, it includes: creating good graphics 202 and bad graphics 201 corresponding to the restricted design rules according to the design rules. Figure 3 In the figure, the good graph 202 is also represented by good, and the bad graph 201 is also represented by bad.

[0047] The first step further includes: designing a standard device unit in accordance with the design rule as the restricted design rule, wherein the standard device unit also matches electrical performance.

[0048] Step 2: forming a first pattern according to the restricted design rule and using a pattern generator, wherein the first pattern is a restricted design rule pattern.

[0049] In the method of the embodiment of the present invention, the generated first graph is stored in a graph database.

[0050] Step three: Use the TCAD model to simulate the first graphic and obtain a first simulation result.

[0051] In the method of the embodiment of the present invention, in step 3, the process parameters of the TCAD model include: MTT, spec; MTT represents the average value of the target line width, and spec represents the specification;

[0052] The first simulation result includes the 3D morphology of each process layer from FEOL to BEOL.

[0053] like Figure 4A , which is a stereogram corresponding to the first simulation result in the method for collaborative optimization of design technology according to an embodiment of the present invention; Figure 4A In the corresponding example, the semiconductor substrate 301 is formed with a plurality of parallel-arranged raised strips 302 composed of the patterned semiconductor substrate 301, and shallow trench isolations 303 are formed between the raised strips 302. The raised strips 302 protruding from the top of the shallow trench isolations 303 serve as active areas for forming semiconductor devices.

[0054] The semiconductor device includes a polysilicon gate 306 , and the polysilicon gates 306 of the semiconductor devices in the same row are connected to form a strip.

[0055] An embedded epitaxial layer is also formed in the raised strips 302 on both sides of the polysilicon gate 306, and the source and drain regions are formed in the embedded epitaxial layer. For NMOS, the material of the embedded epitaxial layer is usually SiP; for PMOS, the material of the embedded epitaxial layer is usually SiGe.

[0056] Figure 4B yes Figure 4A The corresponding two-dimensional plane diagram is obtained by observing along the AA direction, and the AA direction is along the extension direction of the raised strip 302; wherein PD is composed of NMOS and refers to the pull-down tube of SRAM; PU is composed of PMOS and refers to the pull-up tube of SRAM.

[0057] Step 4: Use the OPC model to simulate the first graphic and obtain a second simulation result.

[0058] In the method of the embodiment of the present invention, in step 4, the second simulation result includes a lithography profile diagram and a PV-band diagram, where PV-band represents a process variation bandwidth.

[0059] Step 4 also includes combining retarget and AF to form the second simulation result, where retarget means resetting the target and AF means auxiliary graphics.

[0060] like Figure 5A As shown, it is a PV-band diagram corresponding to the second simulation result in the method for collaborative optimization of design technology according to an embodiment of the present invention; Figure 5AIn the figure, the image of the enlarged area at the bottom corresponds to the enlarged image in the dotted box in the upper area. It can be seen that based on the target graphic 401, the process-related PV-band graphic 402 is displayed. The PV-band graphic 402 includes an inner diameter and an outer diameter. Due to process fluctuations, the actual graphic corresponding to the PV-band graphic 402 can be located in the area between the inner diameter and the outer diameter.

[0061] Step 5: Perform a design rule check based on the first simulation result and the second simulation result and modify the design rule.

[0062] Repeat steps 1 to 5 until the first simulation result and the second simulation result meet the requirements.

[0063] like Figure 5B As shown, it is Figure 5A The error marking diagram obtained by performing a design rule check on the second simulation result of Figure 5A As shown, in the bottom enlarged area, the spacing between the outer diameters of the PV-band graphics 402 in some areas is less than or equal to minLFDspace, so an error mark 404 is set in the spacing area of ​​the target graphics 401. In this way, the second simulation result does not meet the requirements, and it is necessary to continue to repeat steps 1 to 5. Among them, minLFDspace can be provided by the restricted design rule, so that LFD represents lithography-friendly design, space represents spacing, and minLFDspace represents the minimum spacing specified by lithography-friendly design.

[0064] The embodiment of the present invention realizes the application of the restricted design rule graphics formed by the graphics generator to TCAD and OPC simulation to achieve collaborative optimization of design technology, and can obtain the best device electrical performance and the best process window for chip manufacturing.

[0065] In the method of the embodiment of the present invention, for OPC model simulation, the DRC or design rule check improved by the randomly generated RDR graph, i.e., the restricted design rule graph, can check that the process window related to the OPC simulation profile is expanded. The following is further explained by the expansion of the process window corresponding to the spacing, line width and line end:

[0066] like Fig. 6A As shown, it is the target layout, PV-band map and error marking map corresponding to the spacing process window in the method for collaborative optimization of design technology in an embodiment of the present invention; Fig. 6A In the target layout, there is a space between graphics 401a and 401b. Fig. 6A In the figure, the spacing is less than minDRCspace. MinDRCspace is provided by the design rules and indicates the minimum spacing for design rule checking. In the PV-band figure, PV-band figure 402a corresponds to figure 401a, PV-band figure 402b corresponds to figure 401b, and the spacing between the outer diameters of PV-band figures 402a and 402b is less than minLFDspace; the corresponding error mark 404a is shown in the error mark figure. Checking PV-band figure 402b can obtain the error mark 404a in the error mark figure. It can be seen that minLFDspace is less than minDRCspace, and minLFDspace has stricter requirements, which will eventually expand the process window related to the OPC simulation profile corresponding to space.

[0067] like Figure 6B As shown, it is the target layout, PV-band diagram and error marking diagram corresponding to the line width process window in the method for collaborative optimization of design technology in an embodiment of the present invention; Figure 6B In the target layout, graphic 401c is the inspection area graphic, and the width of graphic 401, that is, the target layer width, is greater than or equal to minDRCspace and less than or equal to maxDRCspace; in the PV-band diagram, PV-band graphic 402c includes an inner diameter and an outer diameter, and the inner diameter and outer diameter of PV-band graphic 402c will be measured; the error mark 404b is shown in the error mark diagram, variability ≥ maxCDvariability, variability indicates line width fluctuation, and maxCDvariability indicates the maximum line width fluctuation. This can be obtained from measuring the inner and outer diameters of the PV-band graphic 402c to determine whether variability is greater than or equal to maxCDvariability.

[0068] like Figure 6CAs shown, it is the target layout, PV-band diagram and error marking diagram corresponding to the line end process window in the method for collaborative optimization of design technology in an embodiment of the present invention. The line end (endcap) is the end graphic extending outside the graphic 401e after the intersection of the graphic 401d and the graphic 401e. In some embodiments, the graphic 401d is polysilicon (poly), and the graphic 401e is an active layer (active layer). PV-band graphics 402d and 402e correspond to graphics 401d and 401e, respectively. Figure 6c shows maxPolyWith, minLFDENDCap and minDRCEndCap; wherein maxPolyWith represents the maximum width of polysilicon, i.e., graphic 401d; minLFDENDCap represents the minimum line end length specified by the lithography-friendly design; minDRCEndCap represents the minimum line end length of the design rule check. Figure 6C The error flag 404c is set.

[0069] like Figure 2 , which is a schematic diagram of the structure of a device for collaborative optimization of design technology according to an embodiment of the present invention;

[0070] The device for collaborative optimization of design technology in an embodiment of the present invention includes:

[0071] The restricted design rule generating module 101 is used to realize: forming restricted design rules according to design rules. Figure 2 In the example, the module for forming restricted design rules according to the design rules corresponds to module 101a, namely, Restricted by Design Rule (RDR).

[0072] In the embodiment of the present invention, the restricted design rule generating module 101 further implements the function of: creating good graphics 202 and bad graphics 201 corresponding to the restricted design rule according to the design rule. Figure 2 in: Followdesign rule created good / bad pattern (on / off rule).

[0073] The restricted design rule generation module 101 also implements the function of: designing a standard device unit according to the design rule as the restricted design rule, and the standard device unit also matches the electrical performance. Figure 2 Module 101b in: Design follow Design Rule, Design Standard cell, SRAM as restricted design rule and match electrical performance.

[0074] The pattern generator is used to realize: forming a first pattern according to the restricted design rule and using the pattern generator, wherein the first pattern is a restricted design rule pattern.

[0075] In the embodiment of the present invention, it further includes: a graphics database 102 for storing the first graphics. The graphics database 102 is a Drawing Database. The first graphics correspond to: 1. Pattern generator by RDR (RestrictDR). The graphics database 102 also includes: 2. Real Design device by Auto-R&R, corresponding to the graphics of the real design device.

[0076] The TCAD simulation module 103a is used to implement: using a TCAD model to simulate the first graphic and obtain a first simulation result. Figure 2 In the example, the TCAD simulation module 103a is also represented by TCAD model.

[0077] The process parameters of the TCAD model include: MTT, spec; MTT represents the average target line width, and spec represents the specification. The first simulation result includes the 3D morphology of each process layer from FEOL to BEOL. Figure 2 Shown in: Processparameter:MTT,spec.for TCAD model created 3D profiled of FEOL to BEOL layer.

[0078] The OPC simulation module 103b is used to implement: using the OPC model to simulate the first graphic and obtain a second simulation result. Figure 2 In the example, the OPC simulation module 103b is also represented by the OPC model.

[0079] The second simulation result includes a lithography profile diagram and a PV-band diagram, where PV-band represents the process variation bandwidth. The OPC simulation module 103b also includes combining retarget and AF to form the second simulation result, where retarget represents the reset target and AF represents the auxiliary pattern. Figure 2 Shown in: Retarget, AF created for Litho-Contour&PV-bandgenerated.

[0080] The design rule checking module 104 is used to implement: performing design rule checking in combination with the first simulation result and the second simulation result and modifying the design rule. Figure 3In the embodiment, the design rule checking module 104 corresponds to: OPC, TCAD model check, risk assessment.

[0081] Figure 2 In the above description, Simulation result represents the simulation result, namely, the first simulation result and the second simulation result.

[0082] Modify DRC means modifying the design rule.

[0083] The present invention has been described in detail above through specific embodiments, but these do not constitute limitations of the present invention. Without departing from the principle of the present invention, those skilled in the art may also make many variations and improvements, which should also be considered as the protection scope of the present invention.

Claims

1. A method for collaborative optimization of design technologies, characterized in that: The steps include: Step 1: forming a restricted design rule according to the design rule; Step 2: forming a first pattern according to the restricted design rule and using a pattern generator, wherein the first pattern is a restricted design rule pattern; Step 3: Use the TCAD model to simulate the first graphic and obtain a first simulation result; Step 4: Use the OPC model to simulate the first graphic and obtain a second simulation result; Step 5: performing a design rule check based on the first simulation result and the second simulation result and modifying the design rule; Repeat steps 1 to 5 until the first simulation result and the second simulation result meet the requirements.

2. The method for collaborative optimization of design technologies according to claim 1, characterized in that: The first step includes: creating good patterns and bad patterns corresponding to the restricted design rules in accordance with the design rules.

3. The method for collaborative optimization of design technologies according to claim 2, characterized in that: The first step further includes: designing a standard device unit in accordance with the design rule as the restricted design rule, wherein the standard device unit also matches electrical performance.

4. The method for collaborative optimization of design technologies according to claim 1, characterized in that: The generated first graph is stored in a graph database.

5. The method for collaborative optimization of design technologies according to claim 1, characterized in that: In step 3, the process parameters of the TCAD model include: MTT, spec; MTT represents the average value of the target line width, and spec represents the specification; The first simulation result includes the 3D morphology of each process layer from FEOL to BEOL.

6. The method for collaborative optimization of design technologies according to claim 1, characterized in that: In step 4, the second simulation result includes a lithography profile diagram and a PV-band diagram, wherein the PV-band represents a process variation bandwidth.

7. The method for collaborative optimization of design technologies according to claim 6, characterized in that: Step 4 also includes combining retarget and AF to form the second simulation result, where retarget means resetting the target and AF means auxiliary graphics.

8. A device for collaborative optimization of design technology, characterized in that: include: The restricted design rule generation module is used to realize: forming restricted design rules according to the design rules; A pattern generator, used to implement: forming a first pattern according to the restricted design rule and using the pattern generator, wherein the first pattern is a restricted design rule pattern; A TCAD simulation module is used to implement: simulating the first graphic using a TCAD model and obtaining a first simulation result; An OPC simulation module is used to implement: simulating the first graphic using an OPC model and obtaining a second simulation result; The design rule checking module is used to implement: performing design rule checking in combination with the first simulation result and the second simulation result and modifying the design rule.

9. The device for collaborative optimization of design technology according to claim 8, characterized in that: In the restricted design rule generation module, the implementation function also includes: creating good graphics and bad graphics corresponding to the restricted design rule according to the design rule.

10. The device for collaborative optimization of design technology according to claim 9, characterized in that: In the restricted design rule generating module, the implementation function further includes: designing a standard device unit according to the design rule as the restricted design rule, and the standard device unit also matches the electrical performance.

11. The device for collaborative optimization of design technology according to claim 8, characterized in that: Also includes: A graph database is used to store the first graph.

12. The device for collaborative optimization of design technology according to claim 8, characterized in that: The process parameters of the TCAD model include: MTT, spec; MTT represents the average value of the target line width, and spec represents the specification; The first simulation result includes the 3D morphology of each process layer from FEOL to BEOL.

13. The device for collaborative optimization of design technology according to claim 8, characterized in that: The second simulation result includes a lithography profile diagram and a PV-band diagram, wherein the PV-band represents a process variation bandwidth.

14. The device for collaborative optimization of design technology according to claim 13, characterized in that: The OPC simulation module also includes combining retarget and AF to form the second simulation result, where retarget means resetting the target and AF means auxiliary graphics.

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