Semiconductor device having delay line

Abstract

The invention relates to a semiconductor device having a delay line. An example apparatus includes a first circuit configured to generate a first internal command signal in response to receiving an external command; a second circuit configured to receive the first internal command signal and a degradation control signal to generate a first mixed signal including a first internal command portion and a degradation control signal portion; a third circuit configured to delay the first mixed signal to generate a second mixed signal; and a fourth circuit coupled to the third circuit, the fourth circuit configured to: receive the second mixed signal; the degradation control signal portion starting to mask the second mixed signal at a first timing after receiving the external command; and stopping masking the degradation control signal portion of the second mixed signal at a second timing after the first internal command portion is generated.

Description

Technical Field

[0001] The present application relates generally to semiconductors, and more particularly to a semiconductor device having a delay line. Background Art

[0002] In semiconductor devices such as DRAM, when a P-channel MOS transistor remains turned on for a long time, a phenomenon called negative bias temperature instability (NBTI) occurs and causes the threshold voltage to be higher than the designed value. In order to reduce NBTI, a toggle pattern can be transmitted to the command wiring during a period when no command is generated. Summary of the invention

[0003] One aspect of the present disclosure discloses a device, comprising: a first circuit, which is configured to generate a first internal command signal in response to receiving an external command; a second circuit, which is configured to receive the first internal command signal and a degradation control signal to generate a first mixed signal including a first internal command portion and a degradation control signal portion; a third circuit, which is configured to delay the first mixed signal to generate a second mixed signal; and a fourth circuit, which is coupled to the third circuit, and the fourth circuit is configured to: receive the second mixed signal; start masking the degradation control signal portion of the second mixed signal at a first timing after receiving the external command; and stop masking the degradation control signal portion of the second mixed signal at a second timing (t4, t11) after generating the first internal command portion.

[0004] Another aspect of the present disclosure discloses a device, comprising: a first circuit configured to generate a first signal in which a first two-state trigger mode, a command mode, and a second two-state trigger mode appear in this order; a second circuit configured to mask the first signal to generate a second signal; and a third circuit configured to mask the second signal to generate a third signal, wherein the second circuit is configured to start masking the first signal at a first time before an end time of the first two-state trigger mode, and stop masking the first signal at a second time between the end time of the first two-state trigger mode and the command mode, and wherein the third circuit is configured to stop masking the second signal at a third time between the first time and the second time, and start masking the second signal at a fourth time between the command mode and the start time of the second two-state trigger mode.

[0005] Another aspect of the present disclosure discloses a device, comprising: a first circuit configured to generate a first signal including a command pattern and a plurality of virtual patterns; a second circuit configured to generate a second signal by delaying the first signal; and a third circuit configured to mask the second signal to remove the plurality of virtual patterns, thereby generating a third signal, wherein the third circuit is configured to stop masking the second signal when the command pattern included in the first signal enters an active state, and to start masking the second signal when a first time period has passed after the command pattern included in the first signal enters an inactive state. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 A block diagram showing a configuration of a semiconductor device according to an embodiment of the present disclosure;

[0007] Figure 2 is a block diagram showing the configuration of a command shifter;

[0008] Figure 3 is a schematic timing diagram for explaining a method of removing a toggle mode;

[0009] Figure 4 A block diagram showing the configuration of the delay line / command selector and masking logic;

[0010] Figure 5A and 5B is the circuit diagram of the command selector;

[0011] Fig. 6A , 7A 9A is a block diagram of a signal generating circuit for generating a masking signal;

[0012] Figure 6B , 7B 9B are timing diagrams for explaining the operation of the signal generating circuit;

[0013] Fig. 8A and 8B A circuit diagram for masking logic;

[0014] Fig. 10A is a timing diagram for explaining the operation of the command selector; and

[0015] Fig. 10B is a timing diagram for explaining the operation of the masking logic. DETAILED DESCRIPTION

[0016] Various embodiments of the present disclosure will be explained in detail below with reference to the accompanying drawings. The following detailed description refers to the accompanying drawings, with the aid of illustrations to show specific aspects and various embodiments of the present disclosure. The detailed description provides sufficient details to enable those skilled in the art to practice these embodiments of the present disclosure. Other embodiments may be utilized, and structural, logical, and electrical changes may be made without departing from the scope of the present disclosure. The various embodiments disclosed herein are not necessarily mutually exclusive, as some disclosed embodiments may be combined with one or more other disclosed embodiments to form new embodiments.

[0017] Figure 1 1 is a block diagram showing the configuration of a semiconductor device 10 according to an embodiment of the present disclosure. Figure 1 The semiconductor device 10 shown in FIG. 1 is, for example, a DRAM, and includes a memory cell array 11. When the memory cell array 11 is to be accessed, a command address signal CA is input from the outside to a command address terminal 12. The command address signal CA is supplied to an access control circuit 13. The access control circuit 13 includes a command decoder 13A. In the case where the command included in the command address signal CA indicates a read operation, the access control circuit 13 performs read access to the memory cells included in the memory cell array 11 based on the address included in the command address signal CA. The read data DQ read out from the memory cell thus accessed is output to the outside from the data I / O terminal 15 via the data control circuit 14. In the case where the command included in the command address signal CA indicates a write operation, the write data DQ input from the outside to the data I / O terminal 15 is transmitted to the memory cell array 11 via the data control circuit 14. The write data DQ transmitted to the memory cell array 11 is written to the memory cells included in the memory cell array 11 based on the address included in the command address signal CA.

[0018] In the case where the command included in the command address signal CA indicates a read operation or a write operation, the command decoder 13A included in the access control circuit 13 activates the command burst signal CB. That is, the command burst signal CB does not include information for determining whether the command included in the command address signal CA is a read command or a write command. Information for determining whether the command is a read command or a write command is indicated by a flag FG generated later than the command burst signal CB. The command burst signal CB and the flag FG are supplied to the command shifter 16. Figure 2As shown in , the command shifter 16 includes a command generation circuit 20, which generates a write command signal WR0 or a read command signal RD0 based on the command burst signal CB and the flag FG. The command shifter 16 further includes a gate circuit 21 that mixes the write command signal WR0 and the two-state trigger mode signal TGL together, and a gate circuit 22 that mixes the read command signal RD0 and the two-state trigger mode signal TGL together. In some examples, the two-state trigger mode signal TGL can be understood as a degradation control signal. In other examples, the two-state trigger mode can be understood as a virtual mode. The two-state trigger mode signal TGL is composed of Figure 1 The two-state trigger generating circuit 19 shown in generates so as to enter an active state in which a high level and a low level are repeated alternately in a case in which the command burst signal CB is in an inactive state, and so as to enter an inactive state (at a low level) in a case in which the command burst signal CB is in an active state. Therefore, the write command signal WR1 output from the command shifter 16 becomes a signal containing not only the write command signal WR0 activated to be at a high level but also the two-state trigger mode signal TGL that alternately repeats a high level and a low level at other timings. The read command signal RD1 output from the command shifter 16 becomes a signal containing not only the read command signal RD0 activated to be at a high level but also the two-state trigger mode signal TGL that alternately repeats a high level and a low level at other timings. Due to the contribution of the two-state trigger mode signal TGL, the NBTI in the P-channel MOS transistor included in the transmission path of the internal command signal can be reduced. A predetermined delay time D0 (see Fig. 10A ) at a timing after , the toggle generating circuit 19 enters the active state again. The delay time D0 has a sufficient duration to prevent the active state of the toggle mode signal TGL from interfering with the write command signal WR0 or the read command signal RD0.

[0019] The write command signal WR1 and the read command signal RD1 are supplied to the delay line / command selector 17. The delay line / command selector 17 provides a predetermined delay necessary for performing write control and performing read control to the write command signal WR1 and the read command signal RD1, thereby generating a write command signal WR2 and a read command signal RD2, respectively. These two signals contain the toggle mode signal TGL, and thus the NBTI in the delay line / command selector 17 is reduced. Subsequently, the write command signal WR2 and the read command signal RD2 are supplied to the masking logic 18. The masking logic 18 partially masks the write command signal WR2 and the read command signal RD2 to generate a write command signal WR3 and a read command signal RD3 from which the toggle mode signal TGL has been removed. This removal is performed because if the toggle mode signal TGL in the active state is input to the control circuit as it is, a functional malfunction will result. The write command signal WR3 and the read command signal RD3 are supplied to the data control circuit 14. The data control circuit 14 acquires write data DQ in synchronization with the write command signal WR3 or changes the terminator resistance value of the data I / O terminal 15 in synchronization with the write command signal WR3. In a read operation, the data control circuit 14 outputs read data DQ in synchronization with the read command signal RD3.

[0020] Figure 3 is a schematic timing diagram for explaining a method of removing the toggle mode signal TGL.

[0021] exist Figure 3 In the example shown in , the toggle mode signal TGL exists on the command path for transmitting the write command signal WR1 before time t3 and after time t6. There is a pulse of the write command signal WR1 caused by the command burst signal CB between time t3 and time t6. In the present embodiment, the toggle mode signal TGL existing before and after the pulse of the write command signal WR1 caused by the command burst signal CB is removed by a two-step masking operation. The first step is a masking operation using a masking signal MASK1, and is performed in the delay line / command selector 17. The second step is a masking operation using a masking signal MASK2, and is performed in the masking logic 18.

[0022] The masking signal MASK1 performs a masking operation during a time period from time t1 earlier than time t3 to time t4 later than time t3. During another time period, the transmitted signal passes through. Therefore, the toggle mode signal TGL during the time period from time t1 to time t3 is removed. The masking signal MASK2 performs a pass-through operation during a time period from time t2 between time t1 and time t4 to time t5 earlier than time t6. During another time period, the transmitted signal is masked. Therefore, the toggle mode signal TGL during the time period before time t2 and the time period after time t5 is removed. Therefore, as in Figure 3 As shown by MASK1+MASK2, the toggle mode signal TGL during the time period before time t4 and during the time period after time t5 is removed, and only the transmitted signal appearing during the time period from time t4 to time t5 passes. Therefore, the write command signal WR3 in which the toggle mode signal TGL has been removed is output from the mask logic 18. Here, since the masking operation at the first step is performed in the time period from time t1 to time t4, a sufficient margin is ensured with respect to the time t2 at which the masking operation at the second step is released. Therefore, time t2 may be earlier than time t3 or later than time t3.

[0023] A more specific configuration and operation of the semiconductor device 10 are described in detail below.

[0024] Figure 4 FIG. 1 is a block diagram showing the configuration of the delay line / command selector 17 and the masking logic 18. Figure 4 As shown in , the delay line / command selector 17 includes a gate circuit 23 that mixes the write command signal WR1 and the read command signal RD1 together to generate a mixed command signal MIX1 and a delay line 24 that delays the mixed command signal MIX1 to generate a mixed command signal MIX2. The use of the delay line 24 shared by the write command signal WR1 and the read command signal RD1 can reduce the circuit scale. The mixed command signal MIX2 is commonly supplied to the command selectors 30 and 40. If the mixed command signal MIX2 is caused by the write command signal WR1, the command selector 30 generates the write command signal WR2. If the mixed command signal MIX2 is caused by the read command signal RD1, the command selector 40 generates the read command signal RD2. That is, the write command signal WR1 and the read command signal RD1 that have been mixed together are separated into the write command signal WR2 and the read command signal RD2 by the command selectors 30 and 40. The command selectors 30 and 40 also perform Figure 3The masking operation at the first step shown in FIG. The write command signal WR2 and the read command signal RD2 are supplied to the masking logics 50 and 60, respectively. The masking logic 50 removes the toggle mode signal TGL included in the write command signal WR2 to generate the write command signal WR3. The masking logic 60 removes the toggle mode signal TGL included in the read command signal RD2 to generate the read command signal RD3. The masking logics 50 and 60 perform Figure 3 Since the delay amount of the delay line 24 is variable, the masking operation at the first step and the masking operation at the second step are performed using the command used as a starting point in the present embodiment.

[0025] Figure 5A FIG. 4 is a circuit diagram of the command selector 30. Figure 5A As shown in , the command selector 30 includes a gate circuit 35, which is configured to receive a command burst signal CB and a read command signal RD1. The command selector further includes a flip-flop circuit 31, which is set in response to an active output signal received from the gate circuit 35, for example, when the command burst signal CB or the read command signal RD1 is active. The flip-flop circuit 31 is reset in response to the write command signal WR1. The command selector further includes a latch circuit 33 that is reset in response to the inverted signal CBF of the command burst signal CB and is set in response to the mixed command signal MIX2, and gate circuits 32 and 34. The write selection signal WRSEL output from the flip-flop circuit 31 becomes at a high level in response to the command burst signal CB, and then changes to a low level in response to the write command signal WR1. Thereafter, when the next command burst signal CB is activated, the write selection signal WRSEL returns to a high level again. The write selection signal WRSEL is supplied to one of the input nodes of the gate circuit 32. The mask signal MASK1WRP is supplied to the other input node of the gate circuit 32.

[0026] Fig. 6A FIG. 7 is a block diagram of a signal generating circuit 71 for generating a mask signal MASK1WRP. Figure 6B 71 is a timing chart for explaining the operation of the signal generating circuit 71. Fig. 6A As shown in FIG. 1 , the signal generating circuit 71 generates a mask signal MASK1WRP based on the command burst signal CB and the write selection signal WRSEL. Figure 6B As shown in , the mask signal MASK1WRP changes to be at a high level in response to activation of the command burst signal CB. Subsequently, the mask signal MASK1WRP changes to be at a low level at a timing when a predetermined delay time D1 has passed after the change of the write selection signal WRSEL from the high level to the low level.

[0027] The gate circuit 32 is a NAND circuit, and in the case where both the write selection signal WRSEL and the mask signal MASK1WRP are at a high level, the mask signal MASK1WRPF is placed at a low level. The mask signal MASK1WRPF is supplied to the data input node of the latch circuit 33. Therefore, the mask signal MASK1WR output from the latch circuit 33 has substantially the same waveform as the mask signal MASK1WRPF. The mixed command signal MIX2 is input to the latch node (Lat) of the latch circuit 33. Due to this input, the change of the mask signal MASK1WR in the case where the command pulse caused by the command burst signal CB appears in the mixed command signal MIX2 is prevented. The mask signal MASK1WR is supplied to one of the input nodes of the gate circuit 34. The mixed command signal MIX2 is supplied to the other input node of the gate circuit 34. The gate circuit 34 is an AND circuit, and in the case where the mask signal MASK1WR is at a high level, the mixed command signal MIX2 is allowed to pass therethrough to output the mixed command signal as the write command signal WR2. In the case where the mask signal MASK1WR is at a low level, a signal obtained by masking the mix command signal MIX2 is output as a write command signal WR2.

[0028] Figure 5B FIG. 4 is a circuit diagram of the command selector 40. Figure 5B As shown in FIG. 1 , the command selector 40 has Figure 5A The circuit configuration of the command selector 30 shown in FIG. 4 is the same as the circuit configuration of the command selector 30 shown in FIG. The read command signal RD1 is supplied to the flip-flop circuit 41, and the read selection signal RDSEL is generated in response to the read command signal. The gate circuit 45 is configured to receive the command burst signal CB, and the write command signal WR1 is configured to provide an output signal to the flip-flop circuit 41. The flip-flop circuit 41 is set in response to the active output signal received from the gate circuit 45, for example, when the command burst signal CB or the write command signal WR1 is active. The flip-flop circuit 41 is reset in response to the read command signal RD1. The read selection signal RDSEL is supplied to one of the input nodes of the gate circuit 42. The mask signal MASK1RDP is supplied to the other input node of the gate circuit 42.

[0029] Fig. 7A FIG. 7 is a block diagram of a signal generating circuit 72 for generating a mask signal MASK1RDP. Figure 7B 2 is a timing diagram for explaining the operation of the signal generating circuit 72. Fig. 7A As shown in FIG. 1 , the signal generating circuit 72 generates a mask signal MASK1RDP based on the command burst signal CB and the read selection signal RDSEL. Figure 7BAs shown in , the mask signal MASK1RDP changes to be at a high level in response to activation of the command burst signal CB. Subsequently, the mask signal MASK1RDP changes to be at a low level at a timing when a predetermined delay time D1 has passed after the change of the read selection signal RDSEL from the high level to the low level.

[0030] The gate circuit 42 is a NAND circuit, and in the case where both the read selection signal RDSEL and the mask signal MASK1RDP are at a high level, the mask signal MASK1RDPF is placed at a low level. The mask signal MASK1RDPF is supplied to the data input node of the latch circuit 43. Therefore, the mask signal MASK1RD output from the latch circuit 43 has substantially the same waveform as the mask signal MASK1RDPF. The mask signal MASK1RD is supplied to one of the input nodes of the gate circuit 44. The mixed command signal MIX2 is supplied to the other input node of the gate circuit 44. The gate circuit 44 is an AND circuit, and in the case where the mask signal MASK1RD is at a high level, the mixed command signal MIX2 is allowed to pass therethrough to output the mixed command signal as the read command signal RD2. In the case where the mask signal MASK1RD is at a low level, a signal obtained by masking the mixed command signal MIX2 is output as the read command signal RD2.

[0031] Fig. 8A is a circuit diagram of the masking logic 50 . Figure 8B FIG. 4 is a circuit diagram of the masking logic 60. Fig. 8A and 8B As shown in FIG. 1 , mask logics 50 and 60 are each configured by an AND gate circuit. Mask logic 50 generates a write command signal WR3 based on a write command signal WR2 and a mask signal MASK2. Mask logic 60 generates a read command signal RD3 based on a read command signal RD2 and a mask signal MASK2.

[0032] Fig.9A FIG. 7 is a block diagram of a signal generating circuit 73 for generating a mask signal MASK2. Fig. 9B 73 is a timing chart for explaining the operation of the signal generating circuit 73. Fig.9A As shown in FIG. 1 , the signal generating circuit 73 generates the mask signal MASK2 based on the command burst signal CB and the mixed command signal MIX1. Fig. 9B As shown in , the mask signal MASK2 changes to a high level at a timing when a predetermined delay time D2 has passed after activation of the command burst signal CB. Subsequently, the mask signal MASK2 changes to a low level at a timing when a predetermined delay time D3 has passed after the change of the mix command signal MIX1 from a high level to a low level.

[0033] Fig. 10A is a timing chart for explaining the operation of the command selector 30.

[0034] exist Fig. 10A In the example shown in , the command burst signal CB caused by the write command is activated at time t10. During the time period before time t10, the two-state trigger mode signal TGL appears on the transmission path of the write command signal WR1. Therefore, the NBTI of the P-channel MOS transistor included in the transmission path of the write command signal WR1 is reduced. When the command burst signal CB is activated at time t10, the two-state trigger generation circuit 19 immediately interrupts the generation of the two-state trigger mode signal TGL. In addition, the write selection signal WRSEL output from the trigger 31 remains at a high level. In addition, the mask signal MASK1WRP output from the signal generation circuit 71 changes to be at a high level. In response to this change, the mask signals MASK1WRPF and MASK1WR change to be at a low level. During the time period when the mask signal MASK1WR is at a low level, the mixed command signal MIX2 is masked by the gate circuit 34. Therefore, during the time period when the mask signal MASK1WR is at a low level, the write command signal WR2 output from the command selector 30 is fixed at a low level.

[0035] When the original command caused by the command burst signal CB appears on the transmission path of the write command signal WR1 at time t11, the write selection signal WRSEL output from the flip-flop circuit 31 changes to be at a low level. In response to this change, the mask signals MASK1WRPF and MASK1WR change to be at a high level. During the period in which the mask signal MASK1WR is at a high level, the mix command signal MIX2 passes through the gate circuit 34. The period from time t10 to time t11 is a period in which the write command signal WR1 is masked by the command selector 30, and corresponds to Figure 3 . When the predetermined delay time D1 elapses after the change of the write select signal WRSEL from the high level to the low level (at time t11), the mask signal MASK1WRP changes to be at the low level. Therefore, the mix command signal MIX2 passes through the gate circuit 34 during the time period other than the time period from time t10 to time t11. Subsequently, at the timing when the predetermined delay time D0 has elapsed after the deactivation of the write command signal WR1, the toggle mode signal TGL is generated again. The delay time D0 is sufficiently longer than the delay time D3.

[0036] Through the operation described above, the command selector 30 removes the toggle mode signal TGL during the period immediately before the original write command signal WR1 caused by the command burst signal CB. Fig. 10AIn the example shown in , the command burst signal CB caused by the read command is activated at time t13. In response to this activation, the write selection signal WRSEL and the mask signal MASK1WRP change to be at a high level, and the mask signals MASK1WRPF and MASK1WR change to be at a low level.

[0037] The command selector 40 also performs the same operation as the command selector 30 described above, except that the read command signal RD1 is used instead of the write command signal WR1 and the mask signal MASK1RDP is used instead of the mask signal MASK1WRP.

[0038] Fig. 10B is a timing diagram for explaining the operation of the masking logic 50.

[0039] exist Fig. 10B In the example shown in FIG. 1 , the command burst signal CB caused by the write command is activated at time t20. In response to this activation, the toggle mode signal TGL is removed from the mix command signal MIX1 and the write command signal WR2, as shown in FIG. Fig. 10A As described with reference. When a predetermined delay time D2 elapses after activation of the command burst signal CB (at time t21), the mask signal MASK2 changes to be at a high level. During the period in which the mask signal MASK2 is at a high level, the write command signal WR2 passes through the mask logic 50. When a predetermined delay time D3 elapses after the change of the mix command signal MIX1 from a high level to a low level at time t22 (at time t23), the mask signal MASK2 changes to be at a low level. The period from time t21 to time t23 is the period in which the write command signal WR1 passes through the mask logic 50, and corresponds to Figure 3 During the time period other than the time period from time t21 to time t23, the write command signal WR2 is masked by the mask logic 50. Fig. 10B In the example shown in , the command burst signal CB caused by the read command is activated at time t24. In response to this activation, the toggle mode signal TGL is removed from the mix command signal MIX1 and the write command signal WR2 again.

[0040] The masking logic 60 also performs the same operation as the masking logic 50 described above, except that the read command signal RD2 is used instead of the write command signal WR2.

[0041] As described above, in the semiconductor device 10 according to the present embodiment, the masking operation is stopped in response to the write command signal WR1 and the read command signal RD1 before the write command signal WR1 and the read command signal RD1 pass through the delay line 24. Therefore, it is not necessary to use a dedicated delay line to time the masking operation. In addition, the generation of the toggle mode signal TGL is immediately stopped in response to the command burst signal CB, and the masking of the mixed command signal MIX2 that has passed through the delay line 24 is immediately performed in response to the command burst signal CB. Therefore, a sufficient margin can be provided to the timing of the release of the masking performed by the masking logics 50 and 60. In addition, since a two-step masking operation including the masking operation using the command selectors 30 and 40 and the masking operation using the masking logics 50 and 60 is performed, and the time period of the first masking using the command selectors 30 and 40 is minimized, NBTI can be more effectively reduced.

[0042] Although various embodiments have been disclosed in the context of specific preferred embodiments and examples, it will be understood by those skilled in the art that the scope of the present disclosure extends beyond the specifically disclosed embodiments to other alternative embodiments and / or use embodiments and their obvious variants and equivalents. In addition, it will be readily apparent to those skilled in the art that other modifications within the scope of the present disclosure will be apparent based on the present disclosure. It is also carefully considered that various combinations or sub-combinations of the specific features and aspects of the embodiments may be performed and still be within the scope of the present disclosure. It should be understood that the various features and aspects of the disclosed embodiments may be combined with each other or replace each other in order to form different modes of the disclosed embodiments. Therefore, it is contemplated that the scope of at least some of the present disclosure should not be limited by the specific disclosed embodiments described above.

Claims

1. A device comprising: a first circuit configured to generate a first internal command signal in response to receiving an external command; a second circuit configured to receive the first internal command signal and the degradation control signal to generate a first mixed signal including a first internal command portion and a degradation control signal portion; a third circuit configured to delay the first mixed signal to generate a second mixed signal; as well as a fourth circuit coupled to the third circuit, the fourth circuit being configured to: receiving the second mixed signal; starting to mask the degradation control signal portion of the second mixed signal at a first timing after receiving the external command; and Masking of the degradation control signal portion of the second mixed signal is stopped at a second timing (t4, t11) after the first internal command portion is generated.

2. The device according to claim 1, wherein the fourth circuit is configured to generate a third mixed signal by masking the degradation control signal portion of the second mixed signal, wherein the apparatus further comprises a fifth circuit configured to generate a second internal command signal by masking the degradation control signal portion of the second mixed signal, wherein the fifth circuit is configured to: starting masking the degradation control signal portion of the second mixed signal at a third timing after deactivating the first internal command portion; and The masking of the degradation control signal portion of the second mix signal is stopped at a fourth timing after the external command is received.

3. The apparatus according to claim 1, further comprising a sixth circuit configured to generate the degradation control signal, wherein the sixth circuit is configured to: starting generation of the degradation control signal in response to the first internal command portion; and The generation of the degradation control signal is stopped in response to the external command.

4. The apparatus according to claim 2, further comprising: a memory cell array; as well as Data control circuit, The data control circuit is configured to transmit write data to the memory cell array in response to the second internal command signal when the external command indicates a write operation.

5. The apparatus according to claim 2, further comprising: a memory cell array; as well as Data control circuit, The data control circuit is configured to output read data read from the memory cell array to the outside in response to the second internal command signal when the external command indicates a read operation.

6. The device according to claim 2, wherein the degradation control signal portion comprises a first toggle pattern preceding the first internal command portion, and At least a portion of the first toggle pattern included in the second mixed signal is masked by the fourth circuit.

7. The device according to claim 6, wherein the degradation control signal portion further comprises a second toggle mode following the first internal command portion, and The fifth circuit is configured to start masking the third mixed signal before the second toggle pattern included in the third mixed signal reaches the fifth circuit.

8. A device comprising: a first circuit configured to generate a first signal in which a first toggle mode, a command mode, and a second toggle mode appear in this order; a second circuit configured to mask the first signal to generate a second signal; a third circuit configured to mask the second signal to generate a third signal, wherein the second circuit is configured to start masking the first signal at a first time before an end time of the first toggle mode, and stop masking the first signal at a second time between the end time of the first toggle mode and the command mode, and Wherein the third circuit is configured to stop masking the second signal at a third time between the first time and the second time, and start masking the second signal at a fourth time between the command mode and a start time of the second toggle mode.

9. The device according to claim 8, wherein the first circuit is configured to generate the first signal by delaying a fourth signal, and The second time is defined by the start time of the command mode included in the fourth signal.

10. The apparatus of claim 9, further comprising a fourth circuit configured to generate the fourth signal in response to a fifth signal, The first time is defined by the fifth signal. 11 . The apparatus according to claim 10 , wherein the third time is defined by a timing at which a first time period elapses after the fifth signal is activated. 12 . The apparatus according to claim 11 , wherein the fourth time is defined by a timing at which a second time period elapses after an end time of the command mode included in the fourth signal.

13. The apparatus of claim 8, further comprising: a memory cell array; as well as I / O circuit, Wherein the I / O circuit is configured to transmit write data to the memory cell array in response to the third signal when the command mode indicates a write operation.

14. The apparatus of claim 8, further comprising: a memory cell array; as well as I / O circuit, The I / O circuit is configured to output read data read from the memory cell array to the outside in response to the third signal when the command mode indicates a read operation.

15. An apparatus comprising: a first circuit configured to generate a first signal including a command pattern and a plurality of dummy patterns; a second circuit configured to generate a second signal by delaying the first signal; as well as a third circuit configured to mask the second signal to remove the plurality of dummy patterns, thereby generating a third signal, The third circuit is configured to stop masking the second signal when the command pattern included in the first signal enters an active state, and start masking the second signal when a first time period elapses after the command pattern included in the first signal enters an inactive state.

16. The device according to claim 15, wherein the plurality of virtual modes include a plurality of first virtual modes that disappear before the command mode appears, and The third circuit is configured to stop masking the second signal after the plurality of first dummy patterns disappear and before the command pattern appears.

17. The device according to claim 16, wherein the plurality of virtual modes further include a plurality of second virtual modes that appear after the command mode disappears, and The third circuit is configured to start masking the second signal after the command pattern disappears and before the plurality of second dummy patterns appear. 18 . The apparatus of claim 17 , wherein the plurality of second virtual patterns appear when a second time period elapses after the command pattern included in the first signal enters an inactive state. The apparatus of claim 18 , wherein the second period of time is longer than the first period of time.

20. The apparatus of claim 16, further comprising a fourth circuit configured to activate the command mode in response to a raw command signal, The plurality of first virtual modes of the first signal are stopped in response to the original command signal.

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